Display device and driving method thereof

Abstract

Embodiments of the present disclosure relate to a display device and a driving method, in which, in a first optimization mode, a controller transmits a first locking signal having multiple pulse waveforms to a first source driver circuit among multiple source driver circuits, receives a second locking signal having multiple pulse waveforms from the last source driver circuit receiving the first locking signal, and when the second locking signal is received, multiple phase-loop fixed data for recovering the frequency and phase of a clock used in the operation of each source driver circuit are sent to each source driver circuit, and in a display mode, the controller transmits a first locking signal having a preset voltage level to the first source driver circuit, receives a second locking signal having multiple preset voltage levels from the last source driver circuit receiving the first locking signal, and when the second locking signal is received, provides an image signal and control data to each source driver circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to Korean Patent Application No. 10-2020-0104122 filed in Korea on August 19, 2020, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device and a driving method thereof. Background Art

[0004] As the information society develops, the demand for display devices for displaying images in various forms is increasing. As display devices, various types of display devices are used, such as a liquid crystal display device (LCD) and an electroluminescent display device (ELD).

[0005] Electroluminescent display devices (ELDs) may include quantum dot light-emitting display devices including quantum dots, inorganic light-emitting display devices, and organic light-emitting display devices.

[0006] The above-mentioned display device may include a source driver circuit for supplying data voltages to data lines to display an image.

[0007] There may be a plurality of source driver circuits corresponding to the resolution and size of the display device. The source driver circuits may have characteristic differences with each other, and the signal output from the source driver circuit is distorted depending on the position where the source driver circuit is arranged to the display device, so there may be a problem that the display device may not be able to operate stably. In addition, if the signal has a high frequency, this distortion becomes greater. Summary of the invention

[0008] Embodiments of the present disclosure relate to a display device capable of transmitting signals at high speed and stably operating, and a driving method of the display device.

[0009] In addition, embodiments of the present disclosure relate to a display device capable of reducing frequency and phase deviations between clocks controlling operation timing of each of a plurality of source driver circuits, and a driving method of the display device.

[0010] In addition, embodiments of the present disclosure relate to a display device capable of improving image quality, and a driving method of the display device.

[0011] In one aspect, a display device is provided, including: a controller operating in a first optimization mode and operating in a display mode after the first optimization mode; and a plurality of source driver circuits connected to and controlled by the controller.

[0012] In a first optimization mode, the controller may transmit a first locking signal having multiple pulse waveforms to a first source driver circuit among multiple source driver circuits, receive a second locking signal having multiple pulse waveforms from a last source driver circuit (which receives the first locking signal transmitted from the first source driver circuit to the last source driver circuit in a cascade manner), and when receiving the second locking signal, send multiple phase loop fixed data for recovering the frequency and phase of a clock used in the operation of each source driver circuit to each source driver circuit.

[0013] In the display mode, the controller may transmit a first locking signal having a preset voltage level to the first source driver circuit, receive a second locking signal having multiple preset voltage levels from the last source driver circuit (which receives the first locking signal transmitted from the first source driver circuit to the last source driver circuit in a cascade manner), and provide an image signal and control data to each source driver circuit when receiving the second locking signal.

[0014] On the other hand, a driving method for a display device is provided, comprising: providing a first locking signal having a preset pattern and multiple pulse waveforms and multiple phase-loop fixed data from a controller to multiple source driver circuits; and setting the frequency and phase of a clock recovered by the phase-loop fixed data in each of the multiple source driver circuits; and when a first locking signal having a preset first voltage is provided to the multiple source driver circuits, the clock is recovered in response to the phase-loop fixed data, and an image signal is transmitted to each source driver circuit.

[0015] According to an embodiment of the present disclosure, a display device capable of transmitting a signal at a high speed and operating stably, and a driving method of the display device can be provided.

[0016] In addition, according to an embodiment of the present disclosure, a display device capable of reducing the frequency and phase deviations between clocks that control the operation timing of each of a plurality of source driver circuits by sending phase loop fixed data that can be used to set the frequency and phase to each source driver circuit, as well as a driving method for the display device can be provided.

[0017] In addition, according to an embodiment of the present disclosure, a display device capable of improving image quality by suppressing a transmission error occurring when transmitting an image signal, and a method of driving the display device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1is a plan view showing a display device according to an embodiment;

[0020] Figure 2 is a circuit diagram showing a pixel according to an embodiment;

[0021] Figure 3 is a plan view showing connections between a controller and a plurality of source driver circuits in a display device according to an embodiment;

[0022] Figure 4 It is shown Figure 3 A timing diagram of the operation between the controller and the source driver circuit shown in ;

[0023] Figure 5 It is a conceptual diagram used to explain the EYE characteristics of differential signals;

[0024] Figure 6 Shows Figure 4 A connection relationship between the controller shown in and a connected locking circuit included in a plurality of source driver circuits;

[0025] Figure 7 It is shown Figure 6 A timing diagram of the controller and source driver circuit shown in FIG. 1 operating in a first optimization mode;

[0026] Figure 8 is a diagram showing a method according to an embodiment of the present invention. Figure 7 The timing diagram of the process of converting the phase loop fixed data in the first optimization mode shown;

[0027] Fig. 9 is a diagram showing a method according to another embodiment of the present invention. Figure 7 The timing diagram of the process of converting the phase loop fixed data in the first optimization mode shown;

[0028] Fig.10 and Fig.11 is a timing diagram showing a process of transmitting a first lock signal and phase loop fixed data to a plurality of source driver circuits in a display device according to an embodiment;

[0029] Fig.12 It is shown Figure 4 A timing diagram of an embodiment of a blank period is shown;

[0030] Fig.13 It is shown Figure 4 A timing diagram of an embodiment of the second optimization mode shown;

[0031] Fig.14 is a structural diagram showing the structure of a controller according to an embodiment;

[0032] Fig.15is a block diagram showing a method for improving noise of a source driver circuit in a display device according to an embodiment;

[0033] Fig.16 is a flowchart illustrating a method of driving a display device according to an embodiment. DETAILED DESCRIPTION

[0034] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are illustrated by legend, and the same reference numerals and symbols may be used to designate the same or similar parts in the accompanying drawings (even if shown in different drawings from each other). In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that a detailed description of the well-known functions and components incorporated herein may make the subject matter in some embodiments of the present disclosure unclear, the description will be omitted. Terms such as "including", "having", "comprising", "constituting", "comprising" and "forming" used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0035] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to limit the nature, sequence, order or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0036] When it is mentioned that a first element is “connected or coupled to” a second element or “contacts or overlaps” the second element, it should be interpreted that not only the first element can be “directly connected or coupled to” the second element or “directly contact or overlaps” the second element, but also a third element can be “interposed” between the first element and the second element, or the first element and the second element can be “connected or coupled to”, “contacts or overlaps” each other via a fourth element, etc. Here, the second element can be included in at least one of the two or more elements that are “connected or coupled to”, “contacts or overlaps”, etc., each other.

[0037] When time-related terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe non-sequential or non-sequential processes or operations unless these terms are used with the terms “directly” or “immediately.”

[0038] In addition, when any dimension, relative size, etc. is mentioned, it should be considered that even if no relevant description is specified, the numerical value or corresponding information (such as level, range, etc.) of the element or feature also includes a tolerance or error range that may be caused by various factors (such as process factors, internal or external impact, noise, etc.). In addition, the term "may" fully encompasses all meanings encompassed by the term "can".

[0039] Figure 1 is a plan view showing a display device 100 according to an embodiment of the present disclosure.

[0040] refer to Figure 1 , the display device 100 may include a display panel 110 , a data driver circuit 120 , a gate driver circuit 130 , and a controller 140 .

[0041] The display panel 110 may include a plurality of pixels 101. The plurality of pixels 101 may be arranged in a matrix form within the display panel 110, but the present invention is not limited thereto. Each of the plurality of pixels 101 may emit light of various colors such as red, green, or blue. However, the color of light emitted from each pixel is not limited thereto.

[0042] A plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm may be arranged on the display panel 110. A plurality of pixels 101 may be connected to the gate lines GL1 to GLn and the data lines DL1 to DLm. Each pixel 101 may receive a data signal transmitted through a corresponding data line among the data lines DL1 to DLm in response to a gate signal transmitted through a corresponding gate line among the gate lines GL1 to GLn. In addition, a plurality of light emission control lines EML1 to EMLn may be arranged on the display panel 110. The light emission control lines EML1 to EMLn transmit light emission control signals to the plurality of pixels 101, thereby controlling the time when the plurality of pixels 101 emit light.

[0043] The data driver circuit 120 may be electrically connected to a plurality of data lines DL1 to DLm to transmit data signals to the pixels 101 through the data lines DL1 to DLm. Here, although one data driver circuit 120 is shown, it is not limited thereto. In addition, the data driver circuit 120 may include a plurality of source driver circuits. The number of source driver circuits may be determined according to the resolution and size of the display panel 110.

[0044] The gate driver circuit 130 may be electrically connected to a plurality of gate lines GL1 to GLn, and may provide gate signals to a plurality of pixels 101 through the plurality of gate lines GL1 to GLn. Here, the gate driver circuit 130 is shown as being disposed on one side of the display panel 110, but is not limited thereto, and may be disposed on both sides of the display panel 110. One gate driver circuit may be connected to an odd-numbered gate line, and another gate driver circuit may be connected to an even-numbered gate line. In addition, the display device 100 may not include a separate gate driver circuit, and may include a gate driver circuit 130 disposed in the display panel 110 in a gate generation circuit type (referred to as a GIP (gate in panel) type).

[0045] The controller 140 may control the data driver circuit 120 and the gate driver circuit 130. The controller 140 may provide the image signal RGB and the data control signal DCS to the data driver circuit 120, and may provide the gate control signal GCS to the gate driver circuit 130.

[0046] Figure 2 is a circuit diagram showing a pixel according to the embodiment.

[0047] refer to Figure 2 , the pixel 101 may include a light emitting device ED that emits light by receiving a driving current Id, and a pixel circuit 101p that provides the driving current Id to the light emitting device ED. The pixel circuit 101p may include a first transistor M1, a second transistor M2, and a capacitor Cst. The pixel circuit 101p may further include a third transistor M3. The first transistor M1 may provide the driving current to the light emitting device ED in response to a data signal Vdata. The second transistor M2 may provide the data signal Vdata from the data line DL to the first transistor M1 in response to a first gate signal GATE1. The capacitor Cst may maintain the data signal Vdata provided to the first transistor M1.

[0048] In the first transistor M1, a first electrode is connected to a first node N1, which is connected to a first power line VL1, a first voltage EVDD is supplied to the first power line VL1, a gate is connected to a second node N2, and a second electrode is connected to a third node N3. The first transistor M1 may allow a current to flow from the first node N1 to the third node N3 according to a voltage level of a data signal supplied to the second node N2. The first electrode of the first transistor M1 may be a drain, and the second electrode may be a source. However, the present disclosure is not limited thereto. The current flowing from the first node N1 to the third node N3 corresponds to Equation 1.

[0049] Equation 1

[0050] Id=k(V GS -Vth)2

[0051] Here, Id represents a current value flowing from the first node N1 to the third node N3, k represents electron mobility of the transistor, VGS represents a voltage difference between the gate and the source of the first transistor M1, and Vth represents a threshold voltage of the first transistor M1.

[0052] The second transistor M2 may include a first electrode connected to the data line DL, a second electrode connected to the second node N2, and a gate connected to the first gate line GL1. The second transistor M2 may provide a data signal Vdata flowing through the data line DL to a third node N3 in response to a first gate signal GATE1 transmitted to the first gate line GL1.

[0053] The capacitor Cst may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The capacitor Cst may maintain a voltage between the first node N1 and the second node N2. Therefore, the capacitor Cst may maintain a voltage level of the data signal Vdata transmitted to the second node N2.

[0054] In the light emitting device ED, the anode may be electrically connected to the first node N1, and the cathode may be electrically connected to the second power supply voltage EVSS. The light emitting device ED may include a light emitting layer that emits light by a current flowing from the anode to the cathode. The light emitting layer may include an inorganic layer or an organic layer. In addition, the light emitting layer may include a plurality of layers. The light emitting diode ED may emit red light, green light, and blue light. However, the present disclosure is not limited thereto, and the light emitting diode ED may emit white light.

[0055] The third transistor M3 may include a first electrode connected to a second power line EL2 providing a reference voltage Vref and a second electrode connected to a first node N1. The gate is connected to a sensing signal line SSL providing a sensing signal SENSE. The second power line may be connected to the analog-to-digital converter 220.

[0056] In addition, the third transistor M3 may provide the voltage level of the first node N1 to the analog-to-digital converter 220 in response to the sensing signal SENSE. The analog-to-digital converter 220 may convert the voltage level of the first node N1 into a digital signal. The analog-to-digital converter 220 may be included in Figure 1 In the data driver circuit 120 shown.

[0057] Figure 3 is a plan view showing connections between a controller and a plurality of source driver circuits in a display device according to an embodiment.

[0058] refer to Figure 3, a plurality of films 120a are arranged on one side of the display panel 110. The display panel 110 and the plurality of films 120a may be connected to each other. Each film 120a may be a flexible circuit film.

[0059] In addition, each of the source driver circuits 120b may be disposed on each of the plurality of films 120a. The source driver circuit 120b may be implemented as an integrated circuit. The source driver circuit 120b disposed on each film 120a may correspond to Figure 1 The data driver circuit 120 shown in FIG. 120 b provides a signal and / or voltage to the display panel 110 .

[0060] In addition, a control printed circuit board 140a may be connected to each membrane 120a. The controller 140 may be provided on the control printed circuit board 140a. The controller 140 may be connected to the plurality of membranes 120a through the control printed circuit board 140a.

[0061] A lock signal line transmitting a lock signal and a plurality of data transmission lines EPI may be provided between the control printed circuit board 140a and the film 120a. The lock signal line may include a lock input line LOCK IN, a cascade line CCL, and a lock output line LOCK OUT.

[0062] The lock input line LOCK IN may connect the controller 140 and the source driver circuit 121b on the first film 121a disposed at the leftmost position in the film 120a. In addition, the lock output line LOCK OUT may connect the controller 140 and the source driver circuit 121b on the sixth film 126a disposed at the rightmost position in the film 120a. In addition, the first lock signal is transmitted from the control printed circuit board 140a to the first film 121a through the lock input line LOCK IN, and the second lock signal is transmitted from the control printed circuit board 140a to the sixth film 126a through the lock output line LOCK OUT. The first lock signal may be a signal input to the source driver circuit 120b, and the second lock signal may be a signal output from the source driver circuit 120b in response to the first lock signal.

[0063] In addition, a plurality of source driver circuits 120b disposed on each film 120a may be connected to adjacent source driver circuits 120b in a cascade manner through cascade lines CCL. That is, a signal output from one source driver circuit is transmitted to an adjacent source driver circuit, and a signal received from an adjacent source driver circuit may be transmitted to another adjacent source driver circuit, so that a plurality of source driver circuits 120b may receive signals sequentially.

[0064] Since the first locking signal is transmitted in a cascade manner between the plurality of source driver circuits 120b, the first locking signal output from the controller 140 is transmitted to one source driver circuit 121b through the locking input line LOCK IN, and then sequentially transmitted from the first source driver circuit 121b to the sixth source driver circuit 126b through the cascade line CCL. The second locking signal may be transmitted from the sixth source driver circuit 126b (which is the last source driver circuit that received the first locking signal) to the controller 140 through the locking output line LOCK OUT.

[0065] In addition, a plurality of data transmission lines EPI may connect the controller 140 and the plurality of source driver circuits 120b. That is, the controller 140 may be connected in parallel through each source driver circuit 120a and the data transmission line EPI.

[0066] Each of the lock input line LOCK IN and the lock output line LOCK OUT may include one line. The cascade line CCL may include one line connecting each source driver circuit 120 b. In the plurality of data transmission lines EPI, a pair of lines may be connected to one film 120 a. The signal transmitted through the plurality of data transmission lines EPI may be a differential signal.

[0067] Figure 4 It is shown Figure 3 A timing diagram of the operations between the controller and the source driver circuit is shown. Figure 5 This is a conceptual diagram for explaining the EYE characteristics of a differential signal.

[0068] refer to Figure 4 , the controller 140 and the source driver circuit 120b can be operated by dividing the operation mode into a power-on reset mode POWER ON RESET, a first optimization mode (initial PLL setting, hereinafter referred to as IPS), and a display mode DISPLAY. The controller 140 and the source driver circuit 120b can be designed to operate in the order of the first optimization mode IPS and the display mode DISPLAY after executing the power-on reset mode POWER ON RESET. In addition, the controller 140 can operate in a second optimization mode (auto EQ mode (Auto EQ mode), hereinafter referred to as AEQ), and the second optimization mode AEQ can be executed between the first optimization mode IPS and the display mode DISPLAY. However, the order of the above modes of the controller 140 is not limited to this.

[0069] The power-on reset mode POWER ON RESET is a period for initializing power supplied to the display device 100 including the controller 140 and the plurality of source driver circuits 120b. The power-on reset mode POWER ON RESET may be performed when power is supplied to the display device 100, and when the power-on reset mode POWER ON RESET is performed, power is supplied to the controller 140 and the source driver circuit 120b. When the power-on reset mode POWER ON RESET is maintained for a preset time or longer, the controller 140 and the source driver circuit 120b may start operating.

[0070] The first optimization mode IPS is a period for setting the frequency and / or phase of the clock for the internal operation of the plurality of source driver circuits 120 b .

[0071] In the first optimization mode IPS, the controller 140 provides a plurality of phase loop fixed data CFG to the plurality of source driver circuits 120 b , and the plurality of source driver circuits 120 b may set the frequency and phase of the clock using one of the plurality of phase loop fixed data CFG.

[0072] The second optimization mode AEQ is a period in which the voltage level of data output from the controller 140 is adjusted to reduce the transmission error rate of data sent from the controller 140 to the plurality of source driver circuits 120b. In the second optimization mode AEQ, the controller 140 sends a plurality of error detection data to the plurality of source driver circuits 120b, respectively, and then measures each transmission error rate corresponding to each error detection data.

[0073] In addition, each of the plurality of source driver circuits 120b may send a transmission error rate to the controller 140. Therefore, the controller 140 tracks the voltage level (EQ tracking) with a low transmission error rate. In addition, the controller 140 may output the image signal RWGB by selecting a voltage level with a low transmission error rate according to the received transmission error rate.

[0074] The display mode DISPLAY is when the image signal RWGB and the control data CTRS are provided to the plurality of source driver circuits 120b so that an image is displayed on Figure 1 The period on the display panel 110 shown. Since the controller 140 operates by receiving the clock, but the plurality of source driver circuits 120b do not receive the clock, the plurality of source driver circuits 120b recover and use the clock to perform normal operations. In addition, in the display mode DISPLAY, the plurality of source driver circuits 120b recover the clock by using the phase loop fixed data CFG provided in the first optimization mode IPS, and the image signal RWGB can be processed to generate a data signal and provided to the display panel 110.

[0075] In addition, in the display mode DISPLAY, the image signal may be provided as a voltage level corresponding to a voltage level set to have a low transmission error rate in the second optimization mode AEQ.

[0076] In the power-on reset mode POWER ON RESET, the first driving power supply VCC is started. The first driving power VCC is provided to the controller 140 and / or the source driver circuit 120b. In the power-on reset mode POWER ON RESET, the first locking signal LOCK1 can be in a low state. In addition, the first locking signal LOCK1 begins to be transmitted to the plurality of source driver circuits 120b, and during the period Tpor (the first locking signal LOCK1 has not yet been transmitted to the last source driver circuit 126b), the output state of the second locking signal LOCK2 can be uncertain.

[0077] When the first locking signal LOCK1 is transmitted to the sixth source driver circuit 126b, the second locking signal LOCK2 outputted from the sixth source driver circuit 126b may be transmitted in a low state to the controller 140. In addition, data transmitted to the source driver circuit 120b through the data transmission line EPI in the power-on reset mode POWER ON RESET may be 0.

[0078] In the first optimization mode IPS, the first lock signal LOCK1 may be provided as a plurality of pulse waveforms having a preset pattern. The first lock signal LOCK1 provided in the first optimization mode ISP may be used as a clock in the first optimization mode ISP. Since the second lock signal LOCK2 is output from the source driver circuit 120b receiving the first lock signal LOCK1, the second lock signal LOCK2 may be output as a pulse waveform having the same pattern as the first lock signal LOCK1 after the first lock signal LOCK1 is input in the first optimization mode IPS and a preset time has passed.

[0079] In the first optimization mode IPS, the phase loop fixed data CFG may be sent to the data transmission line EPI. After the first optimization mode IPS starts and then a predetermined time passes, the phase loop fixed data CFG may be provided in parallel to the plurality of source driver circuits 120b through the data transmission line EPI.

[0080] The controller 140 may operate according to a clock, and the control data CTRS and the image signal RGB are synchronized with the clock and may be provided from the controller 140 to the plurality of source driver circuits 120b. The plurality of source driver circuits 120b may process the control data CTRS and the image signal RGB to generate the plurality of source driver circuits 120b. Figure 1An image is displayed on the display panel 110 as shown.

[0081] In order for the source driver circuit 120b to display an image normally, it may operate in synchronization with the clock operated by the controller 140. However, since a clock line for transmitting a clock thereto is not arranged between the controller 140 and the plurality of source driver circuits 120b, the plurality of source driver circuits 120b recover the clock and then use the recovered clock. By processing the control data CTRS and the image signal RGB, an image may be displayed on the display panel 110.

[0082] When recovering the clock, the multiple source driver circuits 120b use the phase loop fixed data. The source driver circuits 120b have different environments and there are hardware differences between them. In addition, when the multiple source driver circuits 120b recover the clock by using the set phase loop fixed data, due to the different environments of the multiple source driver circuits 120b and the hardware differences between them, the phase and frequency of the clock output from the source driver circuit 120b will be different from each other. For example, due to the difference in the position where the multiple source driver circuits 120b are set in the display device 100, the environment between the source driver circuits 120b may be different.

[0083] However, when the phase loop fixed data CFG is sent to each source driver circuit 120b, each source driver circuit 120b can set the phase and frequency of the clock according to the phase loop fixed data CFG and output the clock. Since the phase loop fixed data CFG can be sent to each source driver circuit 120b, each source driver circuit 120b receives and uses the required phase loop fixed data CFG instead of the set phase loop fixed data.

[0084] In addition, if the clock output from each source driver circuit 120b has a phase and frequency deviation due to the received phase loop fixed data CFG, the phase and frequency of the clock output from the source driver circuit 120b can be changed by sending another phase loop fixed data CFG to the source driver circuit 120b.

[0085] For the same reasons as described above, phase and frequency deviations of the clock output from each source driver circuit 120 b can be suppressed.

[0086] As described above, since there is no clock line connecting the controller 140 and the plurality of source driver circuits 120b, the clock used when the phase loop fixed data CFG is sent from the controller 140 to the plurality of source driver circuits 120b in the first optimization mode IPS can be sent through a line other than the clock line. In order for the source driver circuit 120b to use the clock in the first optimization mode IPS, the first lock signal LOCK1 can be used as the clock.

[0087] By connecting the controller 140 to the lock input line LOCK IN of the leftmost source driver circuit 121b provided in the plurality of source driver circuits 120b, a first lock signal LOCK1 having a plurality of pulse waveforms may be provided. Since the first lock signal LOCK1 may be sequentially transmitted to all source driver circuits 120b through the cascade line CCL, the plurality of source driver circuits 120b sequentially receive the first lock signal LOCK1. Therefore, the lock input line LOCK IN and the cascade line CCL may be lines for transmitting a clock in the first optimization mode IPS.

[0088] When the second locking signal LOCK2 corresponding to the first locking signal LOCK1 from the last source driver circuit 126 b receiving the first locking signal LOCK1 is transmitted to the controller 140 through the locking output line LOCK OUT, the controller 140 may provide the phase loop fixed data CFG to each source driver circuit 120 b in parallel.

[0089] The controller 140 may send the phase loop fixed data CFG to each source driver circuit 120b, and each of the plurality of source driver circuits 120b may set the phase and frequency of the clock used in the source driver circuit 120b according to the phase loop fixed data CFG. To this end, during the manufacturing process of the source driver circuit 120b, each source driver circuit 120b does not set the phase and frequency of the clock by the preset phase loop fixed data CFG, but sends the phase loop fixed data CFG to each source driver circuit 120b through the first optimization mode (IPS), and the phase and frequency of the clock output from the source driver circuit 120b may be set by the received phase loop fixed data.

[0090] If the image on the display panel 110 is displayed normally while the source driver circuit 120b operates using a clock whose phase and frequency are set by the received phase loop fixed data CFG, the source driver circuit 120b can operate by the clock generated by the received phase loop fixed data CFG without changing the received phase loop fixed data CFG.

[0091] However, when the source driver circuit 120b operates in response to the clock having the phase and frequency set by the received phase loop fixed data CFG, if the image on the display panel 110 cannot be displayed normally, the first optimization mode IPS is performed again, so that another phase loop fixed data CFG can be sent to the source driver circuit 120b. The phase and frequency of the clock can be set in the source driver circuit 120b by the newly sent phase loop fixed data CFG.

[0092] In the second optimization mode AEQ, the voltage level of the data output from the controller 140 to the plurality of source driver circuits 120b through the data transmission line EPI may be adjusted. The distance between the controller 140 and the plurality of source driver circuits may be adjusted according to the position where the film 120a is attached to the display panel 110 (eg, Figure 3 ). In particular, as the size of the display panel 110 increases, the difference between the controller 140 and the multiple source driver circuits 120b may increase. If the lengths of the data transmission lines EPI connecting the controller 140 and the multiple source driver circuits 120b are different, differences in impedance components such as resistance may occur between the data transmission lines EPI. Therefore, for each of the multiple source driver circuits 120b, the transmission error rate of the data transmitted from the controller 140 to each of the multiple source driver circuits 120b will be different. As the distance from the controller 140 to each of the multiple source driver circuits 120b increases, the transmission error rate of the data transmitted from the controller 140 to each of the multiple source driver circuits 120b will increase.

[0093] The controller 140 may transmit a plurality of error detection data BERT for determining the transmission error rate of data in the second optimization mode AEQ to each of the plurality of source driver circuits 120b. In addition, each of the plurality of source driver circuits 120b may detect the transmission error rate of data corresponding to the plurality of transmitted error detection data BERT. In addition, each of the plurality of source driver circuits 120b may transmit the data transmission error rate to the controller 140.

[0094] The controller 140 may control a voltage level of data output from the controller 140 through the data transmission line EPI in response to the received transmission error rate. In addition, in the second optimization mode AEQ, the controller 140 may prevent an increase in the data transmission error rate by improving the EYE characteristics of the transmitted data.

[0095] The data transmission line EPI includes a pair of lines. Figure 5 As shown in (a), a first signal Sig1 is transmitted through one of a pair of data transmission lines, and a second signal Sig2 having a phase opposite to that of the first signal Sig1 can be transmitted through the other data transmission line. Since the first signal Sig1 and the second signal Sig2 of opposite phases are provided to the source driver circuit 120b, the amplitude of the signal recognized by the source driver circuit 120b is equal to the amplitude of the transmitted first signal Sig1. For this reason, when a differential signal is used, the transmission rate can be increased even when the same voltage as one signal is used.

[0096] And, if Figure 5As shown in (b), the larger or clearer the shape of the diamond 501 in the shaded portion in the middle between the two signals Sig1 and Sig2, the smaller the signal distortion of the transmitted data may be. In addition, the smaller or clearer the diamond 501 in the shaded portion, the greater the signal distortion of the transmitted data may be. Improving the EYE characteristics refers to adjusting the voltage level of the signal so that the diamond 501 appears larger and clearer between the two signals Sig1 and Sig2 provided as a differential signal.

[0097] In the display mode DISPLAY, the controller 140 can provide the image signal RGB and the control data CTRS to the plurality of source driver circuits 120b. Figure 1 The display panel 110 shown in FIG. 1 displays an image corresponding to the image signal RGB. Here, the image signal RGB may include image signals corresponding to red, white, green, and blue, but is not limited thereto. The control data CTRS may include a control signal for controlling the image signal. Figure 1 The data control signals of the data driver circuit 120 and the gate control signals for controlling the gate driver circuit 130 are shown. However, it is not limited thereto.

[0098] Since a line for transmitting a clock is not provided between the controller 140 and the plurality of source driver circuits 120 b , each of the plurality of source driver circuits 120 b generates a clock used for operation of the plurality of source driver circuits 120 b using a signal transmitted from the controller 140 .

[0099] The display mode DISPLAY includes a first display period Phase 1 for providing a clock training pattern CTP to the plurality of source driver circuits 120 b, a second display period Phase 2 including a blank period for not transmitting signals and image signals RGB, a third display period Phase 3 for sending control data CTRS, and a fourth display period Phase 4 for transmitting image signals RGB.

[0100] In the first display period Phase 1, each source driver circuit 120b may receive a clock training pattern CTP and may restore an internal clock of the source driver circuit 120b to correspond to a clock used in the controller 140 in response to the clock training pattern CTP and the set phase loop fixed data CFG.

[0101] In addition, each frame of the image can be distinguished by the second display period Phase 2. In addition, since the control data CTRS is transmitted in the third display period Phase 3, a signal for controlling the source driver circuit 120b can be transmitted. In the fourth display period Phase 4, the source driver circuit 120b can receive the image signal RGB. The source driver circuit 120b can display an image on the display panel 110 by processing the image signal RGB in response to the control data CTRS and the clock.

[0102] In addition, the first optimization mode IPS can operate at a low frequency Low Freq, and the second optimization mode AEQ and the display mode DISPLAY can operate at a higher frequency than the first optimization mode IPS. That is, after a certain period of time after the power-on reset mode POWER ON RESET is executed, the driving frequency of the display device 100 can be increased.

[0103] Figure 6 Shows Figure 4 0014 shows a connection relationship between a controller shown in FIG. 1 and a connected locking circuit included in a plurality of source driver circuits.

[0104] refer to Figure 6 , the plurality of source driver circuits 120b may respectively include latch circuits 621 to 626. Here, the number of the plurality of latch circuits 621 to 626 may correspond to the number of the source driver circuits 120b.

[0105] Each of the plurality of locking circuits 621 to 626 may include a first terminal P1, a second terminal P2, and a third terminal P3. A first locking signal LOCK1 may be provided to the first terminal P1. In the first optimization mode IPS, the phase loop fixed data CFG may be provided to the second terminal P2, and in the second optimization mode AEQ, the error detection data BERT may be provided. In addition, the clock training pattern CTP, the control data CTRS, and the image signal RGB transmitted in the display mode DISPLAY may be transmitted to the second terminal P2.

[0106] Among the plurality of locking circuits 621 to 626, the first locking circuit 621 which first receives the first locking signal LOCK1 is set Figure 3 The sixth locking circuit 626 that finally receives the first locking signal LOCK1 may be disposed in the sixth source driver circuit 126b.

[0107] The lock input line LOCK IN may be connected to the first terminal P1 of the first lock circuit 621 so that the first lock circuit 621 may be connected to the controller 140. In addition, the third terminal P3 of the sixth lock circuit 626 may be connected to the lock output line LOCK OUT so that the sixth lock circuit 626 may be connected to the controller 140. The controller 140 may check the states of the plurality of source driver circuits 120 b through the second lock signal LOCK2 transmitted through the lock output line LOCK OUT.

[0108] In addition, the third terminal P3 of the first locking circuit 621 may be connected to the first terminal P1 of the adjacent second locking circuit 622. The third terminal P3 of the second locking circuit 622 is connected to the first terminal P1 of the third locking circuit 623, and the third terminal P3 of the third locking circuit 623 is the fourth terminal. The first terminal P1 of the locking circuit 624 may be connected, and the third terminal P3 of the fourth locking circuit 624 may be connected to the first terminal P1 of the fifth locking circuit 625. In addition, the third terminal P3 of the fifth locking circuit 625 may be connected to the first terminal P1 of the sixth locking circuit 626. Here, the line connecting the third terminal P3 and the first terminal P1 of the adjacent locking circuits 622 to 626 in each of the locking circuits 621 to 625 may be referred to as a cascade line CCL.

[0109] In addition, each of the locking circuits 621 to 626 may include a mode control logic circuit 601, a clock and data recovery circuit 602, and a logic gate circuit 603. Here, the logic gate circuit 603 is shown as an AND gate, but is not limited thereto.

[0110] The mode control logic circuit 601 can distinguish the mode by receiving the first lock signal LOCK1 transmitted from the first terminal P1. That is, the mode control logic circuit 601 can distinguish the first optimization mode IPS, the second optimization mode AEQ and the display mode DISPLAY using the first lock signal LOCK1. When the first lock signal LOCK1 is a plurality of pulse waveforms having a preset pattern, the mode control logic circuit 601 determines the mode as the first optimization mode IPS, when the first lock signal LOCK1 is in a low state, the mode control logic circuit 601 determines the mode as the second optimization mode AEQ, and when the first lock signal LOCK1 is in a high state, the mode control logic circuit 601 determines the mode as the display mode DISPLAY.

[0111] In addition, the mode control logic circuit 601 may provide an internal clock signal to the logic gate circuit 603 .

[0112] The clock and data recovery circuit 602 may operate in response to the control of the mode control logic circuit 601. The clock and data recovery circuit 602 may receive the phase loop fixed data CFG transmitted to the second terminal P2. When the mode control logic circuit 601 recognizes that the mode is the first optimization mode IPS, the clock and data recovery circuit 602 receives the phase loop fixed data CFG and performs settings using the received phase loop fixed data CFG.

[0113] The clock and data recovery circuit 602 may output a phase loop lock state signal PLL LOCK, which checks whether the clock phase and the clock frequency are fixed in the clock and data recovery circuit 602. When the phase and the frequency of the clock are fixed in the display mode DISPLAY, the phase loop lock state signal PLL LOCK may be output in a high state. On the other hand, when an error occurs in the data transmitted from the controller 140 to the source driver circuit 120b, the phase loop lock state signal PLL LOCK may be output in a low state.

[0114] The logic gate circuit 603 may generate a second locking signal LOCK2 by calculating the first locking signal LOCK1 and the internal clock signal, and output the second locking signal LOCK2 through the third terminal P3 .

[0115] In the first optimization mode IPS, the mode control logic circuit 601 may provide a high-state internal clock signal to the logic gate circuit 603. When the high-state internal clock signal is provided to the logic gate circuit 603, since the logic gate circuit 603 performs an AND operation, the logic gate circuit 603 outputs the second lock signal LOCK2 which is the same as the first lock signal LOCK1. In the first optimization mode IPS, since the first lock signal LOCK1 has a plurality of pulse waveforms including a preset pattern, the second lock signal LOCK2 also has a plurality of pulse waveforms including the same pattern as the first lock signal LOCK1. That is, in the first optimization mode IPS, the first lock signal LOCK1 may be bypassed and output as the second lock signal LOCK2.

[0116] In addition, in the second optimization mode AEQ, the mode control logic circuit 601 can output a low internal clock signal. In the second optimization mode AEQ, the first lock signal LOCK1 is transmitted in a low state, and the logic gate circuit 603 can output a low second lock signal LOCK2.

[0117] In the display mode DISPLAY, the clock and data recovery circuit 602 can use the clock training pattern CTP and the set phase loop fixed data CFG to fix the phase and frequency of the clock. The clock and data recovery circuit 602 can recover the clock according to the fixed clock phase and frequency.

[0118] In addition, in the display mode DISPLAY, the mode control logic circuit 601 can output the internal clock signal in the same state as the phase loop lock state signal PLL LOCK. When the phase and frequency of the clock are fixed in the display mode DISPLAY, the phase loop lock state signal PLL LOCK can be output in a high state. In addition, the internal clock signal can be output in a high state (which is the state of the phase loop lock state signal PLL LOCK), so that the second lock signal LOCK2 can be output in the same state as the first lock signal LOCK1. Therefore, in the display mode DISPLAY, the second lock signal LOCK2 can be output in a high state. The controller 140 can recognize that the phase and frequency of the clock output from the plurality of source driver circuits 120b are fixed to a high state by the first lock signal LOCK1.

[0119] When the phase loop lock state signal PLL LOCK is output in a low state, the internal clock signal is output in a low state (which is the state of the phase loop lock state signal PLL LOCK), and the second lock signal LOCK2 is output in a low state. Since the second lock signal LOCK2 is in a low state, the controller 140 can recognize that the fixed state of the phase and frequency of the clock output from the plurality of source driver circuits 120b is released. When the second lock signal LOCK2 is output in a low state, the controller 140 can cause the first period Phase 1 to be executed again.

[0120] Figure 7 It is shown Figure 6 0 is a timing diagram of the controller and source driver circuit shown in FIG. 1 operating in the first optimization mode.

[0121] refer to Figure 7 , the first optimization mode IPS may be divided into a first period T11, a second period T12, and a third period T13. In the first optimization mode IPS, data may be sent to the data transmission line EPI. Figure 7 The transmitted data in represents differently a pulse waveform transmitted through the data transmission line EPI and a pulse waveform transmitted by a differential signal.

[0122] The first locking signal LOCK1 or the second locking signal LOCK2 may be transmitted through the locking input line LOCK IN or the locking output line LOCK OUT. In addition, the first locking signal LOCK1 may be transmitted between the source driver circuits 120b through the cascade line CCL. Since the second locking signal LOCK2 is generated after the first locking signal LOCK1 passes through the plurality of source driver circuits 120b, the second locking signal LOCK2 may be generated after the first locking signal LOCK1.

[0123] In the first period T11, the data sent to the data transmission line EPI may be zero. In order to make the sent data become 0, the rising edge of the first lock signal LOCK1 may correspond to the time point when the clock sent to the data transmission line EPI is in a low state. In addition, a plurality of pulse waves having a preset pattern may be sent during the second period T12. According to the preset pattern, the first rising edge of the first lock signal LOCK1 corresponds to the high state of the clock, and the second rising edge corresponds to the low state of the clock. Therefore, it can be seen that the data sent is 1010. However, this is illustrative and not limited thereto.

[0124] After a pulse wave having a preset pattern is transmitted through the data transmission line EPI, the phase loop fixed data CFG1 to CFG40 may be started to be transmitted. After a plurality of pulse waves having a preset pattern of 1010 data are input, the third period T13 may be started. The phase loop fixed data CFG1 to CFG40 may be transmitted to the source driver circuit 120b. The phase loop fixed data CFG may be stored in the controller 140. Here, the number of the phase loop fixed data CFG1 to CFG40 is shown as 40, but is not limited thereto.

[0125] In addition, a fourth period T14 may be included, in which the signal transmitted to the transmission line EPI is in a low state and the first locking signal LOCK1 and the second locking signal LOCK2 maintain a state having a plurality of pulses. Since the first locking signal LOCK1 further maintains a state having a plurality of pulses in the fourth period T14, the source driver circuit 120b may further maintain the operation corresponding to the first locking signal LOCK1 for a preset period of time.

[0126] The phase loop fixed data CFG may be input to the clock and data recovery circuit 602 in response to the first lock signal LOCK1. That is, the clock and data recovery circuit 602 may store the phase loop fixed data CFG input to the clock and data recovery circuit 602.

[0127] In addition, the phase loop fixed data CFG can be converted and output. If the phase loop locked data CFG is sent as 0000 or 1111, since the phase loop locked data CFG contains unchanged data, it can be converted to contain 0 and 1 by bit extension. In addition, since the phase loop fixed data CFG is provided as a differential signal, for example, 0 can be converted to 0111 and 1 can be converted to 0001. For this reason, the number of 1s and 0s of the converted numbers can be made the same.

[0128] Figure 8 is a diagram showing a method according to an embodiment of the present invention. Figure 7 FIG. 1 is a timing diagram of the process of converting phase loop fixed data in the first optimization mode.

[0129] exist Figure 8 In the figure, (a) shows the case where the basic phase loop fixed data 1CFG is 0, and (b) shows the case where the basic phase loop fixed data 1CFG is 1.

[0130] refer to Figure 8 The phase loop fixed data 2CFG is data in which the number of bits of the basic phase loop fixed data 1CFG including N bits (N is a natural number greater than or equal to 1) is expanded, and each of the N bits included in the basic phase loop fixed data 1CFG is expanded to more than 2 bits (including at least one 0 and at least one 1). The phase loop fixed data 2CFG can be converted by the controller 140 by bit expansion of the basic phase loop fixed data 1CFG.

[0131] The basic phase-loop fixed data 1CFG may be stored in the controller 140, and the phase-loop fixed data 2CFG may be respectively transmitted from the controller 140 to the plurality of source driver circuits 120b. In addition, the phase-loop fixed data 2CFG may be bit-extended so that one bit included in the basic phase-loop fixed data 1CFG includes at least one 0 and at least one 1. In addition, since the basic phase-loop fixed data 1CFG is a differential signal transmitted through each of the two lines, the number of 1s and 0s included in the extended bit in the phase-loop fixed data 2CFG may be the same.

[0132] The setup time t setup and the hold time t hold are the times required for the source driver circuit 120 b to recognize the data transmitted from the controller 140 to the source driver circuit 120 b. That is, the source driver circuit 120 b can recognize the data only when the data set during the setup time t setup is maintained during the hold time t hold. The sum of the setup time t setup and the hold time t hold may correspond to the time for transmitting one bit of data.

[0133] like Figure 8 As shown in (a), when the basic phase loop fixed data 1CFG is 0, the controller 140 may convert the basic phase loop fixed data 1CFG into 0110, generate the phase loop fixed data 2CFG and send it to the source driver circuit 120b. The source driver circuit 120b may check the basic phase loop fixed data 1CFG using the phase loop fixed data 2CFG converted into 0110 and the first lock signal LOCK1.

[0134] Since the first lock signal LOCK1 is transmitted in the form of a plurality of pulse waves in the first optimization mode IPS, it repeats high and low states. During the period of transmitting two bits of the phase loop fixed data 2CFG, the first lock signal LOCK1 may maintain a high or low state.

[0135] In addition, when the phase loop fixed data 2CFG is at a rising edge, the state of the first locking signal LOCK1 can be identified as the basic phase loop fixed data 1CFG. That is, when the basic phase loop fixed data 2CFG is at a rising edge, the first locking signal LOCK1 is in a low state, so the source driver circuit 120b can recognize that the basic phase loop fixed data 1CFG is 0.

[0136] like Figure 8 As shown in (b), when the basic phase loop fixed data 1CFG is 1, the controller 140 can convert the basic phase loop fixed data 1CFG into 1001, generate the phase loop locking data 2CFG and send it to the source driver circuit 120b. The source driver circuit 120b can use the phase loop fixed data 2CFG converted to 1001 and the first locking signal LOCK1 to check the basic phase loop fixed data 1CFG.

[0137] Since the first lock signal LOCK1 is transmitted in the form of a plurality of pulse waves in the first optimization mode IPS, it repeats high and low states. During the period of transmitting two bits of the phase loop fixed data 2CFG, the first lock signal LOCK1 may maintain a high or low state.

[0138] In addition, when the phase loop fixed data 2CFG is at a rising edge, the state of the first locking signal LOCK1 can be recognized as the phase loop fixed data 1CFG. That is, since the first locking signal LOCK1 is in a high state when the phase loop fixed data 2CFG is at a rising edge, the source driver circuit 120b can recognize that the basic phase loop fixed data 1CFG is 1.

[0139] Fig. 9 is a diagram showing a method according to another embodiment of the present invention. Figure 7 FIG. 1 is a timing diagram of the process of converting phase loop fixed data in the first optimization mode.

[0140] exist Fig. 9 In the figure, (a) shows the case where the basic phase loop fixed data 1CFG is 0, and (b) shows the case where the basic phase loop fixed data 1CFG is 1.

[0141] refer to Fig. 9 The phase loop fixed data 2CFG is data in which the number of bits of the basic phase loop fixed data 1CFG including N bits (N is a natural number greater than or equal to 1) is expanded, and each of the N bits included in the basic phase loop fixed data 1CFG is expanded to more than 2 bits (including at least one 0 and at least one 1). The phase loop fixed data 2CFG can be converted by the controller 140 by bit expansion of the basic phase loop fixed data 1CFG.

[0142] The basic phase loop fixed data 1CFG may be stored in the controller 140, and the phase loop locked data 2CFG may be respectively transmitted from the controller 140 to the plurality of source driver circuits 120b. In addition, the phase loop fixed data 2CFG may be bit-extended so that one bit included in the basic phase loop fixed data 1CFG includes at least one 0 and at least one 1. In addition, since the basic phase loop fixed data 1CFG is a differential signal transmitted through each of the two lines, the number of 1s and 0s included in the extended bit in the phase loop fixed data 2CFG may be the same.

[0143] The setup time t setup and the hold time t hold are times required for the source driver circuit 120 b to recognize data transmitted from the controller 140 to the source driver circuit 120 b. That is, the source driver circuit 120 b can recognize the data only when the data held during the setup time t setup is held during the hold time t hold. The sum of the setup time t setup and the hold time t hold may correspond to the time for transmitting one bit of data.

[0144] like Fig. 9 As shown in (a), when the basic phase loop fixed data 1CFG is 0, the controller 140 may convert the basic phase loop fixed data 1CFG into 1001, generate the phase loop fixed data 2CFG and send it to the source driver circuit 120b. The source driver circuit 120b may check the basic phase loop fixed data 1CFG using the phase loop fixed data 2CFG converted into 1001 and the first lock signal LOCK1.

[0145] Since the first lock signal LOCK1 is transmitted in the form of a plurality of pulse waves in the first optimization mode IPS, it repeats high and low states. During the period of transmitting two bits of the phase loop fixed data 2CFG, the first lock signal LOCK1 may maintain a high or low state.

[0146] In addition, when the phase loop fixed data 2CFG is at a rising edge, the state of the first locking signal LOCK1 can be identified as the basic phase loop fixed data 1CFG. That is, when the basic phase loop fixed data 2CFG is at a rising edge, the first locking signal LOCK1 is in a low state, so the source driver circuit 120b can recognize that the basic phase loop fixed data 1CFG is 0.

[0147] like Fig. 9As shown in (b), when the basic phase loop fixed data 1CFG is 1, the controller 140 can convert the basic phase loop fixed data 1CFG into 0110, generate the phase loop locking data 2CFG and send it to the source driver circuit 120b. The source driver circuit 120b can check the basic phase loop fixed data 1CFG using the phase loop fixed data 2CFG converted into 0110 and the first locking signal LOCK1.

[0148] Since the first locking signal LOCK1 is transmitted in the form of a plurality of pulse waves in the first optimization mode IPS, it repeats high and low states. During a period of transmitting two bits of the phase loop fixed data 2CFG, the first locking signal LOCK1 may maintain a high or low state.

[0149] In addition, when the phase loop fixed data 2CFG is at a rising edge, the state of the first locking signal LOCK1 can be identified as the phase loop fixed data 1CFG. That is, since the first locking signal LOCK1 is in a high state when the phase loop fixed data 2CFG is at a rising edge, this source driver circuit 120b can identify that the basic phase loop fixed data 1CFG is 1.

[0150] Fig.10 and Fig.11 is a timing diagram showing a process of transmitting a first lock signal and phase loop fixed data to a plurality of source driver circuits in an embodiment.

[0151] exist Fig.10 and Fig.11 , (a) shows the phase loop fixed data CFG sent from the controller 140 through the data transmission line EPI and the first lock signal LOCK1 transmitted therefrom through the lock input line LOCK IN. In addition, (b) shows the phase loop fixed data CFG and the first lock signals LOCK1_1 to LOCK1_6 received from each source driver circuit 120b, respectively. The phase loop fixed data CFG may include bits expanded by the controller 140.

[0152] Since the first locking signal LOCK1 is transmitted to each source driver circuit 120b in a cascade manner, the signal received from each source driver circuit 120b is transmitted according to the position of the source driver circuit 120b. For each source driver circuit 120b, the phase loop fixed data CFG and the first locking signals LOCK1_1 to LOCK1_6 may be transmitted at different times. On the other hand, since the phase loop fixed data CFG is sent to each source driver circuit 120b in parallel, it may be sent to each source driver circuit 120b at the same time.

[0153] When the first lock signals LOCK1_1 to LOCK1_6 are transmitted to each source driver circuit 120b at different times, the setup time t setup may be insufficient. Therefore, the source driver circuit 120b cannot recognize the transmitted data. In particular, when a high frequency signal is used, such a problem may become more serious.

[0154] In order to solve the above problem, the controller 140 may delay the phase-loop fixed data CFG and transmit it to each source driver circuit 120b. For each source driver circuit 120b, the delay time Td of the delayed phase-loop fixed data CFG may be set differently.

[0155] To this end, the controller 140 can store the delay time Td corresponding to each source driver circuit 120b, and provide the phase loop fixed data CFG according to the delay time Td stored in each source driver circuit 120b. Therefore, according to the set delay time Td, the setting time in each source driver circuit 120b is constant, so that the controller 140 and the source driver circuit 120b can operate stably.

[0156] like Fig.10 As shown in (b), the source driver circuit 120b may check the provided phase-loop fixed data CFG according to the states of the first locking signals LOCK1-1 to LOCK1-6 in response to the rising edge of the phase-loop fixed data CFG. Fig.11 As shown in (b), the source driver circuit 120b may check the provided phase loop fixed data CFG in response to the rising edge of the first locking signals LOCK1-1 to LOCK1-6.

[0157] Fig.12 It is shown Figure 4 A timing diagram of an embodiment of a blank period is shown.

[0158] like Figure 4 As shown, in the display mode DISPLAY, after the phase and frequency of the signal outputted by the clock training mode CTP are fixed in the first period Phase 1, the third period Phase 3 and the fourth period Phase 4 are performed, so that an image can be displayed on the display panel 110. In addition, the third period Phase 3 and the fourth period Phase 4 can be performed after the blank period BLT is performed, instead of performing the first period Phase 1 again. That is, after being turned on, in the display mode DISPLAY, the first period Phase 1 is performed once, and the third period Phase 3 and the fourth period Phase 4 are repeated so that an image can be displayed on the display panel 110.

[0159] Before displaying an image or during image display, a second period Phase 2 (which is a blank period) occurs. Fig.12 (a) shows Figure 4 The blank period ILT between the third period Phase 3 and the fourth period Phase 4 in the Fig.12 (b) shows a blank period ILT after the third period Phase 3 and the fourth period Phase 4 are performed and before the third period Phase 3 and the fourth period Phase 4 are performed again. Fig.12 Both (a) and (b) can be shown as Figure 4 The second period is Phase 2.

[0160] like Fig.12 As shown in (a), in the blank period ILT, the controller 140 may provide blank data HB having a specific pattern. In addition, the controller 140 may count the number of packets of the blank data HB, so that when the number of packets of the blank data HB reaches a preset value, the third period Phase 3 is started. However, when the blank data HB is transmitted through the data transmission line EPI, it may be transmitted in a preset pulse waveform.

[0161] When the blank data HB is repeated, a signal having the same pulse waveform is repeated through the data transmission line EPI, thereby deteriorating the EMI (electromagnetic interference) of the display device 100. However, in the display mode DISPLAY, the blank period ILT appears once and is not repeated. Therefore, even if the blank data HB is repeated within the blank period ILT, the EMI of the display device 100 does not deteriorate.

[0162] On the other hand, the blank period BLT may be repeated in the display mode DISPLAY When the blank period BLT is repeated, EMI of the display device 100 may be deteriorated due to the repeated blank data HB.

[0163] In order to solve this problem, Fig.12 As shown in (b), in a part of the blank period BLT, after providing random data DUM DATA whose pulse waveform is randomly determined, blank data HB having a specific pattern may be provided. That is, the blank period BLT may be divided into a first blank period for transmitting the random data DUM DATA and a second blank period for transmitting the blank data HB having a preset pulse waveform. Due to the random data DUM DATA, the pulse waveform of the signal transmitted through the data transmission line EPI in the blank period BLT is not repeated, thereby preventing EMI degradation of the display device 100.

[0164] In addition, the controller 140 may provide random data DUM DATA after confirming that the fourth period Phase 4 has ended by counting the number of packets of data of the video signal RGB. The number of packets of blank data HB having a specific pattern must be equal to or greater than a preset number thereof. The controller 140 may include a counter that counts the number of packets of blank data HB or data of the image signal RGB.

[0165] Fig.13 It is shown Figure 4 A timing diagram of an embodiment of the second optimization mode is shown.

[0166] refer to Fig.13 , the second optimization mode AEQ can be divided into a preparation period T21 and an error detection period T22 to operate. In the preparation period T21, a plurality of pulse waves with a preset pattern can be sent through the data transmission line EPI. It can be seen that due to the plurality of pulse waves with a preset pattern transmitted through the data transmission line EPI in the preparation period T21, the source driver circuit 120b has started the second optimization mode AEQ. That is, it can be seen that due to the plurality of pulse waves with a preset pattern to be sent, the source driver circuit 120b has started the error detection period T22.

[0167] In the error detection period T22, a plurality of error detection data BERT may be transmitted. Here, although it is shown that the number of the plurality of error detection data BERT is eight, it is not limited thereto.

[0168] The plurality of source driver circuits 120b may sequentially receive a plurality of error detection data BERT. In addition, the controller 140 may receive a bitwise error rate for each error detection data BERT from each of the plurality of source driver circuits 120b. The plurality of source driver circuits 120b may send the bitwise error rate to the controller 140 through a separate pin. In addition, the controller 140 may adjust and send the voltage level of the data sent through the data transmission line EPI according to the error detection data BERT having the lowest bitwise error rate.

[0169] Fig.14 is a structural diagram showing the structure of a controller according to an embodiment.

[0170] refer to Fig.14 , the controller 140 may include a first transmitting circuit 141 , a first receiving circuit 142 , and a plurality of registers 143 . In addition, the controller 140 may include a counter 144 .

[0171] The first transmitting circuit 141 may provide a first locking signal LOCK1 , phase loop fixed data CFG, a video signal RGB, and control data CTRS through a locking input line LOCK IN and a data transmission line EPI different from each other.

[0172] The first receiving circuit 142 may be connected to the lock output line LOCK OUT to receive the second lock signal LOCK2 .

[0173] The plurality of registers 143 may store a plurality of phase loop fixed data CFG. In addition, the plurality of registers 143 may store a plurality of adjusted data. The plurality of phase loop fixed data CFG and the plurality of adjusted data stored in the plurality of registers 143 may be transmitted to the plurality of source driver circuits 120 through the first transmitting circuit 141. In addition, the delay time set for each source driver circuit 120b may be stored in the plurality of registers 143.

[0174] In addition, the controller 140 may use the counter 144 to count the number of transmitted data or the number of packets of received data.

[0175] Fig.15 is a block diagram illustrating a method of improving noise of a source driver circuit in a display device according to an embodiment.

[0176] refer to Fig.15 The source driver circuit 120 b may include a logic circuit 521 , a data receiving circuit 522 , and an analog-to-digital converter 523 .

[0177] The logic circuit 521 may be operated by receiving the second driving voltage VCCD. The voltage level of the second driving voltage VCCD may be a specific voltage such as 1.2V. However, it is not limited thereto. The logic circuit 521 may perform a logic operation in the source driver circuit 120b. The logic circuit 521 may include a shift register.

[0178] The data receiving circuit 522 can enable the source driver circuit 120b to receive data. The received data may include image signals RGB and control data CTRS. The data receiving circuit 522 may include a latch. The latch may receive the image signal RGB in series under the control of the logic circuit 521 including the shift register. In addition, the latch may output the stored image signal RGB in parallel.

[0179] The analog-to-digital converter 523 may convert the analog signal transmitted to the source driver circuit 120b into a digital signal. The analog-to-digital converter 523 may be connected to Figure 2 An analog-to-digital converter 220 for a pixel is shown.

[0180] The data receiving circuit 522 and the analog-to-digital converter 523 of the source driver circuit 120b as described above may operate by receiving the first driving power VCC. The voltage level of the first driving power VCC may be a specific voltage, for example, 1.8 V. However, it is not limited thereto.

[0181] The first regulator 524 and the second regulator 525 may be respectively connected to the data receiving circuit 522 and the analog-to-digital converter 523. For this reason, since power supplied to the data receiving circuit 522 and the analog-to-digital converter 523 is differentiated, noise is suppressed by one power supply, thereby reducing data transmission errors.

[0182] Since the first voltage regulator 524 and the second voltage regulator 525 are connected to the data receiving circuit 522 and the analog-to-digital converter 523, the voltage level of the first driving power source VCC may be as low as the data receiving circuit 522 and the analog-to-digital converter 523. That is, the voltage level of the power VCC supplied from the first driving power source is lowered by the first voltage regulator 524 and the second voltage regulator 525, and then may be supplied to the data receiving circuit 522 and the analog-to-digital converter 523. In this case, the voltage level of the second driving power source VCCD supplied to the logic circuit 521 may be the same as the voltage level of the voltage output from the first voltage regulator 524 and the second voltage regulator 525.

[0183] Fig.16 is a flowchart illustrating a method of driving a display device according to an embodiment.

[0184] refer to Figure 3 and Fig.16 , when power is supplied to the display device 100, a first lock signal LOCK1 having a plurality of pulse waveforms of a preset pattern may be provided to the plurality of source driver circuits 120b. In addition, in step S1600, a plurality of phase-loop fixed data CFG may be provided in parallel to the plurality of source driver circuits 120b. The plurality of source driver circuits 120b may receive the first lock signal LOCK1 and the plurality of phase-loop fixed data CFG from the controller 140.

[0185] As described above, a period in which the first locking signal LOCK1 and the plurality of phase-loop fixed data CFG are provided to the plurality of source driver circuits 120b may be referred to as the first optimization mode IPS. Figure 3 The source driver circuit 121b shown in FIG. 1 receives a signal from the controller 140. Figure 4 The first locking signal LOCK1 is shown in FIG. The first locking signal LOCK1 may be transmitted between the plurality of source driver circuits 120 b in a cascade manner.

[0186] In addition, if Figure 3 As shown, the controller 140 transmits the Figure 4 The phase loop fixed data CFG shown in FIG. 1 is transmitted to the plurality of source driver circuits 120 b. The controller 140 may provide the phase loop fixed data CFG to the plurality of source driver circuits 120 b through bit extension by increasing the number of bits.

[0187] For example, the second phase loop fixed data 2CFG is data in which the number of bits of the basic phase loop fixed data 1CFG including N bits (N is a natural number greater than 1) is expanded and each of the N bits included in the basic phase loop fixed data 1CFG is expanded to more than 2 bits (including at least one 0 and at least one 1). The second phase loop fixed data 2CFG can be provided as a differential signal. In addition, when the bit is expanded, the number of 1s and 0s included in the expanded bit of the second phase loop fixed data 2CFG can be the same.

[0188] At this time, the first locking signal LOCK1 may be transmitted by sequentially bypassing the plurality of source driver circuits 120b, and then the first locking signal LOCK1 is provided back to the timing control path 140. The first locking signal LOCK1 may be a signal input to the source driver circuit 121b. In addition, the signal output from the source driver circuit 126b receiving the first locking signal LOCK1 may be referred to as a second locking signal LOCK2.

[0189] In step S1600 , when a plurality of phase loop fixed data CFG are provided, a frequency and a phase of a clock restored by the plurality of phase loop fixed data CFG may be set in each of the plurality of source driver circuits 120 b .

[0190] The second optimization mode AEQ may be performed. In the second optimization mode AEQ, data corresponding to the second optimization mode AEQ may be provided. When a first lock signal LOCK1 having a preset voltage level is provided to a plurality of source driver circuits 120b, the second optimization mode AEQ may be performed. In the second optimization mode AEQ, a plurality of error detection data BERT may be provided to the plurality of source driver circuits 120b.

[0191] When the first lock signal LOCK1 is provided as a plurality of pulse waveforms having a preset pattern in the first optimization mode IPS, the preset voltage level of the first lock signal LOCK1 in the second optimization mode AEQ may be a voltage level of the first lock signal LOCK1 in a low state. The controller 140 may transmit the error detection data BERT to the plurality of source driver circuits 120b in parallel. The controller 140 may reduce the transmission error rate of the image signal RGB through one of the plurality of error detection data.

[0192] Then, the display mode DIAPLAY may be performed. In step S1620, in the display mode DIAPLAY, the internal clocks of the plurality of source driver circuits 120b may be restored, and the image signal RGB may be provided to each of the plurality of source driver circuits 120b.

[0193] When the first lock signal LOCK1 reaches the set first voltage, the display mode DISPLAY can be performed. In order to distinguish the voltage level of the first lock signal LOCK1 in the second optimization mode AEQ from the voltage level of the first lock signal LOCK1 in the display mode DISPLAY, the voltage level of the first lock signal LOCK1 in the second optimization mode AEQ can be referred to as a second voltage.

[0194] When the first lock signal LOCK1 is provided as a plurality of pulse waveforms having a set pattern in the first optimization mode IPS, the voltage level of the first voltage of the first lock signal LOCK1 in the display mode DISPLAY may be the voltage level in the high state of the first lock signal LOCK1. When the first lock signal LOCK1 reaches the set first voltage, the display mode DISPLAY is executed, and the internal clock of each of the plurality of source driver circuits 120b in the first optimization mode IPS may be restored to a frequency and phase corresponding to the phase loop fixed data CFG. In addition, the control data CTRS and the image signal RGB may be transmitted to the plurality of source driver circuits 120b. At this time, the voltage level of the data sent from the controller 140 to the plurality of source driver circuits 120b may be adjusted in response to the error detection data BERT set in the second optimization mode AEQ, and the control data CTRS and the image signal RGB having improved EYE characteristics may be transmitted to the plurality of source driver circuits 120b.

[0195] The display mode DISPLAY includes: a first display period Phase 1 for providing a clock training pattern CTP to the plurality of source driver circuits 120b; a second display period Phase 2 including a blank period for not transmitting signals and image signals RGB; a third display period Phase 3 for sending control data CTRS and a fourth display period Phase 4 for transmitting image signals RGB.

[0196] In addition, after a certain period of time after power is supplied, the driving frequency of the display device 100 increases. The display device 100 can be driven at a low frequency in the first optimization mode IPS, and can be driven at a higher frequency in the second optimization mode AEQ and the display mode DISPLAY than in the first optimization mode IPS.

[0197] The above description is given to enable any technician in the field to implement and use the technical ideas of the present disclosure, and the above description is provided in the context of specific applications and their requirements. It will be apparent to those skilled in the art that various modifications, additions and substitutions to the described embodiments will be apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and the accompanying drawings provide examples of the technical ideas of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiments shown, but should conform to the widest scope consistent with the claims. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical ideas within their equivalent ranges should be interpreted as included within the scope of the present disclosure.

Claims

1. A display device, include: a controller that operates in a first optimization mode and, after the first optimization mode, operates in a display mode; as well as a plurality of source driver circuits connected to and controlled by the controller, in, In the first optimization mode, The controller transmits a first locking signal having a plurality of pulse waveforms to a first source driver circuit among the plurality of source driver circuits, receives a second locking signal having a plurality of pulse waveforms from a last source driver circuit, and when receiving the second locking signal, transmits a plurality of phase-loop fixed data for recovering the frequency and phase of a clock used in the operation of each of the source driver circuits to each of the source driver circuits, wherein the last source driver circuit receives the first locking signal transmitted in a cascade manner from the first source driver circuit to the last source driver circuit, In the display mode, The controller transmits a first locking signal having a preset voltage level to the first source driver circuit, the first locking signal is transmitted in a cascade manner from the first source driver circuit to the last source driver circuit, the controller receives a second locking signal having multiple preset voltage levels from the last source driver circuit, and when receiving the second locking signal, the controller provides an image signal and control data to each of the source driver circuits.

2. The display device according to claim 1, in, The phase and the frequency of the clock used in each of the source driver circuits are fixed and correspond to each of the plurality of phase-loop fixed data, respectively.

3. The display device according to claim 1, in, The controller transmits the phase loop fixed data to the source driver circuit with a time difference based on a preset delay time in each of the source driver circuits.

4. The display device according to claim 1, in, The phase loop fixed data is obtained by expanding the bit number of basic phase loop fixed data including N bits, and each bit of the N bits included in the basic phase loop fixed data is expanded to data of more than 2 bits including at least one 0 and at least one 1, wherein N is a natural number greater than 1.

5. The display device according to claim 4, in, Each of the phase loop fixed data is a differential signal, and In each of the phase loop fixed data, the number of bits representing 1 and the number of bits representing 0 are the same.

6. The display device according to claim 4, in: In the first optimization mode, When the phase loop fixed data at the rising edge of the first lock signal is 0, each of the source driver circuits recognizes the basic phase loop fixed data as 0, and when the phase loop fixed data at the rising edge of the first lock signal is 1, each of the source driver circuits recognizes the basic phase loop fixed data as 1, or When the first locking signal is in a high state at the rising edge of the phase loop fixed data, each of the multiple source driver circuits recognizes the basic phase loop fixed data as 1, and when the first locking signal is in a low state at the rising edge of the phase loop fixed data, each of the multiple source driver circuits recognizes the basic phase loop fixed data as 0.

7. The display device according to claim 1, in, The display modes include: a first display period, wherein the controller provides a clock training pattern to the source driver circuit; a second display period, in which a signal for controlling the source driver circuit is not transmitted to the source driver circuit; a third display period, wherein the controller transmits the control data to the source driver circuit; and a fourth display period, wherein the controller outputs the image signal to the source driver circuit.

8. The display device according to claim 7, in, The second display period includes a first blank period for transmitting random data having a random pulse waveform and a second blank period for transmitting blank data having a preset pulse waveform.

9. The display device according to claim 8, in, The controller counts the number of packets of the blank data transmitted during the second blank period to recognize an end of the second display period.

10. The display device according to claim 1, in, A second optimization mode is further performed between the first optimization mode and the display mode, and In the second optimization mode, The controller transmits a plurality of transmission error detection data to each of the source driver circuits, and checks a transmission error rate of data according to the transmission error detection data when each of the source driver circuits receives the transmission error detection data from the controller.

11. The display device according to claim 10, in, The first locking signal has a preset voltage level in the second optimization mode, but has a voltage level different from that of the first locking signal in the display mode.

12. The display device according to claim 1, in, The controller includes a plurality of registers, and the plurality of registers are used to store basic phase loop fixed data required to generate the plurality of phase loop fixed data.

13. The display device according to claim 1, further comprising: include: a lock input line connecting the controller and a first source driver circuit among the plurality of source driver circuits; a lock output line connecting the controller and a last source driver circuit of the plurality of source driver circuits; as well as a cascade line connecting the plurality of source driver circuits, and Among them, the first locking signal is transmitted from the controller to the first source driver circuit through the locking input line, the first locking signal transmitted to the first source driver circuit is transmitted from the first source driver circuit to the last source driver circuit in a cascade manner through the cascade line, and the second locking signal is transmitted from the last source driver circuit to the controller through the locking output line.

14. The display device according to claim 1, further comprising a data transmission line, wherein the data transmission line connects the controller and each of the source driver circuits. in, The phase loop fixed data, the image signal, and the control data are transmitted from the controller to each of the source driver circuits through the data transmission line.

15. The display device according to claim 10, in, Each of the source driver circuits includes a latch circuit, and Wherein, the locking circuit comprises: a mode control logic circuit, the mode control logic circuit receiving the first lock signal to distinguish the first optimization mode, the second optimization mode and one of the display modes, and outputting an internal clock signal corresponding to one of the first optimization mode, the second optimization mode and the display mode; a clock and data recovery circuit that recovers the clock and sends a fixed phase and frequency to the mode control logic circuit; and A logic gate circuit calculates and outputs the internal clock signal and the first lock signal received from the mode control logic circuit.

16. The display device according to claim 1, in, Each of the source driver circuits includes a logic circuit, a data receiving circuit and an analog-to-digital converter.

17. The display device according to claim 16, in, Each of the source driver circuits further includes a first regulator connected to the data receiving circuit and a second regulator connected to the analog-to-digital converter.

18. A method for driving a display device, the display device comprising a controller and a plurality of source driver circuits connected to the controller, the driving method include: providing, from the controller, a first locking signal having a plurality of pulse waveforms of a preset pattern and a plurality of phase loop fixed data to a first source driver circuit among the plurality of source driver circuits; receiving a second lock signal having a plurality of pulse waveforms from a last source driver circuit of the plurality of source driver circuits; When the second lock signal is received, the frequency and phase of the data recovery clock are fixed by using a phase loop; setting, in each of the plurality of source driver circuits, a frequency and a phase of the clock recovered by fixing data using the phase loop; transmitting a first locking signal having a first preset voltage to the first source driver circuit; as well as When a second lock signal having the first preset voltage is received from a last source driver circuit among the plurality of source driver circuits, an image signal is transmitted to each of the source driver circuits.

19. The driving method according to claim 18, in, A delay time is set in each of the source driver circuits, and the phase loop fixed data is provided to each of the source driver circuits corresponding to the set delay time.

20. The driving method according to claim 18, further comprising: include: The controller provides a plurality of error detection data to the source driver circuit when the first lock signal has a second preset voltage different from the first preset voltage, and the controller reduces a transmission error rate of the image signal using one of the error detection data.

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