Polycrystalline fill shape and structure with polycrystalline isolation region under selective active device and related methods

Abstract

The present invention relates to structures having polycrystalline fill shapes and polycrystalline isolation regions below selective active devices and related methods. A structure includes a semiconductor-on-insulator (SOI) substrate, which includes a semiconductor substrate, a buried insulator layer located above the semiconductor substrate, and an SOI layer located above the buried insulator layer. The structure also includes a first active device and a second active device. At least one polycrystalline active region fill shape is located in the SOI layer. A polycrystalline isolation region is located in the semiconductor substrate below the buried insulator layer. The polycrystalline isolation region is located below the first active device but not below the second active device. The polycrystalline isolation region extends to different depths in the semiconductor substrate. The first and second active devices may include single crystal active regions, and a third polycrystalline active region may also be located in the SOI layer above the polycrystalline isolation region.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit (IC) structures, and more particularly to various structures including polycrystalline isolation regions located below polycrystalline active area fill shapes and selected active devices to reduce harmonic and parasitic losses in radio frequency (RF) devices in semiconductor-on-insulator (SOI) applications. Background Art

[0002] In integrated circuit (IC) structures, active devices are electrically isolated by dielectrics. The dielectrics can be provided in multiple locations. Dielectric trench isolation typically isolates the active devices laterally. In radio frequency (RF) device applications such as switches, power amplifiers, and other devices, additional isolation regions are advantageous for reducing harmonics and parasitic losses. One current approach is to form a semiconductor-on-insulator (SOI) substrate with a trap-rich polycrystalline isolation layer located between a buried insulator and the semiconductor substrate. This polycrystalline isolation layer ultimately lies below the RF active devices to provide additional isolation therefrom. In this case, the polycrystalline isolation layer has a uniform depth within the substrate. In another approach, after the devices are formed, polycrystalline isolation regions are formed in the semiconductor substrate (handle wafer) below the devices. The process etches trenches between adjacent active devices and through various layers, including gate and active area fill shapes, trench isolation, and buried insulator layers, to the underlying semiconductor substrate. The process then implants dopants into the semiconductor substrate to form poly isolation regions and refills the trenches with dielectric, leaving only the dielectric above the poly isolation regions. This process is expensive and time-consuming, and carries a high risk of defects in active devices. Summary of the Invention

[0003] One aspect of the present invention relates to a structure comprising: a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer located above the semiconductor substrate, and an SOI layer located above the buried insulator layer; at least one polycrystalline active area fill shape located in the SOI layer; a first active device and a second active device located in the SOI layer; and a polycrystalline isolation region located in the semiconductor substrate below the buried insulator layer, wherein the polycrystalline isolation region is located below the first active device but not below the second active device.

[0004] In another aspect, the present disclosure provides a structure comprising: a semiconductor-on-insulator (SOI) substrate comprising a semiconductor substrate, a buried insulator layer located above the semiconductor substrate, and an SOI layer located above the buried insulator layer; at least one polycrystalline active area fill shape located in the SOI layer; a first active device, a second active device, and a third active device located in the SOI layer; and a polycrystalline isolation region located in the semiconductor substrate below the buried insulator layer, wherein the polycrystalline isolation region is located below the first active device and the third active device, but not below the second active device.

[0005] Another aspect relates to a method comprising: forming a first single crystal active area, a second single crystal active area, and at least one single crystal active area fill shape in a semiconductor-on-insulator (SOI) layer, the semiconductor-on-insulator layer being located above a buried insulator layer, the buried insulator layer being located above a single crystal semiconductor substrate, wherein each single crystal active area fill shape includes a cap located thereover; forming a mask comprising an opening exposing the at least one single crystal active area fill shape and the first single crystal active area in the SOI layer; converting each of the at least one single crystal active area fill shape into a corresponding polycrystalline active area fill shape, converting the first single crystal active area into a first polycrystalline active area, and converting an upper portion of the single crystal semiconductor substrate into a polycrystalline isolation region; performing an anneal to reform the first polycrystalline active area into a first reformed single crystal active area; and removing the mask.

[0006] The foregoing and other features of the present disclosure will become apparent from the following more particular description of embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals represent like elements, and wherein:

[0008] Figure 1 A cross-sectional view showing a preliminary structure for a method according to an embodiment of the present disclosure.

[0009] Figure 2 A cross-sectional view illustrating forming a mask that exposes selected single-crystalline active regions to remove a cap over the selected single-crystalline active regions according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of a structure including a selected single crystalline active region with the cap removed is shown in accordance with an embodiment of the present disclosure.

[0011] Figure 4A cross-sectional view of forming a mask and implanting into a single crystal fill shape, a single crystal active area, and a semiconductor substrate to form a polycrystalline fill shape, an active area, and an isolation area according to an embodiment of the present disclosure is shown.

[0012] Figure 5 A cross-sectional view of reforming a single crystal active region from a polycrystalline active region according to an embodiment of the present disclosure is shown.

[0013] Figure 6 A cross-sectional view of a structure including poly isolation regions underlying poly fill shapes and selected active devices is shown according to an embodiment of the present disclosure.

[0014] Figure 7 A cross-sectional view of a structure including poly isolation regions beneath poly fill shapes and selected active devices and having alternating dopants in the fill shapes is shown according to other embodiments of the present disclosure.

[0015] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, like reference numerals represent like elements between the drawings. DETAILED DESCRIPTION

[0016] In the following description, reference is made to the accompanying drawings which form a part of the present invention and which illustrate, by way of illustration, specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Therefore, the following description is illustrative only.

[0017] It will be understood that when an element, such as a layer, region, or semiconductor substrate, is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0018] References in the specification to "one embodiment" or "an embodiment" of the present disclosure and other variations thereof mean that the particular features, structures, characteristics, etc. described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing throughout the specification do not necessarily refer to the same embodiment. It should be understood that the use of any of " / ", "and / or", and "at least one" in the contexts of, for example, "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As another example, in the case of "A, B, and / or C" and "at least one of A, B, and C," these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to one of ordinary skill in the art, this scenario can be extended to many of the listed options.

[0019] Embodiments of the present disclosure provide structures for semiconductor-on-insulator (SOI) substrates. Such structures can include polycrystalline isolation regions for reducing harmonics and parasitic losses in, for example, radio frequency (RF) applications. The SOI substrate includes a semiconductor substrate, a buried insulator layer located above the semiconductor substrate, and an SOI layer located above the buried insulator layer. According to embodiments of the present disclosure, polycrystalline isolation regions are formed by implanting a material through a single-crystal active region fill shape, selected single-crystal active regions, and a buried insulator layer into a single-crystal semiconductor substrate below the buried insulator layer, followed by a subsequent thermal cycle. The implantation converts the single-crystal material into a crystallographically disordered material that, after a subsequent thermal cycle, forms a polycrystalline active region fill shape, a polycrystalline active region, and a polycrystalline isolation region in the semiconductor substrate. Thus, this process allows for the formation of polycrystalline isolation regions in a semiconductor substrate without having to etch trenches, implant, and refill the trenches, and without having to remove the active region fill shape in the SOI layer. This process also eliminates the expense of manufacturing an SOI substrate with trap-rich isolation regions. The selected polycrystalline active regions can be converted back to single crystal active regions by an annealing step, thereby selectively providing single crystal and / or polycrystalline active regions / devices above the polycrystalline isolation regions. The polycrystalline isolation regions can be located below the first active device but not below the second active device. The first active device and the second active device can include single crystal active regions, and a third polycrystalline active region can also be located in the SOI layer above the polycrystalline isolation regions. In the case where multiple spaced-apart active regions fill the shape and / or the active regions are implanted in place, the polycrystalline isolation regions extend to different depths in the semiconductor substrate.

[0020] With reference to the accompanying drawings, embodiments of the method according to the present disclosure will now be described. Figure 1 1 shows a cross-sectional view of a preliminary structure 100. The preliminary structure 100 includes a semiconductor-on-insulator (SOI) substrate 102 including a semiconductor substrate 104, a buried insulator layer 106 located above the semiconductor substrate 104, and an SOI layer 108 located above the buried insulator layer 106. The semiconductor substrate 104 and the SOI layer 108 include single crystal materials such as, but not limited to, silicon, germanium, silicon germanium, silicon carbide, and a material consisting essentially of a silicon having the chemical formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 Those composed of one or more III-V compound semiconductors of a defined composition, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions, which are respectively greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 is the total relative molar amount). Other suitable substrates include those with a composition of Zn A1Cd A2 Se B1 Te B2 A II-VI compound semiconductor, wherein A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1+A2+B1+B2=1 (1 being the total molar amount). Furthermore, part or all of the semiconductor material may be strained. For example, the SOI layer 108 may be strained.

[0021] The buried insulator layer 106 may include any suitable dielectric material, including but not limited to: carbon-doped silicon dioxide materials; fluorinated silicate glass (FSG); organic polymeric thermoset materials; silicon oxycarbide; SiCOH dielectrics; fluorine-doped silicon oxide; spin-on glass; silsesquioxanes, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB)-based polymer dielectrics; and any silicon-containing low-k dielectric. Examples of spin-on low-k films with SiCOH-type compositions using silsesquioxane chemistry include HOSP. TM (available from Honeywell), JSR 5109 and 5108 (available from Japan Synthetic Rubber), Zirkon TM (available from Shipley Microelectronics, a division of Rohm and Haas), and porous low-k (ELk) materials (available from Applied Materials). Examples of carbon-doped silica materials or organosilanes include BlackDiamond TM (available from Applied Materials) and Coral TM (Available from Lam Research). An example of a HSQ material is FOx TM (Available from Dow Corning.) In one embodiment, the buried insulator layer 106 comprises silicon oxide. The SOI substrate 102 may be formed using any now known or later developed semiconductor fabrication process.

[0022] The SOI layer 108 is segmented to form therein a plurality of single crystal active area segments 110. Although a specific location of each active area segment 110 will be described, it is apparent that other locations are possible. Figure 1The first device active region 112 is formed to one side of at least one single crystal active region filling shape 118 (hereinafter referred to as "single crystal filling shape 118") and the second device active region 114 is formed to the opposite side of the single crystal filling shape 118. Therefore, the SOI layer 108 includes the first device active region 112 and the second device active region 114. In addition, Figure 1 A third active region 116 is shown optionally formed in the SOI layer 108, for example, between the first device active region 112 and the single crystal fill shape 118. As will be described, the third active device region 116 may comprise a polycrystalline material, such as polysilicon. Each of the active regions 112, 114, 116 may ultimately be used to form an active device. The active region segment 110 may be formed in the SOI layer 108 using any now known or later developed semiconductor manufacturing technique (e.g., depositing a blanket single crystal SOI layer 108 and patterning / etching the SOI layer).

[0023] Etching generally refers to the removal of material from a substrate (or structures formed on it) and is typically performed using a mask in place to selectively remove material from specific areas of the substrate while leaving material in other areas unaffected. There are two common types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., an acid) that is chosen for its ability to selectively dissolve a given material (e.g., an oxide) while leaving another material (e.g., polysilicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically etches homogeneous materials (e.g., oxides) isotropically, but wet etching can also anisotropically etch single-crystalline materials (e.g., silicon wafers). Dry etching can be performed using plasma. Plasma systems can operate in several modes by adjusting plasma parameters. Conventional plasma etching generates neutrally charged, high-energy radicals that react on the wafer surface. Because the neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputter etching bombards the wafer with high-energy ions of a noble gas that approach the wafer from roughly one direction, making the process highly anisotropic. Reactive ion etching (RIE), operating under conditions between sputtering and plasma etching, can be used to create deep, narrow features such as STI trenches.

[0024] The SOI layer 108 may also include active area segments 110 (two are shown, but there may be more or fewer) in the form of single-crystal fill shapes 118. The active areas 112, 114, 116 (and the single-crystal fill shapes 118) are electrically isolated from each other by one or more trench isolations 120 (e.g., shallow trench isolations). The single-crystal fill shapes 118 are positioned in the active area layer (i.e., SOI layer 108) to improve pattern density (active and fill) to aid in patterning of the active layer (e.g., endpoint detection, slope, critical dimension control, etc.) and planarization of the trench isolations 120 (e.g., to reduce dishing that may occur in the dielectric of the trench isolations 120 during planarization). Dishing can cause a number of problems in subsequent processing, such as misalignment, underfill, non-planarity, etc. The single-crystal fill shapes 118 may have any lateral shape necessary to provide the desired increased density.

[0025] The trench isolations 120 include trenches etched through the SOI layer 108 and filled with an insulating material, such as an oxide, to isolate a region of the SOI layer 108 from adjacent regions thereof (e.g., active regions 112, 114, 116 and adjacent single crystal fill shape 118). Each trench isolation 120 may be formed of any now known or later developed material for providing electrical insulation, and may include, by way of example, silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon oxycarbon (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, a carbon (C)-doped oxide (i.e., an organosilicate) including atoms of silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H), thermosetting polyarylene ether, a spin-on silicon-carbon-containing polymer material, near frictionless carbon (NFC), or layers thereof. In one non-limiting example, the trench isolation 120 includes the same material as the buried insulator layer 106 .

[0026] The preliminary structure 100 also includes a cap 122 located above each active area segment 110. The cap 122 may include a harder material than the trench isolation 120 material to protect the active area segment 110 during subsequent processing. In one non-limiting example, the cap 122 may include a silicon oxide layer 124 located below a silicon nitride layer 125.

[0027] Figures 2 to 6 A cross-sectional view of a method according to one embodiment of the present disclosure is shown. As will be described, embodiments of the present disclosure can selectively form single crystal device active regions and polycrystalline device active regions with or without underlying polycrystalline isolation regions. Figure 2 1 shows a cross-sectional view of a mask 126 formed over the preliminary structure 100. The mask 126 is used to form the polysilicon isolation regions 138 ( Figure 6 ) above the single crystal device active area 112 (as shown on the far left in the figure). The specific active areas 116 covered by the mask 126 will eventually become polycrystalline, and the specific active areas 114 covered by the mask will remain single crystal. Mask 126 can include any mask material now known or later developed. Common masking materials are photoresists (resists) and nitrides. Nitrides are generally considered to be "hard masks". The mask may include a developable organic planarization layer (OPL) located on the layer to be etched, a developable anti-reflective coating (ARC) located on the developable OPL, and a photoresist mask layer located on the developable ARC layer. Mask 126 includes openings 128. Openings 128 expose the polysilicon isolation regions 138 ( Figure 6 ). Here, the area above the first single crystal device active region 112 is exposed and, as noted, will ultimately include the polycrystalline isolation region 138 thereunder. Areas above other active regions may also be exposed. An etch is performed using mask 126 to remove the cap 122 above the first single crystal device active region 112. The cap 122 above the first single crystal device active region 112 may be removed by, for example, a wet etch suitable for the cap material.

[0028] Figure 3 A cross-sectional view of the structure is shown after removal of the mask 126. The mask 126 may be removed using any suitable removal process, such as a wet etch appropriate for the mask material.

[0029] Figure 4 1 shows a cross-sectional view of the structure after forming a mask 130 including openings 132. Mask 130 is used to expose areas above those active area segments 110 below which polycrystalline isolation regions 138 will be formed. In the example shown, openings 132 expose areas above the single-crystal active area fill shape 118 and the first single-crystal active region 112 in the SOI layer 108. Openings 132 also expose areas above the optional third single-crystal active region 116 in the SOI layer 108, i.e., after forming mask 130 ( Figure 1 ) before forming the third single crystal active region 116. The opening 132 may also expose areas above other active device region segments 110 (not shown) below that require polycrystalline isolation regions 138. The mask 130 may cover the second device active region 114 in the SOI layer 108 and any other active device region segments 110 (not shown) below that do not require polycrystalline isolation regions 138.

[0030] Figure 4 and Figure 5Collectively, the transformation of each single crystal fill shape 118 into a corresponding polycrystalline active area fill shape 133 , the transformation of the first single crystal active area 112 into a first polycrystalline active area 134 , and the transformation of an upper portion 136 of the single crystal semiconductor substrate 104 into a polycrystalline isolation region 138 are shown. Figure 4 shows the dopant implantation ( Figure 4 ) into the exposed active area segment 110 and other areas. As shown, dopants are implanted into the single crystal fill shape 118, the first single crystal active area 112 and the single crystal semiconductor substrate 104. If a third single crystal active area 116 is provided, the implantation also implants dopants into the third single crystal active area 116. Implantation or doping is the process of introducing impurities (dopants) into a material. An ion implanter is typically used for the actual implantation. An inert carrier gas such as nitrogen is typically used to introduce the impurity source (dopant). The dose and energy level suitable for a particular SOI substrate 102 and the desired doping can be specified, and / or the resulting doping level can be specified. The amount of doping can be determined by the amount of doping per square centimeter (cm 2 ) and the energy level (specified in keV (kiloelectron volts)) to give the dose per cubic centimeter (cm 3 ) atomic number doping level (concentration in the substrate). Atomic number is usually specified in exponential notation, where a number like "3E15" means 3 times 10 to the 15th power, or "3" followed by 15 zeros (3,000,000,000,000,000). From this perspective, per cubic centimeter (cm 3 ) of water contains approximately 1E23 (100,000,000,000,000,000,000) atoms of hydrogen and oxygen. An example of doping is about 1E12 to 1E13 atoms / cm 2 The dose is between 40 and 80 keV with argon (Ar) implantation to generate 1E17 to 1E18 atoms / cm 3 In this case, if Figure 4 As shown, the implant is performed so as to damage the single crystal material to which it is applied. Figure 5 One or more thermal cycles are shown, such as anneals indicated by curved arrows, which reorder the damaged and disordered crystalline material into polycrystalline material. The thermal cycles may include one or more intentionally added recrystallization anneals shortly after implantation, or typical high temperature (>600°C) processes associated with semiconductor manufacturing. In this manner, the process transforms each single crystal fill shape 118 into a corresponding polycrystalline active area fill shape 133, transforms the first single crystal active area 112 into a first polycrystalline active area 134, and transforms the upper portion 136 of the single crystal semiconductor substrate 104 into a polycrystalline isolation region 138. If a third single crystal active area 116 ( Figure 3), the implantation also transforms the third single crystal active region 116 into a second polycrystalline active region 140. The implanted dopant may include any material capable of producing a polycrystalline material, including but not limited to: germanium (Ge); a noble gas such as argon (Ar) or xenon (Xe); or a combination of the aforementioned materials, such as Ge-Ar or Ge-Xe.

[0031] like Figure 4 As shown, the implant extends through the buried insulator layer 106 and into the single crystal semiconductor substrate 104, i.e., where it is not covered by the mask 130. Since the mask 130 covers the second device active region 114, the polycrystalline isolation region 138 is not formed in the active device 142 ( Figure 7 ) below. Cap 122, single crystal filling shape 118 ( Figure 3 )、Active region 112( Figure 3 ) and the exposed area above the third single crystal active region 116 ( Figure 3) (where the third single crystal active region 116 is provided) affects the formation of the polycrystalline isolation region 138 (i.e., by affecting the penetration depth of the implant). For example, the polycrystalline active region fill shape 133 (hereinafter referred to as "polycrystalline fill shape 133") can be laterally aligned with the polycrystalline isolation region 138 on one end (the right side as shown). That is, the polycrystalline isolation region 138 extends laterally to the same distance from that side of the outermost polycrystalline fill shape 133. In addition, the width W1 of the polycrystalline isolation region 138 is greater than the width W2 of the polycrystalline fill shape 133 (i.e., from the outermost edge of the outermost fill shape to the outermost edge of the opposite outermost fill shape). Two or more polycrystalline (active region) fill shapes 133 (as shown) with caps 122 thereon can have a space 144 therebetween. In this case, the transition creates a unique shape in the polycrystalline isolation region 138 because the polycrystalline fill shape 133 with the cap 122 changes the degree of penetration of the dopant at its location. As shown, the transformation results in the transformation of the upper portion 136 of the single crystal semiconductor substrate 104 into a polycrystalline isolation region 138 that extends to a first depth D1 in the semiconductor substrate 104. The polycrystalline isolation region 134 can be located at a first position that is laterally aligned with the space 144 between the two or more polycrystalline fill shapes 133. The polycrystalline isolation region 134 can extend to a second depth D2 in the semiconductor substrate 104 at a second position that is not laterally aligned with the space 144 between the two or more polycrystalline fill shapes 133. As shown, the first depth D1 is greater than the second depth D2. Therefore, the polycrystalline isolation region 138 can include a deeper region 150 and a shallower region 152, which is caused by the positioning of the structure with or without the cap 122. In one non-limiting example shown, the polycrystalline isolation region 138 includes a portion having a sawtooth pattern with alternating deeper regions 150 and shallower regions 152. Similar to the fill shape 118 ( Figure 3 ), in the case of setting the third single crystal active region 116, the third single crystal active region 116 including the cap 122 will also affect the penetration of dopants. As shown in the figure, the polycrystalline isolation region 138 is below the second polycrystalline active region 140, that is, below the third single crystal active region 116 ( Figure 3 ) has a shallower region 152 (second depth D2) below. In contrast, the first polycrystalline active region 134 ( Figure 3 ) so that the poly isolation region 138 below it has a deeper region 150 (first depth D1). Combined with the control of implantation, thermal cycling and dopant selection, the active regions 112, 116 ( Figure 3 ) and the exposed area above the single crystal filling shape 118 ( Figure 3) can be shaped, spaced and / or positioned in any manner to produce poly isolation regions 138 having any desired shape, depth and / or width. In this manner, the isolation characteristics of the poly isolation regions 138 can be customized.

[0032] like Figure 5 As shown, at least one of the thermal cycles includes a thermal cycle sufficient to heat the first polycrystalline active region 134 ( Figure 4 ) is annealed (curved arrow) to reform the first reformed single crystalline active region 160. That is, the annealing reforms the single crystalline material. The annealing process may be an additional anneal or may include a conventional anneal used during semiconductor manufacturing, which has an increased effect on the first polycrystalline active region 134 since the first polycrystalline active region 134 is decapped. The annealing (thermal cycle) may have any suitable temperature and duration required to recrystallize the material used to the desired degree (i.e., beyond the polycrystalline state of the other active region segments 110 covered by the cap 122). Figure 5 Also shown is the removal of the mask 130 ( Figure 4 ). The mask 130 may be removed using any suitable removal process (eg, a wet etch appropriate to the mask material).

[0033] Figure 6A cross-sectional view of structure 170 according to an embodiment of the present disclosure is shown, i.e., after subsequent conventional device formation. Subsequent processing may include any now known or later developed front-end-of-the-line (FEOL) semiconductor fabrication process to form devices, such as first active device 172, second active device 142, and third active device 174. For example, one subsequent process may include removing cap 122 above active area segment 110 in SOI layer 108, for example, using any suitable etching process. Subsequent processing (only partially shown) may also include any middle-of-the-line (MOL) or back-end-of-the-line (BEOL) processing, such as for interconnects. Processing may include, for example, removing the cap, forming source / drain electrodes, forming gate 176 (forming an active gate and a dummy fill gate above active area fill shape 133 via a gate-first or replacement metal gate process), forming an interlayer dielectric, and forming interconnects (the last not shown). The formation of active gate 176 above selected active area segment 110 results in the formation of a number of active devices. For example, a first active device 172 may be formed in the first reformed single-crystal active region 160. The first active device 172 may take the form of a radio frequency (RF) device, such as, but not limited to, a switch or a power amplifier, or another (reformed) single-crystal (body) active device requiring a polycrystalline isolation region 138 thereunder. A second active device 142 may be formed in the second single-crystal active region 114. The second active device 142 may take the form of, for example, a complementary metal oxide semiconductor (CMOS) device, such as, but not limited to, a transistor, or another single-crystal active device requiring no polycrystalline isolation region 138 thereunder. The polycrystalline isolation region 138 is located below the first active device 172 but not below the second active device 142. If a third active device 174 is provided, the third active device 174 may include a radio frequency (RF) device, such as, but not limited to, a polycrystalline RF switch, or another polycrystalline active device requiring a polycrystalline isolation region 138 thereunder. The polycrystalline isolation region 138 is located below the third active device 174. Thus, the poly isolation region 138 may be selectively positioned to provide additional harmonic isolation for the first and third active devices 172 , 174 without providing additional harmonic isolation for the second active device 142 .

[0034] like Figure 6As shown, according to one embodiment, structure 170 includes SOI substrate 102, as described herein. Structure 170 also includes polycrystalline fill shape 133 located in SOI layer 108, and polycrystalline isolation region 138 located in semiconductor substrate 104 below buried insulator layer 106. Structure 170 also includes a first active device 172 and a second active device 142 located in SOI layer 108. Polycrystalline isolation region 138 is located below first active device 172, but not below second active device 142. First active device 171 and second active device 142 include single crystalline active regions 160 and 114, respectively. Structure 170 may also optionally include a third active device 174, for example, located in SOI layer 108 between first active device 172 and polycrystalline fill shape 133, including polycrystalline active region 140. Polycrystalline isolation region 138 may be located below third active device 174. Thus, the poly isolation region 138 may be located under the first active device 172 and the third active device 174 , but not under the second active device 142 .

[0035] It can be understood that the mask 130 ( Figure 4 ) can be used to provide polycrystalline isolation regions 138 beneath any desired active device. Thus, the polycrystalline isolation regions 138 can provide RF isolation for any selected sensitive device structures (e.g., RF switches, power amplifiers, etc.) without requiring aggressive etch / implant and refill processes, thereby significantly reducing complexity, defect risk, and cost. The polycrystalline isolation regions 138 also reduce the risk of defects by reducing the size of the conventional single crystal active area fill shape 118 ( Figure 2 ) and provides an improved passive (inductor, transmission line, metal-insulator-metal (MIM) capacitor) quality (Q) factor. As noted, the first active device 172 can take the form of a radio frequency (RF) device, such as, but not limited to, a switch or power amplifier, or another (reformed) single crystal active device requiring a polycrystalline isolation region 138 thereunder. The second active device 142 can take the form of, for example, a complementary metal oxide semiconductor (CMOS) device, such as, but not limited to, a transistor, or another single crystal active device requiring no polycrystalline isolation region 138 thereunder. And, where a third active device 174 is provided, the third active device 174 can include a radio frequency (RF) device, such as, but not limited to, a polycrystalline RF switch, or another polycrystalline active device requiring a polycrystalline isolation region 138 thereunder.

[0036] Structure 170 also has a poly fill shape 133 that is laterally aligned with one side (the right side as shown) above a poly isolation region 138. In contrast to conventional SOI substrates that have a uniform thickness of a trap-rich poly isolation layer between the buried insulator and the semiconductor substrate, poly isolation region 138 is not located under all active devices. Instead, it is located under selected active devices, such as 172, 174 ( Figure 6 ) below. Figure 4 As shown, the width W1 of the poly isolation region 138 is greater than the width W2 of the poly fill shape 133. In the case where two or more poly fill shapes 133 have a space 144 located therebetween, the poly isolation region 138 extends to a first depth D1 in the semiconductor substrate 104 at a first location laterally aligned with the space 144 between the two or more poly fill regions 133, and extends to a second depth D2 in the semiconductor substrate 104 at a second location not laterally aligned with the space 144 between the two or more poly active region fill shapes 133. As indicated, the first depth D1 is greater than the second depth D2. In the case where the structure 170 includes a third active device 174 located in the SOI layer 108, the poly isolation region 138 can have a second depth D2 below the third active device (i.e., because the active region 140 blocks implant penetration). In a non-limiting example, the poly fill shapes 133 and the poly isolation region 138 can include any of the dopants described herein, such as argon, xenon, germanium, or combinations thereof.

[0037] Figure 7 A cross-sectional view of another embodiment is shown in which two or more polycrystalline active area fill shapes 133 have alternating opposite p-type and n-type doping. The doping can be applied in any manner now known or later developed, for example, by ion implantation during source / drain formation. In a non-limiting example, p-type dopants can include boron (B), indium (In); n-type dopants can include: phosphorus (P), arsenic (As), antimony (Sb). Alternating doping provides harmonic improvement by alternating S / D implant types between fill shapes. In any case, each polycrystalline fill shape 133 is separated by a dielectric, thereby creating alternating islands of p-type and n-type doping. In other embodiments, each polycrystalline fill shape 133 can include its own p / n junction, thereby forming a p / n junction island. Dopants can be formed in the fill shapes in any manner now known or later developed (for example, masked ion implantation).

[0038] The above-described method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0039] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or the groups they constitute. "Optional" or "optionally" means that the event or situation described subsequently may or may not occur, and that the description includes situations where the event occurs and situations where the event does not occur.

[0040] Approximate language, as used throughout the specification and claims, may be used to modify any quantitative representation that is permissible to vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by one or more terms such as "about," "approximately," and "substantially" is not limited to the precise value specified. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Herein and throughout the specification and claims, range limitations may be combined and / or interchanged, such ranges are identified and include all subranges contained therein unless the context or language indicates otherwise. "Approximately" applied to a particular value of a range applies to both values ​​and may indicate + / - 10% of the stated value unless otherwise dependent upon the precision of the instrument used to measure the value.

[0041] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular use contemplated.

Claims

1. An integrated circuit structure comprising: A semiconductor-on-insulator (SOI) substrate comprising a semiconductor substrate, a buried insulator layer located above the semiconductor substrate, and an SOI layer located above the buried insulator layer; at least one polycrystalline active area filling shape located in the SOI layer; a first active device and a second active device located in the SOI layer; as well as a polycrystalline isolation region in the semiconductor substrate below the buried insulator layer, The polycrystalline isolation region is located below the first active device but not below the second active device. 2 . The integrated circuit structure of claim 1 , wherein the first active device comprises a radio frequency (RF) device, and the second active device comprises a complementary metal oxide semiconductor (CMOS) device.

3. The integrated circuit structure of claim 1, wherein each of the first active device and the second active device comprises a single crystalline active region.

4. The integrated circuit structure of claim 1, further comprising a third active device located in the SOI layer between the first active device and the at least one poly active area fill shape, wherein the poly isolation region is located below the third active device. 5 . The integrated circuit structure of claim 4 , wherein each of the first active device and the second active device comprises a single crystalline active region, and the third active device comprises a polycrystalline active region.

6. The integrated circuit structure of claim 1, wherein a width of the poly isolation region is greater than a width of the at least one poly active area fill shape.

7. The integrated circuit structure of claim 1 , wherein the at least one polycrystalline active area fill shape comprises two or more polycrystalline active area fill shapes with a space therebetween, and wherein the polycrystalline isolation region extends to a first depth in the semiconductor substrate at a first position that is laterally aligned with the space between the two or more polycrystalline active area fill shapes, and extends to a second depth in the semiconductor substrate at a second position that is not laterally aligned with the space between the two or more polycrystalline active area fill shapes, wherein the first depth is greater than the second depth.

8. The integrated circuit structure of claim 7, wherein the two or more polycrystalline active area fill shapes have alternating opposite p-type and n-type doping. 9 . The integrated circuit structure of claim 7 , further comprising a third active device in the SOI layer, wherein the poly isolation region has the second depth below the third active device.

10. An integrated circuit structure comprising: A semiconductor-on-insulator (SOI) substrate comprising a semiconductor substrate, a buried insulator layer located above the semiconductor substrate, and an SOI layer located above the buried insulator layer; at least one polycrystalline active area filling shape located in the SOI layer; a first active device, a second active device, and a third active device located in the SOI layer; as well as a polycrystalline isolation region in the semiconductor substrate below the buried insulator layer, The polycrystalline isolation region is located below the first active device and the third active device, but is not located below the second active device.

11. The integrated circuit structure of claim 10, wherein each of the first active device and the second active device comprises a single crystalline active region, and the third active device comprises a polycrystalline active region.

12. The integrated circuit structure of claim 10, wherein a width of the poly isolation region is greater than a width of the at least one poly active area fill shape.

13. The integrated circuit structure of claim 10 , wherein the at least one polycrystalline active area fill shape comprises two or more polycrystalline active area fill shapes with a space therebetween, and wherein the polycrystalline isolation region extends to a first depth in the semiconductor substrate at a first position that is laterally aligned with the space between the two or more polycrystalline active area fill shapes, and extends to a second depth in the semiconductor substrate at a second position that is not laterally aligned with the space between the two or more polycrystalline active area fill shapes, wherein the first depth is greater than the second depth.

14. The integrated circuit structure of claim 13, wherein the two or more polycrystalline active area fill shapes have alternating opposite p-type and n-type doping. 15 . The integrated circuit structure of claim 13 , wherein the poly isolation region has the second depth below the third active device.

16. A method for manufacturing an integrated circuit, comprising: forming a first single crystal active area, a second single crystal active area, and at least one single crystal active area fill shape in a semiconductor-on-insulator (SOI) layer, the SOI layer being over a buried insulator layer over a single crystal semiconductor substrate, wherein each single crystal active area fill shape includes a cap thereover; forming a mask including an opening that exposes the at least one single crystal active region filling shape and the first single crystal active region in the SOI layer; converting each of the at least one single crystal active area fill shape into a corresponding polycrystalline active area fill shape, converting the first single crystal active area into a first polycrystalline active area, and converting an upper portion of the single crystal semiconductor substrate into a polycrystalline isolation region; annealing to reform the first polycrystalline active region into a first reformed single crystalline active region; as well as The mask is removed. 17 . The method of claim 16 , wherein forming the first single crystalline active region comprises forming a cap thereover, and further comprising removing the cap from over the first single crystalline active region before forming the mask.

18. The method of claim 16, further comprising forming a first active device in the first reformed single crystalline active region and forming a second active device in the second single crystalline active region, wherein the polycrystalline isolation region is located below the first active device but not below the second active device.

19. The method of claim 16, further comprising: forming a third single crystal active region in the SOI layer before forming the mask, wherein the mask exposes an area above the third single crystal active region, and the transforming transforms the third single crystal active region into a polycrystalline active region; as well as After removing the mask, a third active device is formed in the polycrystalline active region, wherein the polycrystalline isolation region is located below the third active device.

20. The method of claim 16 , wherein the at least one polycrystalline active area fill shape comprises two or more polycrystalline active area fill shapes having a space therebetween, and wherein the transforming transforms the upper portion of the single crystalline semiconductor substrate so that the polycrystalline isolation region extends to a first depth in the semiconductor substrate at a first position that is laterally aligned with the space between the two or more polycrystalline active area fill shapes, and extends to a second depth in the semiconductor substrate at a second position that is not laterally aligned with the space between the two or more polycrystalline active area fill shapes, wherein the first depth is greater than the second depth.

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