Analog-to-digital converter with auto-zero residual amplifier circuit

Abstract

The present disclosure relates to an analog-to-digital converter with an auto-zero residual amplifier circuit. Some examples of analog-to-digital converters (ADCs) are disclosed herein, which can perform auto-zeroing by amplifying a signal to improve the signal-to-noise ratio. The ADC can generate a first digital code representing an analog input signal and a second digital code based on a residual from the first digital code, and the first digital code and the second digital code can be combined to generate a digital output code representing the analog input signal. The ADC can generate the second digital code using a first observation value and a second observation value of an analog residual value representing the residual.

Description

Technical Field

[0001] The present disclosure relates generally to the field of electronic circuits, and more particularly, but not exclusively, to a system and method for data conversion. Background Art

[0002] Analog signals and / or values ​​may be generated in various circuit elements, such as signal generators, sensors, and antennas. However, there may be many situations where having digital signals or values ​​may be beneficial, such as for processing or storing signals or values. In order to take advantage of the advantages of having digital signals or values ​​when generating analog signals or values, analog-to-digital converters (ADCs) have been developed to convert analog signals or values ​​into digital signals or values.

[0003] A signal may be a time-based sequence of values. A digital value may be represented by a code. The name of a code (e.g., CODE1) may refer to the digital value represented by the code. Some (but not all) digital values ​​may be represented by a code using binary weighted encoding. The resolution of a digital value or code represented in multiple bits may be referred to as binary weighted encoding, regardless of the manner in which it is physically encoded.

[0004] In many electronic applications, analog input values ​​are converted to digital output values ​​(e.g., for further digital processing or storage). For example, in precision measurement systems, electronic devices are equipped with one or more sensors to perform measurements, and these sensors can generate analog values. The analog values ​​can be provided as input to an ADC to generate digital output values ​​for further processing or storage.

[0005] ADCs can be found in many places such as broadband communication systems, automatic test equipment, audio systems, vehicles, factory automation systems, etc. ADCs can convert analog electrical values ​​that represent real-world phenomena such as light, sound, temperature, flow, or pressure. Designing ADCs is a very important task because each application may have different requirements in terms of speed, performance, power consumption, cost, and size. As the number of applications that require ADCs grows, the need for accurate and reliable conversion performance also grows.

[0006] Some applications may require precise and accurate conversion of analog values, thus requiring a precision ADC (precision means accurate and / or accurate). Specifications required for a precision ADC may include low noise and a small and stable offset. A constant zero offset may be an ideal situation. The design goal of ADCs and other circuits may be a constant zero offset, but defects in manufacturing processes, mismatches of nominally identical semiconductor devices, atomic-level charge migration, etc. may make the circuit offset potentially non-zero, and it may change with changes in parameters such as time, temperature, and / or supply voltage. An automatic zero (AZ) circuit may be used in a precision ADC to stabilize the potential non-zero offset (i.e., reduce the potential non-zero offset and / or substantially prevent changes in the potential non-zero offset). The offset of the automatic zero circuit may be substantially zero (such as less than 100 microvolts including changes). However, conventional AZ circuits may increase broadband noise levels, which is disadvantageous when low noise and low power are required at the same time. When using AZ circuits, the power consumption of the precision ADC may have to be increased to reduce the noise to an acceptable level. A low-power ADC is needed, including the need for a low-power, low-offset, and low-noise precision ADC.

[0007] Several AZ circuits have been developed. Figure 1 AZ amplifier circuit 120 of the prior art is shown. AZ amplifier circuit 120 can operate in two phases: Phase 1 ( Figure 1 Marking Φ1) and stage 2 ( Figure 1 2 in the figure). Phase 1 and phase 2 do not overlap in time, and the operation may be repeated periodically or non-periodically. Switches 113 and 107 are closed (conductive) during phase 1, otherwise they are open (non-conductive). Similarly, switches 115p, 115m are closed during phase 2, otherwise they are open. The voltage-input voltage-output amplifier circuit 121 has two input terminals 103p, 103m and two output terminals 105p, 105m. In one example, terminal 103m and terminal 105m are connected together and share a common potential, such as ground or 0V. In phase 1, input terminals 103p, 103m are short-circuited by switch 107, which forms a nominal zero voltage on input terminals 103p, 103m. The amplifier circuit 121 has a potential non-zero offset, such as OS=1mV. When switch 107 is closed during phase 1, an amplified offset may be observed at terminals 105p, 105m. For example, if amplifier circuit 121 has a voltage gain factor, GAIN=200, then an amplified offset GAIN·OS=200·1 mV=200 mV is observed as a voltage between output terminals 105p and 105m. Note that offset OS may be an undesirable artifact of amplifier circuit 121, and AZ amplifier circuit 120 does not necessarily include any circuitry for intentionally providing a non-zero offset OS. Therefore, Figure 1There is no source or any other circuitry shown for providing or representing the offset OS, which may be (but need not be) nominally zero. The amplified non-zero offset can be observed as a non-zero voltage between terminals 105p, 105m, even if the voltage between terminals 103p, 103m is exactly zero.

[0008] Capacitor 109 is configured between terminal 105p and terminal 111p. Switch 113 shorts terminals 111p and 105m during phase 1, whereby the amplification offset can be observed as a voltage on capacitor 109. In the transition from phase 1 to phase 2, switch 113 is slightly opened before switch 107 is opened, whereby the observed amplification offset is sampled on capacitor 109. The voltage VRES (i.e., analog value) applied to AZ amplifier circuit 120 at its input terminals 101p, 101m is provided to amplifier circuit 121 at terminals 103p, 103m via switches 115p, 115m closed during phase 2. On the one hand, if (VRES>0), a voltage greater than the amplification offset GAIN·OS is observed between terminals 105p and 105m, and a voltage greater than zero is observed between terminals 111p and 105m. On the other hand, if (VRES<0), a voltage less than the amplified offset GAIN·OS is observed between terminals 105p and 105m, and a voltage less than zero is observed between terminals 111p and 105m. Therefore, the polarity of the voltage VRES applied at the input of the AZ amplifier circuit 120 (terminals 101p, 101m) corresponds to the polarity of the amplified voltage GAIN·VRES observed at the output of the AZ amplifier circuit 120 (terminals 111p, 105m). When the polarities correspond, the effective offset of the AZ amplifier circuit 120 can be zero. Even if the offset OS of the amplifier circuit 121 is non-zero, the effective offset of the AZ amplifier circuit 120 can be zero. The two-stage operation of the AZ amplifier circuit 120 can substantially cancel (i.e., reduce to a small value, nominally zero) the potential non-zero offset of the amplifier circuit 121. A circuit, process, or operation configured to operate using multiple stages and substantially cancel a potential non-zero offset can be referred to as an "auto-zero" circuit, process, or operation. Note that the auto-zero operation may require little or no knowledge of the circuit's potential non-zero offsets. The AZ circuit (e.g., AZ amplifier circuit 120) provides nominal operation (e.g., amplification) during only one phase (e.g., Phase 2) of its multiple phases (e.g., Phase 1 and Phase 2) of operation.

[0009] The AZ amplifier circuit 120 illustrates that the offset OS can be amplified and observed in one stage. The combination of the input VRES and the offset OS can be amplified and observed in another stage. The AZ amplifier circuit 120 combines and outputs a combination of two observations, whereby the combined contribution from the offset OS can be substantially zero. Specifically, the first observation GAIN·OS and the second observation GAIN·(VRES+OS) are combined so that the contribution of the offset in one observation can be substantially offset by an equal and opposite (of equal magnitude and opposite polarity) contribution from the offset in the other observation. For example, the combination of the two observations is GAIN·(VRES+OS)-GAIN·OS=GAIN·VRES. The contribution of the input VRES to the combined output is GAIN·VRES. The contribution of the offset OS to the combined output may be substantially zero, GAIN·(OS-OS)=0. The auto-zero offset may be nominally zero. The AZ circuit can suppress low frequency noise modeled as a time-varying offset.

[0010] Figure 1 The successful operation of the AZ amplifier circuit 120 in the embodiment of the present invention depends on the observed value sampled on the capacitor 109 in phase 1, which remains substantially unchanged during the subsequent phase 2. To achieve this, the AZ amplifier circuit 120 is coupled to an amplifier (or buffer) circuit 117, which is configured to draw only very little charge (if any) from the terminal 111p across the capacitor 109 during phase 2. When referenced to the input VRES, the offset of the amplifier circuit 117 is suppressed by the gain factor (such as GAIN=200) provided by the AZ amplifier circuit 120. In some applications, the amplifier circuit 117 is an auto-zero amplifier circuit, such as the AZ amplifier circuit 120. In some embodiments, the capacitor 109 is split into two parts (not shown) and the first half capacitor is configured to be in series with the terminal 105p and the second half capacitor is configured to be in series with the terminal 105m.

[0011] Figure 2Another prior art type of AZ amplifier circuit 220 is shown. The voltage input voltage output amplifier circuit 221 that performs auto-zeroing has a pair of input terminals 203p and 203m and a pair of output terminals 205p and 205m. It further has an auxiliary input 211 for applying an auxiliary (control) voltage. The effective (auto-zero) offset of the AZ amplifier circuit 220 is a combination of the potential non-zero offset of the amplifier circuit 221 and the auxiliary voltage applied at the input 211 to cancel the offset contribution. The amplifier circuit 221 is a 2-stage amplifier circuit well known to those of ordinary skill in the art (PHOSITA). It includes an input gm stage (i.e., a transconductance circuit, not shown) coupled to the input terminals 203p and 203m and an output stage (e.g., a transimpedance stage, not shown) coupled to the output terminals 205p and 205m. The auxiliary gm stage (not shown) is coupled to the input 211 and the input gm stage. The currents provided by the input gm stage and the auxiliary gm stage are combined so that the current provided by the auxiliary gm stage can cancel the offset of the input gm stage. The auxiliary voltage is sampled and stored on a capacitor 209 coupled to the input 211. The capacitor 209 is not directly coupled to the output terminals 205p, 205m. When the switch 213 is open, the first terminal of the capacitor 209 connected to the input 211 is substantially floating. The output terminals 205p, 205m of the amplifier circuit 221 are also the output terminals of the AZ amplifier circuit 220. The input impedance of the optional load circuit 217 may be relatively unimportant, and the AZ amplifier circuit 220 may be more convenient to use than the AZ amplifier circuit 220. Figure 1 The AZ amplifier circuit 120 is more general.

[0012] The AZ amplifier circuit 220 operates in two phases: Phase 1 ( Figure 2 Marking Φ1) and stage 2 ( Figure 2 2). During phase 1, switch 207 is closed to apply zero voltage on terminals 203p and 203m. The amplified combination of the potential non-zero offset and the auxiliary voltage is observed as a voltage at terminals 205p, 205m, which is connected to the gm stage (transconductance stage circuit) 223. Switch 213 couples the gm stage 223 to capacitor 209 and input 211 during phase 1. The polarity of the amplified combination nominally determines the polarity of the current provided by the gm stage 223, which can increase or decrease the auxiliary voltage at the input 211 during phase 1 when switch 213 is closed. The negative feedback operation mode ensures that the auxiliary voltage at the input 211 is substantially stable at the end of phase 1, and the amplified combination at terminals 205p, 205m can be substantially zero.

[0013] In the transition from phase 1 to phase 2, switch 213 is opened some time before switch 207 is opened. This effectively samples the substantially stable auxiliary voltage on capacitor 209 and holds it at input 211 during phase 2. Switch 219 is closed during phase 2 to divert current that may be provided by gm stage 223. Alternatively, gm stage 223 is temporarily closed during phase 2 to save power, and / or disconnected from terminals 205p, 205m by a switch (not shown). The analog input value VRES is applied to AZ amplifier circuit 220 at input terminals 201p, 201m. The analog input value is provided to amplifier circuit 221 at terminals 203p, 203m via switches 215p, 215m that are closed during phase 2.

[0014] The operation of the AZ amplifier circuit 220 is as follows. In phase 1, the negative feedback operation regulates the auxiliary voltage so that when the auxiliary voltage is sampled on capacitor 209, the amplified combination of the offset and the auxiliary voltage is substantially zero at or near the end of phase 1. The amplified contribution from the sampled auxiliary voltage may be substantially equal and opposite to the amplified contribution from the offset. The sampled auxiliary voltage is the first observed value of the amplified offset.

[0015] In phase 2, amplifier circuit 221 amplifies the combination of input VRES, offset and sampled auxiliary voltage. The amplified combination is observed and output at terminals 205p, 205m. The contribution of the offset to the amplified combination can be substantially equal and opposite to the contribution of the sampled auxiliary voltage to the amplified combination, and the two contributions can substantially cancel each other at terminals 205p, 205m. This is an auto-zero operation. Therefore, the amplified combination observed and output at terminals 205p, 205m responds to VRES and is substantially not responsive to the offset of amplifier circuit 221. The sampled auxiliary voltage is the first observed value of the amplified offset, and it is combined with the second observed value of the amplified offset during phase 2.

[0016] Different kinds of auto-zero amplifiers are known in the prior art. One common characteristic is that they operate in multiple phases and a nominally zero voltage is applied to the input during one of the multiple operating phases. Another common characteristic is that the observations obtained during the multiple phases are combined to substantially cancel out potential non-zero offsets.

[0017] An auto-zero amplifier may be configured to amplify a residual value in an analog-to-digital converter (ADC) circuit. Figure 3 2 shows a block diagram of an ADC 300 including a residue amplifier 320. In some examples, the residue amplifier 320 is Figure 2AZ amplifier circuit 220 shown in FIG. ADC 300 receives analog voltage VIN(t). Sample-and-hold (S / H) circuit 301 samples VIN(t) at a sampling instant (t=T0) and outputs the held analog value VIN. A first quantizer (ADC1) 303 is configured to receive the analog value VIN and derive a first digital value (CODE1) representing VIN. Digital value CODE1 is a relatively low-resolution digital representation of VIN. For example, CODE1 may be a 5-bit digital representation of VIN. As a step of a method for deriving a higher-resolution and more accurate digital representation of VIN, ADC 300 derives and processes a residual of VIN relative to CODE1. Specifically, a digital-to-analog converter (DAC) 305 derives an analog representation of CODE1, and the difference between the analog representations of VIN and CODE1 is a residual value VRES. The residual value VRES is amplified by a residual amplifier 320, and a second quantizer (ADC2) 330 is configured to derive a digital representation CODE2 of the residual value VRES taking into account a gain factor A provided by the residual amplifier 320. The combination of CODE1 and CODE2 is a high resolution, accurate representation of VIN.

[0018] The accuracy that can be achieved by ADC 300 may depend substantially on the accuracy achieved by DAC 305 and residue amplifier 320. For comparison, the accuracy of ADC1 303 may be relatively unimportant, provided that CODE2 is an accurate representation of the residual value VRES. The accuracy required by ADC2 330 is less than the overall accuracy provided by ADC 300, provided that the absolute value of the gain factor A of the residue amplifier 320 is greater than 1. The upper limit of the gain factor A depends on the resolution and accuracy of CODE1 representing VIN. For example, if CODE1 has a 5-bit resolution and the accuracy does not cause overload / saturation of the residue amplifier 320 and / or ADC2 330, then a gain factor A=16 is used.

[0019] For clarity, ADC1 and / or ADC2 may be referred to as a "quantizer" instead of an ADC. PHOSITA recognizes that Figure 3 The ADC2 330 in the embodiment can be implemented as an overall recursive structure as follows: Figure 3 ADC 300. A so-called pipeline ADC is a well-known example of an ADC 300, where ADC2 330 is a cascade of several similar stages.

[0020] Figure 3The block diagram of ADC 300 in represents any of several types of analog-to-digital converters that include a residual amplifier 320. For example, ADC 300 may be a so-called hybrid SAR ADC in which CODE1 is derived at least in part by using a successive approximation type algorithm (PHOSITA recognizes that SAR ADC stands for “successive approximation register analog-to-digital converter.” PHOSITA is familiar with the design and operation of SAR ADCs). In another example, CODE1 is derived by a flash type ADC1 303 configured to receive VIN. In other examples, CODE1 is provided by a flash or other type of ADC configured to receive VIN(t), and the operation (e.g., the operation of sampling VIN(t)) is synchronized with the operation of S / H circuit 301. In still other examples, Figure 3 ADC1 303 in is a SAR quantizer, a hybrid SAR quantizer, a VCO-based quantizer, a two-step quantizer, a multi-step quantizer, or a pipeline quantizer that provides a digital value CODE1 that is a relatively high-resolution representation of VIN (e.g., CODE1 may have a resolution of 10 bits or more). Therefore, Figure 3 ADC1 303 in is a representation of some type of circuit or some type of method that provides a digital representation of VIN, CODE1. ADC 300 derives an analog residual value VRES as the difference between the analog representation of the digital value CODE1 and the analog value VIN. In one example, a capacitive digital-to-analog converter (CDAC) circuit receives the analog value VIN and the digital value CODE1 and generates an analog residual value VRES based on the analog value VIN and the digital value CODE1. One terminology might be that VRES is the residual of VIN relative to CODE 1, or equivalently (with polarity changed) VRES is the residual of CODE 1 relative to VIN. The magnitude and other properties of the residual VRES depend on how CODE1 is derived to represent VIN, particularly including (but not limited to) the resolution and accuracy of CODE1.

[0021] The accuracy that can be achieved by ADC 300 depends substantially on the accuracy that can be achieved by DAC 305 and residual amplifier 320. Some methods include deriving VIN by sampling a combination of an analog input value VIN(t) and an analog jitter value. These methods can generalize the operation of S / H circuit 301 and DAC 305, which are combined via a capacitive digital-to-analog converter (CDAC) circuit. In another method, a high-resolution digital value CODE1 is derived that allows a high gain factor A of residual amplifier 320 (if desired). Therefore, many variations of ADC circuits can be configured to incorporate the low offset residual amplifier circuits described herein.

[0022] Figure 4 Shows the corresponding Figure 3400. It is a differential ADC 400 that receives an analog input voltage difference VIN(t)=Vp(t)-Vm(t) at input terminals 401p and 401m. In the acquisition phase ( Figure 4 0), switches 403p, 403m, 405p, 405m are closed and the analog input voltage is applied to capacitor arrays 407p, 407m. At a sampling time (t=T0) at or near the end of the acquisition phase, sampling switches 405p, 405m are opened to isolate the differential charge at nodes 409p, 409m. Input switches 403p, 403m are opened with a short delay (such as 200 picoseconds) after the sampling time. Capacitor arrays 407p, 407m are part of a CDAC structure. PHOSITA is familiar with CDAC structures. Capacitor array 407p has a shared terminal connected to terminal 409p and a plurality of N1 terminals connected to input switch 403p (similar to that of U.S. Pat. No. 8,810,443). Figure 2 Thus, the input switch 403p may be a switch array having a shared terminal connected to the input terminal 401p and a plurality of N1 terminals connected to the capacitor array 407p. The same applies to 407m, 409m, 403m and 401m.

[0023] Figure 4 Partially shown is a first quantizer ADC1 implemented as a pair of quantizers ADC1p 411p and ADC1m 411m, which is configured to process each voltage Vp(t) and Vm(t) applied at the input terminals 401p, 401m separately (each voltage is observed relative to a predetermined potential (such as ground or 0V)). When the sampling switches 405p, 405m are opened, the quantizers 411p and 411m sample Vp(t) and Vm(t) at the sampling time (t=T0). Therefore, the positive input digital value CODE1p represents the value Vp(T0) at the sampling time Vp(t), and the negative input digital value CODE1m represents the value Vm(T0) at the sampling time Vm(t). The positive and negative digital values ​​CODE1=CODE1p-CODE1m represent the analog input value VIN=Vp(T0)-Vm(T0) at the sampling time. In another embodiment, a single differential quantizer ADC1 is configured to provide a digital value CODE1 to represent VIN=Vp(T0)-Vm(T0) without having to process each input Vp(t) and Vm(t) individually.

[0024] The derived digital value CODE1p is applied via switches 413p, 415p such that the analog value (e.g., voltage) at terminal 409p is a residual VRESp relative to Vp(T0) of CODE1p. Likewise, CODE1m is applied via switches 413m, 415m such that the analog value (e.g., voltage) at terminal 409m is a residual VRESm relative to Vm(T0) of CODE1m. Switches 413p, 413m connect individual capacitors in capacitor arrays 407p, 407m to a first / high reference potential VH in response to individual bits of CODE1p and CODE1m. Likewise, switches 415p, 415m connect individual capacitors in capacitor arrays 407p, 407m to a second / low reference potential VL in response to individual bits of CODE1p and CODE1m. Capacitors in capacitor array 407p or capacitor array 407m are connected to VH or VL in response to bits of CODE1p or CODE1m. The term capacitive digital-to-analog converter (CDAC) may be used to describe the capacitor arrays 407p, 407m and associated switches and reference potentials.

[0025] Thus, an analog value is sampled on the CDAC (e.g., Vp(T0) is sampled on one or more capacitors in the capacitor array 407p via switches 403p and 405p); a digital value is applied to the CDAC (e.g., switches 413p, 415p selectively connect individual capacitors of the capacitor array 407p to a reference potential VH or VL in response to CODE1p); and the CDAC provides an analog value that is a residual of the sampled analog value relative to the digital code (e.g., the potential / voltage at the node 409p is a residual VRESp of Vp(T0) relative to CODE1p).

[0026] The residue amplifier 420 is configured to receive a residue value VRES=VRESp-VRESm (e.g., the voltage between nodes 409p and 409m), which represents the residue of the analog value VIN=Vp(T0)-Vm(T0) relative to the digital value CODE1=CODE1p-CODE1m. The residue amplifier 420 provides an amplified residue value A·VRES that is processed by the quantizer circuit ADC2 430. ADC2 430 is configured to provide a digital value CODE2, which represents the residue VRES of VIN=Vp(T0)-Vm(T0) relative to CODE1=CODE1p-CODE1m taking into account the gain factor A provided by the residue amplifier 420. The digital circuit 440 combines CODE1p, CODE1m and CODE2 to provide a digital output code DOUT, which can be a high resolution representation of VIN=Vp(T0)-Vm(T0). For example, ADC 400 provides an output code DOUT with a 20-bit or 24-bit resolution. To achieve high accuracy, digital circuit 440 optionally receives and processes calibration information. The calibration information includes a plurality of codes representing the capacitance ratios of the capacitors in capacitor arrays 407p, 407m. The calibration information is obtained / measured as part of the manufacturing process and stored in a memory device (not shown). The accuracy achievable by ADC 400 is substantially limited by the offset and noise level of residue amplifier 420. Conventional AZ residue amplifiers (e.g., Figure 2 The AZ amplifier circuit 220) may provide good offset stability, but relatively high / poor noise levels. In contrast, a non-auto-zero residual amplifier may provide relatively low / better noise and power operation, but its offset stability may be relatively poor. Summary of the invention

[0027] Disclosed herein are examples of analog-to-digital converters (ADCs) that can perform auto-zeroing by amplifying a signal to improve a signal-to-noise ratio. The ADC can generate a first digital code representing an analog input signal and a second digital code based on a residual from the first digital code, and can combine the first digital code and the second digital code to generate a digital output code representing the analog input signal. The ADC can generate the second digital code using a first observation value and a second observation value representing an analog residual value of the residual.

[0028] Some embodiments disclosed herein may include an analog-to-digital converter (ADC) circuit including a sampled quantized residual generation (SQRG) circuit, an auto-zero residual amplifier circuit, a quantizer circuit, and a digital circuit. The sampled quantized residual generation (SQRG) circuit may generate a first digital code based at least in part on an analog input value received by the ADC circuit, and may generate an analog residual value based at least in part on the first digital code and the analog input value. The auto-zero residual amplifier circuit may amplify the analog residual value to generate a first observation value of the amplified analog residual value; and generate a second observation value of the amplified analog residual value. The quantizer circuit may generate a second digital code, the second digital code representing a combination of at least the first observation value and the second observation value. The digital circuit is used to generate a digital output code, the digital output code being used to represent the analog input value, wherein the first digital code and the second digital code are combined to generate the digital output code.

[0029] Some embodiments disclosed herein may include an auto-zero residual amplification circuit for offset cancellation, the auto-zero residual amplification circuit comprising an amplification circuit and one or more switches. The amplification circuit is used to amplify a first observation value of an analog residual value and a second observation value of the analog residual value received by the auto-zero residual amplification circuit, the analog residual value being a residue of a digital code generated by an analog-to-digital conversion of an analog input value, wherein the amplified first observation value and the amplified second observation value are to be used with the digital code to generate a digital output code representing the analog input value. The one or more switches are coupled between the amplification circuit and an input of the auto-zero residual amplification circuit, the analog residual value being received via the input of the auto-zero residual amplification circuit, wherein the one or more switches selectively apply the first observation value and the second observation value to the amplification circuit.

[0030] The auto-zero residual amplifier can be configured to operate in two stages, wherein the input residual value can be amplified and observed in two stages. Similar to a conventional auto-zero amplifier, the two observed values ​​can be combined to substantially offset the potential non-zero offset of an active circuit configured to provide amplification. It may be advantageous to space the two observed values ​​closely in time. However, unlike a conventional auto-zero amplifier, both observed values ​​include an amplified residual value. Therefore, compared to the noise level, the combined observed value of the amplified residual value contains a relatively high signal level (residual value). The noise level can be normalized by the signal level, and the relative noise level can be substantially lower than the noise level of a conventional auto-zero residual amplifier circuit. The relatively low noise level helps to achieve an ADC with substantially reduced noise and power operation, which is a significant improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present disclosure may be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, various features are not drawn to scale and are used for illustration purposes only. Where a scale is shown, either explicitly or implicitly, it is provided only as an illustrative example. In other embodiments, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0032] Figure 1 A prior art AZ amplifier circuit is shown.

[0033] Figure 2 Another prior art type of AZ amplifier circuit is shown.

[0034] Figure 3 A block diagram of an ADC including a residue amplifier is shown.

[0035] Figure 4 Shows the corresponding Figure 3 An example of a block diagram of an ADC.

[0036] Figure 5 An example first embodiment of an ADC circuit including an auto-zeroing residual amplification circuit according to various embodiments is shown.

[0037] Figure 6 It is shown that various embodiments can be used to replace Figure 5 Example quantizer ADC2 in ADC2.

[0038] Fig. 7A Another example embodiment of an ADC circuit in accordance with various embodiments is shown.

[0039] Figure 7B It shows various embodiments Fig. 7A An example timing diagram for an ADC circuit is shown in Figure 2.

[0040] Figure 7C An example ADC circuit incorporating a modified AZ residue amplifier circuit according to various embodiments is shown.

[0041] Fig.7D Yet another example embodiment of an ADC circuit according to various embodiments is shown, including a modified AZ residual amplification circuit. DETAILED DESCRIPTION

[0042] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. In addition, the present disclosure may repeat reference numerals and / or letters in various examples or sometimes in different drawings. This repetition is for the purpose of simplicity and clarity, and does not itself specify the specific relationship between the various embodiments and / or configurations discussed. Different embodiments may have different advantages, and any embodiment does not require a specific advantage.

[0043] Figure 5 An example first embodiment of an ADC circuit 500 including an auto-zero residue amplifier circuit 520 according to the present teachings is shown. A sampled quantized residue generation circuit (SQRG circuit) 510 may be implemented, where the SQRG circuit 510 may include Figure 4 The functionality of the SQRG circuit may be similar to that of the SQRG circuit 410. Figure 3 The functionality of the ADC 300 portion indicated by 310 in FIG. Figure 5 The terminals 501p and 501m in the embodiment may correspond to Figure 4 401p and terminal 401m in. In addition, terminal 509p and terminal 509m may correspond to terminal 409p and terminal 409m, respectively. Therefore, the SQRG circuit 510 can provide an analog residual value VRES, which represents the residual of the analog input value VIN=Vp(T0)-Vm(T0) relative to the first digital value CODE1=CODE1p-CODE1m, where T0 is a specific time when the sample is generated. For example, the SQRG circuit 510 may receive the analog input value VIN via terminals 501p and terminal 501m, wherein in the illustrated embodiment, the analog input value VIN includes a differential voltage, and wherein the voltage provided via terminal 501p may include a positive component of the differential voltage, and the voltage provided via terminal 501m may include a negative component of the differential voltage. The SQRG circuit 510 may include ADC1 (such as ADC1 303 ( Figure 3 )), which generates a first digital value CODE1 based on the analog input value VIN. In the illustrated embodiment, the first digital value CODE1 can be represented by a positive digital component value CODE1p representing a positive component of a differential voltage of the input value VIN and a negative digital component value CODE1m representing a negative component of a differential voltage of the analog input value VIN. The SQRG circuit 510 can output the first digital value CODE1. In the illustrated embodiment, the first digital value CODE1 output by the SQRG circuit 510 can include a positive digital component value CODE1p and a negative digital component value CODE1m.

[0044] The SQRG circuit 510 may further include a DAC (such as DAC 305 ( Figure 3 )). For example, the DAC may receive the first digital value CODE1 from ADC1 and generate an analog representation of the first digital value CODE1. In the illustrated embodiment, where the first digital value CODE1 is represented by a positive digital component value CODE1p and a negative digital component value CODE1m, the DAC may receive the positive digital component value CODE1p and the negative digital component value CODE1m, and may generate an analog representation of the positive digital component value CODE1p and an analog representation of the negative digital component value CODE1m to form an analog representation of the first digital value CODE1.

[0045] SQRG circuit 510 may further include subtractor circuitry (such as subtractor circuitry 308 ( Figure 3 )) to generate a residual value VRES between the analog input value VIN and the analog representation of the first digital value CODE1. Specifically, the subtractor circuit system 308 can receive the analog input value VIN and the analog representation of the first digital value CODE1, and generate the residual value VRES from the analog input value VIN and the analog representation of the first digital value CODE1. The residual value VRES can be output by the SQRG circuit 510. In the illustrated embodiment, the residual value VRES can be output as a positive analog component value at the terminal 509p, and as a negative analog component value at the terminal 509m, wherein the positive analog component value and the negative analog component value form a differential representation of the residual value VRES. The residual value VRES can be provided by the SQRG circuit 510 to the auto-zero residual amplifier circuit 520 of the ADC circuit 500. In another embodiment, the digital value CODE1 can be provided as a single code instead of a pair of codes (CODE1p, CODE1m). In another embodiment, VRES may be a residual of CODE1 relative to a combination of the analog input value Vp(T0)-Vm(T0) and the dither value. The resolution of CODE1 may be relatively low (such as 5 bits or less), medium, or relatively high (such as 10 bits or more) depending on a set of design goals.

[0046] The auto-zero residual amplifier circuit 520 can operate in two phases (phase 2 and phase 3). The illustrated auto-zero residual amplifier circuit 520 includes an indication of which switch is closed in which phase, wherein the switch with a Φ2 mark above the switch is closed in phase 2 and opened in phase 3, and wherein the switch with a Φ3 mark above the switch is closed in phase 3 and opened in phase 2. For example, switch 503p and switch 503m can be closed in phase 2 and opened in phase 3. Switch 505p and switch 505m can be opened in phase 2 and closed in phase 3. Phase 2 can occur during a first time period, and phase 3 can occur during a second time period, wherein the first time period and the second time period may not overlap in time. Phase 2 and phase 3 can be repeated periodically or aperiodically.

[0047] The active circuit configured to provide the amplification circuit 521 may receive an analog residual value of a first polarity (such as +VRES) as an input during phase 2. For example, during phase 2, the switch 503p and the switch 503m may be closed, and the switches 505p and 505m may be open. The switch 503p and the switch 503m may couple the SQRG circuit 510 to the amplification circuit 521. The SQRG circuit 510 may provide the analog residual value VRES to the amplification circuit 521 via the switch 503p and the switch 503m, wherein the positive analog component value of the analog residual value VRES is provided to the first input of the amplification circuit 521 via the switch 503p, and the negative analog component value of the analog residual value VRES is provided to the second input of the amplification circuit 521 via the switch 503m. In addition, during phase 3, the active circuit may receive an analog residual value of a second polarity opposite to the first polarity as an input (such as -VRES). For example, during phase 3, switch 505p and switch 505m may be closed, while switch 503p and switch 503m may be open. Switch 505p and switch 505m may couple SQRG circuit 510 to amplification circuit 521. SQRG circuit 510 may provide analog residual value VRES to amplification circuit 521 via switch 505p and switch 505m, wherein a positive analog component value of analog residual value VRES is provided to a second input of amplification circuit 521 via switch 505m, and a negative analog component value of analog residual value VRES is provided to a first input of amplification circuit 521 via switch 505p.

[0048] The amplification circuit 521 may generate a first amplification combination A·(OS+VRES) of the residual value VRES and the potential non-zero offset OS during phase 2, and the amplification circuit 521 may generate its second amplification combination A·(OS-VRES) during phase 3. For example, the amplification circuit 521 may provide the first amplification combination A·(OS+VRES) to the ADC2 530 at or near the end of phase 2, and the amplification circuit 521 may provide the second amplification combination A·(OS-VRES) to the ADC2 530 at or near the end of phase 3. In this embodiment, the AZ amplification circuit 520 itself does not combine the two amplification combinations A·(OS+VRES) and A·(OS-VRES).

[0049] The two amplification combinations are available / observable in two different stages of operation (stage 2 and stage 3) but not simultaneously. For example, the first amplification combination A·(OS+VRES) may be available / observable at the output of the amplification circuit 521 at the end of stage 2 or near the end, and the second amplification combination A·(OS-VRES) may be available / observable at the output of the amplification circuit 521 at the end of stage 3 or near the end. ADC2 530 may observe the first combination A·(OS+VRES) at the end of stage 2 or near the end, and ADC2 530 may generate a digital value CODE2p to represent A·(OS+VRES). ADC2 530 may further observe the second combination A·(OS-VRES) at the end of stage 3 or near the end, and it may generate a digital value CODE2m to represent A·(OS-VRES). ADC2 530 may provide positive digital component values ​​CODE2p and negative digital component values ​​CODE2m at different times in an order corresponding to when ADC2 530 observes each digital value.

[0050] ADC circuit 500 may combine two observations of the amplified residual. In the illustrated embodiment, digital circuit 540 may be coupled to ADC2 530 at the output of ADC2 530 and may receive a positive digital component value CODE2p and a negative digital component value CODE2m from ADC2 530. Two observations that may be quantized separately by ADC2 530 (represented by a positive digital component value CODE2p and a negative digital component value CODE2m produced by ADC2 530) may be digitally combined by digital circuit 540 configured to calculate a digital value CODE2=CODE2p-CODE2m. When CODE2p and CODE2m are combined by subtraction, a potential non-zero offset OS of amplification circuit 521 may be substantially canceled in CODE2. This may be an auto-zero operation. CODE2 may represent an amplified analog residual value 2·A·VRES, or may be scaled to represent VRES by a nominal amplification factor 2·A. By canceling the potential non-zero offset OS and amplifying the analog residual value VRES, the auto-zero residual amplification circuit 520 can produce an improved signal-to-noise ratio representation of the analog residual value VRES compared to a conventional ADC with auto-zeroing, while maintaining or reducing the power consumption of the ADC 500. This can result in improved ADC operation and / or reduced ADC power consumption compared to conventional ADCs.

[0051] The digital circuit 540 may be configured to derive a high resolution representation DOUT of the analog input value VIN=Vp(T0)-Vm(T0) by calculating DOUT=CODE1p-CODE1m+(CODE2p-CODE2m) / (2·A). In another embodiment, the digital circuit 540 may be configured to calculate DOUT=CODE1p-CODE1m+CODE2p-CODE2m. For example, the digital circuit 540 may be coupled to the SQRG circuit 510 and may receive a first digital code CODE1 representing the analog signal VIN from the SQRG circuit 510. The digital circuit 540 may be further coupled to the ADC2 530 and may receive a digital value CODE2 from the ADC2 530. In the illustrated embodiment, where the first digital code CODE1 and the digital value CODE2 are represented differentially, the digital circuit 540 may receive a positive digital component value CODE1p and a negative digital component value CODE1m to represent the first digital code CODE1, and may receive a positive digital component value CODE2p and a negative digital component value CODE2m representing the digital value CODE2. The digital circuit system may generate an output code DOUT of the analog input value VIN by calculating any equation for the output code DOUT. The output code DOUT may also be responsive to calibration information. The calibration information may include a code representing a potential mismatch of the amplification factor A of the SQRG circuit 510 and / or ADC2 530 and / or a potential mismatch of parameters. The calibration information may be derived during a production process (e.g., production testing), or it may be derived during operation by a foreground and / or background calibration process, and the ADC circuit 500 may be deployed for an application (e.g., factory automation).

[0052] In another embodiment, ADC2 530 can be implemented as two separate quantizers. The first quantizer ADC2p (not shown) can observe A·(OS+VRES) at the end of stage 2 or near the end, and provide a digital value CODE2p to represent A·(OS+VRES). Another quantizer ADC2m (not shown) can observe A·(OS-VRES) at the end of stage 3 or near the end, and provide a digital value CODE2m to represent A·(OS-VRES). CODE1p, CODE1m, CODE2p, CODE2m can be combined as described above. A potential advantage of using two separate quantizers to implement ADC2 is that the time interval between the two observations may be smaller. This can improve the suppression of low-frequency noise from the amplifier circuit 521.

[0053] The advantages of the AZ residual amplifier circuit 520 may be easily overlooked. The two observations that can be used to derive CODE2 represent the amplified residual value (A·VRES) and the amplified offset (A·OS). Compare this to the operation of a conventional AZ amplifier (e.g., Figure 1 and 2 ), where only one of the two observations includes the amplified residual value (A·VRES) and both observations include the amplified offset (A·OS). The payload signal content (VRES) of the AZ amplification circuit 520 can be substantially higher (better) than a conventional AZ amplifier. Each observation may be affected in part by an active circuit ( Figure 5 Amplifying circuit 521 in; Figure 1 Amplifying circuit 121; Figure 2 For the ADC circuit 500, when Figure 5 When the residual value VRES is amplified as shown, the signal-to-noise ratio (residual noise ratio) may be better. Figure 1 120 of them; Figure 2 Compared to 220 in FIG. 2, for a given noise specification, the improved signal-to-noise ratio can significantly reduce the power consumption of the AZ residual amplifier circuit 520 (such as nearly 4 times). Therefore, in one embodiment, the present teachings help to significantly reduce the power consumption of the precision ADC. In another embodiment, the present teachings help to significantly improve the signal-to-noise ratio of the precision ADC for a given power budget (such as 20mW).

[0054] Figure 6 Shows that alternative Figure 5 ADC2 630 may be used in conjunction with ADC2 530 in ADC circuit 500. ADC2 630 may combine two observations in the analog domain, and it may perform a single analog-to-digital (A / D) conversion operation to derive a digital value CODE2 to represent the combination of the two observations. Thus, when implemented in place of ADC2 530 in ADC circuit 500, ADC2 630 may receive an amplified combination (such as a first amplified combination A·(OS+VRES) and a second amplified combination A·(OS-VRES)) and may output a digital value CODE2 representing the combination of the amplified combinations.

[0055] ADC2 630 may be a fully differential structure including a positive side CDAC 601p and a negative side CDAC 601m. The first observation value may consist of an amplified analog residual value, such as A·(OS+VRES), given by Figure 5 The AZ residual amplifier circuit 520 in the ADC2 630 is provided. When the sampling switch 625p and the sampling switch 625m are opened at or near the end of phase 2, the first observation value is sampled on the capacitor 623p and the capacitor 623m at or near the end of phase 2 (where the switches closed during phase 2 are closed at Figure 6 is marked with Φ2 and can be compared with Figure 5The connection switch 627p and the connection switch 627m may be opened with a delay of a while (eg, 200 ps) after the sampling switch 625p and the sampling switch 625m are opened.

[0056] The second observation may consist of an amplified simulated residual value, such as A·(OS-VRES), given by Figure 5 The AZ residual amplifier 520 in the ADC2 630 is provided. When the sampling switch 635p and the switch 635m are opened at the end or near the end of the phase 3, the second observation value can be sampled on the capacitor 633p and the capacitor 633m at the end or near the end of the phase 3 (where the closed switch in phase 3 is Figure 6 is marked as Φ3 and can be compared with Figure 5 3 in ). Compared to the first observation value, the sampling polarity of the second observation value may be opposite to the polarity of the positive side CDAC 601p and the negative side CDAC 601m. Specifically, the amplified analog residual value of the first observation value and the amplified analog residual value of the second observation value may each be represented by a differential voltage. Closing switch 627p and switch 627m during stage 2 may result in sampling the positive component of the differential voltage of the first observation value on capacitor 623p of the positive side CDAC 601p, and sampling the negative component of the differential voltage of the first observation value on capacitor 623m of the negative side CDAC 601m. Closing switch 637p and switch 637m during stage 3 may result in sampling the negative component of the differential voltage of the second observation value on capacitor 633p of the positive side CDAC 601p, and sampling the positive component of the differential voltage of the second observation value on capacitor 633m of the negative side CDAC 601m. Therefore, the polarities of the first observation value and the second observation value may be opposite relative to the polarities of the positive side CDAC 601p and the negative side CDAC 601m because the positive component and the negative component of the differential voltage of the observation value are switched between the positive side CDAC 601p and the negative side CDAC 601m between phase 2 and phase 3. The connecting switch 637p and the connecting switch 637m may be opened with a delay of a while (such as 200ps) after the sampling switch 635p and the sampling switch 635m are opened. ADC2 630 may be opened during phase 4 (after phase 2 and phase 3) after phase 4. Figure 6 The switch to be closed during phase 4 is marked as Φ4) to implement a SAR type ADC conversion operation.

[0057] Phase 2, phase 3, and phase 4 may not overlap in time, and they may be repeated periodically or non-periodically. For example, phase 2 may occur during a first time period, phase 3 may occur during a second time period after the first time period, and phase 4 may occur during a third time period after the second time period. In some embodiments, the order of the time periods of phase 2 and phase 3 may be swapped so that the first time period in which phase 2 occurs is after the second time period in which phase 3 occurs. Non-periodic operation may select a sequence of phases 2 and 3 substantially randomly before phase 4 (i.e., in one conversion cycle, the phase sequence may be 0, 1, 2, 3, 4, and in another conversion cycle, the phase sequence may be 0, 1, 3, 2, 4). Example embodiments may operate with a periodic phase sequence (0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1 ...).

[0058] Switch 641p and switch 643p may be closed during phase 4, whereby the first observation value and the second observation value sampled on capacitor 623p and capacitor 633p during phase 2 and phase 3 may be combined by a charge sharing operation; the combined value may be represented by a charge value at node 603p. Since the polarities of the first observation value and the second observation value applied to the positive side CDAC 601p are opposite, the combination by the charge sharing operation may result in a combination of a positive component of the differential voltage of the first observation value sampled on capacitor 623p and a negative component of the differential voltage of the second observation value sampled on capacitor 633p. The charge value at node 603p may further include a charge value sampled on segment 605p of CDAC 601p at or near the end of phase 3. The charge value sampled on CDAC segment 605p may be a fixed value. In another embodiment, it may be a dithered value.

[0059] As described, the negative side CDAC 601m can be operated in a similar manner to the positive side CDAC 601p. Specifically, the switch 641m and the switch 643m can be closed during stage 4, whereby the observations sampled on the capacitor 623m and the capacitor 633m during stages 2 and 3 can be combined by a charge sharing operation and represented by a charge value at the node 603m. Since the polarities of the first observation value and the second observation value applied to the negative side CDAC 601m are opposite, the combination by the charge sharing operation can result in a combination of a negative component of the differential voltage of the first observation value sampled on the capacitor 623m and a positive component of the differential voltage of the second observation value sampled on the capacitor 633m. The charge at the node 603m may further include a charge value sampled on the segment 605m of the CDAC 601m at or near the end of stage 3. The charge value sampled on the CDAC segment 605m may be a fixed value. In another embodiment, it may be a jitter value.

[0060] PHOSITA recognizes that a digital state machine 607, which may be referred to as a SAR (successive approximation register), may be configured to provide a successive approximation sequence of codes to continuously reduce the uncertainty range of the difference observed by the comparison circuit 609. The comparison circuit 609 may direct the SAR 607 to select a single code in the successive approximation sequence of codes. The result code provided by the SAR 607 may be a digital value CODE2 representing a combination of two observations. Specifically, CODE2 may represent a residual value VRES. The contribution of a potential non-zero offset OS of a circuit configured to provide amplification may be substantially offset in CODE2 because the contribution from the first observation may be equal and opposite to the contribution from the second observation. For example, exchanging the polarity of the first observation and the second observation relative to the positive side CDAC 601p and the negative side CDAC 601m may result in one of the observations being processed as a negative differential voltage relative to the other observation. For the sake of understanding, it can be considered that the positive component of the differential voltage of the first observation value is applied to the positive side CDAC 601p, and the negative component of the differential voltage of the first observation value is applied to the negative side CDAC 601m, resulting in the first observation value being positive, such as A·(OS+VRES). The positive component of the differential voltage of the second observation value is applied to the negative side CDAC 601m, and the negative component of the differential voltage of the second observation value is applied to the positive side CDAC 601p, resulting in the second observation value being negative, such as -(A·(OS-VRES)). The combination of the first observation value and the second observation value may result in the positive first observation value and the negative second observation value being added, resulting in the value in which the offset OS is substantially canceled and the amplified residual value A·VRES is substantially doubled. For example, the combination of the positive first observation value and the negative second observation value may produce a value of 2·A·VRES. Switch 611p (i.e., the switch within dashed rectangle 611p) and switch 611m (i.e., the switch within dashed rectangle 611m) can connect a single capacitor in CDAC 601p and CDAC 601m to a high reference potential VH or a low reference potential VL in response to the state of each bit of each code in the successive approximation sequence of the code. PHOSITA recognizes that the operation of switch 611p can compensate for the operation of switch 611m in fully differential ADC2 630. The description of how CDAC 601p operates herein should also be equivalent to the description of how CDAC 601m operates.

[0061] The switch 611p driving capacitor 623p and capacitor 633p can be controlled by a single bit of each code in the code successive approximation sequence. Therefore, with respect to the successive approximation sequence of the code, capacitor 623p and capacitor 633p can be switched as a single capacitor (C / 4+C / 4), the nominal size (capacitance) of which is twice the size (capacitance) of the largest capacitor (C / 4) in CDAC segment 605p. In one embodiment, the nominal weight factors of the individual bits in CDAC 601p that can be switched during the SAR ADC operating mode can be scaled in binary proportion (e.g., with weight factors: 1 / 2, 1 / 4, 1 / 8, 1 / 16...). In another embodiment, the nominal weight factors of the individual bits in the modified CDAC (not shown) can include redundancy (e.g., with weight factors: 1 / 2, 1 / 4, 1 / 8, 1 / 8, 1 / 16, 1 / 32, 1 / 64, 1 / 64, 1 / 128...). The resolution of ADC2 630 may be relatively low (such as 5 bits or less), medium, or relatively high (such as 10 bits or more).

[0062] PHOSITA recognizes that ADC2 630 can be modified to incorporate any type of A / D conversion principle (including but not limited to SAR ADC, pipeline ADC, VCO-based ADC, flash ADC, cyclic ADC, interpolation ADC, hybrid ADC, etc.). ADC2 630 can be configured to sample and convert a combination of multiple analog values. In some embodiments, an ADC that can be configured to sample and convert a combination of an analog input value and a dither value (i.e., a plurality of two analog values) can be implemented. The two analog values ​​can be sampled on separate segments of the CDAC. Figure 6 ADC2 630 of the embodiment can be configured to sample and convert a combination of a first analog value (such as A·(OS+VRES)), a second analog value (such as A·(OS-VRES)), and a third analog value (such as a fixed value or a dithered value applied via switch 611p and switch 611m). Thus, ADC2 630 can be configured to sample and convert a plurality of combinations of three analog values. Multiple analog values ​​can be sampled on multiple segments of CDAC 601p (e.g., capacitor 623p, capacitor 633p, and CDAC segment 605p). Each segment can include one or more capacitors that can be switched individually or in combination during the A / D conversion mode of operation. Multiple analog values ​​can be sampled individually on separate segments of the CDAC at multiple nominally different sampling moments (e.g., at or near the end of phase 2 and at or near the end of phase 3). Various segments of a CDAC configured to sample multiple analog values ​​may be combined prior to or as part of an analog-to-digital conversion operation (eg, switch 641p and switch 643p may be closed in phase 4). Figure 6Switches 643p, switch 643m, switch 635p, and switch 635m in may nominally be redundant or superfluous, but they may be included to mitigate secondary artifacts, such as switch charge injection, with which PHOSITA is familiar. PHOSITA is also familiar with many types of circuits and methods for A / D converting analog values ​​represented as an amount of charge isolated at a node (e.g., node 603p) of a CDAC, i.e., after sampling it as described herein. Therefore, no further description of how to construct and operate comparison circuit 609, SAR circuit 607, and / or switches 611p and 611m need be provided herein.

[0063] In another embodiment, Figure 6 ADC2 630 of the embodiment may be configured to provide A / D conversion operation, wherein switches 611p and 611m may connect capacitors 623p, 633p, 623m, and 633m to a set of predefined potentials (e.g., they may all be connected to VH) during phase 4, regardless of any bit of any code in the successive approximation code sequence provided by SAR 607. Thus, CDAC segment 605p may be configured to sample multiple input values ​​(e.g., A·(OS+VRES) and A·(OS-VRES)) on multiple segments of the CDAC (e.g., first capacitor 623p and second capacitor 633p) that are different from CDAC segments (e.g., segment 605p) that are configured to apply a successive approximation sequence of codes via switches (e.g., switch 611p) during A / D conversion operation.

[0064] In another embodiment, switch 611p and switch 611m cannot drive capacitor 623p, capacitor 633p, capacitor 623m, and capacitor 633m during phase 4 or at any time. Instead, during phase 4, Figure 6 The left terminals of capacitors 623p, 633p, 623m and 633m can be Figure 64 switches not shown in the figure are shorted to each other (and they may not be connected to any fixed potential). During phase 4, the purpose of nominally shorting and floating the 4 terminals may be to suppress the common mode components of the first observation and the second observation (such as A·(OS+VRES) and A·(OS-VRES)). CDAC segment 605p and CDAC segment 605m may be switched according to the code successive approximation sequence provided by SAR 607. CDAC segment 605p and CDAC segment 605m may be scaled relative to capacitor 623p, capacitor 623m, capacitor 633p and capacitor 633m to provide a scaling ratio of CODE2 relative to the reference voltage difference (VH-VL) and the full-scale input range of ADC2 630. For example, the size of each capacitor in CDAC segment 605p and CDAC segment 605m may be reduced by a factor of 3 to compensate for the potential reduction of the full-scale input range by a factor of 3.

[0065] In yet another embodiment, the quantizer ADC2 may be configured to sample and combine more than two (such as 3, 4, 5, ...) observations and derive a digital value CODE2 to represent a weighted combination of more than two observations. For example, capacitor 623p and capacitor 623m may each be divided into two half-size (C / 8) capacitors and configured with switches to sample analog values ​​at 2 different time points (such as at or near the end of phase 2a, and at or near the end of phase 2b). The quantizer ADC2 may incorporate a circuit similar to Figure 5 The control circuit may provide a switch control signal to provide a modified sequence of operation phases: (phase 0, phase 1, phase 2a, phase 3, phase 2b, phase 4). Phase 2 may be an OR combination of phase 2a and phase 2b. Specifically, Figure 5Switches 503p and 503m of the AZ amplification circuit 520 in can be closed in phase 2a as well as phase 2b. Therefore, the AZ amplification circuit 520 can be configured to provide a sequence of amplified analog residual values: A·(OS+VRES) during phase 2a; A·(OS-VRES) during phase 3; A·(OS+VRES) during phase 2b. A first value A·(OS+VRES) can be observed and sampled on the first half (C / 8) of capacitor 623p and capacitor 623m during phase 2a. A second value A·(OS-VRES) can be observed and sampled on (C / 4) of capacitor 633p and 633m during phase 3. A third value A·(OS+VRES) can be observed and sampled on the second half (C / 8) of capacitor 623p and capacitor 623m during phase 2b. Potential non-zero offsets of the amplification circuit 521 can be substantially offset in CODE2, which can represent a weighted combination of the 3 sampled observations. Thus, the modified ADC circuit 500 including the quantizer ADC2 and operating in the modified sequence of stages can be configured to provide an automatic zeroing operation for a potential non-zero offset of the circuit 521, which is configured to provide amplification. Compared to the ADC circuit of the prior art, the modified ADC circuit 500 can provide improved robustness to secondary artifacts such as charge injection, and / or it can provide improved suppression of low-frequency noise. ADC2 can be configured to observe and combine any number (two or more) of amplified analog residual values. It can be configured to combine multiple observations with nominally uniform or non-uniform weights. The example embodiments described herein can be configured to apply nominal non-uniform weighting: [+0.25; -0.50; +0.25]. The weighting factor (-0.50) may occupy significantly more weight (such as greater than 20% weight) than the other two weighting factors (+0.25; +0.25). The three weighting factors may represent the nominal weighting of the first observed amplified analog residual value, the second observed amplified analog residual value, and the third observed amplified analog residual value. In another embodiment, the first weighting factor may be substantially equal to the second weighting factor (such as, the absolute value of each of the two weighting factors may be within the range of ±5%, eg, [-0.48; +0.52]).

[0066] Fig. 7A Another example embodiment of an ADC circuit 700 according to the present teachings is shown. The ADC circuit 700 may have a configuration similar to Figure 3 The structure of the ADC circuit 300 can include a sampling quantization residual generation (SQRG) circuit 710 (respectively with Figure 3 , Figure 4 and Figure 5Compared with the SQRG circuit 310, SQRG circuit 410, SQRG circuit 510 in FIG. 1 ), the auto-zeroing residual amplifier circuit 720 (respectively compared with Figure 3 and Figure 4 ) and the quantizer circuit ADC2 730 (respectively with the residual amplifier circuit 320 and the amplifier circuit 420 in Figure 3 and Figure 4 ADC2 330 and ADC2 430 in FIG. 1 are compared).

[0067] The amplified analog residual value may be a differential charge amount provided via terminal 707p and terminal 707m. The amplified analog residual value may be derived in part by combining two (or more) observed values ​​of the amplified analog residual value to provide an auto-zero operation. ADC2 730 may receive an analog value (e.g., a differential charge amount) from the AZ residual amplifier circuit 720 and perform an A / D conversion operation to provide a digital value CODE2, which may represent an analog residual value VRES, which may be a voltage difference output by the SQRG circuit 710 at terminal 709p and terminal 709m. Thus, the AZ residual amplifier circuit 720 may be configured to combine two (or more) observed values ​​as part of an auto-zero operation and output a differential charge amount (i.e., an analog value) to the ADC circuit 730.

[0068] Figure 7B Shows Fig. 7A AZ residual amplifier circuit 720 can provide amplification by integrating an analog value over a predefined period TINT, which analog value can be derived from the residual value VRES received from the SQRG circuit 710. Figure 7B The first observation value is obtained during the period (marked as Φ2 in the figure), where the transconductance circuit (GM circuit) 721 can receive the residual value VRES via the switch 703p and the switch 703m, and provide a differential output current GM·(VRES+OS). As shown in the figure, OS can be a potential non-zero offset of the circuit 721 configured to provide amplification, and GM can be a transconductance factor (i.e., a voltage-current gain factor). The differential output current can be integrated on the capacitor 743p and the capacitor 743m for a predetermined period TINT to accumulate a differential charge amount Q2=TINT·GM·(VRES+OS) on the capacitor 743p and the capacitor 743m. The differential charge amount Q2 can be the first observation value of the amplified analog residual value.

[0069] In Phase 3 ( Figure 7BThe second observation value may be obtained during the period (marked as Φ3 in the figure), wherein the GM circuit 721 may receive the residual value VRES via the switch 705p and the switch 705m, and provide a differential output current via the switch 715p and the switch 715m. The residual value VRES of the second observation value received by the GM circuit 721 may have an opposite polarity to the residual value VRES of the first observation value. Specifically, the residual value VRES output by the SQRC circuit 710 may be a differential voltage. In stage 2, when the switch 703p and the switch 703m are closed, the positive component of the residual voltage of the first observation value is provided to the first input of the GM circuit 721, and the negative component of the residual voltage of the first observation value is provided to the second input of the GM circuit 721. In stage 2, when the switch 705p and the switch 705m are closed, the positive component of the residual voltage of the second observation value is provided to the second input of the GM circuit 721, and the negative component of the residual voltage of the second observation value is provided to the first input of the GM circuit 721, thereby being opposite to the polarity of the residual voltage of the first observation value provided to the GM circuit 721. In addition, the polarity of the output of GM circuit 721 may be opposite to the polarity of the first observation value and the second observation value. Specifically, for the first observation value, the closure of switch 713p and switch 713m during phase 2 may cause the first output of GM circuit 721 to be coupled to capacitor 743p, and the second output of GM circuit 721 to be coupled to capacitor 743m. For the second observation value, the closure of switch 715p and switch 715m during phase 3 may cause the first output of GM circuit 721 to be coupled to capacitor 745m, and the second output of GM circuit 721 to be coupled to capacitor 745p. Since capacitor 743p and capacitor 745p are used to generate a positive component when combining the observation values ​​(as described below), and capacitor 743m and capacitor 745m are used to generate a negative component when combining the observation values, the polarity of GM circuit 721 may be opposite to the polarity of the combination of the first observation value and the second observation value. The differential output current may be integrated on capacitors 745p and 745m for a predefined period TINT to accumulate a differential charge amount Q3 = TINT·GM·(VRES-OS) on capacitors 745p and 745m. The differential charge amount Q3 may be a second observation value of the amplified analog residual value.

[0070] When switches 723p, 723m, 725p, 725m, 753p, 753m, 755p and 755m can be closed, the Fig. 7A and Figure 7B4 in the figure, two (or more) observations are combined at the beginning of phase 4. A charge sharing operation may occur between capacitor 743p and capacitor 745p and between capacitor 743m and capacitor 745m, which combines the two (or more) observations (e.g., Q2 and Q3). The combined observation may be an amplified analog residual value, which is represented by the charge amount Q=Q2+Q3=2·TINT·GM·VRES, which can be obtained via terminal 707p and terminal 707m. Specifically, the zero voltage between terminal 707p and terminal 707m may indicate that during phase 4, the differential charge amount Q=Q2+Q3 may have been transmitted by terminal 707p and terminal 707m. ADC2 730 may be a SAR type ADC including a comparison circuit 761. The SAR state machine 763 may be configured to derive a digital value CODE2 for which the voltage between the terminal 707p and the terminal 707m may be approximately zero (the degree of approximation may depend on the resolution of CODE2, ADC2 730).

[0071] The term "amplification" may not be limited to characterizing signal processing in which the input value and the output value have the same properties (such as voltage input voltage output or current input current output). For example, the AZ residual amplifier circuit 720 may be a voltage input charge output amplifier circuit, and its amplification factor A may be expressed in units such as coulombs / volt. A relatively large amplification factor A may indicate that when a noise source within ADC2 730 is associated with the input (e.g., terminal 701p and terminal 701m), its contribution to the overall noise level of the ADC circuit 700 is relatively small.

[0072] Switch 765p and switch 765m may apply a first predetermined bias voltage to terminal 707p and terminal 707m, and SAR state machine 763 may be configured with a predetermined reset code during phase 3 (i.e., SAR state machine 763 may be in a predetermined reset state). A second predetermined bias voltage may optionally be the same as the first predetermined bias voltage and may be applied via switch 733p, switch 733m, switch 735p, and switch 735m. A third predetermined potential may optionally be the same as the first and / or second predetermined bias voltage and may be applied via switch 723p, switch 723m, switch 725p, and switch 725m. The first predetermined bias voltage, the second predetermined bias voltage, and the third predetermined bias voltage may not be applied during phase 3. Fig. 7A Marked in.

[0073] Figure 7BThe example timing diagram in shows that switches 723p, 723m, 725p, 725m, 733p, 733m, 735p, and 735m may be closed before phase 2, whereby capacitors 743p, 743m, 745p, and 745m may be reset to a predetermined voltage and charge (e.g., nominally zero differential voltage and zero differential charge). In addition, before phase 2, switches 703p, 703m, 713p, and 713m may be closed, and differential current GM·(OS+VRES) may flow via switches 713p, 723p, 713m, and 723m. Phase 2 may begin when switches 723p and 723m are opened and differential current flows through capacitors 743p and 743m and switches 713p, 733p, 713m, and 733m. Phase 2 may end a predefined period TINT later when switches 733p and 733m are open and differential charge Q2=TINT·GM·(OS+VRES) is effectively sampled on capacitors 743p and 743m. Switches 723p and 723m may be closed a short time (e.g., 200ps) after opening switches 733p and 733m, for example, to provide a path for current flowing through GM circuit 721. Switches 703p, 703m, 705p, 705m, 713p, 713m, 715p, and 715m may be switched at substantially the same time to prepare for obtaining a second observation during phase 3. The control signals (Φ2x and Φ3x) for controlling switches 703p, 703m, 705p, 705m, 713p, 713m, 715p and 715m may not overlap in time, for example, to avoid establishing a transient conductive path (with respect to Φ3x) between terminal 709p and terminal 709m. Figure 4 The non-overlapping period may be very short, such as 200 ps. PHOSITA is familiar with the use of non-overlapping control signals and with implementing circuits to generate switch control signals, including non-overlapping switch control signals.

[0074] Figure 7BThe example timing diagram of shows that switches 725p, 725m, 735p, and 735m may be closed before stage 3, whereby capacitors 745p and 745m may be reset to a predetermined voltage and charge (e.g., nominally zero differential voltage and zero differential charge). In addition, before stage 3, switches 705p, 705m, 715p, and 715m may be closed, and differential current GM·(VRES-OS) may flow via switches 715p, 725p, 715m, and 725m. Stage 3 may begin when switches 725p and 725m are opened and differential current flows via capacitors 745p and 745m and switches 715p, 735p, 715m, and 735m. Phase 3 may end a predefined period TINT later when switches 735p and 735m are open and differential charge Q3=TINT·GM·(VRES-OS) is effectively sampled on capacitors 745p and 745m. Switches 725p and 725m may be closed a short time (such as 200ps) after opening switches 735p and 735m, for example, to provide a flow path for the current of GM circuit 721. After completing phase 3, the residual voltage VRES may not be needed, and SQRG circuit 710 may be reset at the beginning of phase 4.

[0075] SAR ADC 730 may be configured to receive the amplified residual value Q=Q2+Q3 and provide a digital value CODE2 to represent the analog residual value VRES through a successive approximation charge balancing operation provided during stage 4. A digital circuit (not shown) may be configured to receive and combine CODE1p, CODE1m, and CODE2 (and optional calibration information) to derive and output a code DOUT to represent the analog input value VIN=Vp(T0)-Vm(T0). Methods for combining CODE1p, CODE1m, and CODE2 may include correcting for mismatches in CDAC capacitor ratios (e.g., digital correction) and / or any other known and / or useful techniques.

[0076] Figure 7C Shown with Fig. 7A The example ADC circuit 702 including the modified AZ residual amplifier circuit 722 is compared to the AZ residual amplifier circuit 720. The SQRG circuit 710 and the ADC2 circuit 730 are Fig. 7A The ADC circuit 700 and Figure 7C More generally, the same reference numerals may correspond to Fig. 7A and Figure 7C The same parts. Figure 7BThe timing diagram may be applied to either or both of the ADC circuit 700 and the ADC circuit 702. The AZ residual amplifier circuit 722 may be an extension of the AZ residual amplifier circuit 720. Specifically, the AZ residual amplifier circuit 722 may have 4 capacitors (capacitor 741p, capacitor 741m, capacitor 747p, and capacitor 747m) added to the AZ residual amplifier circuit 720. Capacitor 741p and capacitor 741m may be configured to provide negative feedback to the GM circuit 721 when switch 703p, switch 703m, switch 713p, and switch 713m are closed (Φ2x=1). When switch 705p, switch 705m, switch 715p, and switch 715m are closed (Φ3x=1), capacitor 747p and capacitor 747m may be configured to provide negative feedback to the GM circuit 721. Stage 2 and Stage 3 (see Figure 7B ) can be long enough to allow the GM circuit 721 to substantially settle to an asymptotic output voltage and a nominally zero input voltage (which PHOSITA identifies as a "virtual short circuit"). Various defects of the GM circuit 721 can cause the virtual short circuit input voltage to be non-zero. Such defects may include a potential non-zero offset OS.

[0077] AZ residual amplifier circuit 722 may be configured to operate as a charge-input charge-output AZ residual amplifier circuit. When GM circuit 721 approaches the asymptotic state in stage 2 and / or stage 3, charge may be transferred via terminal 709p and terminal 709m and negative feedback capacitor 741p, capacitor 741m, capacitor 747p, and capacitor 747m. The output impedance of SQRG circuit 710 may be capacitive (see Figure 4; SQRG circuit 710 may be implemented as SQRG circuit 410). SQRG circuit 710 may provide an analog residual value that may be represented as a charge amount QRES=VRES·C, where C may be a capacitance (e.g., output impedance) characterizing SQRG circuit 710. A zero voltage between terminal 709p and terminal 709m may indicate a charge amount QRES transmitted via terminal 709p and terminal 709m since a sampling time (t=T0), the charge amount QRES representing an analog residual value. AZ residual amplification circuit 722 may amplify QRES during stage 2 and store a first observed value of the amplified residual value on capacitor 743p and capacitor 743m as charge Q2=A·(VRES+OS)·C=A·(QRES+OS·C). AZ amplifier circuit 722 may further amplify QRES during phase 3 and store a second observation of the amplified residual value on capacitor 745p and capacitor 745m as charge Q3=A·(VRES-OS)·C=A·(QRES-OS·C). The two observations may be combined at the beginning of phase 4 by a charge sharing operation Q=Q2+Q3=2A·QRES (as described for AZ amplifier circuit 720).

[0078] In phase 2, switches 725p and 725m may be closed, and switches 723p and 723m may be opened. GM circuit 721 may then approach an asymptotic state by transferring charge (nominally QRES) via terminals 709p and 709m and capacitors 741p and 741m to establish a virtual short circuit voltage (e.g., OS is nominally zero) at its input. When switches 725p and 725m are closed shortly after phase 2, the transferred charge may be returned (carried back) via terminals 709p and 709m and capacitors 741p and 741m (see Figure 7B ). Subsequently, in phase 3, switches 725p and 725m may be closed, and switches 723p and 723m may be closed. GM circuit 721 may then approach an asymptotic state by transferring charge (nominally QRES) via terminals 709p and 709m and capacitors 747p and 747m to establish a virtual short circuit voltage at its input.

[0079] The first amplification factor for the operation of the AZ amplification circuit 722 during phase 2 can be substantially a function of the ratio of the capacitance of capacitor 743p and capacitor 743m and capacitor 741p and capacitor 741m. The second amplification factor for the operation of the AZ amplification circuit 722 during phase 3 can be substantially a function of the ratio of the capacitance of capacitor 745p and capacitor 745m and capacitor 747p and capacitor 747m. The first amplification factor and the second amplification factor can be nominally the same. Capacitor 743p, capacitor 743m, capacitor 745p, and capacitor 745m can be nominally the same. Capacitor 741p, capacitor 741m, capacitor 747p, and capacitor 747m can be nominally the same.

[0080] In comparison, the AZ amplifier circuit 720 ( Fig. 7A ) can be a combination of time period (TINT), transconductance (GM), and capacitance. In one comparison, the amplification factor of AZ residual amplifier circuit 722 may be relatively insensitive to manufacturing process variations compared to AZ residual amplifier circuit 720. In another comparison, AZ residual amplifier circuit 720 may be relatively less sensitive to noise from GM circuit 721 than AZ amplifier circuit 722. The advantage of AZ residual amplifier circuit 720 over AZ residual amplifier circuit 722 (or vice versa) may depend on one or more design goals. In another embodiment, Figure 7C The ADC circuit 702 may be configured to be not fully stable during phase 2 and phase 3. For example, compared to the time period required for the AZ amplifier circuit 722 to be substantially fully stable, Figure 7B The predefined period TINT shown in the timing diagram of may be relatively short. For example, the AZ residual amplification circuit 722 may be configured to settle to a predetermined fraction (such as 63%, 86%, 95%, 98%, or ...) of the asymptotic value.

[0081] The operation of the AZ amplifier 722 may not significantly depend on the linearity of capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and 747m (linear capacitors can provide a linear relationship between voltage and charge). In some embodiments, capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and 747m may be implemented using somewhat nonlinear MOS capacitors, i.e., MOS (metal oxide semiconductor) semiconductor devices that are biased to provide a relatively constant (such as ±10%) capacitance for the voltage range used in operation. MOS capacitors may be relatively smaller and less expensive than MOM (metal oxide metal) capacitors, which may be relatively more linear. Any insulating barrier structure (including many semiconductor devices) configured to store charge can be used to implement capacitor 741p, capacitor 741m, capacitor 743p, capacitor 743m, capacitor 745p, capacitor 745m, capacitor 747p and / or capacitor 747m. PHOSITA will recognize that MOS semiconductors do not need to be constructed with metal gate terminals, and the general term / acronym "MOS" (metal oxide semiconductor) should not be interpreted as a limitation on the materials used to manufacture semiconductor devices. The term "MOS semiconductor device" should include a wide range of semiconductor devices, including nominally non-conductive barriers (which can but need not be made of oxides). Any capacitor or other circuit component described in this teaching may be at least slightly nonlinear. If the common-mode voltages at node 709p, terminal 709m, node 707p and terminal 707m are made substantially equal (such as within a ±50mV range), the charge input charge output operation of the AZ amplifier circuit 722 may largely offset a large number of capacitor nonlinearities. In other words, the charge-input charge-output operation of AZ amplifier circuit 722 may be substantially linear even though capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and 747m are relatively less linear. The common-mode voltage may be a voltage across switches 733p, 733m, 735p, and 735m ( Figure 7C ) and the bias voltage applied via switch 405p and switch 405m in SQRG circuit 710 ( Figure 4 ) is a function of the bias voltage applied, which can be realized as Figure 4 The SQRG circuit 410.

[0082] Fig.7D Yet another example embodiment of the ADC circuit 704 is shown, including a modified AZ residual amplification circuit 724. Figure 7CThe AZ residual amplifier circuit 722, Figure 7C The four capacitors (capacitor 741p, capacitor 741m, capacitor 747p, capacitor 747m) of 741p can be replaced by two capacitors (capacitor 771p and capacitor 771) and four switches (switch 773p, switch 773m, switch 775p and switch 775m). Compared with the AZ residual amplification circuit 722, the benefit of the AZ residual amplification circuit 724 is the reduced sensitivity to the noise from the GM circuit 721.

[0083] Fig.7D The AZ circuit 724 may be further modified (in part) by replacing the GM circuit 721 with a voltage-input voltage-output circuit configured to provide amplification. An example voltage-input voltage-output amplifier circuit may be a two-stage amplifier circuit including well-known Miller-type frequency compensation. Other embodiments may include other types of circuits configured to provide amplification.

[0084] Example Implementations

[0085] The following examples are illustrated.

[0086] Example 1 may include an analog-to-digital converter (ADC) circuit for receiving an analog input value and providing a digital output code to represent the analog input value. The ADC circuit includes a sampled quantized residual generation (SQRG) circuit, the SQRG circuit being configured to receive the analog input value and provide a first digital code derived at least in part from the analog input value, the SQRG circuit being further configured to provide an analog residual value derived at least in part from the analog input value and the first code; an auto-zero residual amplification circuit, the auto-zero residual amplification circuit being configured to receive and amplify the analog residual value and provide a first observation value and a second observation value of the amplified analog residual value; a quantizer circuit, the quantizer circuit being configured to derive a second code to represent a combination of at least the first observation value and the second observation value of the amplified analog residual value; and a digital circuit, the digital circuit being configured to combine at least the first code and the second code to derive the digital output code.

[0087] Example 2 may include the ADC circuit of Example 1, wherein the first code is derived at least in part from a combination of the analog input value and a dither value.

[0088] Example 3 may include an ADC circuit according to Example 1, wherein the auto-zero residual amplification circuit includes an active circuit configured to provide amplification, the active circuit is configured to receive the analog residual value at a first polarity to provide the first observation value of the amplified analog residual value, and the active circuit is further configured to receive the analog residual value at a second polarity opposite to the first polarity to provide the second observation value of the amplified analog residual value.

[0089] Example 4 may include an ADC circuit according to Example 1, wherein the auto-zero residual amplification circuit includes an active circuit having a potential non-zero offset, wherein the potential non-zero offset contributes to the first observation and the second observation of the amplified analog residual value, and wherein a combination of the first observation and the second observation of the amplified analog residual value substantially cancels the contribution of the offset to the second code.

[0090] Example 5 may include an ADC circuit according to Example 1, wherein the auto-zero amplification circuit is further configured to generate a third observation value of the amplified analog residual value, and wherein the second code provided by the quantizer circuit represents a weighted combination of the first observation value, the second observation value, and the third observation value of the amplified residual value.

[0091] Example 6 may include the ADC circuit of Example 5, wherein the weighted combination places substantially more weight on at least one of the three observations of the amplified residual value.

[0092] Example 7 may include an ADC circuit according to Example 1, wherein the second code provided by the quantizer circuit is a weighted combination of the first observation value and the second observation value of the amplified residual value, and wherein an absolute value of a first weighting factor for the first observation value of the amplified residual value is substantially the same as an absolute value of a second weighting factor for the second observation value of the amplified residual value.

[0093] Example 8 may include an ADC circuit according to Example 1, wherein the quantizer circuit derives a third code to represent the first observation value of the amplified analog residual value, and further derives a fourth code to represent the second observation value of the amplified analog residual value, and wherein the second code is derived at least in part by combining the third code and the fourth code.

[0094] Example 9 may include an ADC circuit according to Example 1, wherein the first observation value and the second observation value of the amplified analog residual value are represented by a first analog value and a second analog value, respectively, and the first analog value and the second analog value are combined to provide a combined analog value.

[0095] Example 10 may include the ADC circuit according to Example 9, wherein the first analog value and the second analog value are combined by a charge sharing operation.

[0096] Example 11 may include an ADC circuit according to Example 1, wherein the quantizer circuit includes a CDAC circuit, which is configured to sample the first observation value of the amplified residual value on a first segment of the CDAC circuit, and is further configured to sample the second observation value of the amplified residual value on a second segment of the CDAC circuit.

[0097] Example 12 may include the ADC circuit of Example 11, wherein the first section and the second section of the CDAC circuit are used to digitally-analog convert a plurality of codes in a successive approximation code sequence.

[0098] Example 13 may include the ADC circuit of Example 1, wherein the quantizer circuit comprises a successive approximation register (SAR) state machine.

[0099] Example 14 may include the ADC circuit according to Example 1, wherein the analog residual value is a charge amount provided as an input to the auto-zero residual amplification circuit.

[0100] Example 15 may include the ADC circuit according to Example 14, wherein the quantizer circuit is configured to receive a charge amount representing a combination of the first observation value and the second observation value of the amplified analog residual value.

[0101] Example 16 may include the ADC circuit according to Example 15, wherein the semiconductor device is configured to store an amount of charge representing one of the two observation values ​​of the amplified residual value.

[0102] Example 17 may include the ADC circuit according to Example 1, wherein a resolution of the first code is at least 10 bits.

[0103] Example 18 may include the ADC circuit of Example 1, wherein the auto-zero residual amplification circuit is configured to provide amplification by substantially integrating an analog quantity derived from the analog residual value over a predefined time period.

[0104] Example 19 may include the ADC circuit of Example 1, wherein the auto-zero residual amplification circuit is configured to provide amplification by settling at a predefined fraction of the asymptotic value, and wherein the predefined fraction is at most 98%.

[0105] Example 20 may include the ADC circuit of Example 1, wherein the SQRG circuit is configured to derive the first code in part by deriving a residual relative to a code having a resolution at least 3 bits less than a resolution of the first code.

[0106] Example 21 may include an analog-to-digital converter (ADC) circuit comprising a sampled quantization residual generation (SQRG) circuit, the SQRG circuit being used to generate a first digital code based at least in part on an analog input value received by the ADC circuit, and to generate an analog residual value based at least in part on the first digital code and the analog input value; an auto-zero residual amplifier circuit, the auto-zero residual amplifier circuit being used to amplify the analog residual value, generate a first observation value of the amplified analog residual value, and generate a second observation value of the amplified analog residual value; a quantizer circuit, the quantizer circuit being used to generate a second digital code, the second digital code representing a combination of at least the first observation value and the second observation value; and a digital circuit, the digital circuit being used to generate a digital output code, the digital output code representing the analog input value, wherein the first digital code and the second digital code are combined to generate the digital output code.

[0107] Example 22 may be an ADC circuit according to Example 21, wherein the auto-zero residual amplification circuit includes an amplification circuit for providing amplification, wherein, in order to generate the first observation value of the amplified analog residual value, the amplification circuit will receive an analog residual value of a first polarity, and wherein, in order to generate the second observation value of the amplified analog residual value, the amplification circuit will receive an analog residual value of a second polarity, and the second polarity is opposite to the first polarity.

[0108] Example 23 may include the ADC circuit of Example 22, wherein the auto-zero residue amplification circuit includes a first switch and a second switch, the first switch and the second switch are closed during a phase to invert the polarity of the analog residual value.

[0109] Example 24 may include the ADC circuit of Example 22, wherein the polarity of the analog residual value is swapped prior to amplification to produce the second observation value.

[0110] Example 25 may include an ADC circuit according to Example 21, wherein the second digital code comprises a weighted combination of the first observation value and the second observation value, and wherein the absolute value of the first weighting factor of the first observation value is substantially equal to the absolute value of the second weighting factor of the second observation value.

[0111] Example 26 may include an ADC circuit according to Example 21, wherein the quantizer circuit is to combine the first observation value and the second observation value to produce at least the combination of the first observation value and the second observation value, and wherein the first observation value and the second observation value are to be combined so that the offset is substantially canceled.

[0112] Example 27 may include an ADC circuit according to Example 26, wherein the auto-zero residual amplification circuit includes an active circuit, wherein the offset is caused by the active circuit, and wherein the offset contributes to the first observation and the second observation.

[0113] Example 28 may include the ADC circuit of Example 21, wherein the first digital code is generated based at least in part on the analog input value and a dither value.

[0114] Example 29 may include an ADC circuit according to Example 21, wherein the auto-zero amplifier circuit is further used to generate a third observation value of the amplified analog residual value, and wherein at least the combination of the first observation value and the second observation value includes a weighted combination of the first observation value, the second observation value and the third observation value.

[0115] Example 30 may include an ADC circuit according to Example 21, wherein the first observation value is represented by a first analog value, wherein the second observation value is represented by a second analog value, and wherein the first analog value and the second analog value are to be combined to produce a combined analog value, and the combined analog value is to be used to produce the second digital code.

[0116] Example 31 may include an ADC circuit according to Example 30, wherein a charge sharing operation is utilized to comb the first analog value and the second analog value.

[0117] Example 32 may include the ADC circuit according to Example 21, wherein the analog residual value is converted into a charge amount as an input of the auto-zero residual amplification circuit.

[0118] Example 33 may include an ADC circuit according to Example 32, wherein the charge quantity is a first charge quantity, and wherein the quantizer circuit is to receive a second charge quantity, the second charge quantity representing at least the combination of the first observation value and the second observation value.

[0119] Example 34 may include an ADC circuit according to Example 33, wherein the semiconductor device is used to store the second amount of charge.

[0120] Example 35 may include the ADC circuit of Example 24, wherein the polarity of the amplified analog residual value is swapped after amplification to produce the second observation value.

[0121] Example 36 may include an auto-zero residual amplification circuit for offset cancellation. The auto-zero residual amplification circuit includes: an amplification circuit, the amplification circuit being used to amplify a first observation value of an analog residual value and a second observation value of the analog residual value received by the auto-zero residual amplification circuit, the analog residual value being a residue of a digital code generated by analog-to-digital conversion of an analog input value, wherein the amplified first observation value and the second observation value are used together with the digital code to generate a digital output code representing the analog input value; and one or more switches, the one or more switches being coupled between the amplification circuit and an input of the auto-zero residual amplification circuit, the analog residual value being received via the input of the auto-zero residual amplification circuit, wherein the one or more switches selectively apply the first observation value and the second observation value to the amplification circuit.

[0122] Example 37 may include an auto-zero residual amplification circuit according to Example 36, wherein the second group of one or more switches applies the first observation value to the second capacitor and the third capacitor during the first stage, and wherein the second group of one or more switches applies the second observation value to the first capacitor and the fourth capacitor during the second stage.

[0123] Example 38 may include an automatic return-to-zero residual amplifier circuit according to Example 37, wherein the one or more switches include a first group of one or more switches, wherein the automatic return-to-zero residual amplifier circuit further includes a first capacitor and a second capacitor for storing a first charge and combining the first charge, a third capacitor and a fourth capacitor for storing a second charge and combining the second charge, and a second group of one or more switches coupled between the amplifier circuit and the first capacitor, the second capacitor, the third capacitor and the fourth capacitor, the second group of one or more switches being used to selectively apply the first observation value and the second observation value to the first capacitor, the second capacitor, the third capacitor and the fourth capacitor, the first observation value and the second observation value forming the first charge on the first capacitor and the second capacitor and the second charge on the third capacitor and the fourth capacitor.

[0124] Example 39 may include an auto-zero residual amplification circuit according to Example 38, wherein the second group of one or more switches applies the first observation value to the second capacitor and the third capacitor with a first output polarity during the first stage, wherein the second group of one or more switches applies the second observation value to the first capacitor and the fourth capacitor with a second output polarity during the second stage, and wherein the second output polarity is opposite to the first output polarity.

[0125] Example 40 may include an auto-zero residual amplifier circuit according to Example 38, further comprising a third group of one or more switches, wherein the third group of one or more switches are coupled between the first capacitor, the second capacitor, the third capacitor and the fourth capacitor and the output of the auto-zero residual amplifier circuit, wherein the third group of one or more switches will combine the first charges of the first capacitor and the second capacitor during a third stage, wherein the third group of one or more switches will combine the second charges of the third capacitor and the fourth capacitor during the third stage, and wherein the third stage is separated from the first stage and the second stage.

[0126] Example 41 may include an auto-zero residual amplifier circuit according to Example 36, further comprising one or more capacitors, wherein the one or more capacitors are coupled between an input of the amplifier circuit and an output of the amplifier circuit, and the one or more capacitors provide feedback for the auto-zero residual amplifier circuit.

[0127] The foregoing summarizes the features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable a person of ordinary skill in the art (PHOSITA) to better understand the various aspects of the present disclosure. Certain well-understood terms and underlying technologies and / or standards may be referenced without detailed description. It is expected that PHOSITA will have or have access to background knowledge or information of those technologies and standards sufficient to practice the teachings of the present disclosure.

[0128] PHOSITA will understand that they can easily use this disclosure as a basis for designing or modifying other processes, structures or variations to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. PHOSITA will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications to this article without departing from the spirit and scope of the present disclosure.

[0129] Note that the activities discussed above with reference to the accompanying drawings apply to any integrated circuit involving signal processing (e.g., gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), especially those that can execute specialized software programs or algorithms, some of which may be associated with processing digitized real-time data. Certain embodiments may involve multi-DSP, multi-ASIC or multi-SoC signal processing, floating-point processing, signal / control processing, fixed-function processing, microcontroller applications, etc. In some cases, the features discussed herein may be applicable to medical systems, scientific instruments, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instruments (which may be highly accurate), and other digital processing-based systems. In addition, certain embodiments discussed above may be provided in digital signal processing technologies for medical imaging, patient monitoring, medical instruments, and home healthcare. This may include, for example, lung monitors, accelerometers, heart rate monitors, or pacemakers, and their peripherals. Other applications may involve automotive technologies for safety systems (e.g., stability control systems, driver assistance systems, braking systems, infotainment, and any type of interior applications). In addition, powertrain systems (e.g., in hybrid and electric vehicles) can use high-precision data conversion, rendering, and display products in battery monitoring, control systems, reporting controls, maintenance activities, and the like. In other example scenarios, the teachings of the present disclosure can be applied to industrial markets including process control systems that help improve productivity, energy efficiency, and reliability. In consumer applications, the teachings of the signal processing circuits discussed above can be used for image processing, autofocus, and image stabilization (e.g., for digital cameras, camcorders, etc.). Other consumer applications may include audio and video processors for home theater systems, DVD recorders, and high-definition televisions. However, other consumer applications may involve advanced touch screen controllers (e.g., for any type of portable media device). Therefore, these technologies can easily become part of smartphones, tablets, security systems, PCs, gaming technology, virtual reality, simulation training, and the like.

[0130] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications to this article without departing from the spirit and scope of the present disclosure.

[0131] Certain embodiments of the present disclosure may readily include a system-on-chip (SoC) central processing unit (CPU) package. SoC represents an integrated circuit (IC) that integrates components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and radio frequency functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), where multiple chips are located within a single electronic package and are configured to interact closely with each other through the electronic package. Where appropriate, any module, function, or block element of an ASIC or SoC may be provided in a reusable "black box" intellectual property (IP) block that may be distributed separately without disclosing the logical details of the IP block. In various other embodiments, digital signal processing functions may be implemented in one or more silicon cores in application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and other semiconductor chips.

[0132] In some cases, the teachings of the present disclosure may be encoded into one or more tangible, non-transitory computer-readable media having executable instructions stored thereon, which, when executed, instruct a programmable device (such as a processor or DSP) to perform the methods or functions disclosed herein. Where the teachings herein are at least partially embodied in a hardware device (such as an ASIC, IP block, or SoC), the non-transitory medium may include a hardware device programmed with logic hardware to perform the methods or functions disclosed herein. The teachings may also be practiced in the form of register transfer level (RTL) or other hardware description languages ​​such as VHDL or Verilog, which may be used to program a manufacturing process to produce the disclosed hardware elements.

[0133] In example implementations, at least some of the processing activities outlined herein may also be implemented in software. In certain embodiments, one or more of these features may be implemented in hardware provided outside the elements of the disclosed drawings, or may be combined in any appropriate manner to achieve the desired functionality. Various components may include software (or reciprocating software) that may be coordinated to achieve the operations outlined herein. In further embodiments, these elements may include any suitable algorithm, hardware, software, component, module, interface, or object that facilitates its operation.

[0134] In addition, some components associated with the described microprocessor may be removed or otherwise combined. In a general sense, the arrangement depicted in the figure may be more logical in its representation, and the physical architecture may include various arrangements, combinations and / or mixtures of these elements. It must be noted that countless possible design configurations can be used to achieve the operational goals outlined in this article. Therefore, there are countless alternative arrangements, design choices, equipment possibilities, hardware configurations, software implementations, equipment options, etc. for the associated infrastructure.

[0135] Any appropriately configured processor component can execute any type of instruction associated with data to implement the operations detailed here. Any processor disclosed herein can convert an element or article (e.g., data) from one state or thing to another state or thing. In another example, some activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software and / or computer instructions executed by a processor), and the elements identified herein can be a certain type of programmable processor, programmable digital logic (e.g., FPGA, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), ASICs including digital logic, software, code, electronic instructions, flash memory, optical disk, CD-ROM, DVD ROM, magnetic card or optical card, other types of machine-readable media suitable for storing electronic instructions, or any suitable combination thereof. In operation, the processor can store information in any suitable type of non-temporary storage medium (e.g., random access memory (RAM), read-only memory (ROM), FPGA, EPROM, electrically erasable programmable ROM (EEPROM), etc.), software, hardware, or any other suitable component, device, element, or object (where appropriate and based on specific needs). In addition, based on specific needs and implementations, information tracked, sent, received, or stored in the processor may be provided in any database, register, table, cache, queue, control list, or storage structure, all of which may be referenced within any appropriate time frame. Any memory item discussed herein should be understood to be included within the broad term "memory". Similarly, any potential processing element, module, and machine described herein should be interpreted as being included within the broad term "microprocessor" or "processor". In addition, in various embodiments, the processor, memory, network card, bus, storage device, related peripherals, and other hardware elements described herein may be implemented by processors, memories, and other related devices configured by software or firmware to simulate or virtualize the functions of those hardware elements.

[0136] The computer program logic that implements all or part of the functions described herein is embodied in various forms, including but not limited to source code form, computer executable form, hardware description form, and various intermediate forms (e.g., mask work, or forms generated by assemblers, compilers, linkers, or locators). In an example, the source code includes a series of computer program instructions implemented in various programming languages, such as object code, assembly language, or high-level languages ​​such as OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, JAVA, or HTML, for use with various operating systems or operating environments. The source code can define and use various data structures and communication messages. The source code can be in a computer executable form (e.g., via an interpreter), or the source code can be converted (e.g., via a converter, assembler, or compiler) to a computer executable form.

[0137] In the discussion of the above embodiments, capacitors, buffers, graphic elements, interconnect boards, clocks, DDR, camera sensors, converters, inductors, resistors, amplifiers, switches, digital cores, transistors and / or other components can be easily replaced, substituted or otherwise modified to suit the needs of a particular circuit system. In addition, it should be noted that the use of complementary electronic devices, hardware, non-transitory software, etc. provides equally viable options for implementing the teachings of the present disclosure.

[0138] In an example embodiment, any number of circuits in the figure can be implemented on a board of an associated electronic device. The board can be a general circuit board that can accommodate various components of the internal electronic system of the electronic device and further provide connectors for other peripheral devices. More specifically, the board can provide an electrical connection through which other components of the system can communicate electrically. Any suitable processor (including a digital signal processor, a microprocessor, a support chipset, etc.), a memory element, etc. can be appropriately coupled to the circuit board based on specific configuration requirements, processing requirements, computer design, etc. Other components, such as external storage devices, additional sensors, controllers for audio / video display, and peripheral devices can be connected to the board as plug-in cards, via cables, or integrated onto the board. In another example embodiment, the circuit in the figure can be implemented as an independent module (e.g., a device with related components and circuit systems configured to perform a specific application or function), or as a plug-in module inserted into the specific application hardware of the electronic device.

[0139] Note that in the numerous examples provided herein, two, three, four or more electronic components may be used to describe the interaction. However, this is done only for the purpose of clarity and example. It should be understood that the system can be integrated in any suitable manner. Along similar design alternatives, any of the components, modules and elements shown in the figure can be combined in various possible configurations, all of which are obviously within the broad scope of the present disclosure. In some cases, it may be easier to describe one or more functions of a given set of processes by referring only to a limited number of electrical components. It should be understood that the accompanying drawings and their teachings are easy to expand and can accommodate a large number of components and more complex / complex arrangements and configurations. Therefore, the examples provided should not limit the scope or suppress the broad teaching of the circuit because it may be applied to countless other architectures.

[0140] Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained by those skilled in the art, and the present disclosure is intended to cover all such changes, substitutions, variations, alterations, and modifications that fall within the scope of the appended claims. To assist the United States Patent and Trademark Office (USPTO) and any reader of any patent issued under this application in interpreting the claims appended hereto, applicants wish to note that applicants: (a) do not intend to invoke 35 U.S.C. § 112(f) as it exists on the date of filing this application unless “means” or “step” is specifically used in a particular claim; and (b) do not intend, by any statement in this disclosure, to limit the present disclosure in any manner not reflected in the appended claims.

Claims

1. A circuit comprising: An analog-to-digital converter ADC for receiving an analog input value; a digital-to-analog converter DAC coupled to the output of the ADC; subtractor circuitry for generating a positive component of a residual value and a negative component of a residual value at a positive terminal and a negative terminal, respectively, the residual value being a difference between the analog input value and an output of the DAC; a first switch and a second switch coupled to the positive terminal and the negative terminal, respectively, the first switch and the second switch being open during the first phase and closed during the second phase; a third switch and a fourth switch, coupled to the negative terminal and the positive terminal, respectively, the third switch and the fourth switch being closed during the first phase and being opened during the second phase; as well as an active circuit having a positive terminal coupled to the first switch and the third switch and a negative terminal coupled to the second switch and the fourth switch; another ADC coupled to the output of the active circuit; Therein, the further ADC obtains a first observation of the output of the active circuit during a first phase and obtains a second observation of the output of the active circuit during a second phase.

2. The circuit of claim 1 , further comprising: A digital circuit is provided for receiving a first digital code based on a first observation of the output of the active circuit obtained during a first phase and for receiving a second digital code based on a second observation of the output of the active circuit obtained during a second phase.

3. The circuit of claim 2, wherein the digital circuit is configured to receive a further digital code from the further ADC.

4. The circuit of claim 2, wherein the digital circuit is configured to output a final digital code representing the analog input value.

5. The circuit of claim 1, wherein: The further ADC comprises a first quantiser for obtaining a first observation of the output of the active circuit during a first phase and a second quantiser for obtaining a second observation of the output of the active circuit during a second phase.

6. A circuit comprising: a positive terminal for receiving a positive component of a residual value, the residual value being a difference between an analog input value and a digital code generated from the analog input value; a negative terminal for receiving a negative component of the residual value; a first switch and a second switch coupled to the positive terminal and the negative terminal, respectively, the first switch and the second switch being open during the first phase and closed during the second phase; a third switch and a fourth switch, coupled to the negative terminal and the positive terminal, respectively, the third switch and the fourth switch being closed during the first phase and being opened during the second phase; an active circuit having a positive input terminal coupled to the first switch and the third switch and a negative input terminal coupled to the second switch and the fourth switch; another ADC coupled to the output of the active circuit; as well as Therein, the further ADC obtains a first observation of the output of the active circuit during a first phase and obtains a second observation of the output of the active circuit during a second phase.

7. The circuit of claim 6, further comprising: a first capacitor capable of being coupled to a positive output terminal of the active circuit during a first phase; a second capacitor capable of being coupled to a negative output terminal of the active circuit during the first phase; a third capacitor capable of being coupled to a negative output terminal of the active circuit during the second phase; as well as A fourth capacitor can be coupled to the positive output terminal of the active circuit during the second phase.

8. The circuit of claim 7, further comprising: a first switch for coupling the first capacitor to a positive input node of the comparison circuit during a fourth phase; a comparison switch for coupling the second capacitor to a negative input node of the comparator circuit during a fourth phase; a third switch for coupling a third capacitor to a positive input node of the comparison circuit during a fourth phase; as well as A fourth switch is used to couple the fourth capacitor to the negative input node of the comparison circuit during the fourth phase.

9. The circuit of claim 8, further comprising: a first capacitive digital-to-analog converter stage coupled to a positive input node of the comparison circuit; as well as A second capacitive digital-to-analog converter stage is coupled to the negative input node of the comparison circuit.

10. The circuit of claim 8, further comprising: A digital state machine is coupled to the output of the comparison circuit.

11. The circuit of claim 6, further comprising: a first capacitive digital-to-analog converter stage capable of being coupled to an output of the active circuit during a first phase; as well as A second capacitive digital-to-analog converter stage can be coupled to the output of the active circuit during the second phase, but with an opposite polarity relative to the first phase.

12. The circuit of claim 6, further comprising: A third capacitive digital-to-analog converter stage can be coupled to sample the dither value.

13. The circuit of claim 7, comprising a switch for shorting one side of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor together.

14. The circuit of claim 6, further comprising: a first capacitive digital-to-analog converter stage couplable to sample a first analog value; a second capacitive digital-to-analog converter stage couplable to sample a second analog value; and A third capacitive digital-to-analog converter stage is couplable to sample a third analog value.

15. A circuit comprising: a positive input terminal for receiving a positive component of a residual value, the residual value being a difference between an analog input value and a digital code generated from the analog input value; a negative input terminal for receiving a negative component of the residual value; a first switch and a second switch coupled to the positive terminal and the negative terminal, respectively, operable to conduct a residual value having a first polarity during a first phase; a third switch and a fourth switch coupled to the negative terminal and the positive terminal, respectively, operable to conduct a residual value having a second polarity during a second phase, the second polarity being opposite to the first polarity; a transconductance circuit coupled to receive a residual value during a first phase and a second phase; a first capacitor and a second capacitor for integrating a residual value having a first polarity during a first phase; a third capacitor and a fourth capacitor for integrating a residual value having a second polarity during a second phase; a switch operable to short together one plate of the first capacitor and the third capacitor at the positive output terminal during the third phase; as well as A switch operable to short together one plate of the second capacitor and the fourth capacitor at the negative output terminal during the third phase.

16. The circuit of claim 15, further comprising: The residual generation circuit is used to output the positive component and the negative component of the residual value at the positive input terminal and the negative input terminal respectively.

17. The circuit of claim 15, further comprising: An analog-to-digital converter is coupled to the positive output terminal and the negative output terminal.

18. The circuit of claim 15, further comprising: a comparison circuit coupled to the positive output terminal and the negative output terminal; as well as A state machine is coupled to the output of the comparison circuit.

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