3D NAND flash memory devices and integration methods thereof

Abstract

The embodiment of the present application discloses a memory device, which comprises a CMOS die, at least one NOR flash memory arranged on the CMOS die, and an open NAND flash interface (ONFI) connected between the at least one NOR flash memory and the CMOS die.

Description

[0001] This application is a divisional application of the patent with an application date of May 20, 2020, application number 202080001324.0, and invention name "3D NAND flash memory device and its integration method". Technical Field

[0002] Embodiments of the present application relate to a 3D NAND flash memory device and an integration method thereof, and relate to, but are not limited to, a 3D NAND flash memory device and an integration method thereof that can improve storage space and read / write performance. Background Art

[0003] To improve the performance of solid-state drives (SSDs), conventional SSD implementations widely utilize a combination of single-level cell (SLC) NAND flash memory and 3D triple-level cell (TLC) NAND flash memory. Hot data, which is frequently read / written, is stored in the SLC NAND flash memory, while cold data, which is infrequently read / written, is stored in the 3D TLC NAND flash memory. However, the 3D TLC NAND flash memory used in this combination structure reduces storage density and increases the cost of the SSD. Furthermore, the read / write performance of the SLC NAND flash memory in this combination structure is unsatisfactory. Therefore, improvements to the existing technology are necessary. Summary of the Invention

[0004] The present disclosure provides a 3D NAND flash memory device and a method for manufacturing the same, to improve storage space and read / write performance. The present disclosure provides a 3D NAND flash memory device and a method for manufacturing the same, to improve storage space and read / write performance.

[0005] Embodiments of the present disclosure disclose an integration method for a 3D NAND flash memory device, comprising: providing a plurality of 3D triple-level cell (TLC) NAND flash memories on a CMOS die; providing at least one NOR flash memory on the CMOS die of the 3D NAND flash memory device; and connecting the at least one NOR flash memory to an open NAND Flash interface (ONFI) of the 3D NAND flash memory device; wherein the at least one NOR flash memory is provided on an unused area of ​​the CMOS die.

[0006] Another embodiment of the present disclosure discloses a 3D NAND flash memory device integrated on a CMOS die, comprising: a plurality of 3D triple-level cell (TLC) NAND flash memories disposed on the CMOS die; and at least one NOR flash memory disposed on the CMOS die, the at least one NOR flash memory being connected to an open NAND flash interface (ONFI) of the 3D NAND flash memories; wherein the at least one NOR flash memory is disposed on an unused area of ​​the CMOS die.

[0007] These and other objects of the presently disclosed embodiments will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments as illustrated in the various accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0009] Figure 1 is a schematic diagram of an integration process for a 3D NAND flash memory device according to an embodiment of the present disclosure;

[0010] Figure 2-Figure 3 FIG. 1 is a schematic diagram of a 3D NAND flash memory device using the integration process according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Figure 1 FIG1 is a schematic diagram of an integration process 10 for a 3D NAND flash memory device according to an embodiment of the present disclosure. The integration process 10 for a 3D NAND flash memory device includes the following steps:

[0012] Step 102: Start.

[0013] Step 104: Arrange a plurality of 3D triple-level cell (TLC) NAND flash memories on the CMOS die.

[0014] Step 106: Dispose at least one NOR flash memory on the CMOS die of the 3D NAND flash memory device.

[0015] Step 108: Connecting the at least one NOR flash memory to an open NAND flash interface (ONFI) of the 3D NAND flash memory device.

[0016] Step 110: Connect a data path logic unit between the at least one NOR flash memory of the 3D NAND flash memory device and the ONFI.

[0017] Step 112: End.

[0018] For explanation of the integration process 10, please also refer to Figure 2 and Figure 3 , Figure 2 and Figure 3 FIG is a schematic diagram of a 3D NAND flash memory device 20 using the integrated process 10 according to an embodiment of the present disclosure. Figure 2 As shown in FIG, a 3D NAND flash memory device 20 includes a CMOS die 202 embedded with a plurality of 3D TLC NAND flash memories 204 .

[0019] According to the integration process 10 , in step 104 , the 3D TLC NAND flash memory 204 is disposed on the CMOS die 202 , and each 3D TLC NAND flash memory 204 does not overlap each other, thereby forming a gap between each 3D TLC NAND flash memory 204 on the CMOS die 202 .

[0020] In step 106, at least one NOR flash memory is provided on the CMOS die 202 of the 3D NAND flash memory device 20, wherein the at least one NOR flash memory is provided on an unused area of ​​the CMOS die 202. The unused area of ​​the CMOS die 202 may be a gap between each of the 3D TLC NAND flash memories 204, a redundant or blank area of ​​the CMOS die 202. Similarly, Figure 3 As shown, a plurality of NOR flash memories 206 are provided in an unused area of ​​the CMOS die 202, so that as the NOR flash memories 206 are provided, the storage space of the 3D NAND flash memory device 20 is increased and the flexibility of the 3D NAND flash memory device 20 is improved. It should be noted that the amount of the NOR flash memory 206 is not limited to Figure 2 and Figure 3 As shown in FIG, other amounts of NOR flash memories of a certain deployment density may be provided in the unused area of ​​the CMOS die 202 according to other requirements.

[0021] In step 108, the NOR flash memory 206 is connected to the ONFI interface of the 3D NAND flash memory device 20. ONFI is an interface that standardizes the pin assignments and commands of the 3D NAND flash memory device 20. The ONFI interface is connected to the 3D TLC NAND flash memory 204. In step 110, a data path logic unit is connected between the NOR flash memory 206 and the ONFI interface. After the data path logic unit of the NOR flash memory 206 is connected to the ONFI interface in step 108, the NOR flash memory 206 can be instructed to read / write data according to the ONFI interface and commands. In other words, the NOR flash memory 206 can share the ONFI interface with the 3D TLC NAND flash memory 204 to read / write data via the ONFI interface, or the NOR flash memory 206 can directly read / write data via the ONFI interface.

[0022] Because the NOR flash memory 206 supports random reads and writes, the read and write performance of the 3D NAND flash memory device 20 is improved when writing multiple small pieces of data. Furthermore, the controller of the 3D NAND flash memory device 20 is used to perform an error control encoding process for the data stored in the 3D TLC NAND flash memory 204. However, the data processed by the NOR flash memory 206 does not have error control encoding, which reduces the complexity of the controller of the 3D NAND flash memory device 20 and improves the performance of the 3D NAND flash memory device 20.

[0023] The 3D NAND flash memory device 20 provided with the NOR flash memory 206 according to the embodiment of the present disclosure can be applied to conventional solid-state disk (SSD) products to improve read / write performance. In addition, by providing the NOR flash memory 206 in an unused area of ​​the CMOS die 202, the manufacturing cost of the 3D NAND flash memory device 20 is maintained.

[0024] like Figure 3As shown in FIG, a 3D NAND flash memory device 20 integrated on a CMOS die 202 according to an embodiment of the present disclosure using the integration method 10 includes a 3D TLC NAND flash memory 204 and a NOR flash memory 206. The 3D TLC NAND flash memory 204 is provided on the CMOS die 202, and the NOR flash memory 206 is provided on an unused area of ​​the CMOS die. Furthermore, because the data path logic unit of the NOR flash memory 206 is connected to the ONFI, the ONFI standardizes the pin assignments and commands of the 3D NAND flash memory device 20, thereby reducing the complexity of the 3D NAND flash memory device 20 and improving read / write performance without increasing the manufacturing cost of the 3D NAND flash memory device 20.

[0025] It should be noted that the above embodiments illustrate the concepts of the present disclosure, and those skilled in the art may make appropriate modifications accordingly and are not limited thereto.

[0026] In summary, the present disclosure provides a 3D NAND flash memory device and an integration method thereof, which improves storage space and read / write performance without increasing manufacturing costs.

[0027] Those skilled in the art will readily appreciate that various modifications and variations can be made to the apparatus and methods while maintaining the teachings of the present disclosure.Accordingly, the above disclosure should be construed as being limited only by the scope of the appended claims.

[0028] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0029] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0030] The above is merely an embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A memory device, characterized in that: The memory device comprises a 3D NAND flash memory device, and the 3D NAND flash memory device comprises: CMOS die; At least one NOR flash memory disposed on the CMOS die; The at least one NOR flash memory is connected to an open NAND flash interface ONFI on the CMOS die.

2. The memory device according to claim 1, wherein: The device further comprises: A data path logic unit is connected between the at least one NOR flash memory and the ONFI.

3. The memory device according to claim 1, wherein: The at least one NOR flash memory reads and / or writes data via the ONFI.

4. The memory device according to claim 3, wherein: The at least one NOR flash memory reads and / or writes data according to the pin assignment and commands of ONFI.

5. The memory device according to claim 1, wherein The at least one NOR flash memory is configured to perform random reading and random writing.

6. The memory device according to claim 1, wherein: The 3D NAND flash memory device comprises: 3D TLC NAND flash memory.

7. The memory device according to claim 6, wherein: The 3D TLC NAND flash memory and the NOR flash memory are located in different areas of the CMOS die.

8. The memory device according to claim 6, wherein: The 3D NAND flash memory and the NOR flash memory share an open NAND flash interface ONFI on the CMOS die.

9. The memory device according to claim 1, wherein: The storage device is applied to a solid state hard disk.

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