Shiftable memory and method for operating the shiftable memory

Abstract

The present disclosure relates to a shiftable memory, comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected to form a memory cell chain; at least one first serial output data port; output data logic for connecting the output of any one of the memory cell chain to the first serial output data port, or at least one first parallel output data port and at least one read shift register, which is configured to serially collect serial output data from the output of any one of the memory cell chain; and / or at least one first serial input data port; input data logic for connecting the first serial input data port to the input of any one of the memory cell chain, or at least one parallel input data port and at least one write shift register, which is used to serially shift input data to the input of any one of the memory cell chain; and a controller configured to control the shifting of data in the memory cell chain, the controller also configured to control the output data logic and / or the input data logic. The present disclosure also relates to a method for operating a shiftable memory.

Description

Technical Field

[0001] The present disclosure relates to a shiftable memory, such as a static random access memory or a dynamic random access memory, and a method of operating the shiftable memory. Background Art

[0002] In many modern advanced system-on-chip (SoC) designs, a large memory subsystem (MSS) is needed to meet various requirements. Many applications require large memories in terms of the number of memory elements. For example, a computer typically includes a central processing unit (CPU) for providing arithmetic and logical operations and other operations, and typically many CPU operations involve reading data from or writing data to the memory.

[0003] There are two types of RAM: static random access memory (SRAM) and dynamic random access memory (DRAM). The main memory in a computer is usually DRAM. Static random access memory is widely used in integrated circuits and can account for a large portion of the circuit area and power consumption. SRAM is faster and more expensive than DRAM and can be used, for example, in CPU caches. SRAM is often used in situations where speed is more important than cost and area. A typical memory cell of SRAM memory is a six-transistor (6T) memory cell consisting of six MOSFETs. Each bit is stored on four transistors that form two cross-coupled inverters. In addition to the four transistors, the two cross-coupled inverters are connected to the bit line and the inverted bit line through two additional access transistors, which are controlled by the common word line in a standard single-port 6T SRAM cell.

[0004] DRAM stores each bit in a small capacitor that can be charged or discharged. The advantages of DRAM are the small size and simplicity of the memory cell. However, DRAM must be refreshed periodically, which is disadvantageous in terms of complexity timing and power consumption. DRAM is widely used in digital electronic devices that require low-cost and high-capacity memory.

[0005] The memory cells of the memory are accessed via bit lines, which are typically arranged in the direction of the columns of the memory cell array connected to the storage nodes via transistors. Access is controlled via word lines, which are typically arranged in the direction of the rows of the memory cell array. Control of the individual bit lines and word lines is typically based on instructions or addresses on the memory port. In the case of a dual-port (or multi-port) RAM, which is a type of memory that allows multiple reads or writes to be performed simultaneously, additional bit lines and additional logic must be added to the memory, which is typically costly in terms of area and power.

[0006] Attempts have been made to introduce shift functions into memories for various purposes. Such shift functions typically involve multiplexers and / or additional logic and typically have the purpose of rearranging data, manipulating data in, for example, a data matrix, vector repositioning, or data processing related tasks. Shift functions typically add functionality to the memory, but also increase complexity and size. Summary of the invention

[0007] A first aspect of the present disclosure relates to a shiftable memory, the purpose of which is to reduce complexity, thereby reducing area and power costs or overhead. In particular, in one embodiment, the shiftable memory disclosed in the present application can be implemented without internal bit lines, which can significantly reduce power consumption. In a preferred embodiment, the shiftable memory may include:

[0008] - a plurality of memory cells arranged in rows and columns, wherein the memory cells of a row are interconnected to form a chain of memory cells;

[0009] - at least one first serial output data port; output data logic for connecting the output of any one of the memory cell chains to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured to serially collect serial output data from the output of any one of the memory cell chains; and / or

[0010] - at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any one of the memory cell chain, or at least one parallel input data port and at least one write shift register for serially shifting input data to an input of any one of the memory cell chain; and

[0011] - a controller configured to control the shifting of data in the chain of memory cells, the controller further configured to control the output data logic and / or the input data logic.

[0012] According to one embodiment, the shiftable memory can thus operate without the need for internal bit lines. In read access, the controller is configured to shift the data of the row until the data is sequentially read to the serial output data port or the read shift register, and then the data can be accessed from the parallel output data port. In write access, the controller is configured to connect the first serial input data port to the input of any one of the memory cell chain and sequentially shift the data, alternatively write the data from the parallel input data port to the write shift register, and then serially shift the data to the input of any one of the memory cell chain.

[0013] The inventor has found that shiftable memory can be particularly efficient for dual-port and multi-port memories. By shifting several rows in parallel, the additional cost of reading and writing from / to multiple configurable ports is very low, which contrasts with the dual-port and multi-port capabilities of conventional memories. The output data logic can be configured to connect the output of any one of the memory cell chains to a second serial output data port, or at least one second parallel output data port and at least one second read shift register, which is configured to collect serial output data from the output of any one of the memory cell chains in series. This can be done for multiple rows so that n memory cell chains can be shifted in parallel to n serial output data ports, or to n shift registers. In the same way, the input data logic can be configured to connect the second serial input data port to the input of any one of the memory cell chains, or a second parallel input data port and a second write shift register to serially shift the input data to the input of any one of the memory cell chains. This can be done for several rows so that m memory cell chains can be shifted, wherein the controller is configured to shift data from m serial input data ports in parallel to m memory cell chains. Reading and writing can also be done simultaneously.

[0014] The interconnection of the memory cells in the row can be realized by a switch element. In order to keep a simple and robust embodiment, the memory cells can be separated by, for example, transistors. The enable signal can be controlled by the bit line in the conventional memory cell in a way that the word line signal controls the access to the storage node to control the shift. In order to avoid the value shifting in the wrong direction of the chain and the value being accidentally overwritten, each memory cell of the shiftable memory of the present invention can include two memory elements connected in series, such as a bit cell separated by another switch element (such as a transistor). This means that each memory cell can have two memory elements and two switch elements. Two different control signals can be used to control the shift of two memory elements connected in series, wherein the two different control signals operate with two different phases. This can be, for example, a first clock signal and a second clock signal inverted or delayed relative to the first clock.

[0015] Further uses of the shiftable memory disclosed in the application include refresh processes for dynamic random access memory. The inventors have realized that parallel shifting of all rows or a sequence including shifting of all rows (shifting as little as one step) will cause all memory cells to be rewritten and therefore refreshed.

[0016] The present disclosure also relates to a method for operating a shiftable memory. In a first embodiment, the method comprises the following steps:

[0017] - shifting data of at least one row of a shiftable memory having a plurality of memory cells arranged in rows and columns, wherein the memory cells of a row are interconnected to form a chain of memory cells;

[0018] - sequentially read the shifted data from the first serial output data port of the shiftable memory connected to the output of any one of the memory cell chain, or sequentially shift the data to the internal read shift register and read the data from the internal read shift register through the parallel output data port, or sequentially write the data to the first serial input port of the shiftable memory connected to the input of any one of the memory cell chain, or write the data from the parallel input data port to the internal write shift register and sequentially shift the data from the internal write shift register to the input of any one of the memory cell chain.

[0019] One embodiment involves a further step of shifting each row by at least one step. The inventors have realized that this can be an efficient way to perform refresh operations of dynamic random access memory. The refresh process can also be performed seamlessly in parallel with read / write operations of the memory. In the case of DRAM, typically a refresh operation blocks memory access, i.e., part or all of the memory enters a refresh state, where normal read / write operations are blocked. The inventors have realized that refreshing of the memory can be performed in parallel with read / write access. In one embodiment, the controller is therefore configured to simultaneously perform a refresh operation and read and / or write data from / to the chain of memory cells. In addition, the refresh can be performed using a slower clock, which can also be configured based on the retention time. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a conceptual top-level exemplary illustration of the shiftable memory disclosed in the present application.

[0021] FIG. 2 shows an example of shifting and reading operations of the shiftable memory disclosed in the present application.

[0022] FIG. 3 shows an example of shifting and reading operations of the shiftable memory disclosed in the present application for two read ports.

[0023] Figure 4 An example of multiple parallel shift operations is shown.

[0024] Figure 5 An example of simultaneously reading and writing data in the same row is shown.

[0025] Figure 6 An example of a reset operation is shown.

[0026] FIG. 7 shows an embodiment of a memory cell chain of a static random access memory.

[0027] Figure 8 An embodiment of a memory cell or memory element of a memory cell chain of a static random access memory is shown.

[0028] FIG. 9 shows an embodiment of a memory cell chain of a dynamic random access memory.

[0029] Fig.10 An example of an improved configuration of a control signal for shifting data in a shiftable memory is shown.

[0030] Fig.11 Another example of an improved configuration of a control signal for shifting data in a shiftable memory is shown.

[0031] Fig.12 An example of a clock scheme of the shiftable memory disclosed in the present application is shown, in which data is shifted individually.

[0032] Fig.13 An example of separate control signals for each memory cell within a row is shown.

[0033] Fig.14 An example of a shiftable memory disclosed in the present application is shown, which has output logic, such as arithmetic logic, to perform logic operations on data shifted out of the chain of memory cells.

[0034] Fig.15 An example of a shiftable memory having output logic including a plurality of operation units disclosed in the present application is shown. DETAILED DESCRIPTION

[0035] The present disclosure relates to a shiftable memory, which includes a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected to form a memory cell chain. The shiftable memory may also include at least one first serial output data port and output data logic for connecting the output of any one of the memory cell chain to the first serial output data port. The output data logic may be implemented as a multiplexer controlled by a controller, wherein the output of the memory cell chain may be connected to the first serial output data port through the multiplexer. Alternatively, the shiftable memory may have at least one internal read shift register for serially collecting serial output data from the output of any one of the memory cell chain. When the read data is collected, the data may be read through the first parallel output data port. Preferably, the shiftable memory also includes at least one first serial input data port and input data logic for connecting the first serial input data port to the input of any one of the memory cell chain. The input data logic may be, for example, a switch on each input of the memory cell chain controlled by a controller. Alternatively, data may be written from the parallel input data port to the write shift register and then serially shifted to the input of any one of the memory cell chain. The controller may be configured to control the shifting of data in the chain of memory cells. The controller may also be configured to control output data logic and input data logic. The controller may include a decoder for decoding the address and enable signals of the memory and passing them to the shift operation. As an example, a read operation of a specific address provided by, for example, a read enable signal and a read address may generate an internal enable signal for shifting a specific row of the memory and optionally routing the output of the chain to an output port through an internal read shift register. Preferably, during a read operation, the output of the last cell in the chain is routed back to the input of the first memory cell of the chain unless there is a write to the chain at the same time.

[0036] The shiftable memory may have word lines or other control lines for controlling access of data to the memory cells.

[0037] In the sense that parallel reading or writing can still be performed using bit lines like conventional memory, the shiftable memory can also be a combination of parallel and serial memory. In this embodiment, the memory can, for example, include one port for conventional parallel reading and another port for shifted serial reading.

[0038] The shiftable memory disclosed in the present application can be implemented and operated without internal bit lines in the columns. This can reduce the area and power consumption of the memory. Instead of connecting the bit lines to the memory cells in the columns, the memory cells can be connected to each other using shift logic elements. The shift logic element can be, for example, a switch, which can be implemented as a gate element, for example in the form of a single transistor.

[0039] Two-level memory cell

[0040] As mentioned above, the memory cells can be separated between each cell by switches, for example in the form of transistors. The enable signal can control the shifting of the chain by closing the switch. Each memory cell of the shiftable memory of the present invention can include two memory cells, such as bit cells, connected in series, which are separated by another switching element, such as a transistor. Fig.7D An example is shown in FIG. Each memory cell (2) is implemented as two memory elements (3) connected in series. The data is shifted in two steps, wherein the first enable signal (EN1, Fig.7D ; SHIFT EN1, Figure 7B ) controls the shift of the first memory element, and the second enable signal (EN2, Fig.7D ; SHIFT EN2, Figure 7B ) controls the shift of the second memory element. Each memory cell may thus comprise two memory elements and two switching elements. The shift of two memory elements connected in series may be controlled using two different control signals, wherein the two different control signals operate at two different phases. This may be, for example, a first clock signal and a second clock signal which is inverted or delayed relative to the first clock, such as Figure 7B and Fig. 9B As shown. The control signals (clock signal and / or enable signal) can be, for example, inverted or offset relative to each other. The control signals can control the shift logic element accordingly.

[0041] operate

[0042] One advantage of the shiftable memory disclosed in the present application is that by shifting several rows in parallel and adding any desired number of input and / or output and / or bidirectional ports, dual-port and multi-port memories can be obtained at relatively low additional cost. In conventional memories, it is costly to achieve true dual-port functionality due to the need for, for example, additional transistors and complex wiring of bit lines. More ports are even more complicated and sometimes not even possible in practice due to congestion. The controller can then control the individual shifting of the chains based on accesses or instructions to multiple memory ports. In addition, rows can be read and written simultaneously and / or freely combined as well as read and written in combination. Therefore, the shiftable memory can be configured to simultaneously shift data in through the serial input data port and shift data out through the serial output data port. Figure 3 shows an example of multiple parallel shift operations. In Figure 3A In , two rows are read and shifted out serially on two serial output ports. Figure 3B In the READ_READ_SCHEMA, the two rows are shifted into two read shift registers, which can then be accessed through the parallel data port. Figure 4Another example of multiple parallel shift operations is shown. Both read and write operations utilize the shift of the first row. The same applies to the second row. The data of the third row is read. The data of the fourth row is written. The data of the sixth row is read and the data of the last memory cell is shifted back to the first cell, just like in a circular shift register. In one embodiment, the controller is also configured to shift the data from the last memory cell in the row to the first memory cell in the row. The controller can be configured to perform a shift operation of one or several of the memory cell chains based on an external command or based on a logic value on an input port of the shiftable memory.

[0043] The output data logic may be configured to connect the output of any one of the memory cell chains to a second serial output data port, or at least one second parallel output data port and at least one second read shift register, which is configured to serially collect serial output data from the output of any one of the memory cell chains. This can be done for multiple rows so that n memory cell chains can be shifted in parallel. Therefore, the shiftable memory may include at least one second serial output data port, wherein the output data logic is also configured to connect the output of any one of the memory cell chains to the second serial output data port, or at least one second parallel output data port and at least one second read shift register, which is configured to serially collect serial output data from the output of any one of the memory cell chains. The controller may be correspondingly configured to shift two memory cell chains in parallel with the first serial output data port and the second serial output data port, respectively. In one embodiment, the shiftable memory further includes a configurable number of n serial output data ports, wherein the controller is configured to shift the n memory cell chains in parallel to the n serial output data ports. According to one embodiment, the controller is configured to shift the two memory cell chains in parallel with any configurable delay between the two memory cell chains. This means, for example, that it might be useful to shift chains of memory cells individually, depending on what the data is used for and when it is needed.

[0044] Since multiple chains can be shifted and thus can be read in parallel, adding output logic (e.g., arithmetic logic) connected between the output of the chain or the read shift register and the memory output port may be another option. Preferably, the arithmetic logic is configurable to perform operations on the read data. In this way, the memory can be used, for example, to read several rows in parallel and perform logic operations on the read data during the read operation. The controller can be configured to use the output logic to perform logic operations on the first serial data output, the second serial output data port, and the optional configurable number of n serial output data ports. In one embodiment, the shiftable memory disclosed in the present application also includes output logic, such as arithmetic logic, wherein the controller is configured to use the output logic to perform logic operations on the first serial data output and / or the second serial output data port and the optional configurable number of n serial output data ports. Such operations can be performed based on external commands or based on the logic values ​​on the input ports of the shiftable memory. The controller can also be configured to connect the result of the logic operation to at least one first serial input data port and serially shift the result to any one of the memory cell chains. The output logic may include a plurality of operation units, wherein the output of each operation unit may be connected to a memory output port, another operation unit, or back to at least one first serial input data port. The shiftable memory disclosed in the present application may include "logic-in-memory", i.e., reducing energy and latency by integrating logic operations in the memory. The inventors have realized that significant advantages can be obtained by combining these logic operations with the features related to the shiftable memory disclosed in the present application.

[0045] The shiftable memory may also include at least one second serial input data port, wherein the input data logic is also configured to connect the second serial input data port to the input of any one of the memory cell chains, or at least one second parallel input data port and at least one second write shift register, which is used to serially shift the input data to the input of any one of the memory cell chains. In this way, a dual-port memory can be implemented. The controller may be configured to shift data from the first serial input data port and the second serial input data port in parallel to two parallel memory cell chains. This concept can be extended to any number of rows / chains. Therefore, in one embodiment, the shiftable memory also includes a configurable number of m serial input data ports, wherein the controller is configured to shift data from the m serial input data ports in parallel to the m memory cell chains.

[0046] Resetting of a shiftable memory may be performed by shifting all rows until all memory cells are written to a predetermined reset value. Such an operation may be initiated manually by accessing the row through a write process, preferably by writing all rows in parallel. Alternatively, the memory may have a reset port which may trigger a reset instruction into an operation of shifting all rows until all memory cells are written.

[0047] The present disclosure relates to a shiftable memory. A shiftable memory can be implemented without bit lines. In other embodiments, bit lines can still be used. In embodiments without bit lines, data will have to be serially shifted in and out of a chain of memory cells during write and read operations. This means that the operation may take multiple clock cycles, i.e., when reading data, for example, a process or cell read from a memory will have to wait for multiple clock cycles until the data is ready on an output port. For some applications, this delay may be acceptable. Since acceptable delays are usually different between applications, the inventors have realized that having a faster and configurable internal clock signal (or an enable signal for the shift process) can provide a solution with power and area efficiency of a shiftable memory, but still maintain a suitable access speed for the application. In one embodiment, the shiftable memory includes an internal dynamically configurable enable signal for shifting data in a chain of memory cells, the internal dynamically configurable enable signal having a configurable frequency. The memory can receive such a signal, such as a clock signal, from a port. The switch logic element can be controlled by an enable signal based on the clock on the port. In one embodiment, the shiftable memory receives a first clock signal or an enable signal for shifting data in a memory cell chain, and the shiftable memory comprises a clock generation unit for generating a second clock signal or the enable signal based on the first clock signal.

[0048] In one embodiment of the shiftable memory disclosed in the present application, the controller is further configured to shift data to an output data port, wherein only data in a memory cell without valid data in the next adjacent memory cell is shifted to the output data port. Fig.12 . In this embodiment, the data can be shifted individually one by one. In the example, data 1 is the data closest to the output port. In the first clock cycle, data 1 is shifted out. In the second clock cycle, data 2 is shifted one step closer to the output port. In the third clock cycle, since there is an unoccupied memory cell between data 2 and data 3, both data 2 and data 3 can be shifted, and so on. In one embodiment, the shiftable memory also includes a separate control signal for each bit in the row.

[0049] The interconnection of the memory storage cells within a row can be achieved by means of switching elements. In one embodiment, the memory cells are separated by two switching elements (e.g., a first switching element, such as a first transistor, and a second switching element, such as a second transistor) connected in series. Fig.10 and 11 As shown, 20 and 21 represent a first switching element and a second switching element.

[0050] Each row may be connected to a word line signal connected to all first switching elements of the row, such as Fig.11 Each column can be connected to a selection signal connected to all second switch elements of the column, such as Fig.11 Alternatively, each row may be connected to at least two word line signals, wherein at least two word line signals are alternately connected to the first switch element of the row, such as Fig.10 As shown. It can be seen that for the first row, there are two word line signals WLA0 and WLB0, where WLA0 is connected to the first and third of the first switch elements, and where WLB0 is connected to the second and fourth of the first switch elements. Also in this case, each column can be connected to a selection signal that is connected to all second switch elements of the column.

[0051] In one embodiment, the row of the shiftable memory is divided into a plurality of sections. As described above, each section can be connected to an input and / or output data port, or to a read and / or write shift register. By shifting these sections in parallel, read and write operations can be performed faster than sequential shifting of the entire row.

[0052] The controller of the shiftable memory disclosed in the present application can also be configured to control the power supply voltage level of the row and / or column and / or each memory cell of the shiftable memory. In one embodiment, during the write operation to the memory cell of, for example, a 6T bit cell, the controller can be configured to reduce the voltage of the entire column to make it easier to write. In one embodiment, during the read operation, the controller can be configured to increase the power supply voltage of the bit cell being read to make it easier / faster to read. The adjustment of the power supply voltage can be viewed as temporarily increasing or decreasing by row, by column or even at the individual cell level.

[0053] Static Random Access Memory

[0054] In one embodiment, the shiftable memory is a static random access memory. A metal oxide semiconductor field effect transistor (MOSFET) has an insulating gate whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used to amplify or switch electronic signals. In one embodiment of the shiftable memory disclosed in the present application, a MOSFET is used to implement the memory cell. MOSFET technology is used in digital complementary metal oxide semiconductor (CMOS) logic, which uses p-channel and n-channel MOSFETs as building blocks.

[0055] In one embodiment of the shiftable memory disclosed in the present application, the memory cell is a five-transistor (5T) or six-transistor (6T) CMOS static random access memory type, preferably without a bit line connection and / or without a bit line pass gate. In an example, the memory cell includes:

[0056] - a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming a first storage node (Q) and an inverted first storage node Two cross-coupled inverters;

[0057] - Connected to the first storage node inverting a fifth transistor (M5);

[0058] - optionally, a sixth transistor (M6) connected to the first storage node (Q);

[0059] - a first word line (WL1) connected to the fifth transistor (M5), the first word line (WL1) controlling the first inverted storage node access; and

[0060] - Optionally, a second word line (WL2) connected to the sixth transistor (M6), said second word line (WL2) controlling access to the first storage node (Q).

[0061] Figure 8 An example of a 6T memory cell is shown. In the shiftable memory disclosed in the present application, instead of connecting the access node (10) to a bit line of the memory, the node can be connected to a memory cell of an adjacent column. Fig.7D An example of such a series connection is shown in . The control / shift enable signal for shifting data in the memory cell may be connected to the word line (11) and / or the power supply line of the memory cell.

[0062] Memory cells can also be implemented in practice as latches (two back-to-back inverters) and switches. Memory cells can also be implemented as standard cell-based Latches and Flip-Flops .

[0063] Dynamic Random Access Memory

[0064] In one embodiment, the shiftable memory is a dynamic random access memory. DRAM stores each bit in a small capacitor that can be charged or discharged. The advantages of DRAM are the small size and simplicity of the memory cell. In the DRAM embodiment of the shiftable memory disclosed in the present application, the memory cell is implemented as a data recovery and amplification unit, such as an inverter. Fig.9E An example of how to implement a memory cell is shown. The recovery and amplification unit can be implemented as a complementary transistor pair, in the example an NMOS gate and a PMOS gate. Each memory cell can include two memory elements connected in series. Alternatively, each memory cell can include a single memory element. Each memory element can include a data recovery and amplification unit and a switching element connected in series, and a capacitor connected in parallel for storing a bit value.

[0065] Compared with SRAM, each bit of DRAM is very cheap in terms of power and area. However, one disadvantage of DRAM is that they must be refreshed periodically. Therefore, conventional DRAM requires external memory refresh circuits. The inventors have found that the shiftable memory disclosed in the present application is very useful in an embodiment as a dynamic random access memory, because all bits can be refreshed by shifting all chains by at least one bit. One bit shift of all rows will cause all bits to be updated. This process can be triggered by a dedicated refresh instruction, such as by enabling a dedicated refresh port, or by reading from all rows in parallel, row by row, or in groups, for example. In this embodiment, each row can be implemented as a circular shift register, wherein, when the row is shifted, the last bit of the row is written to the first bit of the row so that the data that has been read is kept in the row after it is read. In one embodiment, the controller of the shiftable memory is also configured to track the current position of the bit in the memory cell chain. The refresh operation of the dynamic random access memory can be performed by shifting each row by at least one step. All rows can be shifted simultaneously.

[0066] Method for operating shiftable memory

[0067] The present disclosure also relates to a method for operating a shiftable memory, the method comprising the following steps:

[0068] - shifting data of at least one row of a shiftable memory having a plurality of memory cells arranged in rows and columns, wherein the memory cells of a row are interconnected to form a chain of memory cells;

[0069] - sequentially read the shifted data from the first serial output data port of the shiftable memory connected to the output of any one of the memory cell chain, or sequentially shift the data to the internal read shift register and read the data from the internal read shift register through the parallel output data port, or sequentially write the data to the first serial input port of the shiftable memory connected to the input of any one of the memory cell chain, or write the data from the parallel input data port to the internal write shift register and sequentially shift the data from the internal write shift register to the input of any one of the memory cell chain.

[0070] As described above, each memory cell may include two memory elements connected in series, wherein two different control signals are used to control the shifting of the two memory elements connected in series, wherein the two different control signals operate at two different phases. Therefore, in one embodiment, the method further includes the step of shifting at least one row of the shiftable memory by shifting the first memory element of the two memory elements using the first control signal and shifting the second memory element of the two memory elements using the second control signal. The first and second control signals may operate at two different phases. For example, the first and second control signals may be inverted or offset relative to each other.

[0071] In one embodiment, at least two rows are shifted in parallel. In a dual-port configuration, for example, two rows can be shifted in parallel to read data from two different ports simultaneously in a dual-port memory configuration. In a dual-port memory configuration, two rows (same row or other rows) can also be shifted in parallel to write data from two different ports simultaneously. The method can also be included in the step of shifting n rows in parallel in a multi-port memory configuration to read data from n different ports simultaneously, wherein n is 3 or higher. Alternatively or in combination, the method also includes the step of shifting m rows in parallel in a multi-port memory configuration to write data from m different ports simultaneously, wherein m is 3 or higher.

[0072] The method of operating a shiftable memory may also shift the data of the memory cells individually. In one embodiment, the data is shifted to an output data port, wherein only the data in the memory cells that do not have valid data in the next adjacent memory cell are shifted to the output data port. This Fig.12 In this embodiment, the data can be shifted individually one by one.

[0073] The method of operating a shiftable memory may further comprise the step of shifting each row by at least one step, thereby performing a refresh operation of the shiftable memory. The step of shifting each row by at least one step may be performed in parallel, i.e., shifting all rows simultaneously, which may be triggered by a dedicated refresh instruction, such as by enabling a dedicated refresh port, or, for example, by reading from all rows while routing the output of the last cell to the input of the first cell. The process may also be performed by shifting rows row by row or in groups.

[0074] In one embodiment, the row of the shiftable memory is divided into a plurality of parts. Therefore, the method of operating the shiftable memory may include the step of parallel shifting of data in the parts to parallel input and / or parallel output of data to and / or from the plurality of parts.

[0075] Those skilled in the art will appreciate that the method may include the step of providing any variation of the shiftable memory described in the present disclosure.

[0076] Detailed description of the drawings

[0077] The present invention will be described in more detail below with reference to the accompanying drawings. The accompanying drawings are exemplary and are intended to illustrate some features of the shiftable memory and the method of operating the shiftable memory disclosed in the present application, and should not be interpreted as limiting the invention disclosed in the present application.

[0078] Figure 1 The present invention is a conceptual top-level exemplary illustration of a shiftable memory (1) disclosed in the present application. The shiftable memory (1) has a plurality of memory cells (2) arranged in rows (4) and columns (12), wherein the memory cells of the rows are interconnected to form a chain of memory cells. The shiftable memory (1) also includes a controller (5) configured to control the shifting of data in the chain of memory cells (4) and to control output data logic (7) and input data logic (8). The shiftable memory may have a standard interface having, for example, address and data ports, write enable, read enable, and clock signals. The peripheral logic may include a read and / or write decoder and / or a sense amplifier and / or control and / or timing logic and drivers and other logic. An enable and / or clock generation unit (9) may be configured to generate a shift enable signal to the chain.

[0079] FIG2 shows an example of the shift and read operation of the shiftable memory (1) disclosed in the present application. Figure 2A In , the data shifted out from row 2 is serially shifted to the data output port (13). Figure 2B In the example, the data shifted out from row 2 is shifted to the internal read shift register (14) from which the parallel data port can read the data.

[0080] FIG3 shows an example of the shift and read operations of the shiftable memory (1) disclosed in the present application for two read ports. Figure 3A In , data is shifted in parallel in two rows. Data is shifted out serially to two data output ports (13). Figure 3B In the embodiment, the data shifted out of the row is shifted to two internal read shift registers (14) from which the parallel data port can read the data.

[0081] Figure 4 An example of multiple parallel shift operations is shown. First data is read from and written to the first row (4a). Second data is read from and written to the second row (4b). Third data is read from the third row (4a). The shift of the data of the third row (4c) is arranged so that the data from the last cell is routed back to the first cell of the chain, just like in a circular shift register. Fourth data is written to the fourth row (4d). Fifth data is read from the fifth row (4f). The shift of the data of the fifth row (4f) is arranged so that the data from the last cell is routed back to the first cell of the chain, just like in a circular shift register.

[0082] Figure 6 An example of a reset operation for row (4) is shown. By shifting a one "1" or a zero ("0"), the row can be reset. By shifting all rows in parallel in this manner, the entire memory can be reset.

[0083] FIG. 7 shows an embodiment of a memory cell chain of a static random access memory. Fig. 7A A chain of memory cells is shown separated by shift logic elements (15) in the form of switches (15). Figure 7B It is shown how the switches are controlled by two different control signals (SHIFT EN1 and EN2). Figure 7C An example is shown where the memory cell is implemented as a cross-coupled inverter (16). Fig.7D In the embodiment of the present invention, each memory cell (2) is implemented as two memory elements (3) connected in series. The data is shifted in two steps, wherein a first enable signal (EN1) controls the shifting of the first memory element and a second enable signal (EN2) controls the shifting of the second memory element. The memory elements can be implemented as 5T or 6T memory cells, for example. Fig.7D In the example of FIG. 4 , the memory element is implemented as a 6T memory cell.

[0084] Figure 8An embodiment of a memory cell (2) or memory element (3) of a memory cell chain of a static random access memory is shown. The memory cell comprises: a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4), which form a first storage node (Q) and an inverted first storage node (Q). The memory cell also includes a first storage node connected to the inverting a fifth transistor (M5); a sixth transistor (M6) connected to the first storage node (Q); a first word line (WL1, 11) connected to the fifth transistor (M5), the first word line (WL1) controlling the first inverted storage node access; and a second word line (WL2, 11') connected to a sixth transistor (M6), which controls access to the first storage node (Q). The access node (10, 10') can be connected in series to the corresponding access node of the adjacent memory cell. For example, this can be achieved by connecting the fifth transistor (M5) of one cell to the fifth transistor (M5) of the adjacent cell, and connecting the sixth transistor (M6) of one cell to the sixth transistor (M6) of the adjacent cell. The chain can thus be formed by the sequence..M5-M5-(M1 / M2 / M3 / M4 inverter)-M6-M6-(M1 / M2 / M3 / M4 inverter)-M5-M5, etc. The fifth and sixth transistors (M5, M6) can be switching logic elements of the chain.

[0085] FIG. 9 shows an embodiment of a memory cell chain of a dynamic random access memory. Fig. 9A A chain of memory cells is shown separated by shift logic elements (15) in the form of switches (15). Fig. 9B It is shown how the switches are controlled by two different control signals (SHIFT EN1 and EN2). Fig. 9C An example in which the memory unit is implemented as a recovery and amplification unit (17) is shown. Fig.9D In the embodiment of the present invention, each memory cell (2) is implemented as a recovery and amplification unit (17) having a capacitor (19) for storing a bit value and a switching element (18) in the form of a transistor arranged between the recovery and amplification unit (17) and the capacitor (19). Data is shifted in two steps, wherein a first enable signal (EN1) controls the shifting of the first memory element and a second enable signal (EN2) controls the shifting of the second memory element. Fig.9E An example of how a memory cell (2) may be implemented is shown. The recovery and amplification unit (17) is implemented as a complementary transistor pair, in the example an NMOS gate and a PMOS gate. Each memory cell (2) comprises two memory elements (3) connected in series.

[0086] Fig.10 An example of an improved configuration of control signals for shifting data in a shiftable memory is shown. A first switching element 20 and a second switching element 21 are present between each memory cell. For the first row, there are two word line signals WLA0 and WLB0, wherein WLA0 is connected to the first and third of the first switching elements, and wherein WLB0 is connected to the second and fourth of the first switching elements. For the second row, there are two word line signals WLA1 and WLB1, wherein WLA1 is connected to the first and third of the first switching elements of the second row, and wherein WLB1 is connected to the second and fourth of the first switching elements of the second row. The third and fourth rows are controlled in the same manner using WLA2 and WLB2 and WLA3 and WLB3, respectively. In this example, each column is connected to a select signal (CS0, CS1, CS2, CS3) that is connected to all second switch elements (21) of the column.

[0087] Fig.11 Another example of an improved configuration of control signals for shifting data in a shiftable memory is shown. There are first switching elements 20 and second switching elements 21 between each memory cell. For each row, there is a word line signal connected to all first switching elements (20) of the row. For the first row, there is a word line signal WL0 connected to all first switching elements (20) of the first row. For the second row, there is a word line signal WL1 connected to all first switching elements (20) of the second row, and so on. Each column is connected to a selection signal (CS0, CS1, CS2, CS3) which is connected to all second switching elements (21) of the column.

[0088] Fig.12 An example of a clock scheme for a shiftable memory disclosed in the present application is shown, wherein data is shifted individually. In this example, data 1 is the data closest to the output port. In the first clock cycle, data 1 is shifted out. In the second clock cycle, data 2 is shifted one step toward the output port. In the third clock cycle, since there is an unoccupied memory cell between data 2 and data 3, both data 2 and data 3 can be shifted. In the fourth clock cycle, data 3 and data 4 are shifted. In the fifth and sixth clock cycles, data 4 is shifted.

[0089] Fig.13 An example of individual control signals for each memory cell within a row is shown (bit cntrl 1, bit cntrl 2, bit cntrl 3, and bit cntrl 4). The figure shows how the control signals are active during the first four clock cycles for individual shifting of data.

[0090] Fig.14 An example of a shiftable memory (1) disclosed in the present application is shown, which has output logic (22), such as arithmetic logic, to perform logic operations on data shifted out of a chain of memory cells. The memory preferably includes output data logic for connecting the output of any one of the chain of memory cells to a first serial output data port, or at least one first parallel output data port and at least one read shift register, which is configured to serially collect serial output data from the output of any one of the chain of memory cells. The output can then be used to perform a logic / arithmetic operation. The result of such an operation can then be sent out or written back (23) to the memory (1) through the memory read port. If there is no logic / arithmetic operation, the read data can bypass the output logic (22).

[0091] Fig.15 An example of a shiftable memory (1) disclosed in the present application having an output logic (22) is shown, the output logic (22) comprising a plurality of operation units (24). The output of each operation unit (24) can be connected to a memory output port, another operation unit (24) or back to at least one first serial input data port.

[0092] Further details of the invention

[0093] 1. A shiftable memory, comprising:

[0094] - a plurality of memory cells arranged in rows and columns, wherein the memory cells of a row are interconnected to form a chain of memory cells;

[0095] - at least one first serial output data port; output data logic for connecting the output of any one of the memory cell chains to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured to serially collect serial output data from the output of any one of the memory cell chains; and / or

[0096] - at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any one of the memory cell chain, or at least one parallel input data port and at least one write shift register for serially shifting input data to an input of any one of the memory cell chain; and

[0097] - a controller configured to control the shifting of data in the chain of memory cells, the controller further configured to control the output data logic and / or the input data logic.

[0098] 2. A shiftable memory according to item 1, wherein the shiftable memory is operable without bit lines interconnecting the memory cells within a column.

[0099] 3. A shiftable memory according to any one of the preceding clauses, wherein one of the input data port and the output data port is a parallel port.

[0100] 4. A shiftable memory according to any of the preceding clauses, wherein the memory cells of a row are separated by shift logic elements, for example by switch elements and / or gate elements and / or transistors.

[0101] 5. A shiftable memory according to any of the preceding clauses, wherein each memory cell comprises two memory elements, such as bit cells, connected in series.

[0102] 6. A shiftable memory according to item 5, wherein the shifting of two serially connected memory elements is controlled using two different control signals, wherein the two different control signals operate in two different phases.

[0103] 7. A shiftable memory according to item 6, wherein the control signal is a clock signal and / or wherein the two control signals are inverted or offset relative to each other.

[0104] 8. A shiftable memory according to any one of items 6-7, wherein the control signal controls the shift logic element.

[0105] 9. A shiftable memory according to any one of the preceding clauses, wherein the memory cells are composed of MOSFETs.

[0106] 10. A shiftable memory according to any of the preceding clauses, wherein the memory cells are of a five-transistor (5T) or six-transistor (6T) CMOS static random access memory type, without a bit line connection and / or without a bit line pass gate.

[0107] 11. The shiftable memory according to item 10, wherein each memory cell comprises:

[0108] - a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming a first storage node (Q) and an inverted first storage node Two cross-coupled inverters;

[0109] - Connected to the first storage node inverting a fifth transistor (M5);

[0110] - optionally, a sixth transistor (M6) connected to the first storage node (Q);

[0111] - A first word line (WL1) connected to the fifth transistor (M5), the first word line (WL1) controlling the first inverted storage node access; and

[0112] - Optionally, a second word line (WL2) connected to the sixth transistor (M6), said second word line (WL2) controlling access to the first storage node (Q).

[0113] 12. The shiftable memory according to item 6 and item 11, wherein the control signal is connected to a word line or a control line of the memory cell.

[0114] 13. The shiftable memory according to any of the preceding clauses, wherein the memory cell is implemented as a data recovery and amplification unit, such as an inverter.

[0115] 14. The shiftable memory according to item 13, wherein the restoration and amplification unit is implemented as a complementary transistor pair.

[0116] 15. The shiftable memory according to any one of items 13-14, wherein each memory cell comprises a data recovery and amplification unit and a switching element connected in series, and a capacitor for storing a bit value connected in parallel.

[0117] 16. A shiftable memory according to any of the preceding clauses, wherein the output of the chain of memory cells is connectable to the first serial output data port via one or more multiplexers.

[0118] 17. The shiftable memory according to any of the preceding items further includes at least one second serial output data port, wherein the output data logic is also configured to connect the output of any one of the memory cell chains to the second serial output data port, or at least one second parallel output data port and at least one second read shift register, which is configured to serially collect serial output data from the output of any one of the memory cell chains.

[0119] 18. A shiftable memory according to item 17, wherein the controller is configured to shift two chains of memory cells in parallel with the first serial output data port and the second serial output data port, respectively.

[0120] 19. The shiftable memory according to any of the preceding clauses, wherein the controller is further configured to shift data towards an output data port, wherein only data in memory cells having no valid data in the next adjacent memory cell are shifted towards the output data port.

[0121] 20. A shiftable memory according to item 19, further comprising a separate control signal for each bit within a row.

[0122] 21. A shiftable memory according to any of the preceding clauses, wherein a memory cell is separated by two series-connected switching elements, such as a first switching element, such as a first transistor; and a second switching element, such as a second transistor.

[0123] 22. A shiftable memory according to any of the preceding clauses, wherein each row is connected to a word line signal connected to all first switching elements of the row, and wherein each column is connected to a select signal connected to all second switching elements of the column.

[0124] 23. A shiftable memory according to any one of items 1-21, wherein each row is connected to at least two word line signals, wherein the at least two word line signals are alternately connected to the first switching elements of the row, and wherein each column is connected to a selection signal connected to all second switching elements of the column.

[0125] 24. A shiftable memory according to any of the preceding clauses, wherein the controller is further configured to control supply voltage levels of rows and / or columns and / or for individual memory cells of the shiftable memory.

[0126] 25. A shiftable memory according to any of the preceding clauses, further comprising a configurable number n of serial output data ports, wherein the controller is configured to shift n chains of memory cells in parallel with the n serial output data ports.

[0127] 26. The shiftable memory according to any one of items 18-25 further comprises output logic, wherein the controller is configured to use the output logic to perform logic operations on the first serial data output, the second serial output data port and an optional configurable number n of serial output data ports.

[0128] 27. The shiftable memory according to item 26, wherein the controller is configured to perform the operation based on an external command or based on a logic value on an input port of the shiftable memory.

[0129] 28. The shiftable memory according to any of the preceding items further includes at least one second serial input data port, wherein the input data logic is also configured to connect the second serial input data port to the input of any one in the memory cell chain, or at least one second parallel input data port and at least one second write shift register, which is used to serially shift the input data to the input of any one in the memory cell chain.

[0130] 29. A shiftable memory according to item 28, wherein the controller is configured to shift data from the first and second serial input data ports into the two parallel chains of memory cells in parallel.

[0131] 30. The shiftable memory according to any of the preceding clauses, further comprising a configurable number m of serial input data ports, wherein the controller is configured to shift data from the m serial input data ports into the m memory cell chains in parallel.

[0132] 31. A shiftable memory according to any preceding clause, the memory being configured to simultaneously shift data in through a serial input data port and shift data out through a serial output data port.

[0133] 32. A shiftable memory according to any of the preceding clauses, wherein the controller is configured to shift a plurality of rows in parallel.

[0134] 33. A shiftable memory according to any one of the preceding items, wherein the shiftable memory receives a first clock signal or an enable signal for shifting data in a memory cell chain, and wherein the shiftable memory includes a clock generation unit for generating a second clock signal or an enable signal based on the first clock signal.

[0135] 34. A shiftable memory according to any of the preceding clauses, wherein the shiftable memory comprises an internal dynamically configurable enable signal for shifting data in the chain of memory cells, the internal dynamically configurable enable signal having a configurable frequency.

[0136] 35. A shiftable memory according to any of the preceding clauses, wherein the controller is further configured to shift data from the last memory cell in a row to the first memory cell in the row.

[0137] 36. A shiftable memory according to any of the preceding clauses, wherein the shifting of data in the chain of memory cells is based on a decoded logic value of an input port of the shiftable memory.

[0138] 37. A shiftable memory according to any preceding clause, configured to decode a reset instruction as an operation to shift all rows until all memory cells have been written.

[0139] 38. A shiftable memory according to any one of the preceding clauses, wherein the shiftable memory is a static random access memory.

[0140] 39. A shiftable memory according to any one of the preceding items, wherein the shiftable memory is a dynamic random access memory.

[0141] 40. The shiftable memory according to item 39, wherein a refresh operation of the dynamic random access memory is performed by shifting each row by at least one step.

[0142] 41. A shiftable memory according to any of the preceding clauses, wherein the row / rows are divided into a plurality of sections and wherein an input data port and / or an output data port is connectable to each section.

[0143] 42. A method of operating a shiftable memory, the method comprising the steps of:

[0144] - shifting data of at least one row of a shiftable memory having a plurality of memory cells arranged in rows and columns, wherein the memory cells of a row are interconnected to form a chain of memory cells;

[0145] - sequentially read the shifted data from the first serial output data port of the shiftable memory connected to the output of any one of the memory cell chain, or sequentially shift the data to the internal read shift register and read the data from the internal read shift register through the parallel output data port, or sequentially write the data to the first serial input port of the shiftable memory connected to the input of any one of the memory cell chain, or write the data from the parallel input data port to the internal write shift register and sequentially shift the data from the internal write shift register to the input of any one of the memory cell chain.

[0146] 43. Method of operating a shiftable memory according to item 42, wherein at least two rows are shifted in parallel.

[0147] 44. A method of operating a shiftable memory according to any of items 42-43, wherein two rows are shifted in parallel to read data from two different ports simultaneously in a dual port memory configuration.

[0148] 45. A method of operating a shiftable memory according to any of items 42-44, wherein two rows are shifted in parallel to write data simultaneously from two different ports in a dual port memory configuration.

[0149] 46. ​​A method of operating a shiftable memory according to any of items 42-45, wherein n rows are shifted in parallel to read data from n different ports simultaneously in a multi-port memory configuration.

[0150] 47. A method of operating a shiftable memory according to any one of items 42-46, wherein m rows are shifted in parallel to write data simultaneously from m different ports in a multi-port memory configuration.

[0151] 48. A method of operating a shiftable memory according to any one of items 42-47, wherein each memory cell comprises two memory elements, such as bit cells, connected in series, and wherein a first control signal is used to shift the first of the two memory elements and a second control signal is used to shift the second of the two memory elements.

[0152] 49. A method of operating a shiftable memory according to item 43, wherein the first and second control signals operate at two different phases and / or wherein the first and second control signals are inverted or offset relative to each other.

[0153] 50. The method for operating a shiftable memory according to any one of items 42 to 49, further comprising the step of shifting each row by at least one step, thereby performing a refresh operation of the shiftable memory.

[0154] 51. A method of operating a shiftable memory according to any one of items 42-50, wherein the shiftable memory is a memory according to any one of items 1-40.

[0155] 52. A method of operating a shiftable memory according to any one of items 42-51, wherein one / more rows are divided into a plurality of parts, and wherein data in each part is shifted in parallel to input data to the plurality of parts in parallel and / or output data from the plurality of parts in parallel.

Claims

1. A shiftable memory, comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected to form a chain of memory cells; at least one first serial output data port; output data logic for connecting the output of any one of the memory cell chains to the first serial output data port, or to at least one first parallel output data port and at least one read shift register configured to serially collect serial output data from the output of any one of the memory cell chains; and / or at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any one of the memory cell chains, or to at least one parallel input data port and at least one write shift register for serially shifting input data to an input of any one of the memory cell chains; and a controller configured to control shifting of data in the memory cell chain, the controller further configured to control the output data logic and / or the input data logic, Wherein the controller is configured to shift the chains of memory cells individually.

2. The shiftable memory according to claim 1, wherein: The shiftable memory is capable of operating without bit lines interconnecting the memory cells within the columns, wherein the data is serially shifted into and / or out of a chain of memory cells during write and read operations.

3. A shiftable memory according to any one of the preceding claims, wherein: Each memory cell includes two memory elements connected in series.

4. The shiftable memory according to claim 3, wherein: Two different control signals are used to control shifting of the two serially connected memory elements, wherein the two different control signals operate in two different phases.

5. The shiftable memory according to any one of the preceding claims, further comprising at least one second serial output data port, wherein: The output data logic is also configured to connect the output of any one of the memory cell chains to a second serial output data port, or at least one second parallel output data port and at least one second read shift register, which is configured to serially collect serial output data from the output of any one of the memory cell chains.

6. The shiftable memory according to claim 5, wherein: The controller is configured to shift two chains of memory cells in parallel to the first and second serial output data ports, respectively.

7. The shiftable memory according to any one of claims 5 to 6, wherein: The controller is configured to shift two chains of memory cells in parallel with an arbitrary configurable delay between the two chains of memory cells.

8. The shiftable memory according to any one of claims 5 to 7, further comprising output logic, wherein: The controller is configured to use the output logic to control the first serial output data port and / or the second serial output data port and a configurable number of n The serial output data port performs logic operations.

9. The shiftable memory according to claim 8, wherein: The controller is configured to perform an operation based on an external command or based on a logic value on an input port of the shiftable memory.

10. The shiftable memory according to any one of claims 8 to 9, wherein: The controller can also be configured to connect a result of the logic operation to the at least one first serial input data port and serially shift the result to any one of the chain of memory cells.

11. A shiftable memory according to any one of the preceding claims, wherein: The controller is further configured to shift data toward the output data port, wherein data in only memory cells that do not have valid data in a next adjacent memory cell is shifted toward the output data port, the memory further comprising a separate control signal for each bit within a row.

12. A shiftable memory according to any one of the preceding claims, wherein: The storage cell is separated by two switching elements connected in series.

13. A shiftable memory according to any one of the preceding claims, wherein: Each row is connected to a word line signal connected to all first switching elements of the row, and wherein each column is connected to a select signal connected to all second switching elements of the column.

14. A shiftable memory as claimed in any preceding claim, the memory being configured to simultaneously shift data in through the serial input data port and shift data out through the serial output data port.

15. A shiftable memory according to any one of the preceding claims, wherein: The controller is configured to shift a plurality of rows in parallel.

16. A shiftable memory according to any one of the preceding claims, wherein: The shiftable memory comprises an internal dynamically configurable enable signal for shifting data in the chain of memory cells, the internal dynamically configurable enable signal having a configurable frequency.

17. A shiftable memory as claimed in any preceding claim, configured to decode a reset instruction as an operation to shift all rows until all memory cells have been written.

18. A shiftable memory according to any one of the preceding claims, wherein: The shiftable memory is a dynamic random access memory, wherein a refresh operation of the dynamic random access memory is performed by shifting each row by at least one step.

19. The shiftable memory according to claim 18, wherein: The controller is configured to simultaneously perform the refresh operation and read data from and / or write data to the memory cell chain.

20. The shiftable memory according to claim 3, wherein: The two serially connected memory elements are a bit cell.

21. The shiftable memory according to claim 8, wherein: The output logic is arithmetic logic.

22. The shiftable memory according to claim 12, wherein: The two switching elements connected in series are a first switching element and a second switching element.

23. The shiftable memory according to claim 22, wherein: The first switching element is a first transistor; the second switching element is a second transistor.

24. The shiftable memory according to claim 13, wherein: Each row is connected to at least two word line signals, wherein the at least two word line signals are alternately connected to the first switching elements of the row, and wherein each column is connected to a selection signal connected to all second switching elements of the column.

25. A method for operating a shiftable memory, the method comprising the following steps: shifting data of at least one row of a shiftable memory having a plurality of memory cells arranged in rows and columns, wherein the memory cells of the row are interconnected to form a chain of memory cells, wherein the chain of memory cells is shifted individually; The shifted data is sequentially read from the first serial output data port of the shiftable memory connected to the output of any one of the memory cell chains, or the data is sequentially shifted to an internal read shift register and read from the internal read shift register through a parallel output data port, or the data is sequentially written to the first serial input port of the shiftable memory connected to the input of any one of the memory cell chains, or the data is written from the parallel input data port to the internal write shift register and the data is sequentially shifted from the internal write shift register to the input of any one of the memory cell chains.

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