Electronic device and corresponding self-test method

Abstract

Embodiments of the present disclosure relate to electronic devices and corresponding self-test methods. An electronic device (such as an e-fuse) includes an analog circuit device configured to be set to one or more self-test configurations. To this end, the device has a self-test controller circuit device, which includes: an analog configuration and a sensing circuit configured to set the analog circuit device to one or more self-test configurations and sense a test signal that appears in the analog circuit device set to such a self-test configuration; a data acquisition circuit configured to collect the test signal sensed at the analog sensing circuit device and convert the sensed test signal to digital; and a fault event detection circuit configured to check the test signal converted to digital against a reference parameter. The device includes a self-test controller integrated therein, which is configured to control parts or levels of the device to configure circuits, acquire data, and control test execution under the coordination of a test sequencer.

Description

[0001] Priority declaration

[0002] This application claims the benefit of priority from Italian Patent Application No. 102020000020422, filed on August 25, 2020, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present description relates to electronic devices. One or more embodiments may be applied to provide self-test capabilities in electronic devices. For example, one or more embodiments may be applied in power control for vehicle electrification in the automotive industry. Background Art

[0004] Various technology areas can benefit from devices that exhibit self-test capabilities.

[0005] For example, these areas may include: power control electronics for automotive applications that may be controlled via a host microcontroller; devices that implement diagnostic and protection functions for power components to facilitate safe control behavior under fault conditions; applications with strict specifications for device failure time (e.g., FIT<1); devices that can detect failed parts in a timely manner and take corresponding actions to facilitate achieving a safe condition; and automatic diagnostic functions that remain active during normal operation.

[0006] It may be desirable to monitor in real time a circuit control chain of diagnostic / protection mechanisms associated with an internal power section or an external power section.

[0007] To this end, desirable features of a device provided with self-test features may include the ability to force, sense, process, and detect operations in order to examine device behavior over time with the ability to communicate faults to an embedded system (e.g., a host controller), or to take action on the device hardware in order to implement application safety specifications.

[0008] Keeping device behavior substantially unchanged while monitoring / testing certain functions while preserving data context represents another desirable feature as it facilitates fully restoring operating conditions once certain protection features have been tested.

[0009] Another point of interest is to define standard methodologies and / or common design architectures that can be migrated between different devices. This can improve flexibility of use while also reducing design effort and development cycles, thus having a beneficial impact on costs.

[0010] These factors may help overcome deficiencies associated with "ad hoc" solutions, which may be specific to a device and therefore difficult to be compatible with the desired programmable control of a host controller and / or with hardware automatic activation.

[0011] This may be the case, for example, with a currently available technology from Mentor Tessent that is based on a DFT proprietary architecture and serial methodology.

[0012] Since this conventional approach is specific to certain field built-in self-test (BIST) applications, this traditional approach may exhibit poor flexibility and portability between products / platforms. It may also exhibit inherent slowness due to serial access (making this solution hardly suitable for latency-critical checks), and may also impose restrictions on the time interval of in-application testing related to specific device states.

[0013] There is a need in the art to help overcome the above-mentioned shortcomings. Summary of the invention

[0014] One or more embodiments may be directed to an electronic device.

[0015] One or more embodiments may be directed to a corresponding method.

[0016] One or more embodiments may provide one or more of the following advantages: a programmable set of self-test routines in applications for device monitoring; flexible control: single test / sequence execution, serial execution / parallel execution; reduced development costs associated with enriching the self-test set by adding controls and registers; and easier portability between different projects / platforms with similar requirements.

[0017] One or more embodiments promote architectural standardization in providing a test sequencer with good design configurability and programmability, which may represent a valuable alternative to more specific / ad hoc solutions.

[0018] One or more embodiments are suitable for use in environments where real-time monitoring of hardware resources is desired to facilitate controlled and safe behavior when failures occur.

[0019] One or more embodiments may provide an alternative for simultaneous execution of multiple self-test selections (where applicable); for example, self-test execution may be initiated under hardware control in certain time windows, in certain specific device states defined by a finite state machine or FSM, and in the presence of well-defined application events.

[0020] For example, in those applications where latency is not critical (so-called "soft" event monitoring), one or more embodiments may be implemented in software via a microcontroller. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments will now be described by way of example with reference to the accompanying drawings, in which:

[0022] Figure 1A and Figure 1B is an example of a functional block diagram of a possible embodiment according to the present description,

[0023] Figure 2 is a functional block diagram example of possible details of the implementation of the embodiment,

[0024] Figure 3 is a diagrammatic example of possible operation of a test sequencer in an embodiment of the present description,

[0025] Figure 4 is a diagrammatic example of possible operations of a finite state machine (FSM) in an embodiment, and

[0026] Figure 5 is a combined diagram / flow chart example of performing testing in an embodiment of the present description. DETAILED DESCRIPTION

[0027] In the following description, one or more specific details are described to provide a deeper understanding of examples of embodiments of the present description. These embodiments can be obtained without one or more of the specific details, or by using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not described or explained in detail so as not to obscure certain aspects of the embodiments.

[0028] References to "an embodiment" or "one embodiment" in the framework of this description are intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this description do not necessarily refer to one and the same embodiment.

[0029] Furthermore, in one or more embodiments, particular conformations, structures, or characteristics may be combined in any suitable manner.

[0030] The headings / references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0031] In the figure, reference numeral 10 denotes a device (electronic circuit) as a whole, in which a collection of self-test features in applications are implemented at an architectural level for device protection / diagnostic function monitoring.

[0032] Figure 1A and Figure 1Bis an architectural diagram of the interaction between the self-test controller 12 and the functionality available in the hybrid analog / digital electronic circuits (in application) that may be controlled or observed to enable monitoring and diagnostic checks.

[0033] Those skilled in the art will further appreciate that some of these functions may not be visible in the figures because the instant detailed description is primarily directed to functions discussed as examples of functions involved in self-test operations as discussed herein.

[0034] Figure 1A and Figure 1B The functions illustrated in the example are intended to cooperate with a self-test controller (such as 12) can be found in a variety of electronic devices. Although possible applications to e-fuses will be discussed below by way of example, these embodiments are largely "transparent" to the properties and characteristics of device 10.

[0035] One or more embodiments illustrated herein may include a configurable and programmable digital controller 12 (self-test controller in application) capable of: managing a collection of control signals with the ability to force device configuration, acquisition ports for digital conversion values, data processing and fault / event simulation to perform real-time testing during normal operation of the device 10; and reacting to detected possible faults, communicating with (for example) a host controller and / or taking appropriate measures for delay / critical situations or specific safety specifications.

[0036] exist Figure 1A and Figure 1B In the figure of FIG. 1 , block 14 represents a fail-safe device control circuit arrangement, which is illustrated here as being incorporated into the circuit 10, but may also be arranged outside the circuit 10. The circuit arrangement 14 is intended to cooperate with a control interface 142 in the self-test controller 12, exchanging signals therewith, such as abort / stop control signals from the fail-safe control circuit arrangement 14 to the self-test controller 12 (in order to control the operation of the latter), and / or diagnostic / alarm control signals from the self-test controller 12 to the fail-safe device control circuit arrangement 14 (in order to implement a low-latency fail-safe protection mechanism).

[0037] For example, via a programming interface (I / F) 144 for host-controller communications, possibly in conjunction with a serial peripheral interface (SPI) 144A, communications may be programmed as desired.

[0038] In one or more embodiments, the controller 12 can be configured to cooperate with multiple circuit elements or stages in the device, including, for example, an analog sensing stage 16, an analog-to-digital (A / D) conversion stage 18, and a fault / event detection stage 22 that form the functional backbone of the device 10.

[0039] Figure 1A and Figure 1B The diagrams are examples of the flexibility of one or more embodiments in accommodating different devices 10 and different usage contexts.

[0040] For example, Figure 1A As illustrated: analog sensing stage 16 may include a current sensing circuit; stage 18 may include a current sensing analog-to-digital (A / D) converter; and fault / event detection stage 22 may include a hard short circuit current (HSHT) and over current (OVC) detection stage.

[0041] On the contrary, Figure 1B As illustrated: analog sensing stage 16 may include a voltage sensing circuit, for example, sensing the drain-source of a power field effect transistor (such as a power MOS); stage 18 may include a voltage monitoring analog-to-digital (A / D) converter; and fault / event detection stage 22 may include a voltage monitoring fault detection stage.

[0042] The foregoing is also a (further) example of the fact that, as previously discussed, the device 10 as illustrated herein may include alternative / additional functionalities that are not visible in the figures for the sake of simplicity.

[0043] In one or more embodiments, analog sensing stage 16 may be configured to cooperate with controller 12 via analog (configuration) interface (I / F) 162 to issue control signals to arrange analog circuitry (not explicitly visible in the figure) in device 10 according to a selected self-test configuration.

[0044] As described above, and as discussed in the examples below, in the case of electronic fuses, these self-test configurations can include multiple self-test selection options (whose execution can be managed sequentially via corresponding hardware) such as: external short circuit fault detection chain monitoring; external power MOS saturation fault detection chain monitoring; and external power MOS stuck-on detection monitoring.

[0045] The A / D conversion stage 18 as illustrated herein may be configured to acquire digitally converted measurements in the device 10 for use in data refinement and / or inspection.

[0046] To this end, the data collected in this way by the stage 18 can be transmitted to the controller 12 via the data acquisition interface 182 .

[0047] As illustrated, the fault / event detection stage 22 as illustrated herein may be configured to cooperate with a fault / event simulation interface 222 in the controller 12 to set configuration design parameters (eg, thresholds, etc.) for fault / event generation and / or simulation.

[0048] As illustrated, data path configuration features (as schematically represented by 20 ) may be provided intermediate the acquisition circuitry 18 , 182 and the fault event detection circuitry 22 , 222 to facilitate multiple digital processing data path configurations for test signals converted to digital.

[0049] Various suitable types of calculations may be implemented in self-test controller 12 (eg, differential or delta measurements for data acquisition).

[0050] In one or more embodiments, self-test configuration and execution may be programmed via a serial peripheral interface (SPI), such as 144A.

[0051] For example, such an interface may be configured to exchange data between a microcontroller and small peripherals such as shift registers, sensors, and SD cards.

[0052] In one or more embodiments, dedicated registers and fields may be mapped into the device address space with the ability to report the status for each self-test run. For example, IDLE / RUN / END / ABORT test information may be provided to the host controller via registers mapped in the device address space.

[0053] Figure 2 The block diagram is as follows Figure 1A and Figure 1B An exemplary representation of a possible embodiment of a controller 12 included in the device 10 is illustrated in . The main functionality of the controller 12 illustrated herein may be represented by a test sequencer circuit (test sequencer for short) 120 .

[0054] The test sequencer 120 may be configured to control the execution of defined self-tests to be run, other (internal) functions of the self-test controller 12 are intended to be combined with the previously described Figure 1A and Figure 1B Describes the interface interactions.

[0055] For example, Figure 2 The block diagram illustrates a self-test controller function interacting with a device control interface 142, which is configured to receive an abort / end control signal from a control source (at 1421) and transmit the abort / end control signal to a test sequencer 120 when delay critical control information is issued (at 1422) toward a device control entity.

[0056] Similarly, the self-test controller function that interacts with the programming interface 144 can be configured to receive, decode and transmit to the test sequencer 120 test selection and configuration data (at 1441) while collecting into registers and transmitting data / status information and fault checks for monitoring of each self-test performed (at 1442) from the test sequencer 120.

[0057] Figure 2 The figure is also an example of a device control interface 142 that is configured to exchange automatic start control information with the test sequencer 120 at 1423 for those situations or tests that begin execution based on hardware conditions and are not controlled by software through a programming interface (such as, 144, 1441).

[0058] like Figure 2 As illustrated, the self-test controller 12 may also be configured, depending on the test being performed, to issue analog and data path configuration controls via interface 162, receive test data from the digital data path via interface 182, and elaborate / check (e.g., by performing incremental measurements) the information received at 1821. In addition, the self-test controller 12 may be configured to manage the selection of tested protection faults by disabling true fault flags of the device to avoid false fault signaling, and to perform testing by collecting results of simulation of fault / event detection at 2221 via interface 222.

[0059] Figure 3 is an example of a possible solution that may be employed in the test sequencer 120 to provide abort / end mapping information for the various tests starting with the information provided to the controller 12 at 1421 .

[0060] Previously discussed Figure 1A and Figure 1B is the current sensing ( Figure 1A ) and voltage (Vds) monitoring ( Figure 1B ) are examples of circuits (stages) that may be involved in the self-test procedure in the case of the test sequencer 120 in the self-test controller 12. The test sequencer 120 in the self-test controller 12 may be configured to provide a sequencer for both tests (i.e., FSM1 ( Figure 1A ) and FSM2 ( Figure 1B Each test in )) executes this procedure.

[0061] Figure 3is an example of an embodiment of a test sequencer 120 configured to perform three tests T1, T2, T3, wherein corresponding test enable signals TE1, TE2, TE3 are derived from the configuration selection information received at 1441. Each test involves a respective finite state machine FSM1, FSM2 and FSM3, wherein the three FSMs are linked together so as to be able to support both a single (individual) test run and a sequence of tests (e.g., a sequence of two tests or three tests as exemplified herein).

[0062] like Figure 3 As shown, the completion of the execution of T1 controlled by FSM1 generates a signal T1END in response to being enabled by TE2, and starts executing the test T2 controlled by FSM2; similarly, the completion of the test T2 by FSM2 generates a signal T2END in response to being enabled by TE3, and starts executing T3 controlled by FSM3.

[0063] like Figure 3 As illustrated, the completion of the execution of the last test (eg, T3 executed by FSM3) generates a signal T3END to notify the preceding FSMs (here, FSM1 and FSM2) that the test sequence has been completed.

[0064] In this way, each FSM can be transitioned to its idle state (as shown below in conjunction with Figure 4 discussed), while generating a self-test end signal STE, which notifies the device 10 including the self-test controller 12 that the test sequence has been completed, wherein the corresponding data / status information available in the relevant registers can be passed (such as Figure 2 ) programming interface 144, 1442 for access.

[0065] Figure 3 Exemplary signals exchanged between the previously discussed FSMs that facilitate initiation and / or termination of execution of each self-test are illustrated.

[0066] For example, if combined Figure 4 As discussed, in response to execution of FSM3 being terminated (T3END), signals may be generated for FSM2 and FSM1 to complete their execution and / or transition to an idle state (STE).

[0067] Figure 4 is a finite state machine configured to perform certain tests (i.e. Figure 3 An example of a possible arrangement of FSM1 or FSM2 or FSM3 in , and includes four states, namely: a self-test idle state at 1001; a self-test running state at 1002; a self-test waiting state at 1003; and a self-test end state at 1004.

[0068] like Figure 4 As shown, in response to a test start signal and under the control of the device fail-safe function, the state of the FSM can be switched from the self-test idle state at 1001 to the self-test run state 1002, and the FSM may return to the self-test idle state from the self-test run state 1002 in response to a test termination signal so as to (immediately) stop the self-test execution.

[0069] The transition of the FSM from the self-test running state 1002 to the self-test ending state 1004 via the self-test waiting state 1003 may be generated by the test running ending signal and the test ending signal subsequently issued.

[0070] The self-test wait state 1003 is advantageously introduced to allow the (analog) circuit under test to return to its normal configuration and operation after the self-test execution is completed and the specific circuit configuration required to run the test has been removed.

[0071] Finally, the transition from the self-test end state 1004 back to the self-test idle state at 1001 can be in response to a last test end signal, where the machine may transition from the self-test idle state 1001 to the self-test end state 1004 in response to a test skip signal received from the "last" FSM of the test sequencer 120, indicating the end of execution of the programmed / configured self-test sequence.

[0072] Transitioning from the self-test idle state 1001 to the self-test end state 1004 in response to a test skip signal facilitates execution of the skipped test in case this is not included in the configured test sequence. Figure 3 , if the programmed self-test sequence includes execution of T1 and T3 (not T2), once T1 is completed and the T2 FSM is (nominally) enabled, assertion of the test skip signal facilitates moving directly to the corresponding self-test end state 1004 (without actually executing T2) which enables the FSM of T3 to begin.

[0073] Figure 5 is a hybrid diagram / flowchart representation example applied to an embodiment of a device 10 that embeds, for example, an electronic fuse (e-fuse) functionality.

[0074] In the exemplary case discussed herein, such a device 10 is provided with a self-test controller 12 as discussed previously. For example, the device (electronic fuse) 10 may be configured to respond to a corresponding (auto) start signal being asserted, for example, S_T_START=1 (see, for example, Figure 2 142, 1423) in the figure switches from the unlocked state 2001 (normal operation) to the self-test state 2002.

[0075] like Figure 5As illustrated, persistence in the self-test state 2002 depends on whether a watchdog (WD) timeout interval may expire and / or a hardware lockout condition (HWLO=1), both of which are examples of abort signals from the device fail-safe control logic as described above. For example, this may result in the self-test sequence execution being aborted and the device finite state machine being converted from the self-test state 2002 to a fail-safe state (in the current example, the so-called lockout state 2003).

[0076] Otherwise, as a result of the self-test being completed, the system transitions back to the unlocked state 2004. For example, this may be in response to the stop signal S_T_STOP=1 being asserted (eg, see again Figure 2 142, 1423) or in response to the stop signal S_T_STOP = 1 from the programming interface or device control is asserted (see Figure 2 144-1441 or 142-1421 in the English version).

[0077] Figure 5 The right hand side of is an example of a possible sequence of steps or actions performed by the self-test controller 12 after activation by the device 10 (in this case the e-fuse) with a corresponding device FSM control transition (unlock→selftest→unlock).

[0078] Step or action 3001 is an example of a current sensing self-test configuration for an e-fuse (here considered as an example of device 10), which results in current sensing self-test configuration parameters being set at 3002, such as:

[0079] CR#1→S_T_CFG[2:0]=xx1 (x indicates “don’t care” bit)

[0080] CR#2→OVC_THR=<User Option>

[0081] CR#3→HSHT_THR=<User Option>

[0082] For example: the first parameter CR#1 can indicate the selected self-test that the user wants to perform; in an embodiment, the least significant bit (S_T_CFG(0)) of the configuration word S_T_CFG[2:0] can select the current sensing self-test to be performed; and the two subsequent parameters CR#2 and CR#3 can indicate that the user-selected thresholds OVC_THR and HSHT_THR are set to overcurrent (OVC_THR) fuse limit check or hard short circuit current (HSHT_THR) limit check in order to test the correct behavior of the current sensing protection activation.

[0083] The block designated 3003 is an example of a current sensing self test being performed (in response to S_T_START=1 being asserted).

[0084] Figure 5 Boxes 3004, 3005, and 3006 illustrated in FIG. 3004 are examples of various actions that may be performed via Figure 1A and Figure 1B This is accomplished by stages 16, 18, and 22 in device 10 cooperating with self-test controller 12 in the device.

[0085] These actions may include: Block 3004 —turning on / pulling down a current generator in the e-fuse 10 to produce an (additional) voltage drop across the current sense amplifier input, depending on the selected self-test configuration;

[0086] Block 3005—Analog-to-digital (A / D) conversion of current sensing circuit measurements, performing an optional differential measurement between the self-test measurement and (for example) the last measurement performed before the device 10 entered a self-test state, as per 3004, the self-test state being available and stored in the device status register to check the correct functionality of all current sensing measurement circuit chains. In addition, the A / D conversion can be used in conjunction with the OVC and HSHT threshold settings (CR#2 and CR#3) to verify that fault protection is activated when the conversion value exceeds the selected threshold, so that the selected self-test also covers the protection trigger. The self-test measurement of both the differential conversion and the protection fault simulation check results can be provided on the status register of the device 10;

[0087] Block 3006 —Self-test conclusion with current generator in e-fuse turned off / pulled down to restore normal voltage drop across current sense amplifier input, where current sense A / D conversion is interrupted during these time frames.

[0088] Blocks 3004 and 3005 may have a (joint) TS_T_ACTIVE duration, and block 3006 may have a TS_T_WAIT duration, in order to have a self-controlled test duration and a safe transition from the self-test configuration to the normal operating mode configuration.

[0089] During the TS_T_ACTIVE and TS_T_WAIT time frames, the fast trip protection and slow trip protection of the e-fuse corresponding to the hard short circuit (HSHT) and over current (OVC) conditions discussed previously may be disabled to allow their functional checks to continue operating while all other protection measures are active while avoiding affecting the device 10 (e.g., the e-fuse).

[0090] Figure 5 Block 3007 in the example is where a test complete signal is sent back to the device controller ( Figure 1A and Figure 1B An example of completion of a self-test procedure (e.g., current sensing) of the device (e.g., e-fuse) in block 14 and interface 142 so that the device (e.g., e-fuse) can be returned to an unlocked state as illustrated by 2004.

[0091] As discussed, Figure 5 is an example of an embodiment applied to a self-test configuration that is programmable through a serial peripheral interface (SPI) of a device having dedicated registers and fields mapped within the device address space, and utilizing multiple self-test configurations supported by sequentially managing execution via hardware.

[0092] The (purely exemplary) case considered is that of an electronic device 10 comprising an electronic fuse (e-fuse).

[0093] Such a device 10 may include analog sensing circuitry (see Figure 1A and Figure 1B In box 16 in the figure, the analog sensing circuit device (via interface 162) can be configured into multiple self-test configurations, for example, the multiple self-test configurations include: an external short circuit fault detection chain monitor; an external power MOS saturation fault detection chain monitor; and an external power MOS insertion detection monitor, which, when set to those self-test configurations, has such analog sensing circuits that are capable of sensing corresponding (voltage and (or current)) test signals occurring in the analog circuit device.

[0094] Similarly, it will be assumed that, in the (purely exemplary) cases discussed herein, digital processing circuitry (of any type known for this purpose to a person skilled in the art) may be provided to perform processing on the data acquisition as required (e.g. differential measurement calculations or “delta” measurement calculations and / or comparisons with certain thresholds).

[0095] It is also assumed that status reporting of each self-test run as well as idle / running / finished / aborted test information can be provided to the host controller via registers mapped in the device address space.

[0096] Tables I and II below are examples of (purely indicative and non-limiting) values ​​for control, and status register bits and fields, which may be employed to control and monitor via a programmable interface a self-test application embedded in a device 10 of a self-test controller 12 as previously described.

[0097] Specifically, Table I is an example of a device control register view for self-test software configuration and control, where the columns in the table indicate: first column: bit position in the control register dedicated to self-test; second column: default value at reset; third column: bit / field name; and fourth column: functional description according to the embodiment under consideration.

[0098] Table I - Device Control Register View

[0099]

[0100]

[0101] In contrast, Table II is an example of a device status register view for self-test software configuration (e.g., current sensing), where the columns in the table indicate: first column: bit position in the device status register; second column: default value at reset; third column: bit / field register name; fourth column: functional description according to the embodiment discussed as an example; and fifth column: bit / field reset strategy (itself not relevant to the embodiment).

[0102] Table II - Device Status Register View

[0103]

[0104]

[0105] The electronic device illustrated herein (e.g., device 10 embedded with an e-fuse) may include an analog circuit device and a self-test control circuit device (e.g., 12), wherein the analog circuit device is configured to be set to at least one self-test configuration, and the self-test control circuit device further includes: an analog configuration and sensing circuit (e.g., 16, 162), configured to set the analog circuit device to at least one self-test configuration and sense a test signal appearing in the analog circuit device set to the at least one self-test configuration; a data acquisition circuit (e.g., 18, 182), configured to acquire the sensed test signal and convert the sensed test signal into digital; and a fault event detection circuit (e.g., 22, 222), configured to check the test signal converted into digital against a reference parameter.

[0106] In an electronic device as illustrated herein, a self-test controller circuit device may include a test coordination circuit device (e.g., test sequencer 120) having an input port (e.g., 142, 1421) configured to receive a device control signal indicating a set of self-test events, wherein the analog configuration and sensing circuit (e.g., 16, 162) is configured to set the analog circuit (e.g., T1, T2, T3) to multiple self-test configurations (e.g., TE1, TE2, TE3) according to the device control signal received at the test coordination circuit.

[0107] The test sequencer 120 discussed extensively above may be an example of such test coordination circuitry configured to coordinate the execution of multiple self tests.

[0108] For simplicity, this may occur in some "serial" order as described herein.

[0109] Those skilled in the art will additionally appreciate that one or more embodiments may contemplate tests that are performed at least partially simultaneously (ie, in parallel with one another).

[0110] In an electronic device as illustrated herein, the test coordination circuit device (as illustrated by sequencer 120) may include a finite state machine (e.g., 1001, 1002, 1003, 1004) that is sensitive to a transition signal (e.g., ST_T_START, S_T_STOP), causing the test coordination circuit device to transition between an idle state (e.g., 2001, 2004) through a self-test state (e.g., 2002), during which the analog configuration and sensing circuit (16, 162) sets the analog circuit device to the at least one self-test configuration.

[0111] In an electronic device as exemplified herein, the finite state machine in the test coordination circuitry may be configured to transition to a locked state (eg, 2003 ) in response to a self-test being aborted during the self-test state (eg, 2002 ).

[0112] In the electronic device as illustrated herein, the self-test controller circuit device may include a data path configuration circuit (e.g., 20) between the data acquisition circuit (18, 182) and the fault event detection circuit (22, 222), the data path configuration circuit being configured to provide a plurality of digital processing data path configurations for converting the test signal to digital.

[0113] A method for operating an electronic device as illustrated herein may include activating (e.g., 142, 1423) the self-test controller circuit device, wherein in response to the self-test controller circuit being activated: the analog configuration and sensing circuit sets the analog circuit device to at least one self-test configuration, and senses a test signal appearing in the analog circuit device set to the at least one self-test configuration; the data acquisition circuit acquires the sensed test signal and converts the sensed test signal into a digital form; the fault event detection circuit checks the test signal converted into a digital form against a reference parameter, and issues at least one fault detection signal (e.g., 1442) in response to the check indicating that the test signal converted into a digital form does not match the reference parameter.

[0114] In methods as illustrated herein, activating the self-test controller circuitry may include automatic start control of the self-test controller circuitry (eg, 1423).

[0115] In the method as exemplified herein, activating the self-test controller circuit may include activating a plurality of self-test events (in the method as exemplified herein, T1, TE1; T2, TE2;

[0116] T3, TE3), wherein the analog configuration and sensing circuit device sets the analog circuit into a plurality of self-test configurations.

[0117] The details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without prejudice to the underlying principle and without departing from the scope of protection.

[0118] The claims are an integral part of the technical teaching provided herein with respect to the exemplary embodiments.

Claims

1. An electronic device comprising: an analog circuit device configured to be configurable into at least one self-test configuration; as well as A self-test controller circuit device comprising: a test coordination circuit arrangement having an input port configured to receive a device control signal indicative of a set of self-test events; an analog configuration and sensing circuit configured to set the analog circuit device to a plurality of different self-test configurations in a self-test state according to the device control signal received by the test coordination circuit device, and to sense test signals appearing in the analog circuit device set to the plurality of different self-test configurations; a data acquisition circuit configured to acquire and digitize the sensed test signal; and a fault event detection circuit configured to check the digitized, sensed test signal against a reference parameter; Wherein the test coordination circuitry includes a finite state machine configured to transition to a locked state in response to suspending a self-test during the self-test state.

2. The electronic device of claim 1, wherein the finite state machine operates in response to a transition signal that causes the test coordination circuitry to transition between idle states through the self-test state.

3. The electronic device of claim 1 , wherein the self-test controller circuit arrangement comprises a data path configuration circuit coupled between the data acquisition circuit and the fault event detection circuit, the data path configuration circuit being configured to provide a plurality of digital processing data path configurations for digitizing the sensed test signals.

4. A method of operating an electronic device having analog circuitry and self-test controller circuitry for cooperating with the analog circuitry to perform a test of the electronic device, the method comprising: activating the self-test controller circuit arrangement; responsive to activation of the self-test controller circuitry, placing the analog circuitry into a plurality of different self-test configurations in a self-test state according to device control signals received by a finite state machine, and then sensing a test signal present in the analog circuitry, the finite state machine transitioning through a self-test state and to a locked state in response to aborting self-testing during the self-test state; collecting and digitizing the sensed test signal; checking the digitized, sensed test signal against a reference parameter; as well as In response to the checking indicating that the digitized, sensed test signal does not match the reference parameter, at least one fault detection signal is generated.

5. The method of claim 4, wherein activating the self-test controller circuit arrangement comprises: Automatic start-up control of the self-test controller circuit device is performed.

6. The method of claim 4, wherein activating the self-test controller circuitry comprises: When the analog configuration and sensing circuits are configured to place the analog circuit device into the plurality of different self-test configurations, a plurality of self-test events are activated.

7. An electronic device comprising: an analog circuit device configured to be configurable into at least one self-test configuration; as well as A self-test controller circuit device comprising: an analog configuration and sensing circuit configured to set the analog circuit device to the at least one self-test configuration in a self-test state and to sense a test signal appearing in the analog circuit device set to the at least one self-test configuration; a data acquisition circuit configured to acquire and digitize the sensed test signal; a fault event detection circuit configured to check the digitized, sensed test signal against a reference parameter; a data path configuration circuit coupled between the data acquisition circuit and the fault event detection circuit, the data path configuration circuit configured to provide a plurality of digital processing data paths for digitizing the sensed test signals; test coordination circuitry comprising an input port configured to receive a device control signal indicative of at least one self-test event; Wherein the test coordination circuitry includes a finite state machine configured to transition to a locked state in response to suspending a self-test during the self-test state.

8. The electronic device of claim 7, wherein the analog configuration and sensing circuitry is configured to set the analog circuitry to a corresponding at least one self-test configuration in accordance with the device control signal received at the test coordination circuitry.

9. The electronic device of claim 8, wherein the finite state machine operates in response to a transition signal that causes the test coordination circuitry to transition between idle states through the self-test state.

10. A method of operating an electronic device having analog circuitry and self-test controller circuitry for cooperating with the analog circuitry to perform a test of the electronic device, the method comprising: activating the self-test controller circuit arrangement; responsive to activation of the self-test controller circuitry, setting the analog circuitry to at least one self-test configuration in a self-test state according to device control signals received by a finite state machine and then sensing a test signal present in the analog circuitry, the finite state machine transitioning through the self-test state and transitioning to a locked state in response to aborting self-testing during the self-test state; collecting and digitizing the sensed test signal; checking the digitized, sensed test signal against a reference parameter; In response to the checking indicating that the digitized, sensed test signal does not match the reference parameter, at least one fault detection signal is generated.

11. The method of claim 10, wherein activating the self-test controller circuitry comprises: Automatic start-up control of the self-test controller circuit device is performed.

12. The method of claim 10, wherein activating the self-test controller circuitry comprises: At least one self-test event is activated when the analog configuration and sensing circuitry is configured to place the analog circuitry into the at least one self-test configuration.

Images