Multi-threshold device manufacturing method and device structure

Abstract

The present invention discloses a method for manufacturing a multi-threshold device and a device structure, including: providing an SOI substrate; making trench isolation; forming five first conductivity type wells and five second conductivity type wells by two ion implantations; forming a first conductivity type ion implantation channel layer only on the oxide buried layer on the second conductivity type well 1 and the first conductivity type well 4; forming a second conductivity type ion implantation channel layer only on the oxide buried layer on the second conductivity type well 3 and the first conductivity type well 2; forming a first conductivity type work function metal layer and a second conductivity type work function metal layer at a specified position; forming each transistor gate; forming each transistor source and drain. The present invention can form transistors with five threshold voltages of N / P without adding additional processes, only by increasing the permutations and combinations between different processes, thereby reducing production costs and improving production efficiency.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a multi-threshold device manufacturing method and a multi-threshold device structure. Background Art

[0002] N-type and P-type devices using a single metal electrode require doping technology to adjust the threshold voltage. The use of dual metal electrodes is more conducive to improving the performance of N-type and P-type devices respectively. If multiple threshold voltage devices are required, additional ion implantation is generally required for adjustment. Usually, one mask can only adjust one Vt. The integration of multiple threshold voltage devices requires the addition of multiple masks, which greatly increases the cost. Summary of the invention

[0003] A series of simplified concepts are introduced in the Summary of the Invention, which are all simplifications of the prior art in the field, and will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a multi-threshold device capable of manufacturing at least ten transistors with different threshold voltages at one time without adding additional production processes.

[0005] Correspondingly, the present invention also provides a multi-threshold device structure.

[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a multi-threshold device, which is characterized by comprising the following steps:

[0007] S1, providing an SOI substrate;

[0008] S2, making trench isolation and defining the well regions of the first transistor to the tenth transistor;

[0009] S3, ion implantation to form five wells of the first conductivity type and five wells of the second conductivity type;

[0010] The first conductive type well 1 and the second conductive type well 1 to the second conductive type well 4 are sequentially arranged in parallel, and the second conductive type well 5 and the first conductive type well 2 to the second conductive type well 5 are sequentially arranged in parallel;

[0011] It should be noted that the second conductivity type well 1 to the second conductivity type well 4 are substantially a well region, and for the convenience of describing each device, they are artificially divided into the second conductivity type well 1 to the second conductivity type well 4 according to the device structure;

[0012] The first conductivity type well 2 to the first conductivity type well 5 are substantially a well region, and for the convenience of describing each device, they are artificially divided into the first conductivity type well 2 to the first conductivity type well 5 according to the device structure;

[0013] S4, forming a first conductivity type ion implantation channel layer only on the oxide buried layer on the second conductivity type well 1 and the first conductivity type well 4;

[0014] S5, forming a second conductivity type ion implantation channel layer only on the buried oxide layer on the second conductivity type well three and the first conductivity type well two;

[0015] S6, forming a gate dielectric layer before forming a work function metal layer;

[0016] A first conductivity type work function metal layer is formed on the non-ion implanted channel layer on the first conductivity type well 1, on the first conductivity type ion implanted channel layer on the second conductivity type well 1, on the non-ion implanted channel layer on the second conductivity type well 2, on the second conductivity type ion implanted channel layer on the second conductivity type well 3, and on the non-ion implanted channel layer on the first conductivity type well 5;

[0017] S7, forming a second conductivity type work function metal layer on the non-ion-implanted channel layer on the second conductivity type well four, on the non-ion-implanted channel layer on the second conductivity type well five, on the second conductivity type ion-implanted channel layer on the first conductivity type well two, on the non-ion-implanted channel layer on the first conductivity type well three, and on the first conductivity type ion-implanted channel layer on the first conductivity type well four;

[0018] S8, forming the gate of each transistor;

[0019] S9, forming the source and drain of each transistor.

[0020] Optionally, the multi-threshold device manufacturing method is further improved so that the first conductivity type is N-type and the second conductivity type is P-type.

[0021] Alternatively, the first conductivity type is P type, and the second conductivity type is N type.

[0022] Optionally, the multi-threshold device manufacturing method is further improved, and the work function metal layer includes an n-type work function metal or a p-type work function metal.

[0023] Optionally, the multi-threshold device manufacturing method is further improved, wherein the N-type work function metal includes at least one of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn or Zr;

[0024] The P-type work function metal includes at least one of TiN, TaN, Ru, Mo, Al or WN.

[0025] Optionally, the multi-threshold device manufacturing method is further improved, and the first conductivity type well and the second conductivity type well are used to form a back gate to adjust the work function of the channel.

[0026] In order to solve the above technical problems, the present invention provides a multi-threshold device structure, comprising:

[0027] A first transistor to a tenth transistor are formed on an SOI substrate and isolated from each other by trenches, the threshold voltages of the first transistor to the fifth transistor gradually increase, and the threshold voltages of the sixth transistor to the tenth transistor gradually increase;

[0028] A first transistor comprises a first conductive type well on a substrate, an oxide buried layer on the first conductive type well, an ion-free layer on the oxide buried layer, a first conductive type work function metal layer on the ion-free layer, a gate on the first conductive type work function metal layer, and a first conductive type source and drain on both sides of the gate;

[0029] A second transistor includes a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, a first conductivity type ion implantation layer on the oxide buried layer, a first conductivity type work function metal layer on the first conductivity type ion implantation layer, a gate on the first conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate;

[0030] A third transistor includes a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, an ion-free layer on the oxide buried layer, a first conductivity type work function metal layer on the ion-free layer, a gate on the first conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate;

[0031] a fourth transistor, comprising a second conductivity type well on the substrate, a buried oxide layer on the second conductivity type well, a second conductivity type ion implantation layer on the buried oxide layer, a first conductivity type work function metal layer on the second conductivity type ion implantation layer, a gate on the first conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate;

[0032] a fifth transistor, comprising a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, an ion-free layer on the oxide buried layer, a second conductivity type work function metal layer on the ion-free layer, a gate on the second conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate;

[0033] a sixth transistor, comprising a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, an ion-free layer on the oxide buried layer, a second conductivity type work function metal layer on the ion-free layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate;

[0034] a seventh transistor, comprising a first conductivity type well on the substrate, a buried oxide layer on the first conductivity type well, a second conductivity type ion implantation layer on the buried oxide layer, a second conductivity type work function metal layer on the second conductivity type ion implantation layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate;

[0035] an eighth transistor, comprising a first conductivity type well on a substrate, an oxide buried layer on the first conductivity type well, an ion-free layer on the oxide buried layer, a second conductivity type work function metal layer on the ion-free layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate;

[0036] a ninth transistor, comprising a first conductivity type well on the substrate, a buried oxide layer on the first conductivity type well, a first conductivity type ion implantation layer on the buried oxide layer, a second conductivity type work function metal layer on the first conductivity type ion implantation layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate;

[0037] a tenth transistor, comprising a first conductivity type well on a substrate, an oxide buried layer on the first conductivity type well, an ion-free layer on the oxide buried layer, a first conductivity type work function metal layer on the ion-free layer, a gate on the first conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate;

[0038] Optionally, the multi-threshold device structure is further improved, the first conductivity type is N-type, and the second conductivity type is P-type;

[0039] Alternatively, the first conductivity type is P type, and the second conductivity type is N type.

[0040] Optionally, the multi-threshold device structure is further improved, and the functional metal layer includes an n-type work function metal or a p-type work function metal.

[0041] Optionally, the multi-threshold device structure is further improved, wherein the N-type work function metal includes at least one of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn or Zr;

[0042] The P-type work function metal includes at least one of TiN, TaN, Ru, Mo, Al or WN.

[0043] Optionally, the multi-threshold device structure is further improved, and the first conductivity type well and the second conductivity type well are used to form a back gate to adjust the work function of the channel.

[0044] The present invention provides a multi-threshold voltage structure and a method for manufacturing the multi-threshold voltage structure, wherein the multi-threshold voltage device structure includes a super low threshold voltage (SLVT) transistor, a low threshold voltage (LVT) transistor, a standard threshold voltage (RVT) transistor, a high threshold voltage (HVT) transistor, and an ultra-high threshold voltage (UHVT) transistor of a first conductivity type and a second conductivity type, respectively. Only two work function metal layers, two well ion implantations, and two channel ion implantations are used to implement the aforementioned SLVT, LVT, SVT, HVT, and UHVT transistors of the first conductivity type and the second conductivity type. In other words, a total of 10 transistors with different threshold voltages can be formed using two work function metal material depositions and four ion implantation operations.

[0045] The standard threshold voltage transistor in the present invention is composed of a well of the opposite conductivity type, a channel without ion implantation, and a work function metal of the same conductivity type. Ion implantation in the channel can adjust the threshold voltage. The low threshold voltage transistor is based on the standard threshold voltage transistor, and the same type of ion implantation is performed on its channel; on the contrary, the high threshold voltage transistor is based on the standard threshold voltage transistor, and the inverse type of ion implantation is performed on its channel.

[0046] The gate stack of the present invention includes work function metal layers with different conductivity types. The work function metal layer includes an n-type work function metal or a p-type work function metal. The n-type work function metal includes Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other appropriate n-type work function metals or combinations thereof. The p-type work function metal includes TiN, TaN, Ru, Mo, Al, WN, other appropriate p-type work function metals or combinations thereof. The work function value is associated with the material composition of the work function metal layer, and the work function value of the selected material in the present invention is in the range of 3.8eV to about 5.5eV. Generally speaking, the work function metal layer of a transistor is the same as its conductivity type. However, a work function metal layer of the opposite conductivity type to the transistor is selected. Since the work function difference between it and the channel is increased, the threshold voltage is increased, and an ultra-high threshold voltage transistor can be made. Therefore, the ultra-high threshold voltage transistor is prepared on the basis of a standard threshold voltage transistor using a work function metal of the opposite conductivity type.

[0047] Due to the presence of buried oxide layer, there is almost no leakage between the channel and substrate of silicon on insulator. The role of well is to form back gate and adjust the work function of the channel. On the basis of standard threshold voltage transistor, using well of the same conductivity type to reduce the work function difference between channel and gate can form ultra-low threshold voltage transistor.

[0048] Traditionally, two work function metal material depositions and four ion implantation operations can only form transistors with two N / P threshold voltages. However, the present invention can form transistors with five N / P threshold voltages without adding any additional steps, only by increasing the permutations and combinations of different processes, thereby reducing production costs and improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific exemplary embodiments of the present invention, and to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the range of values ​​or properties covered by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:

[0050] Figure 1 It is a schematic diagram of the structure of the present invention.

[0051] Description of Reference Numerals

[0052] SOI substrate 1

[0053] Trench Isolation 2

[0054] The first conductive type well 1 to the first conductive type well 5 3 to 7

[0055] The second conductivity type well 1 to the second conductivity type well 5 8 to 12

[0056] Buried oxide layer 13

[0057] The first conductive type ion implantation channel layer 14

[0058] The second conductive type ion implantation channel layer 15

[0059] No ion implantation channel layer 16

[0060] The first conductive type work function metal layer 17

[0061] The second conductive type work function metal layer 18

[0062] Transistor gate 19

[0063] The transistor has a source and a drain 20 . DETAILED DESCRIPTION

[0064] The following is an explanation of the embodiments of the present invention by specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without deviating from the general design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to another element, or there can be an intermediate element. The difference is that when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0065] First embodiment;

[0066] The present invention provides a method for manufacturing a multi-threshold device, comprising the following steps:

[0067] S1, providing an SOI substrate 1;

[0068] S2, making trench isolation 2, defining the well regions of the first transistor to the tenth transistor;

[0069] S3, ion implantation forms a first conductivity type well and a second conductivity type well; the first conductivity type well is formed by only one ion implantation, and the second conductivity type well is also formed by only one ion implantation;

[0070] The first conductive type well 1 3 and the second conductive type well 1 8 to the second conductive type well 4 11 of the first transistor to the fifth transistor are sequentially arranged in parallel, and the second conductive type well 5 12 and the first conductive type well 2 4 to the first conductive type well 5 7 of the sixth transistor to the tenth transistor are sequentially arranged in parallel;

[0071] Exemplarily, the first to fifth transistors are super low threshold voltage (SLVT) transistors, low threshold voltage (LVT) transistors, standard threshold voltage (RVT) transistors, high threshold voltage (HVT) transistors, and ultra high threshold voltage (UHVT) transistors.

[0072] The sixth to tenth transistors are a super low threshold voltage (SLVT) transistor, a low threshold voltage (LVT) transistor, a standard threshold voltage (RVT) transistor, a high threshold voltage (HVT) transistor, and an ultra high threshold voltage (UHVT) transistor.

[0073] S4, forming a first conductivity type ion implantation channel layer 14 only on the oxide buried layer 13 on the second conductivity type well 1 8 and the first conductivity type well 4 6;

[0074] S5, forming a second conductivity type ion implantation channel layer 15 only on the buried oxide layer 13 on the second conductivity type well 10 and the first conductivity type well 4;

[0075] S6, forming a first conductivity type work function metal layer 17 on the non-ion implanted channel layer 16 on the first conductivity type well 1 3, on the first conductivity type ion implanted channel layer 14 on the second conductivity type well 1 8, on the non-ion implanted channel layer 16 on the second conductivity type well 2 9, on the second conductivity type ion implanted channel layer 15 on the second conductivity type well 3 10, and on the non-ion implanted channel layer 16 on the first conductivity type well 5 7;

[0076] S7, forming a second conductivity type work function metal layer 18 on the non-ion-implanted channel layer 16 on the second conductivity type well four 11, on the non-ion-implanted channel layer 16 on the second conductivity type well five 12, on the second conductivity type ion-implanted channel layer 15 on the first conductivity type well two 4, on the non-ion-implanted channel layer 16 on the first conductivity type well three 5, and on the first conductivity type ion-implanted channel layer 14 on the first conductivity type well four 6;

[0077] S8, forming the gate 19 of each transistor;

[0078] S9, forming the source and drain 20 of each transistor, forming the first conductive type source and drain on the first conductive type well 13 and the second conductive type well 18 to the second conductive type well 4 11 of the first transistor to the fifth transistor, forming the second conductive type source and drain 21 on the second conductive type well 5 and 12 of the sixth transistor to the tenth transistor, and finally forming the following. Figure 1 The structure shown.

[0079] The first conductivity type is N-type, and the second conductivity type is P-type; or the first conductivity type is P-type, and the second conductivity type is N-type.

[0080] The work function metal layer includes an n-type work function metal or a p-type work function metal.

[0081] The N-type work function metal includes at least one of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn or Zr; the P-type work function metal includes at least one of TiN, TaN, Ru, Mo, Al or WN.

[0082] The first conductivity type well and the second conductivity type well are used to form a back gate and adjust the work function of the channel.

[0083] In addition, it should be understood that, although the terms "first", "second", etc. may be used herein to describe different elements, parameters, components, regions, layers and / or parts, these elements, parameters, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or part from another element, parameter, component, region, layer or part. Therefore, without departing from the teachings of exemplary embodiments of the present invention, the first element, parameter, component, region, layer or part discussed below may also be referred to as the second element, parameter, component, region, layer or part.

[0084] Second embodiment;

[0085] The present invention provides a multi-threshold device structure, comprising:

[0086] A first transistor to a tenth transistor are formed on an SOI substrate and isolated from each other by trenches, the threshold voltages of the first transistor to the fifth transistor gradually increase, and the threshold voltages of the sixth transistor to the tenth transistor gradually increase;

[0087] A first transistor comprises a first conductive type well on a substrate, an oxide buried layer on the first conductive type well, an ion-free layer on the oxide buried layer, a first conductive type work function metal layer on the ion-free layer, a gate on the first conductive type work function metal layer, and a first conductive type source and drain on both sides of the gate;

[0088] A second transistor includes a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, a first conductivity type ion implantation layer on the oxide buried layer, a first conductivity type work function metal layer on the first conductivity type ion implantation layer, a gate on the first conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate;

[0089] A third transistor includes a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, an ion-free layer on the oxide buried layer, a first conductivity type work function metal layer on the ion-free layer, a gate on the first conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate;

[0090] a fourth transistor, comprising a second conductivity type well on the substrate, a buried oxide layer on the second conductivity type well, a second conductivity type ion implantation layer on the buried oxide layer, a first conductivity type work function metal layer on the second conductivity type ion implantation layer, a gate on the first conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate;

[0091] a fifth transistor, comprising a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, an ion-free layer on the oxide buried layer, a second conductivity type work function metal layer on the ion-free layer, a gate on the second conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate;

[0092] a sixth transistor, comprising a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, an ion-free layer on the oxide buried layer, a second conductivity type work function metal layer on the ion-free layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate;

[0093] a seventh transistor, comprising a first conductivity type well on the substrate, a buried oxide layer on the first conductivity type well, a second conductivity type ion implantation layer on the buried oxide layer, a second conductivity type work function metal layer on the second conductivity type ion implantation layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate;

[0094] an eighth transistor, comprising a first conductivity type well on a substrate, an oxide buried layer on the first conductivity type well, an ion-free layer on the oxide buried layer, a second conductivity type work function metal layer on the ion-free layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate;

[0095] a ninth transistor, comprising a first conductivity type well on the substrate, a buried oxide layer on the first conductivity type well, a first conductivity type ion implantation layer on the buried oxide layer, a second conductivity type work function metal layer on the first conductivity type ion implantation layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate;

[0096] a tenth transistor, comprising a first conductivity type well on a substrate, an oxide buried layer on the first conductivity type well, an ion-free layer on the oxide buried layer, a first conductivity type work function metal layer on the ion-free layer, a gate on the first conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate;

[0097] The first conductivity type is N-type, and the second conductivity type is P-type; or the first conductivity type is P-type, and the second conductivity type is N-type.

[0098] The work function metal layer includes an n-type work function metal or a p-type work function metal, and the n-type work function metal includes at least one of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn or Zr;

[0099] The P-type work function metal includes at least one of TiN, TaN, Ru, Mo, Al or WN.

[0100] The first conductivity type well and the second conductivity type well are used to form a back gate and adjust the work function of the channel.

[0101] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not interpreted in an ideal or overly formal sense.

[0102] The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for manufacturing a multi-threshold device, characterized in that: The following steps are involved: S1, providing an SOI substrate; S2, making trench isolation and defining the well regions of the first transistor to the tenth transistor; S3, ion implantation to form a first conductivity type well and a second conductivity type well; The first conductive type well 1 and the second conductive type well 1 to the second conductive type well 4 are sequentially arranged in parallel, and the second conductive type well 5 and the first conductive type well 2 to the second conductive type well 5 are sequentially arranged in parallel; S4, forming a first conductivity type ion implantation channel layer only on the oxide buried layer on the second conductivity type well 1 and the first conductivity type well 4; S5, forming a second conductivity type ion implantation channel layer only on the buried oxide layer on the second conductivity type well three and the first conductivity type well two; S6, forming a first conductivity type work function metal layer on the non-ion implanted channel layer on the first conductivity type well 1, on the first conductivity type ion implanted channel layer on the second conductivity type well 1, on the non-ion implanted channel layer on the second conductivity type well 2, on the second conductivity type ion implanted channel layer on the second conductivity type well 3, and on the non-ion implanted channel layer on the first conductivity type well 5; S7, forming a second conductivity type work function metal layer on the non-ion-implanted channel layer on the second conductivity type well four, on the non-ion-implanted channel layer on the second conductivity type well five, on the second conductivity type ion-implanted channel layer on the first conductivity type well two, on the non-ion-implanted channel layer on the first conductivity type well three, and on the first conductivity type ion-implanted channel layer on the first conductivity type well four; S8, forming the gate of each transistor; S9, forming the source and drain of each transistor.

2. The method for manufacturing a multi-threshold device according to claim 1, wherein: The first conductivity type is N type, and the second conductivity type is P type; Alternatively, the first conductivity type is P type, and the second conductivity type is N type.

3. The method for manufacturing a multi-threshold device according to claim 2, wherein: The work function metal layer includes an n-type work function metal or a p-type work function metal.

4. The method for manufacturing a multi-threshold device according to claim 3, wherein: The N-type work function metal includes at least one of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn or Zr; The P-type work function metal includes at least one of TiN, TaN, Ru, Mo, Al or WN.

5. The method for manufacturing a multi-threshold device according to claim 1, wherein: The first conductivity type well and the second conductivity type well are used to form a back gate and adjust the work function of the channel.

6. A multi-threshold device structure, characterized in that: include: A first transistor to a tenth transistor are formed on an SOI substrate and isolated from each other by trenches, the threshold voltages of the first transistor to the fifth transistor gradually increase, and the threshold voltages of the sixth transistor to the tenth transistor gradually increase; A first transistor comprises a first conductive type well on a substrate, an oxide buried layer on the first conductive type well, an ion-free layer on the oxide buried layer, a first conductive type work function metal layer on the ion-free layer, a gate on the first conductive type work function metal layer, and a first conductive type source and drain on both sides of the gate; A second transistor includes a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, a first conductivity type ion implantation layer on the oxide buried layer, a first conductivity type work function metal layer on the first conductivity type ion implantation layer, a gate on the first conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate; A third transistor includes a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, an ion-free layer on the oxide buried layer, a first conductivity type work function metal layer on the ion-free layer, a gate on the first conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate; a fourth transistor, comprising a second conductivity type well on the substrate, a buried oxide layer on the second conductivity type well, a second conductivity type ion implantation layer on the buried oxide layer, a first conductivity type work function metal layer on the second conductivity type ion implantation layer, a gate on the first conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate; a fifth transistor, comprising a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, an ion-free layer on the oxide buried layer, a second conductivity type work function metal layer on the ion-free layer, a gate on the second conductivity type work function metal layer, and a first conductivity type source and drain on both sides of the gate; a sixth transistor, comprising a second conductivity type well on the substrate, an oxide buried layer on the second conductivity type well, an ion-free layer on the oxide buried layer, a second conductivity type work function metal layer on the ion-free layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate; a seventh transistor, comprising a first conductivity type well on the substrate, a buried oxide layer on the first conductivity type well, a second conductivity type ion implantation layer on the buried oxide layer, a second conductivity type work function metal layer on the second conductivity type ion implantation layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate; an eighth transistor, comprising a first conductivity type well on a substrate, an oxide buried layer on the first conductivity type well, an ion-free layer on the oxide buried layer, a second conductivity type work function metal layer on the ion-free layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate; a ninth transistor, comprising a first conductivity type well on the substrate, a buried oxide layer on the first conductivity type well, a first conductivity type ion implantation layer on the buried oxide layer, a second conductivity type work function metal layer on the first conductivity type ion implantation layer, a gate on the second conductivity type work function metal layer, and a second conductivity type source and drain on both sides of the gate; The tenth transistor includes a first conductive type well on the substrate, a buried oxide layer on the first conductive type well, an ion-free implantation layer on the buried oxide layer, a first conductive type work function metal layer on the ion-free implantation layer, a gate on the first conductive type work function metal layer, and a second conductive type source and drain on both sides of the gate.

7. The multi-threshold device structure according to claim 6, characterized in that: The first conductivity type is N type, and the second conductivity type is P type; Alternatively, the first conductivity type is P type, and the second conductivity type is N type.

8. The multi-threshold device structure according to claim 7, characterized in that: The work function metal layer includes an n-type work function metal or a p-type work function metal.

9. The multi-threshold device structure according to claim 8, characterized in that: The N-type work function metal includes at least one of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn or Zr; The P-type work function metal includes at least one of TiN, TaN, Ru, Mo, Al or WN.

10. The multi-threshold device structure according to claim 6, characterized in that: The first conductivity type well and the second conductivity type well are used to form a back gate and adjust the work function of the channel.

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