Trench MOSFET device and method for manufacturing the same

Abstract

The present invention provides a trench MOSFET device, comprising: an epitaxial layer of a first doping type located on a substrate; a trench, the trench being located in the epitaxial layer of the first doping type; a body region, the body region being located in the upper region of the epitaxial layer of the first doping type and being adjacent to the trench; a floating region of a second doping type, the floating region of the second doping type being located in the epitaxial layer of the first doping type and being adjacent to the bottom of the trench and the bottom sidewall of the trench; the floating region of the second doping type being in electrical contact with the body region, and the floating region of the second doping type and the body region being at the same potential. Based on the trench MOSFET device of the present invention, the withstand voltage BV of the trench MOSFET device is improved, Crss / Ciss is reduced, and the reliability of the trench MOSFET device is thereby improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to a trench MOSFET device and a preparation method thereof. Background Art

[0002] Power MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) is a multi-conducting device with a wide variety of types and rapid changes. This is the current status of power MOSFET application. Power MOSFET is mainly trench power MOSFET. Trench MOSFET is a device with a vertical conductive channel. When the trench MOSFET is in the on state, the current will flow vertically from the drain end to the source end. Trench MOSFET has the advantages of low on-resistance, small gate leakage current, and high switching rate. These advantages make it widely used in industrial control, aerospace, communications, automobiles, computers and portable appliances, home appliances, office supplies and other fields, especially in the application of switching power supplies. It has achieved rapid development and greatly improved the efficiency of electronic systems.

[0003] like Figure 1 As shown, it is a schematic diagram of the structure of the existing trench MOSFET, Ciss and Crss are the input capacitance and feedback capacitance of the MOS tube respectively. By observing the inter-electrode capacitance and parasitic gate charge Qg of the trench MOSFET tube, it can be seen that the inter-electrode capacitance of the MOS tube is determined by its conductive channel structure and process. In order to reduce Qg and Crss / Ciss, the existing trench MOSFET preparation method injects impurities into the epitaxial layer 202 on the substrate 201 after the trench 203 is etched, and the substrate 201 is subjected to a high-temperature process to form a floating area 204 in the drift area at the bottom of the trench 203. The floating area 204 prepared according to the existing preparation method is a floating potential.

[0004] During the process of forming the body region 205, the floating region 204 with suspended potential is affected by factors such as hot carriers and plasma injection, resulting in unstable and uncontrollable Qg and Crss / Ciss, which has an adverse effect on reducing Qg and Crss / Ciss, and affects the reliability of the device. Under the premise of not affecting the withstand voltage, Qg and Crss / Ciss are reduced, and the performance of trench MOSFET is continuously improved and enhanced, so that trench MOSFET applications can gain a larger market. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and to provide a trench MOSFET device and a method for preparing the same.

[0006] To achieve the above-mentioned purpose, the first aspect of the present invention provides a trench MOSFET device, characterized in that it includes: a substrate; an epitaxial layer of a first doping type located on the substrate; a groove, the groove is located in the epitaxial layer of the first doping type, extends longitudinally from the top of the epitaxial layer of the first doping type to the bottom of the substrate and terminates in the epitaxial layer of the first doping type; a gate dielectric layer is located at the inner wall and bottom of the groove, and a gate electrode layer is located on the gate dielectric layer, the gate electrode layer fills the groove; a body region, the body region is located in the upper area of ​​the epitaxial layer of the first doping type and is adjacent to the groove; a floating region of a second doping type, the floating region of the second doping type is located in the epitaxial layer of the first doping type and is adjacent to the bottom of the trench and adjacent to the bottom sidewall of the trench; the floating region of the second doping type is electrically contacted with the body region, and the floating region of the second doping type and the body region are at the same potential.

[0007] Preferably, the floating region of the second doping type includes a bottom floating region adjacent to the bottom of the trench, and a sidewall floating region adjacent to the side wall of the bottom of the trench and located under the body region, the bottom floating region is connected to the sidewall floating region, the vertical distance between the upper surface of the sidewall floating region and the bottom surface of the trench is a first height, and the vertical distance between the upper surface of the sidewall floating region and the bottom surface of the body region is a second height.

[0008] Preferably, the second height is 0, the upper surface of the sidewall floating region is in direct contact with the bottom surface of the body region, and the electrical contact is a direct electrical contact.

[0009] Preferably, the second height is greater than 0, and further includes: a contact hole penetrating the body region, and the contact hole vertically extending to the upper surface of the sidewall floating region; a metal plug filling the contact hole, the metal plug connecting the body region and the second doping type floating region, and the electrical contact is an indirect electrical contact.

[0010] Preferably, it also includes: a source region located on the body region, the contact hole also penetrates the source region, the metal plug connects the source region, the body region and the second doping type floating region, and the second doping type floating region is at the same potential as the body region and the source region.

[0011] Preferably, the material of the metal plug includes tungsten; the first doping type is opposite to the second doping type: the first doping type is N type and the second doping type is P type; or the first doping type is P type and the second doping type is N type.

[0012] The second aspect of the present invention provides a method for preparing a trench MOSFET device, characterized in that it includes: step S01, providing a substrate and forming an initial epitaxial layer on the surface of the substrate; step S02, doping the initial epitaxial layer to form an epitaxial layer of a first doping type; step S03, forming a trench in the epitaxial layer of the first doping type; step S04, through N ion implantation processes, doping the epitaxial layer of the first doping type located at the bottom and bottom sidewall of the trench to form a floating region of a second doping type; step S05: depositing a gate dielectric layer on the inner wall and bottom of the trench; step S06: forming a gate electrode layer filling the trench on the gate dielectric layer; step S07, doping the epitaxial layer of the first doping type adjacent to the upper area of ​​the trench and located on the floating region of the second doping type to form a body region; step S08, performing an annealing process, forming an electrical contact between the floating region of the second doping type and the body region, and the floating region of the second doping type and the body region are at the same potential.

[0013] Preferably, the trench extends longitudinally from the top of the first doping type epitaxial layer to the bottom of the substrate and terminates in the first doping type epitaxial layer; the second doping type floating region includes a bottom floating region adjacent to the bottom of the trench, and a sidewall floating region adjacent to the sidewall of the bottom of the trench and located under the body region; the N ion implantations are N ion implantations with implantation angles, and N is an integer greater than or equal to 1.

[0014] Preferably, the implantation angle is an acute angle between the ion implantation direction and a vertical direction perpendicular to the substrate, and the implantation angle is -60 degrees to 60 degrees.

[0015] Preferably, when N is greater than 1, the implantation angle of each ion implantation is increased or decreased in a step-by-step manner.

[0016] Preferably, when N is greater than 1, the injection angle of a single ion injection is 0 degrees to form the bottom floating area; the injection angle of each ion injection is increased or decreased in a stepwise manner to form the sidewall floating area connected to the bottom floating area.

[0017] Preferably, the implantation dose of each ion implantation is increased or decreased in a step-by-step manner.

[0018] Preferably, the N ion implantations are N rotational ion implantations with implantation angles.

[0019] Preferably, the vertical distance between the upper surface of the sidewall floating region and the bottom surface of the groove is a first height, and the vertical distance between the upper surface of the sidewall floating region and the bottom surface of the body region is a second height; the injection angle is proportional to the first height.

[0020] Preferably, the second height is 0, the upper surface of the sidewall floating region is in direct contact with the bottom surface of the body region, and the electrical contact is a direct electrical contact.

[0021] Preferably, the second height is greater than 0, and after the annealing process is completed, a contact hole penetrating the body region is formed, and the contact hole vertically extends to the upper surface of the floating region on the sidewall; the contact hole is filled with metal to form a metal plug, and the metal plug connects the body region and the floating region of the second doping type, and the electrical contact is an indirect electrical contact;

[0022] Preferably, before forming the contact hole, a source region is also doped in the body region, the contact hole also penetrates the source region, the metal plug connects the source region, the body region and the floating region of the second doping type, and the floating region of the second doping type is at the same potential as the body region and the source region.

[0023] Preferably, the material of the metal plug includes tungsten; the first doping type is opposite to the second doping type: the first doping type is N type and the second doping type is P type; or the first doping type is P type and the second doping type is N type.

[0024] The trench MOSFET device prepared by the method of the present invention realizes the equipotential of the floating region and the body region, so that the drift region is depleted laterally and vertically, the withstand voltage BV of the trench MOSFET device is improved while reducing Qg, and the hot carrier injection introduced in the process is effectively controlled, thereby reducing Crss / Ciss, and further improving the reliability of the trench MOSFET device; at the same time, the existing conventional trench MOSFET process technology is adopted, and the injection angle is adjusted by an implanter, so as to adjust the position of the floating region at the predetermined position on both sides of the trench, so as to achieve the process controllability of Qg and Crss / Ciss. The manufacturing process of the above-mentioned floating region is simple, the process stability is high, and it has significant significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A schematic diagram of the structure of an existing trench MOSFET

[0027] Figure 2A flowchart showing the preparation of a trench MOSFET according to a first embodiment of the present invention is shown.

[0028] Figures 3 to 5 A schematic cross-sectional diagram showing a staged process of preparing a trench MOSFET according to a first embodiment of the present invention

[0029] Figure 6 Schematic diagram of a primary ion implantation according to the first embodiment of the present invention

[0030] Figure 7 Schematic diagram of secondary ion implantation according to the first embodiment of the present invention

[0031] Figure 8 A schematic cross-sectional diagram showing the stages of fabrication of a trench MOSFET according to a first embodiment of the present invention

[0032] Fig. 9 A schematic diagram showing the structure of a trench MOSFET device according to a first embodiment of the present invention is shown.

[0033] Fig.10 A schematic diagram showing the structure of a trench MOSFET device according to a second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0034] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0035] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly above the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0036] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used herein. In the present invention, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0037] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of the semiconductor device, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0038] Unless otherwise specified below, the various layers or regions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si and Ge. The gate conductor and electrode layer may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials. The gate dielectric may be composed of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric may be formed not only of materials known to those skilled in the art, but also of materials developed in the future for the gate dielectric.

[0039] In the present invention, the term "semiconductor structure" refers to the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "lateral extension" refers to extension in a direction substantially perpendicular to the depth direction of the trench.

[0040] The present invention provides a trench MOSFET device, comprising: a substrate; an epitaxial layer of a first doping type located on the substrate; a trench, the trench is located in the epitaxial layer of the first doping type, extends longitudinally from the top of the epitaxial layer of the first doping type to the bottom of the substrate and terminates in the epitaxial layer of the first doping type; a gate dielectric layer is located at the inner wall and bottom of the trench, and a gate electrode layer is located on the gate dielectric layer, the gate electrode layer fills the trench; a body region, the body region is located in the upper region of the epitaxial layer of the first doping type and is adjacent to the trench; a floating region of a second doping type, the floating region of the second doping type is located in the epitaxial layer of the first doping type and is adjacent to the bottom of the trench and adjacent to the bottom sidewall of the trench; the floating region of the second doping type is electrically in contact with the body region, and the floating region of the second doping type and the body region are at the same potential.

[0041] The present invention may be embodied in various forms, some examples of which will be described below.

[0042] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples. Figure 2 FIG. 1 is a flow chart showing the preparation of a trench MOSFET according to a first embodiment of the present invention. Figures 3 to 5 A schematic diagram showing the phased results of the preparation of a trench MOSFET according to the first embodiment of the present invention is shown.

[0043] See also Figure 2 , Figure 2 A total of 8 steps are shown, which are combined below Figure 2 See also Figure 3-Figure 9 :

[0044] Step S01 , providing a substrate 101 , and forming an initial epitaxial layer (not shown) on a surface of the substrate 101 .

[0045] Step S02 , doping the initial epitaxial layer to form an epitaxial layer 102 of a first doping type.

[0046] See also Figure 3 , Figure 3 FIG. 1 is a schematic diagram of the combined production of step S01 and step S02. Figure 3 As shown, in this embodiment, the substrate 101 is a silicon substrate, but the present invention does not impose any restrictions on the material of the substrate 101. In other embodiments, materials such as germanium or silicon germanium can also be used as the substrate 101. The substrate 101 also includes other conductor layers between the substrate 101 and the epitaxial layer 102 of the first doping type. In order to reduce the instability of the interface between the substrate 101 and the epitaxial layer 102 of the first doping type due to defects in the substrate 101, the doping type of the conductor layer is the same as the epitaxial layer 102 of the first doping type. The initial epitaxial layer can be formed by chemical vapor deposition, and the thickness of the initial epitaxial layer is set according to specific circumstances. In one embodiment, the epitaxial layer 102 of the first doping type is formed by doping during the deposition of the initial epitaxial layer. Specifically, the epitaxial layer 102 of the first doping type is a silicon epitaxial layer, and an N-type epitaxial layer or a P-type epitaxial layer is formed after N-doping or P-doping. After the first doping type epitaxial layer 102 is formed, the surface of the first doping type epitaxial layer 102 is flattened by chemical mechanical polishing, and the substrate 101 serves as the drain of the trench MOSFET. In the present invention, the first doping type epitaxial layer 102 is of the first doping type, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. The first doping type epitaxial layer 102 can also be implanted with N-type dopants (such as P, As) on the surface of the substrate 101; in order to form a P-type first doping type epitaxial layer 102, a P-type dopant (such as B) can be implanted on the surface of the substrate 101.

[0047] Step S03 , forming a trench 103 in the epitaxial layer 102 of the first doping type.

[0048] See also Figure 4 In this embodiment, a groove 103 is formed in the epitaxial layer 102 of the first doping type, and the groove 103 extends longitudinally from the top of the epitaxial layer 102 of the first doping type to the bottom of the substrate 101 and terminates in the epitaxial layer 102 of the first doping type. The groove 103 is formed in the epitaxial layer 102 of the first doping type by photolithography and etching technology, and the etching technology includes one of dry etching or wet etching. In this embodiment, the pattern of the groove 103 is first defined by a photolithography process, and then a silicon etching process is used to obtain the groove 103 with a high aspect ratio. Among them, the silicon etching process here can be a typical deep silicon etching process (Bosch process), which includes a silicon etching process step and a sidewall passivation process step, and the groove 103 with a relatively flat sidewall is obtained by continuously repeating the two process steps. Next, the etched trench 103 is wet cleaned, generally using a conventional cleaning solution, such as a mixed cleaning solution of HCl / H2O2 / H2O or NH4OH / H2O2 / H2O.

[0049] Step S04 , doping the first doping type epitaxial layer 102 located at the bottom and the bottom sidewall of the trench 103 by N ion implantation processes to form a second doping type floating region 104 .

[0050] Please refer to Figure 5, a floating region 104 of a second doping type is formed in the epitaxial layer 102 of the first doping type, the floating region 104 of the second doping type includes a bottom floating region (not shown) adjacent to the bottom of the trench, and a sidewall floating region (not shown) adjacent to the bottom sidewall of the trench 103, the bottom floating region is connected to the sidewall floating region, the vertical distance between the upper surface of the sidewall floating region and the bottom surface of the trench 104 is a first height, and the injection angle is proportional to the first height. The N ion injections are N ion injections with injection angles, and N is an integer greater than or equal to 1. In one embodiment, N is greater than 1, the injection angle of one ion injection is 0 degrees, the remaining ion injections are rotary ion injections with injection angles, and the injection doses of the remaining ion injections are increased or decreased in a stepwise manner. The conventional trench MOSFET manufacturing process is adopted, and the injection angle is adjusted by using an implanter, thereby adjusting the position of the floating region at the predetermined position on both sides of the trench, so as to achieve process controllability of Qg and Crss / Ciss. The injection angle is the acute angle between the ion injection direction and the vertical direction perpendicular to the substrate, and the injection angle is -60 degrees to 60 degrees, and the injection angle is proportional to the first height. The larger the injection angle, the larger the first height, and the larger the vertical distance between the upper surface of the sidewall floating area and the bottom surface of the groove 103. In the subsequent annealing process, the floating area 104 of the second doping type diffuses along the epitaxial layer 102 of the first doping type, which is conducive to forming an electrical contact with the body region formed subsequently. The first doping type is opposite to the second doping type. In one embodiment, the first doping type is N-type and the second doping type is P-type; in another embodiment, the first doping type is P-type and the second doping type is N-type.

[0051] When N is greater than 1, the injection angle of the first ion injection is 0 degrees, forming the bottom floating area; the injection angles of the remaining ion injections are increased or decreased stepwise to form the sidewall floating area connected to the bottom floating area. In the first embodiment of the present invention, the ion injection is an ion injection with an injection angle, and N is equal to 2, the injection angle of the first ion injection is 0 degrees, the secondary ion injection is an ion injection with an injection angle, and the injection angle of the secondary ion is -60 degrees to 60 degrees. Please refer to Figure 6 and Figure 7 , Figure 6 is a schematic diagram of a primary ion implantation according to a first embodiment of the present invention, Figure 7The schematic diagram of the secondary ion implantation of the first embodiment of the present invention is shown in FIG. 1 . In the first embodiment of the present invention, the floating region 104 is formed by first ion implantation, the angle of which is 0 degrees, and a bottom floating region is first formed in the bottom region of the first doping type epitaxial layer 102 adjacent to the groove 103; and then a secondary ion implantation is performed, the angle of which is -60 degrees to 60 degrees, and a sidewall floating region is formed in the first doping type epitaxial layer 102 adjacent to the bottom sidewall of the groove 103. In other embodiments, multiple ion implantations with implantation angles are performed, and when N is greater than 1, the implantation angle of each ion implantation increases or decreases in a stepwise manner, and the implantation dose of each ion implantation increases or decreases in a stepwise manner, and the N ion implantations are N rotational ion implantations with implantation angles.

[0052] In this step, a floating region 104 of a second doping type is formed, and the implanted ions can reduce the electric field strength at the bottom of the trench 103, and can transfer the high electric field strength area from the bottom of the trench 103 to a position in the floating region 104 away from the bottom of the trench 103, thereby reducing the leakage current caused by the high electric field strength, thereby improving the reliability of the trench MOSFET. The type of implanted ions of the second doping type is related to the type and conductivity type of the substrate 101. When the substrate 101 is N-type single crystal silicon, the implanted ions are preferably boron ions. When the substrate 101 is P-type single crystal silicon, the implanted ions are preferably phosphorus ions or arsenic ions. Of course, the type of implanted ions is not limited to the above preferred manner. Those skilled in the art can set the implantation angle, dose and energy of the above implanted ions according to the teachings of the present invention. Preferably, when N is greater than 1, the implantation angle of an ion implantation is 0 degrees, and each ion implantation is a rotary ion implantation with an implantation angle, and each implantation angle is increased or decreased in a step-by-step manner, and the implantation dose of each ion implantation is increased or decreased in a step-by-step manner. The inventors have found through experimental research that the reliability of trench MOSFET can be further improved by performing ion implantation in this preferred manner. At the same time, the first height formed can be set according to actual process requirements. The larger the implantation angle of the ion implantation, the larger the first height. In this embodiment, the second doping type floating region 104 is P type, and the second doping type floating region 104 is formed by implanting boron ions and undergoing an annealing process.

[0053] Step S05 : depositing a gate dielectric layer 113 on the inner wall and bottom of the trench 103 .

[0054] Step S06 : forming a gate electrode layer 123 filling the trench 103 on the gate dielectric layer 113 .

[0055] See also Figure 8 , Figure 8The schematic diagram of the combination of S05 and S06 is shown. A gate dielectric layer 113 is deposited on the inner wall and bottom of the trench 103 using thermal oxidation technology. Thermal oxidation technology is generally a process in which silicon reacts with a gas containing an oxidizing substance, such as water vapor and oxygen, at high temperature to produce a dense silicon dioxide (SiO2) film on the surface of the silicon wafer, which is an important process in silicon planar technology. Further, polysilicon is filled in the trench 103 covered with the gate dielectric layer 113 by low-pressure chemical vapor deposition to form a gate electrode layer 123, and then back etching or chemical mechanical planarization is used to make the gate electrode layer 123 flush with the trench 103.

[0056] Step S07, doping the first doping type epitaxial layer 102 adjacent to the upper region of the trench 103 and located on the second doping type floating region 104 to form a body region 105;

[0057] Step S08 , performing an annealing process, so that electrical contact is formed between the second doping type floating region 105 and the body region 104 , and the second doping type floating region 104 and the body region 105 are at the same potential.

[0058] See also Fig. 9 , Fig. 9 The schematic diagram of the structure of the trench MOSFET device of the first embodiment of the present invention is shown. The vertical distance between the upper surface of the sidewall floating region and the bottom surface of the body region is a second height. In this embodiment, the second height is 0. The upper surface of the floating region 104 located at the predetermined position on both sides of the trench is in direct contact with the bottom surface of the body region 105, and the electrical contact is a direct electrical contact. The formation of the body region 105 includes a doping process. When the doping depth of the body region 105 is deep, the bottom surface of the body region 105 is level with the upper surface of the second doping type floating region 104. The second height is 0. The electrical contact connects the second doping type floating region 104 with the body region 105, realizes the equipotential of the second doping type floating region 104 and the body region 105, makes the drift region depleted laterally and vertically, improves the withstand voltage BV of the trench MOSFET device, reduces Qg and controls the hot carrier injection introduced in the process, reduces Crss / Ciss, and thus improves the reliability of the trench MOSFET device. A photomask may be used to block the implantation to form the body region 105 of the device. The specific dosage and energy of the implantation of impurities into the body region 105 are determined according to the threshold voltage required by the trench MOSFET.

[0059] In another embodiment, the formation of the body region 105 includes ion implantation and annealing processes, the doping depth of the body region 102 is relatively shallow, and the initial second height is greater than 0. As the annealing process proceeds, the sidewall floating regions on both sides of the trench 103 expand outward along the sidewalls on both sides of the trench 103, the upper surface of the second doping type floating region 104 is in direct contact with the bottom surface of the body region 105, the second doping type floating region 104 forms electrical contact with the body region 105, and the height of the second height is 0. Due to the error in the implantation angle accuracy or the poor implantation angle accuracy, the initial height of the second height is greater than 0, and the temperature effect of the annealing can be diffused to the sidewall floating regions on both sides of the trench 103, so that the second doping type floating region 104 forms electrical contact with the body region 105. The annealing process is not limited to the formation of the body region 105, and the annealing process after the formation of the body region 105 can achieve the same purpose as this annealing process, thereby reducing the process difficulty of achieving electrical contact between the second doping type floating region 104 and the body region 105.

[0060] The second height is greater than 0. After the annealing process is completed, a contact hole (not shown) is formed that penetrates the body region 105, and the contact hole vertically extends to the upper surface of the sidewall floating region; the contact hole is filled with metal to form a metal plug 107, and the metal plug 107 connects the body region 105 and the second doping type floating region 104, and the electrical contact is indirect electrical contact.

[0061] See also Fig.10 , Fig.10 The schematic diagram of the structure of the trench MOSFET device of the second embodiment of the present invention is shown. In the second embodiment of the present invention, the second height is greater than 0, and before forming the contact hole, the body region 105 is doped to form a source region 109, and the contact hole also penetrates the source region 109, and a metal is filled in the contact hole to form a metal plug 107, and the material of the metal plug 107 includes tungsten, and the metal plug 107 connects the source region 109, the body region 105 and the second doping type floating region 104, and the second doping type floating region 104 is at the same potential as the body region 105 and the source region 109.

[0062] The trench MOSFET device prepared based on the method of the present invention realizes the equipotential of the floating region and the body region of the second doping type, so that the drift region located at the bottom of the trench is depleted laterally and vertically, the withstand voltage BV of the trench MOSFET device is improved, Qg is reduced and the hot carrier injection introduced in the process is controlled, Crss / Ciss is reduced, and the reliability of the trench MOSFET device is improved; at the same time, the existing conventional process technology is adopted, and the injection angle is adjusted by using an implanter, so as to adjust the position of the side wall floating region adjacent to the side wall of the trench, so as to achieve the process controllability of Qg and Crss / Ciss, which has significant significance.

[0063] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for preparing a trench MOSFET device, characterized in that: include: Step S01, providing a substrate, forming a conductive layer on the substrate, and forming an initial epitaxial layer on a surface of the conductive layer; Step S02, doping the initial epitaxial layer to form an epitaxial layer of a first doping type; the doping type of the epitaxial layer of the first doping type is the same as the doping type of the conductive layer; Step S03, forming a trench in the epitaxial layer of the first doping type; Step S04, doping the epitaxial layer of the first doping type located at the bottom and the bottom sidewall of the trench to form a floating region of the second doping type through N ion implantation processes; Step S05, depositing a gate dielectric layer on the inner wall and bottom of the trench; Step S06, forming a gate electrode layer filling the trench on the gate dielectric layer; Step S07, doping the epitaxial layer of the first doping type adjacent to the upper region of the trench and located on the floating region of the second doping type to form a body region; Step S08, performing an annealing process, so that electrical contact is formed between the floating region of the second doping type and the body region, and the floating region of the second doping type and the body region are at the same potential; wherein, The floating region of the second doping type includes a bottom floating region adjacent to the bottom of the groove, and a sidewall floating region adjacent to the sidewall of the bottom of the groove and located below the body region; the N ion implantations are N ion implantations with implantation angles, where N is an integer greater than or equal to 1; the implantation angle is an acute angle between the ion implantation direction and a vertical direction perpendicular to the substrate, and the implantation angle is -60 degrees to 60 degrees; when N is greater than 1, the implantation angle of one ion implantation is 0 degrees to form the bottom floating region, and the implantation angle of each subsequent ion implantation is increased or decreased in a stepwise manner to form the sidewall floating region connected to the bottom floating region; the implantation dose of each ion implantation is increased or decreased in a stepwise manner; The vertical distance between the upper surface of the sidewall floating region and the bottom surface of the groove is a first height, and the vertical distance between the upper surface of the sidewall floating region and the bottom surface of the body region is a second height; the absolute value of the injection angle is proportional to the first height; when the second height is 0, the formation of the body region includes a doping process, after which the upper surface of the sidewall floating region is in direct contact with the bottom surface of the body region, and the electrical contact is a direct electrical contact; when the second height is greater than 0, the formation of the body region includes an ion implantation process and an annealing process; after the ion implantation and annealing are completed, a contact hole penetrating the body region is formed, and the contact hole vertically extends to the upper surface of the sidewall floating region; The contact hole is filled with metal to form a metal plug, and the metal plug connects the body region and the floating region of the second doping type, and the electrical contact is indirect electrical contact; the larger the absolute value of the injection angle, the larger the first height, and the larger the vertical distance between the upper surface of the sidewall floating region and the bottom surface of the groove. In the subsequent annealing process, the floating region of the second doping type diffuses along the epitaxial layer of the first doping type, which is conducive to forming an electrical contact with the formed body region; when the second height is 0, the bottom surface of the body region is flush with the upper surface of the floating region of the second doping type, and the electrical contact connects the floating region of the second doping type with the body region, achieving the equipotential between the floating region of the second doping type and the body region, so that the drift region is depleted laterally and vertically, thereby improving The trench MOSFET device has a withstand voltage BV, reduces the parasitic gate charge Qg and controls the hot carrier injection introduced in the process, reduces the feedback capacitance Crss and the input capacitance Ciss, and thus improves the reliability of the trench MOSFET device; due to an injection angle accuracy error or a poor injection angle accuracy, the initial height of the second height is greater than 0, the formation of the body region includes ion implantation and annealing processes, the temperature effect of the annealing diffuses to the sidewall floating regions on both sides of the trench, so that the second doping type floating region forms an electrical contact with the body region, the annealing process is not limited to the formation of the body region, and the annealing process after the formation of the body region can achieve the same purpose as this annealing process, thereby reducing the process difficulty of achieving electrical contact between the second doping type floating region and the body region.

2. The method for preparing a trench MOSFET device according to claim 1, wherein: The trench extends longitudinally from the top of the epitaxial layer of the first doping type toward the bottom of the substrate and terminates within the epitaxial layer of the first doping type.

3. The method for preparing a trench MOSFET device according to claim 1, wherein: The N ion implantations are N rotational ion implantations with implantation angles.

4. The method for preparing a trench MOSFET device according to claim 1, wherein: Before forming the contact hole, a source region is doped in the body region, and the contact hole also penetrates the source region. The metal plug connects the source region, the body region and the floating region of the second doping type, and the floating region of the second doping type is at the same potential as the body region and the source region.

5. The method for preparing a trench MOSFET device according to claim 1, wherein: The material of the metal plug includes tungsten; the first doping type is opposite to the second doping type: the first doping type is N type and the second doping type is P type; or the first doping type is P type and the second doping type is N type.

6. A trench MOSFET device, characterized in that: Prepared by the method for preparing a trench MOSFET device according to any one of claims 1 to 5; the trench MOSFET device comprises: substrate; an epitaxial layer of a first doping type located on the substrate; a trench, the trench being located in the epitaxial layer of the first doping type, extending longitudinally from the top of the epitaxial layer of the first doping type to the bottom of the substrate and terminating in the epitaxial layer of the first doping type; a gate dielectric layer located on the inner wall and bottom of the trench, and a gate electrode layer located on the gate dielectric layer, wherein the gate electrode layer fills the trench; a body region, the body region being located in an upper region of the epitaxial layer of the first doping type and adjacent to the trench; a floating region of a second doping type, the floating region of the second doping type being located in the epitaxial layer of the first doping type and being adjacent to a bottom of the trench and adjacent to a bottom sidewall of the trench; The floating region of the second doping type is in electrical contact with the body region, and the floating region of the second doping type and the body region are at the same potential.

7. The trench MOSFET device according to claim 6, characterized in that: The floating region of the second doping type includes a bottom floating region adjacent to the bottom of the trench, and a sidewall floating region adjacent to the side wall of the bottom of the trench and located under the body region, the bottom floating region is connected to the sidewall floating region, the vertical distance between the upper surface of the sidewall floating region and the bottom surface of the trench is a first height, and the vertical distance between the upper surface of the sidewall floating region and the bottom surface of the body region is a second height.

8. The trench MOSFET device according to claim 7, characterized in that: The second height is 0, the upper surface of the sidewall floating region is in direct contact with the bottom surface of the body region, and the electrical contact is a direct electrical contact.

9. The trench MOSFET device according to claim 7, characterized in that: The second height is greater than 0 and also includes: a contact hole that penetrates the body region, and the contact hole vertically extends to the upper surface of the sidewall floating region; a metal plug filling the contact hole, the metal plug connects the body region and the second doping type floating region, and the electrical contact is an indirect electrical contact.

10. The trench MOSFET device according to claim 9, characterized in that: Also includes: The source region is located on the body region, the contact hole also penetrates the source region, the metal plug connects the source region, the body region and the second doping type floating region, and the second doping type floating region is at the same potential as the body region and the source region.

11. The trench MOSFET device according to claim 10, characterized in that: The material of the metal plug includes tungsten; the first doping type is opposite to the second doping type: the first doping type is N type and the second doping type is P type; or the first doping type is P type and the second doping type is N type.

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