Systems and methods for forming solder bumps

Abstract

A method of forming solder bumps, the method comprising: preparing a transfer mold having solder pillars extending from a mold substrate and through a first photoresist layer, the solder pillars having a shape partially defined by a second photoresist layer, wherein the preparation of the transfer mold includes removing at least a portion of the second photoresist layer; configuring a device substrate to include a wettable pad; aligning the transfer mold with the device substrate such that the solder pillars are aligned with the wettable pads; forming a metal bond between the solder pillars and the wettable pads; and removing the mold substrate and the first photoresist layer.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, manufacturing methods, and manufacturing systems for forming solder bumps. Background Art

[0002] Hereinafter, unless explicitly distinguished in use, the prefix "Q" or "q" in a phrase or word indicates a reference to that word or phrase in the context of quantum computing.

[0003] Molecules and subatomic particles follow the laws of quantum mechanics, which is a branch of physics that explores how the physical world works at the most fundamental level. At this level, particles behave in strange ways, simultaneously assuming more than one state and interacting with other particles that are very far away. Quantum computing utilizes these quantum phenomena to process information.

[0004] The computers we use today are called classical computers (also referred to herein as "conventional" computers or conventional nodes, or "CN"). Conventional computers use conventional processors, semiconductor memories, and magnetic or solid-state storage devices manufactured using semiconductor materials and technologies, known as the Von Neumann architecture. Specifically, the processors of conventional computers are binary processors, i.e., they operate on binary data represented by 1s and 0s.

[0005] Quantum processors (q-processors) use the peculiar properties of entangled qubit devices (compactly referred to herein as "qubits", plural "qubits") to perform computational tasks. In the specific realm where quantum mechanics operates, matter particles can exist in multiple states - such as "on" state, "off" state, and simultaneously "on" and "off" states. While binary calculations using semiconductor processors are limited to using only on and off states (equivalent to 1 and 0 in binary coding), quantum processors utilize these quantum matter states to output signals that can be used for data calculations.

[0006] Conventional computers encode information in bits. Each bit can take on a value of 1 or 0. These 1s and 0s act as on / off switches that ultimately drive the functions of the computer. On the other hand, quantum computers are qubit-based and operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both 1 and 0 simultaneously. Entanglement means that qubits in a superposition can be correlated with each other in a non-classical way; that is, the state of one qubit (whether it is a 1 or a 0 or both) can depend on the state of another qubit, and more information can be ascertained when the two qubits are entangled than when they are processed separately.

[0007] Using these two principles, qubits operate as more complex information processors, enabling quantum computers to operate in ways that allow them to solve difficult problems that are intractable using traditional computers. IBM has successfully built and demonstrated the operability of quantum processors (IBM is a registered trademark of International Business Machines Corporation in the United States and other countries).

[0008] Superconducting qubits can include Josephson junctions. A Josephson junction is formed by separating two thin film superconducting metal layers by a non-superconducting material. When the metal in the superconducting layer is caused to become superconducting (e.g., by lowering the temperature of the metal to a specified cryogenic temperature), electron pairs can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. In a superconducting qubit, the Josephson junction (which has a small inductance) is electrically coupled in parallel with one or more capacitive devices that form a non-linear resonator.

[0009] The information processed by the qubits is emitted in the form of microwave energy in the microwave frequency range. These microwave emissions are captured, processed, and analyzed to decipher the quantum information encoded therein. To make the quantum computing of the qubits reliable, the quantum circuits (e.g., the qubits themselves, the readout circuits associated with the qubits, and other types of superconducting quantum logic circuits) must not change the energy states of these particles or microwave emissions in any significant way. This operating constraint on any circuit that operates using quantum information makes it necessary to take special considerations when fabricating semiconductor structures used in such circuits. SUMMARY OF THE INVENTION

[0010] Exemplary embodiments provide a method of forming solder bumps. In an embodiment, the method includes preparing a transfer mold having solder pillars extending from a mold substrate and through a first photoresist layer, the solder pillars having a shape partially defined by a second photoresist layer, wherein preparing the transfer mold includes removing at least a portion of the second photoresist layer. In an embodiment, the mold substrate is flexible and increases the flexibility of the transfer mold. In an embodiment, the transfer mold is flexible and conforms to a non-planar receiving surface when transferring solder to the non-planar receiving surface. In an embodiment, the method includes providing a device substrate having wettable pads. In an embodiment, the method includes placing the transfer mold and the device substrate in alignment contact such that the solder pillars contact the wettable pads. In an embodiment, the method includes forming a metal bond between the solder pillars and the wettable pads. In an embodiment, the method includes removing the mold substrate and the first photoresist layer.

[0011] In one embodiment, the method includes a first photoresist layer comprising a permanent photoresist material and a second photoresist layer comprising a peelable photoresist material.

[0012] In an embodiment, the method includes forming a wetting layer on a mold substrate. In an embodiment, the method includes forming a seed layer above the mold substrate. In an embodiment, the method includes forming a non-wetting layer on a second photoresist layer.

[0013] In an embodiment, the mold substrate is flexible, and the preparation of the transfer mold includes forming the transfer mold into a flexible transfer mold.

[0014] In an embodiment, the method includes that the device substrate is an interposer, and providing the device substrate includes forming holes therethrough. In an embodiment, the method includes attaching the interposer to a qubit semiconductor device, where the qubit semiconductor device includes a Josephson junction, and where attaching the interposer to the qubit semiconductor device includes aligning the holes through the interposer with the Josephson junction to provide a path for accessing the Josephson junction. In one embodiment, the method includes that the solder pillar is one of a plurality of solder pillars formed around a hole between the qubit semiconductor device and the interposer for providing a thermal isolation amount for the Josephson junction.

[0015] In an embodiment, the method includes a device substrate that includes an organic substrate and forming holes through the device substrate.

[0016] In an embodiment, the method includes: the solder pillar is one of a plurality of solder pillars of the transfer mold, and the plurality of solder pillars includes a first solder pillar having a first diameter and a second solder pillar having a second diameter, the first diameter being greater than the second diameter.

[0017] In an embodiment, the method includes that the device substrate includes a semiconductor substrate and further includes forming deep recesses in the semiconductor substrate. In an embodiment, the method includes that the semiconductor substrate includes circuit components in the deep recesses.

[0018] In an embodiment, the formation of the metal bond includes a cold welding process for forming a metal bond between the solder pillar and the wettable pad.

[0019] In an embodiment, the formation of the metal bond includes performing a reflow process for forming a metal bond between the solder pillar and the wettable pad.

[0020] In an embodiment, the method includes: patterning a first photoresist layer and a second photoresist layer to define recesses extending through the first photoresist layer and the second photoresist layer; and filling the recesses with solder using injection molding soldering (IMS) to form solder pillars.

[0021] In an embodiment, the method includes: patterning the first photoresist layer and the second photoresist layer to define a recess extending through the first photoresist layer and the second photoresist layer; and forming a seed layer, wherein at least a portion of the seed layer is disposed in the recess; and using electroplating to fill the recess with solder and form the solder pillar.

[0022] Embodiments include a method of fabricating a transfer mold for transferring solder to a substrate. In an implementation, the method includes preparing a mold substrate having an upper surface. In an embodiment, the method includes forming a first photoresist layer formed of a permanent photoresist material above the upper surface of the mold substrate. In one implementation, the method includes forming a second photoresist layer formed of a peelable photoresist material on the first photoresist layer. In an embodiment, the method includes patterning the first photoresist layer and the second photoresist layer to form a recess extending through at least a portion of the second photoresist layer and the first photoresist layer. In an embodiment, the method includes forming a solder pillar in the recess. In an embodiment, the method includes removing the second photoresist layer after forming the solder pillar, leaving a portion of the solder pillar extending above the first photoresist layer.

[0023] In an embodiment, the mold substrate is a flexible substrate. In an embodiment, the method includes forming a seed layer above the mold substrate, wherein forming the solder pillar includes using electroplating to form the solder pillar.

[0024] In an embodiment, the method includes using injection molding soldering (IMS) to form the solder pillar.

[0025] Embodiments include a transfer mold device for transferring solder to a substrate. In an embodiment, the device includes a mold substrate, a first photoresist layer formed of a permanent photoresist material over at least a portion of the mold substrate, and a solder pillar extending above the mold substrate through a gap in the first photoresist layer. In an embodiment, the solder pillar includes an extrusion extending above the first photoresist layer. In one implementation, the extrusion has a shape partially defined by a second photoresist layer formed of a peelable photoresist material on the first photoresist layer. In an embodiment, the second photoresist layer is substantially absent from at least a portion of the surface of the first photoresist layer to define an opening region around the extrusion.

[0026] An embodiment includes a superconducting quantum processor that includes: a superconducting chip that includes qubits; an interposer coupled to the superconducting chip, the interposer defining holes aligned with the qubits on the superconducting chip; and a plurality of solder interconnects that form a circular wall around the qubits and between the interposer and the superconducting chip.

[0027] In one embodiment, the circular wall includes at least one gap therethrough.

[0028] In an embodiment, the gap is at least 10 μm wide.

[0029] In an embodiment, the solder interconnects are connected to the superconducting chip and the interposer by corresponding metal bonds. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The novel features believed to be characteristic of the invention are set forth in the appended claims. However, the invention itself, as well as the preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, in which:

[0031] Figure 1 Schematic cross-sections depicting an exemplary method for forming solder bumps, in accordance with an exemplary embodiment Figure 1 A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1J;

[0032] Figure 2A A plan view of an interposer, in accordance with an illustrative embodiment; Figure 2B A plan view of an inserter, in accordance with an illustrative embodiment;

[0033] Figure 3 A cross-sectional view of a semiconductor package, in accordance with an illustrative embodiment;

[0034] Figure 4 A cross-sectional view of a transfer mold, in accordance with an illustrative embodiment;

[0035] Figure 5 Schematic cross-sections depicting an example method for forming solder bumps, in accordance with an exemplary embodiment Figure 5 A, 5B, 5C, 5D, 5E, and 5F;

[0036] Figure 6 A schematic cross-sectional view showing an interposer, in accordance with an illustrative embodiment; and

[0037] Figure 7 A flowchart depicting an example process for forming solder bumps, in accordance with an illustrative embodiment. DETAILED DESCRIPTION

[0038] And the illustrative embodiments used to describe the present invention generally address and solve the problem of incorporating qubits in a wide variety of semiconductor or superconductor packages (hereinafter compactly referred to as packages or a plurality of packages, unless explicitly distinguished in use). Qubits have been successfully incorporated into wirebond packages, where the qubit chip is wirebonded to a substrate, with the Josephson junction facing away from the substrate. It is desirable to incorporate qubits into other types of packages, such as flip-chip packages, which allow a larger number of qubits in a given chip area and can avoid crosstalk problems. However, the inability to access the Josephson junction after manufacturing the package has prevented the use of qubits in other types of packages.

[0039] For example, it is desirable to access the Josephson junction in order to adjust its design frequency. However, certain types of packages do not allow adjustment of the design frequency because there is no line-of-sight access available to apply heat or reactive species to the Josephson junction. For example, a flip-chip package includes a semiconductor or superconductor device disposed face-down on a silicon interposer, so the Josephson junction will face the interposer. The interposer thus prevents access to the Josephson junction, thereby preventing thermal or chemical processes on the Josephson junction. This is problematic because it is desirable to be able to adjust the design frequency of the qubit after manufacturing, since the ideal frequency is not known until the device is assembled and cooled.

[0040] The illustrative embodiments used to describe the present invention generally address and solve the above problem of adjusting the design frequency of qubits in a flip-chip semiconductor package by using a solder transfer method that allows vias in the substrate that would otherwise prevent the use of conventional patterning techniques.

[0041] An embodiment provides a method for forming solder bumps on a substrate. In an embodiment, the method includes preparing a transfer mold that is used during a manufacturing process. In an implementation, the transfer mold is used to transfer a structure onto a component of a package being manufactured. In an embodiment, the transfer mold has solder pillars that extend from a mold substrate and through a first photoresist layer, and the solder pillars have a shape that is partially defined by a second photoresist layer, wherein preparing the transfer mold includes removing at least a portion of the second photoresist layer. In an embodiment, the method includes preparing a device substrate having a wettable pad. In an embodiment, the wettable pad is a pad that promotes the diffusion of liquid solder thereon or forms a metallic bond therewith. In an embodiment, the method includes placing the transfer mold and the device substrate in alignment contact such that the solder pillars contact the wettable pads. In an embodiment, the method includes performing a soldering process that forms a metallic bond between the solder pillars and the wettable pads. In an embodiment, the method includes removing the mold substrate and the first photoresist layer.

[0042] For purposes of the description hereinafter, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the disclosed structures and methods as oriented in the drawings. Terms such as “above,” “overlying,” “on top,” “atop,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, where an intermediate element, such as an interface structure, may be present between the first and second elements. The term “in direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are joined without any intermediate conductive, insulating, or semiconductor layer at the interface of the two elements. The term “substantially” or “substantially similar” means that a difference in length, height, or orientation is not expressed where there is no actual difference between the recited (e.g., the phrase without substantially similar terms) and substantially similar variations. In one implementation, a substantial (and derivatives thereof) represents a difference within generally accepted engineering or manufacturing tolerances for similar devices, up to, for example, a value deviation of 10% or an angular deviation of 10°.

[0043] For clarity of description and without implying any limitation thereto, some example configurations are used to describe illustrative embodiments. In accordance with the present disclosure, those of ordinary skill in the art will be able to envision many variations, adaptations, and modifications of the described configurations for achieving the described purposes, and such variations, adaptations, and modifications are envisioned within the scope of the illustrative embodiments.

[0044] In addition, by way of example only, illustrative embodiments are described with respect to specific actual or hypothetical components. Any specific manifestation of these and other similar products is not intended to limit the present invention. Within the scope of the illustrative embodiments, any suitable manifestation of these and other similar products may be selected.

[0045] The examples in this disclosure are for clarity of description only and are not limited to the illustrative embodiments. Any advantages listed herein are only examples and are not intended to limit these illustrative embodiments. Additional or different advantages may be achieved through specific illustrative embodiments. In addition, a particular illustrative embodiment may have some, all, or none of the advantages listed above.

[0046] See Figure 1 , which shows a schematic cross-section Figure 1 A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1J, which show an example method for forming solder bumps according to an exemplary embodiment. For example, in a specific embodiment, a transfer mold 100 is formed according to the process shown in Figure 1 A-1F, and then, according to the manufacturing processes shown in Figure 1 H and 1J, the transfer mold 100 is used to form solder bumps on the interposer 114 shown in Figure 1 G.

[0047] See Figure 1 A. In a particular embodiment, a substrate 102 is prepared for assembly. In one embodiment, the preparation of the substrate 102 includes one or more processes for improving the adhesion of a forthcoming photoresist material to the substrate 102. For example, in one embodiment, the substrate 102 is prepared in such a way that includes at least one of the following: (1) cleaning to remove contaminants, (2) dehydration baking to remove moisture, and (3) adding an adhesion promoter to the substrate. In an embodiment, the substrate 102 is a substrate formed of any suitable material. For example, in an embodiment, the substrate 102 includes a flexible or rigid material that is stable at the molten solder temperature and stable with respect to a stripping solvent used to remove the photoresist material. For example, in an embodiment, the substrate 102 is rigid and formed of one or more of the following non-limiting example materials: (1) a silicon wafer, (2) a glass plate, (3) a ceramic plate, or (4) a metal plate.

[0048] As another example, substrate 102 is a non-rigid or flexible substrate formed of one or more of the following non-limiting example materials: (1) polyimide film (such as Kapton), (2) polyethylene terephthalate (PET), (3) polyethylene naphthalate (PEN), (4) polyetheretherketone (PEEK), (5) polyethylene (PE), (6) polyvinyl chloride (PVC), and (7) thin flexible metal or glass. In one embodiment, substrate 102 is a flexible substrate having a relatively low Young's modulus. For example, in an embodiment, substrate 102 is a flexible substrate having a Young's modulus of 60 kPa - 3 MPa. In an embodiment, substrate 102 includes a wafer-sized substrate having a circular or other shape. In an embodiment, substrate 102 is formed from a base substrate having a solder resist (SR) surface.

[0049] See Figure 1 B, in a particular embodiment, a first photoresist layer 104 is formed and patterned over substrate 102 using any known lithography process suitable. For example, in an embodiment, the first photoresist layer 104 includes one or more sub-layers of a dry film photoresist laminate applied according to known techniques. As another example, in one embodiment, the first photoresist layer 104 is formed by one or more applications of a coating material, including each application of the spin-coated coating material to form one or more thin, uniform sub-layers that together form the first photoresist layer 104 having a specific predetermined thickness. In an embodiment, the first photoresist layer 104 is patterned to selectively remove portions of the photoresist material, thereby forming recesses 106. In an embodiment, the recesses 106 extend to the substrate 102. In an embodiment, the first photoresist layer 104 is composed of a photoresist material that is relatively difficult to remove. For example, in one embodiment, the first photoresist layer 104 is composed of a photo-patternable resist that is stable at the molten solder temperature and stable relative to a strippable solvent (such as a highly cross-linked epoxy resin).

[0050] In one embodiment, the first photoresist layer 104 is formed of one or more sub-layers of the following non-limiting example materials: (1) a dry film negative photoresist that is water-resistant and can form a layer having a thickness in the range of 5 μm to 100 μm, such as the Engineering Materials Systems (EMS) DF-1000 series, such as EMS DF-1050, (2) a dry film negative photopolymer that forms a layer having a thickness in the range of 5 μm to 100 μm, such as DuPont Vacrel solder mask film, and (3) an epoxy-based negative photoresist that can be spin-coated or spread as a viscous polymer that forms a layer having a thickness in the range of 1 μm to 300 μm, such as SU-8 epoxy resist. For example, in one embodiment, the first photoresist layer 104 is formed by laminating and patterning 5 to 10 sub-layers of EMS DF-1050 (or one of other relevant EMS photoresists having alternative thicknesses and / or resolutions), each sub-layer film having a thickness in the range of 5 μm to 100 μm, to form a layer 104 having a thickness in the range of 25 μm to 1000 μm. As another example, in one embodiment, the DuPont Vacrel solder mask film is used for the first photoresist layer 104 together with Figure 4 the optional solvent barrier or adhesion layer 414 shown in between the first photoresist layer and the second photoresist layer to protect the solder mask film from the main resist stripping chemicals. In an embodiment, the upper surface of the first photoresist layer 104 is flat and has a uniform height from the upper surface of the substrate 102.

[0051] See Figure 1C-1D, in a particular embodiment, the second photoresist layer 108 is formed on the first photoresist layer 104 and patterned to pattern the first photoresist layer 104 according to the same patterning used to pattern the first photoresist layer 104 using any known suitable lithography process. For example, in one embodiment, the second photoresist layer 108 includes one or more dry film resist laminates applied according to known techniques. As another example, in one embodiment, the second photoresist layer 108 is formed by one or more applications of a coating material, including each application of a spin-coated coating material to form one or more thin, uniform sub-layers that together form the second photoresist layer 108 having a specific predetermined thickness. In an embodiment, the second photoresist layer 108 is patterned to selectively remove portions of the photoresist material, thereby forming recesses 110. In an embodiment, the recesses 110 extend to the substrate 102. In an embodiment, the second photoresist layer 108 is composed of a photoresist material that is relatively easy to remove. For example, in one embodiment, the second photoresist layer 108 is composed of a peelable photo-patternable resist that is stable at the molten solder temperature but is also easily peeled off with a solvent.

[0052] In one embodiment, the second photoresist layer 108 is formed from one or more sub-layers of the following non-limiting example materials: dry film negative photoresists such as (1) DuPont WBR series, WBR2050, WBR2100, WBR2150 (50, 100, and 150 μm thick), (2) Hitachi RY5325 and RY5345 (25 and 45 μm thick), (3) Asahi dry film (Sunfort), and (4) DuPont Riston series materials. For example, in one embodiment, the second photoresist layer 108 is formed by laminating and patterning 5 to 10 sub-layers of a WBR series dry film resist, each sub-layer film having a thickness in the range of 50 μm to 100 μm, to form a layer 104 having a thickness in the range of 250 μm to 1000 μm. In an embodiment, the upper surface of the second photoresist layer 104 is flat and has a uniform height from the upper surface of the substrate 102.

[0053] In an embodiment, the upper surface of the second photoresist layer 108 is flat and has a uniform height from the upper surface of the substrate 102. In an embodiment, the recesses 110 are cylindrical in shape. In another embodiment, the shape of the recesses 110 is frustoconical, with the inner diameter of the recesses 110 being relatively larger at the upper surface of the second photoresist layer 108 and relatively smaller at the bottom of the recesses 110 at the upper surface of the substrate 102. The relatively wide opening at the top of the recesses 110 facilitates separation after solder injection, as described below.

[0054] See Figure 1 E. In a particular embodiment, injection molding soldering (IMS) is used to fill the recess 110, where the filling head 116 traverses the substrate 102 and injects molten solder into the recess 110 to form the pillar 112. In an embodiment, the recess 110 is completely filled to the top, thereby ensuring the uniformity of the height of the resulting solder bumps without leaving solder residues on the mask and allowing the pillar 112 to solidify, conforming to the shape of the recess 110. In an embodiment, no solder flux is used in the recess 110. In an implementation, the pillar 112 is conductive and has a relatively high melting point, although preferably below 285 °C or other temperatures incompatible with the substrate 102. For example, non-limiting examples of materials used as solder to form the pillar 112 are lead-free solders using tin, indium, tin alloys, or indium alloys containing Ag, Cu, Zn, Bi, In, Sb, Ni, Co, Ge, and / or Fe. Sn-20Au (280 °C), Sn-5Sb (243 °C), pure Sn (232 °C), Sn-0.7Cu (227 °C), Sn-3.5Ag (221 °C), and Sn-3.8AG-1.0Cu (217 °C) having relatively high melting points indicated in parentheses.

[0055] In one embodiment, the material for the pillar 112 is deposited to a height greater than the combined thickness of the first photoresist layer 104 and the second photoresist layer 108, and a backgrinding, etching, or other planarization process is performed such that the top surface of the pillar 112 and the upper surface of the second photoresist layer 108 are coplanar, as Figure 1 shown in E. In another embodiment, the conductive pillar 112 is a 3D metal pillar formed by copper plating or copper pillar bumps.

[0056] Refer to Figure 1 F. The reason for the two different photoresist layers 104 and 108 is shown by the presence of the first photoresist layer 104 and the absence of the second photoresist layer 108. In an embodiment, the stripping process for removing the photoresist layer is performed according to known methods, such as those described above for the second photoresist layer 108. For example, in an embodiment, a resist remover suitable for wafer-level packaging (WLP) is used to remove the second photoresist layer 108, which is an aqueous organic mixture formulated to effectively remove wafer bumps and thick photoresists used in WLP, such as DuPont TM EKC162 TMResist remover. Since the first photoresist layer 104 is formed of a photoresist material that is stable with respect to such resist removal, the first photoresist layer 104 remains, while the remaining portion of the second photoresist layer 108 is stripped away leaving the conductive pillars 112. In an embodiment, after removing the second photoresist layer 108, the pressing of the pillars 112 is maintained above the first photoresist layer 104. The remaining structure is shown in Figure 1 F and is an example of an embodiment of a transfer mold 100 for forming solder bumps 122 on an interposer 114.

[0057] Reference Figure 1 G and Figure 2A and 2B , Figure 1 G shows a cross-sectional view of an interposer 114 according to an illustrative embodiment, and Figure 2A and 2B show a plan view of an interposer 114 according to an illustrative embodiment. In a particular embodiment, the interposer 114 is formed from a wafer or a substrate formed of a suitable semiconductor substrate material. For example, in one implementation, the interposer 114 is formed of one or more of the following non-limiting example materials: (1) silicon, (2) glass, and (3) organic substrate material. In an embodiment, the interposer 114 includes conductive structures that provide high density interconnects between the upper and lower surfaces of the interposer 114. For example, in an embodiment, the interposer 114 includes a plurality of through-silicon vias (TSVs) that connect metallization layers on the upper and lower surfaces.

[0058] In an embodiment, the interposer 114 defines a plurality of through-holes 118 that are selectively positioned to align with a plurality of qubits on a semiconductor device that will be connected to the interposer 114 in a flip-chip manner, as discussed below and shown in Figure 3 . For example, in an embodiment, the through-holes 118 have an inner diameter in the range of 50 μm to 500 μm. In an embodiment, the interposer 114 also includes a plurality of wettable pads 120. For example, in an embodiment, the interposer 114 includes under-bump metallurgy (UBM) pads 120. For example, in an embodiment, the UBM pads 120 can be arranged and constructed according to known techniques to allow alignment with and connection to the pillars 112 of the transfer mold 100. In an embodiment, the various through-holes are formed by an etching lithography process or laser drilling.

[0059] Reference Figure 1 H, which shows the result of mounting the interposer 114 onto the transfer mold 100 according to a schematic embodiment. In a particular embodiment, the interposer 114 is aligned above the transfer mold 100, and a soldering process is performed that forms a metal bond between the corresponding die pillars 112 of the interposer UBM pads 120.

[0060] As used herein, the term "metallic bond" generally refers to a metallurgical bond between joined metallic articles, where the joined metallic articles are held together by the same attraction between adjacent electrons of the metal, and where the valence electrons of the joined metallic articles are free to move between the joined metallic articles.

[0061] Examples of metallic bonds include, but are not limited to, bonds created by soldering at a filler-metal / substrate-metal interface, where the solder reacts with a small amount of the substrate metal and wets the metal by forming an intermetallic compound, and where, upon curing, the solder joint is a metallic bond between the solder and the substrate metal that is greater than an adhesion or mechanical attachment.

[0062] Unless otherwise specified, the term "soldering process" as used herein generally refers to any process for joining metals that results in a metallic bond. Examples of soldering processes include, but are not limited to, bonds created by soldering at a filler-metal / substrate-metal interface, where the solder reacts with a small amount of the substrate metal and wets the metal by forming an intermetallic compound, and where, upon curing, the solder joint is a metallic bond between the solder and the substrate metal that is greater than an adhesion or mechanical attachment.

[0063] In one embodiment, the columns 112 are attached to the respective UBM pads 120 using a reflow process that heats the columns 112 until they begin to melt upon contact with the UBM pads 120 and then allows them to cool and re-cure. This process results in soldering between the columns 112 and the respective UBM pads 120. In another embodiment, the metallic bond between the columns 112 and the UBM pads 120 is formed by a cold welding process that joins certain metals at a temperature below the reflow temperature, such as room temperature diffusion or diffusion at a temperature between room temperature and the reflow temperature. For example, in an embodiment, the metallic bond between the columns 112 and the UBM pads 120 is formed by a cold welding process that includes applying pressure at room temperature or applying a certain amount of heat.

[0064] See Figure 1 J, which shows the interposer 114 with vias 118 and solder bumps 122 after removal of the substrate 102 and the first photoresist layer 104. In a particular embodiment, the substrate 102 and the first photoresist layer 104 may be lifted off the interposer 114 and leave the columns 112 attached to the interposer 114 because the metallic bond between the solder in the columns 112 and the UBM pads 120 is much stronger than a second type of force that holds the columns 112 to the substrate 102, such as force of dispersion or van der Waals type.

[0065] See Figure 2A and2B , these figures depict Figure 1 a plan view of an embodiment of the interpolator 114 shown in J, on which solder bumps 122 are formed. In Figure 2A the illustrative embodiment shown, configuration 200a includes a plurality of solder bumps 122 separated by gaps 202, which are formed around the vias 118. In Figure 2B the exemplary embodiment shown, configuration 200b includes a plurality of solder bumps 122, each of which contacts an adjacent bump 122 and is formed around the vias 118. The solder bumps 122 in configurations 200a and 200b together improve the thermal isolation of the Josephson junction 304 (shown in Figure 3 ) during the thermal or chemical operations described below, thereby helping to prevent heat from the annealing operation from affecting or damaging other components.

[0066] In an embodiment, the configuration 200a of the solder bumps 122 is arranged around the vias 118 without physically contacting each other, so that there is a gap 202 between adjacent solder bumps 122. For example, in an embodiment of configuration 200a, the solder bumps 122 formed around the vias 118 block at least half of the cylindrical region that is aligned with the vias 118 and extends between the interpolator 114 and the substrate 302 mounted thereon. In an embodiment, the configuration 200b of the solder bumps 122 is arranged around the vias 118 without a gap 202. However, although such an embodiment provides good thermal isolation, it is difficult to access these qubits, for example, through a bus if these solder bumps 122 form a continuous ring. Therefore, it is preferred to form an almost continuous ring, leaving at least one or more gaps 202 as small as 10 μm (e.g., in the range of 10 μm to 20 μm), which are small enough to minimize heat transfer and mass transfer. In an embodiment, the number of gaps 202 depends on the qubit connectivity (e.g., the number of readout resonators plus the number of qubit-to-qubit buses). In an embodiment, a continuous or almost continuous ring of solder bumps 122 is formed by lithography and IMS or electroplating one or more ring segments of any shape. In another embodiment, a continuous or almost continuous ring of solder bumps 122 is formed by transferring spherical bumps 122 to a substrate with a patterned wettable segmented ring, and then performing a second reflow after removing the transfer mold, which will cause the solder to wet the segmented ring. In yet another embodiment, a continuous or almost continuous ring of solder bumps 122 is formed by patterning the bumps at a close pitch within the perimeter of the segmented ring, such that when the interpolator is attached to the superconducting chip 300 (or other substrate), these bumps 122 merge according to the applied pressure and heat (e.g., higher pressure during the bonding process produces shorter and wider bumps that physically contact each other).

[0067] See Figure 3 , which depicts a cross-sectional view of an example semiconductor package according to an illustrative embodiment. In a particular embodiment, the semiconductor package is a flip-chip package that includes a superconducting chip 300 disposed face-down on a silicon interposer 114. The superconducting chip 300 includes a substrate 302 that has a plurality of qubit Josephson junctions 304. In an embodiment, the Josephson junctions 304 are aligned with vias 118 defined by the interposer 114. In an embodiment, these vias 118 provide a line-of-sight path 308 to allow direct heat, electromagnetic (EM) radiation, or reactive chemical species to pass through the interposer 114 such that the junction modification system 306 can direct such heat, radiation, or chemical species onto the Josephson junctions 304 to tune the frequency of the qubits. In an embodiment, the path 308 has an outer diameter in the range of 10 μm to 20 μm. For example, in an embodiment, the path 308 has an outer diameter of about 15 μm.

[0068] In an embodiment, the substrate 302 on which the qubit circuit is formed is a high-resistivity (intrinsic) silicon wafer. In another embodiment, the Josephson junctions 304 are fabricated using aluminum as a starting compound to form an Al / AlOx / Al structure on the silicon (Si) substrate 302. For example, in an embodiment, the substrate 302 is selected to reduce the dielectric loss tangent at low temperatures. For example, in an embodiment, the substrate 302 is selected as a material that is selectively etched into superconducting and dielectric materials for the Josephson junctions 304. For example, in an embodiment, it can be achieved that the substrate 302 is a high-resistivity Si wafer.

[0069] In an embodiment, the Josephson junctions 304 are adjusted to tune the frequencies of the qubits. In an embodiment, the adjustment of the Josephson junctions 304 includes heating, irradiating, or applying a chemical species to the Josephson junctions 304 to allow physical changes to occur within the Josephson junctions 304 that result in a change in resistance.

[0070] See Figure 4 , which depicts a cross-sectional view of an example transfer mold according to an illustrative embodiment, showing optional layers that may be included.

[0071] For example, embodiments include forming pillars 112 using solder of a problematic type or a problematic pillar aspect ratio that prevents proper filling of the recess 410 with solder. Thus, at the bottom of the recess, the wetting layer is a thin layer of metal that allows the solder to fill the recess and remain at the bottom, and because the solder is being established. In such embodiments, a wetting layer is employed to correct the problem by forming a wetting layer at layer location 412 and also optionally at layer location 418. The wetting layer allows subsequent conductive materials to reflow with minimized interaction with the surface having the wetting layer (i.e., at layer locations 412 and / or 418). For example, embodiments include a wetting layer that includes one or more of titanium and gold, silver, or copper formed at layer locations 412 and 418, and pillars 112 including aluminum (Al) are subsequently deposited and reflowed to fill the recess 410 and are allowed to form pillars 112, wherein the interaction between the aluminum (Al) of the pillars 112 and the wetting layer at layer locations 412 and 418 is minimized. For example, embodiments include a wetting layer that includes titanium and one or more of gold, silver, and copper, wherein the titanium acts as an adhesion layer between the substrate and the gold, silver, and / or copper, such that the gold / silver / copper will be consumed by the material of the pillars 112 during subsequent reflow (for a period of time), and subsequently the titanium will be dewetted, such that the pillars 112 can be more easily separated from the substrate 402.

[0072] In an embodiment, a seed layer is formed at layer location 412 to allow the formation of pillars 112 by known electroplating processes as an alternative to using injection molding as described above in connection with Figure 1 E. In another embodiment, a gold layer is formed at layer location 412, and solder is injected into the recess 410 to form pillars; gold is a high-energy metal that reacts with the solder to ensure that the solder remains in the recess 410. For example, in one such embodiment, when heated, the gold at layer location 412 also acts as a release layer to allow easier separation while helping to hold the solder in the recess during various processing stages, which is helpful when transferring pillars 112 having a relatively high aspect ratio.

[0073] In one embodiment, one or both of layer locations 412 and 414 are provided as a metal or adhesion layer to help fix the first photoresist layer 404 to the substrate 402 (at layer location 412) or to help fix the second photoresist layer 408 to the first photoresist layer 404 (at layer location 414).

[0074] In an embodiment, layer location 416 is provided as a non-wetting layer to prevent solder deposition on the second photoresist layer 408. For example, in an embodiment, a layer of titanium, molybdenum, or graphite at layer location 416 acts as a non-wetting layer because when the solder reflows and contacts the exposed titanium, molybdenum, or graphite, the non-wetting properties of these materials cause the solder to tend to form loose solder balls rather than a metal bond.

[0075] See Figure 5 , which shows a schematic cross-section Figure 5 A, 5B, 5C, 5D, 5E, and 5F, showing an exemplary method for forming solder bumps according to an exemplary embodiment. For example, in a particular embodiment, a transfer mold 506 is used to form solder bumps 514 on an organic substrate 502 having vias 504. In an embodiment, the semiconductor device 516 is flip-chip mounted such that the Josephson junction 518 can be tuned by emitting direct heat, electromagnetic (EM) radiation, or reactive chemical species along a path 528 that passes through the via 504 in the organic substrate 502.

[0076] See Figure 5 A and 5B, in a particular embodiment, an organic substrate 502 is provided and vias 504 are cut, drilled, or otherwise formed therethrough. In an embodiment, the vias 504 are formed by an etching lithography process or laser drilling. In an alternative embodiment, the organic substrate 502 is pre-formed with vias 504. In an implementation, as a non-limiting example, the organic substrate 502 includes a laminate made of glass fibers in an epoxy resin and a bismaleimide triazine (BT) resin. In an embodiment, the via 504 is one of a plurality of vias in the substrate 502.

[0077] As another example, the substrate 502 is a non-rigid or flexible substrate formed of one or more of the following non-limiting example materials: (1) a polyimide film (such as Kapton), (2) polyethylene terephthalate (PET), (3) polyethylene naphthalate (PEN), (4) polyether ether ketone (PEEK), (5) polyethylene (PE), (6) polyvinyl chloride (PVC), and (7) thin flexible metal or glass. In one implementation, the substrate 502 is a flexible substrate having a relatively low Young's modulus. For example, in an embodiment, the substrate 502 is a flexible substrate having a Young's modulus in the range of 60 kPa to 3 MPa.

[0078] See Figure 5 C, as Figure 1 shown in A-1F and as described above for fabricating the transfer mold 506, resulting in the structure shown having a substrate 508, a first photoresist layer 510, and a plurality of posts 512, including a pair of small posts 512 and a pair of large posts 512.

[0079] In one embodiment, the substrate 508 is a non-rigid or flexible substrate formed of one or more of the following non-limiting example materials: (1) a polyimide film (such as Kapton), (2) polyethylene terephthalate (PET), (3) polyethylene naphthalate (PEN), (4) polyether ether ketone (PEEK), (5) polyethylene (PE), (6) polyvinyl chloride (PVC), and (7) thin flexible metal or glass. In one implementation, the substrate 508 is a flexible substrate having a relatively low Young's modulus. For example, in an embodiment, the substrate 508 is a flexible substrate having a Young's modulus in the range of 60 kPa to 3 MPa.

[0080] In an embodiment, the transfer mold 506 is flexible, allowing it to conform to a flat or macroscopically curved substrate for transferring solder to the substrate. For example, in an embodiment, both the transfer mold 506 and the substrate 508 are flexible and non-planar, and solder is transferred from the transfer mold 506 to the substrate 502. In an embodiment, the substrate 508 is rigid but macroscopically curved, and the transfer mold 506 is flexible and bends to conform to the shape of the substrate 508 while transferring solder to the substrate 502.

[0081] See Figure 5 D, the transfer mold 506 forms solder bumps 514 on the organic substrate 502, as described above in See Figure 1 H and 1J, such that the pillars 512 become solder bumps 514. In an embodiment, the organic substrate 502 may include wettable pads (not shown) formed of copper, gold, or nickel to provide a contact surface for forming a metal bond with the solder bumps 514.

[0082] See Figure 5 E and 5F, which depict cross-sectional views of an example semiconductor package according to an illustrative embodiment. In a specific embodiment, the semiconductor package is a flip-chip package that includes a semiconductor device 516 having a plurality of qubit Josephson junctions 518 disposed face-down on an organic substrate 502.

[0083] In an embodiment, the Josephson junctions 518 are aligned with vias 504 defined by the organic substrate 502. In an embodiment, the vias 504 allow the junction modification system 526 to emit direct heat, electromagnetic (EM) radiation, or reactive chemical species along a path 528 to tune each qubit Josephson junction 518.

[0084] For example, in an embodiment, the junction modification system 526 modifies the Josephson junctions 518 by emitting direct heat, electromagnetic (EM) radiation, or reactive chemicals along the path 528 to the Josephson junctions 518 to allow physical changes to occur within the Josephson junctions 518 that result in a change in resistance.

[0085] See Figure 6 , which depicts an interposer 600 having deep well features 604 between solder bumps 606, and the deep well features 604 can be formed using a transfer mold in the same manner as described above in connection with Figure 1 A-1J. In a particular embodiment, the interposer 600 includes a substrate 602 having recessed circuit components 608 at the bottom of the recesses 604. For example, in an embodiment, the recesses 604 are microwave cavities and the circuit elements are qubits having Josephson junctions. In an embodiment, the solder bumps 606 are formed of indium or an indium alloy. In an embodiment, a transfer mold (such as Figure 1 the transfer mold 100 shown in F) is used to form the solder bumps 606 on the substrate 602, where the solder for the solder bumps 606 is transferred from the posts 112 on the transfer mold 100.

[0086] See Figure 7 , which depicts a flowchart of an example process 700 for solder bumps according to an illustrative embodiment. In a particular embodiment, the process 700 includes the processes described above in connection with Figure 1 A-1J, 2, and 3.

[0087] In a particular embodiment, at block 702, the substrate is prepared for assembly. In one embodiment, the preparation of the substrate includes one or more processes for improving the adhesion of the upcoming photoresist material to the substrate. For example, in one implementation, the substrate is prepared in such a way that includes at least one of the following: (1) cleaning to remove contaminants, (2) dehydration baking to remove moisture, and (3) adding an adhesion promoter to the substrate.

[0088] In an embodiment, at block 704, a first photoresist layer is formed and patterned over the substrate using any suitable known lithography process. In one embodiment, the first photoresist layer consists of one or more sublayers of a relatively difficult-to-remove "permanent" photoresist material. For example, in one implementation, the first photoresist layer consists of a photo-patternable resist that is stable at the molten solder temperature and stable relative to a strippable solvent (such as a highly cross-linked epoxy resin). In an embodiment, the first photoresist layer is formed by coating the coating material one or more times, including each coating of the coating material by spin coating to form one or more thin, uniform sublayers, which together form a second photoresist layer having a specific predetermined thickness, and then patterned to selectively remove portions of the photoresist material, thereby forming recesses. In an embodiment, the recesses extend into the substrate.

[0089] In an embodiment, at block 706, a second photoresist layer is formed and patterned over the first photoresist layer according to the same patterning used to pattern the first photoresist layer using any known lithography process suitable therefor. In one embodiment, the second photoresist layer consists of one or more sub-layers of a photoresist material that is relatively easy to remove. For example, in one implementation, the second photoresist layer consists of a "peelable" photo-patternable resist that is stable at the molten solder temperature but is also easily peelable with a solvent. In an embodiment, the second photoresist layer is formed by coating the coating material one or more times, including each coating of the spin-coated coating material to form one or more thin, uniform sub-layers that together form the second photoresist layer having a specific predetermined thickness, and then patterned to selectively remove portions of the photoresist material, thereby forming recesses.

[0090] In an embodiment, at block 708, the patterning at blocks 704 and 706 includes pattern features in which recesses are formed and arranged such that the recesses formed at block 704 are aligned with the recesses formed at block 706. In an embodiment, the recesses formed at blocks 704 and 706 extend from the upper surface of the second photoresist layer to the upper surface of the substrate. In some embodiments, blocks 706 and 708 may optionally include forming any one or more of the layers described at positions 412, 414, 416, and 418 See Figure 4 any one or more of the layers described.

[0091] In an embodiment, at block 710, injection molding soldering (IMS) is used to fill the recesses, where a fill head traverses the substrate and injects molten solder into the recesses to form pillars. In an embodiment, the recesses are completely filled to the top, thereby ensuring uniformity in the height of the resulting solder bumps without leaving solder residues on the mask, and allowing the pillars to solidify, conforming to the shape of the recesses. It will be appreciated that block 710 may alternatively include using electroplating to form the pillars.

[0092] In an embodiment, at block 712, a resist remover suitable for wafer-level packaging (WLP) is used to remove the second photoresist layer. For example, in an embodiment, the resist remover is an aqueous organic mixture that is formulated to effectively remove thick photoresists used in wafer bumps and WLP, such as DuPont TM EKC162 TM resist remover. Since the first photoresist layer is formed of a photoresist material that is stable relative to such resist removal, the first photoresist layer remains while the remainder of the second photoresist layer is stripped away leaving the conductive pillars.

[0093] In an embodiment, at block 714, the interposer is formed from a wafer or a substrate formed of a suitable semiconductor substrate material. In an embodiment, the interposer defines a plurality of vias that are selectively positioned to align with a plurality of qubits on a semiconductor device that will be connected to the interposer in a flip-chip manner. In an embodiment, the vias are formed by an etching lithography process or laser drilling.

[0094] In an embodiment, at block 716, the interposer is mounted to the transfer mold by flipping the interposer such that the solder pads on the interposer face and align with the posts of the transfer mold.

[0095] In an embodiment, at block 718, the interposer is attached to the transfer mold by forming a metal bond between the interposer UBM pads and the corresponding transfer mold posts. In one embodiment, a reflow process is used to attach the posts to the corresponding UBM pads, the reflow process heating the posts until they begin to melt upon contact with the UBM pads and then allowing them to cool and re-solidify, thereby creating a solder joint between the posts and the corresponding UBM pads. In another embodiment, a metal bond between the posts and the UBM pads is formed by a cold welding process that joins certain metals at a temperature below the reflow temperature, such as room temperature diffusion or diffusion at a temperature between room temperature and the reflow temperature. For example, in an embodiment, the metal bond between the posts and the UBM pads is formed by a cold welding process that includes applying pressure at room temperature or applying a certain amount of heat.

[0096] In an embodiment, at block 720, the substrate and the first photoresist layer are removed from the posts that are now metallically bonded to the interposer. In a particular embodiment, the substrate and the first photoresist layer can be lifted away from the interposer and the posts attached to the interposer are left behind because the metal bond between the solder in the posts and the UBM pads is much stronger than a second type of force that holds the posts to the substrate, such as a force of dispersion or van der Waals type.

[0097] In an embodiment, at block 722, a semiconductor device having a plurality of qubit Josephson junctions is disposed face down on the silicon interposer. In an embodiment, the Josephson junctions are aligned with the vias defined by the interposer to allow the junction modification system to emit direct heat, electromagnetic (EM) radiation, or reactive chemical species to tune the qubit Josephson junctions on the semiconductor device.

[0098] In an embodiment, at block 724, the process tunes the resistance of the Josephson junctions in order to tune the frequency of the qubits. In an embodiment, the junction modification system adjusts the Josephson junctions by applying direct heat, electromagnetic (EM) radiation, or reactive chemicals using a path through the vias in the interposer.

[0099] The following definitions and abbreviations will be used to interpret the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0100] In addition, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are to be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" is to be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include indirect "connection" and direct "connection."

[0101] References in the specification to "one embodiment," "an embodiment," "exemplary embodiment," etc., mean that the particular embodiment described may include a particular feature, structure, or characteristic, but each embodiment may or may not include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is considered within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments (whether or not explicitly described).

[0102] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with a particular measurement of a given quantity based on the equipment available at the time of filing the application. For example, "about" may include a range of ±8% or 5%, or 2% of a given value.

[0103] The description of the various embodiments of the invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to one of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein have been chosen to best explain the principles of the embodiments, the practical application, or a technical improvement over the technology found in the marketplace, or to enable one of ordinary skill in the art to understand the embodiments described herein.

[0104] Descriptions of various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein have been chosen to best explain the principles of the embodiments, practical application, or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments described herein.

[0105] Accordingly, in an illustrative embodiment, there is provided a computer-implemented method, system, or apparatus, and a computer program product for managing participation in an online community and other related features, functions, or operations. When an embodiment or a part thereof is described in terms of a type of device, the computer-implemented method, system, or apparatus, the computer program product, or a part thereof is adapted or configured to be used with a suitable and comparable performance of that type of device.

[0106] Where an embodiment is described as being implemented in an application, the delivery of the application in a software-as-a-service (SaaS) model is contemplated within the scope of the illustrative embodiments. In the SaaS model, the ability to implement the application of the embodiment is provided to users by executing the application in a cloud infrastructure. Users can access the application using various client devices through a thin client interface such as a web browser (e.g., web-based email) or other lightweight client applications. The users do not manage or control the underlying cloud infrastructure including the network, servers, operating systems, or storage of the cloud infrastructure. In some cases, the users may not even manage or control the capabilities of the SaaS application. In some other cases, the SaaS implementation of the application may allow for possible exceptions for limited user-specific application configuration settings.

[0107] The present invention may be a system, method, and / or computer program product of any possible technical detail integration level. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the present invention.

[0108] A computer-readable storage medium can be a tangible device that retains and stores instructions for use by an instruction execution device. A computer-readable storage medium may be, for example but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punched card, or a raised structure with instructions recorded thereon in a recess, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0109] The computer-readable program instructions described herein can be downloaded to a corresponding computing / processing device from a computer-readable storage medium via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or an external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the corresponding computing / processing device.

[0110] The computer-readable program instructions for carrying out operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc. and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, an electronic circuit, including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit, so as to perform various aspects of the present invention.

[0111] The present invention will hereinafter be described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0112] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions executed via the processor of the computer or other programmable data processing device create a means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which instructions cause a computer, a programmable data processing device, and / or other devices to work in a particular manner, so that the computer-readable storage medium in which the instructions are stored includes a manufacture including instructions for implementing aspects of the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0113] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing device, or other device, such that a series of operation steps are performed on the computer, other programmable device, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable device, or other device implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0114] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of the possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, depending on the functions involved, two consecutive blocks shown may actually be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions or a combination of dedicated hardware and computer instructions.

[0115] In a preferred embodiment of the present invention, a method of manufacturing a transfer mold for transferring solder to a substrate is provided. The method includes: preparing a mold substrate having an upper surface; forming a first photoresist layer formed of a permanent photoresist material on the upper surface of the mold substrate; forming a second photoresist layer formed of a peelable photoresist material on the first photoresist layer; patterning the first and second photoresist layers to form recesses extending through at least a portion of the second photoresist layer and the first photoresist layer; forming solder pillars in the recesses; and removing the second photoresist layer after forming the solder pillars, leaving portions of the solder pillars extending above the first photoresist layer.

[0116] Viewed from another aspect of the present invention, a transfer mold for transferring solder to a substrate is provided. The transfer mold includes: a mold substrate; a first photoresist layer formed of a permanent photoresist material on at least a portion of the mold substrate; and solder pillars extending above the mold substrate through gaps in the first photoresist layer. The solder pillars include extrusions extending above the first photoresist layer, wherein the extrusions have a shape partially defined by a second photoresist layer formed of a peelable photoresist material on the first photoresist layer, and wherein the second photoresist layer is substantially absent from at least a portion of the surface of the first photoresist layer to define an opening area around the extrusions.

Claims

1. A method of forming solder bumps, the method comprising: Preparing a transfer mold having solder pillars extending from a mold substrate and through a first photoresist layer, the solder pillars having a shape partially defined by a second photoresist layer, wherein the preparation of the transfer mold includes removing at least a portion of the second photoresist layer; Configuring a device substrate to include a wettable pad; Aligning the transfer mold with the device substrate such that the solder pillars are aligned with the wettable pads; Forming a metal bond between the solder pillars and the wettable pads; And Removing the mold substrate and the first photoresist layer.

2. The method according to claim 1, wherein, The first photoresist layer comprises a permanent photoresist material, and the second photoresist layer comprises a peelable photoresist material.

3. The method according to claim 1, wherein, The preparation of the transfer mold includes forming at least one of the following: A wetting layer above the mold substrate; A seed layer located on the mold substrate; And A non-wetting layer on the second photoresist layer.

4. The method according to claim 1, wherein The mold substrate is flexible, and the preparation of the transfer mold includes forming the transfer mold as a flexible transfer mold.

5. The method according to claim 1, further comprising forming a hole through the device substrate.

6. The method according to claim 5, further comprising attaching an interposer to a qubit semiconductor device, wherein the qubit semiconductor device includes a Josephson junction, and wherein attaching the interposer to the qubit semiconductor device includes aligning the hole through the interposer with the Josephson junction to provide a path for accessing the Josephson junction.

7. The method according to claim 6, wherein The solder pillar is one of a plurality of solder pillars formed around the hole between the qubit semiconductor device and the interposer to provide a thermal isolation amount for the Josephson junction.

8. The method according to claim 1, wherein, The device substrate includes an organic substrate and further includes forming a hole through the device substrate.

9. The method according to claim 1, wherein, The solder pillar is one of a plurality of solder pillars of the transfer mold, and wherein the plurality of solder pillars includes a first solder pillar having a first diameter and a second solder pillar having a second diameter, the first diameter being greater than the second diameter.

10. The method according to claim 1, wherein, The device substrate includes a semiconductor substrate, and the method further comprises forming a deep recess in the semiconductor substrate.

11. The method according to claim 10, wherein, The semiconductor substrate includes circuit components in the deep recess.

12. The method according to claim 1, wherein The formation of the metal bond includes a cold welding process that forms the metal bond between the solder pillar and the wettable pad.

13. The method according to claim 1, wherein, Forming the metal bond includes a reflow process that forms the metal bond between the solder pillar and the wettable pad.

14. The method according to claim 1, wherein The preparation of the transfer mold includes: Patterning the first and second photoresist layers to define recesses extending through the first and second photoresist layers; and Filling the recesses with solder using injection molding soldering (IMS) to form the solder pillars.

15. The method according to claim 1, wherein The preparation of the transfer mold includes: Patterning the first and second photoresist layers to define recesses extending through the first and second photoresist layers; Form a seed layer, wherein at least a part of the seed layer is disposed in the recess; and Fill the recess with electroplating solder and form the solder column.

16. The method according to claim 1, wherein The preparation of the transfer mold includes: Prepare a mold substrate having an upper surface; Form a first photoresist layer above the upper surface of the mold substrate, the first photoresist layer being formed of a permanent photoresist material; Form a second photoresist layer formed of a peelable photoresist material on the first photoresist layer; Pattern the first and second photoresist layers to form a recess extending through at least a part of the second photoresist layer and the first photoresist layer; Form a solder column in the recess; and After forming the solder column, remove the second photoresist layer, leaving a portion of the solder column extending above the first photoresist layer.

17. The method according to claim 16, wherein, The mold substrate is a flexible substrate.

18. The method according to claim 16, further comprising forming a seed layer over the mold substrate, wherein, Forming the solder column includes using electroplating to form the solder column.

19. The method according to claim 16, wherein Forming the solder column includes using injection molding soldering (IMS) to form the solder column.

20. A superconducting quantum processor, comprising: A superconducting chip including qubits; An interposer connected to the superconducting chip, the interposer defining a hole therethrough, the hole being aligned with the qubits on the superconducting chip; And A plurality of solder interconnections forming a circular wall around the qubits and between the interposer and the superconducting chip.

21. The processor according to claim 20, wherein, The circular wall includes at least one gap therethrough.

22. The processor according to claim 21, wherein, The at least one gap is at least 10 μm wide.

23. The processor according to claim 20, wherein, The solder interconnections are connected to the superconducting chip and the interposer by respective metal bonds.

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