Power semiconductor device and preparation method thereof

Abstract

The embodiment of the present application provides a power semiconductor device and a method for preparing the same. The power semiconductor device includes: a first electrode layer, a semiconductor substrate, and a first interlayer dielectric layer stacked in sequence, wherein the semiconductor substrate is provided with a body region, and the body region is provided with a doped region; a first trench, a second trench, and a third trench, wherein the first trench and the third trench are respectively provided with a gate dielectric layer; a first metal plug, a second metal plug, and a third metal plug, wherein the first metal plug is located in the first trench, the second metal plug is located in the second trench, and the third metal plug is located in the third trench; a second interlayer dielectric layer located on the first interlayer dielectric layer; a second electrode layer and a gate arranged at intervals on the second interlayer dielectric layer. The trenches in the power semiconductor device are filled with metal, which has stable withstand voltage, low charge, fast response speed, low resistance, faster response to alternating signals, and can effectively reduce switching time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and a method for preparing the same. Background Art

[0002] Currently, as a type of power semiconductor device, the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has become a mainstream device in today's electronic devices. MOSFETs are voltage-controlled components that operate at very low currents and voltages. Their simple integration process has led to their widespread use in large-scale integrated circuits. Trench MOSFETs offer a high cost-performance ratio. For example, MOSFETs with a U-shaped trench (UMOSFET) are widely used in various applications, including motor speed control, inverters, power supplies, electronic switches, audio equipment, and automotive electronics.

[0003] The existing UMOSFET manufacturing process is complex, and the device performance parameters are closely correlated with the process parameters. The device performance reacts sharply to process fluctuations, which easily leads to abnormalities such as device performance degradation and increased failure rate, resulting in waste of resources.

[0004] Therefore, the structure of current power semiconductor devices and their preparation methods still need to be improved. Summary of the Invention

[0005] To address the above problems, the present invention provides a power semiconductor device that can balance device performance and manufacturing process, reducing the significant impact of process fluctuations on device performance. The present invention also provides a method for manufacturing the power semiconductor device.

[0006] To achieve the above-mentioned object, according to one aspect of the present invention, a power semiconductor device is provided, comprising: a first electrode layer, a semiconductor substrate, and a first interlayer dielectric layer stacked in sequence; a body region is provided in the semiconductor substrate, and a doped region is provided in the body region; the body region includes a first region, a second region, and a third region;

[0007] a first trench, a second trench, and a third trench, wherein the first trench is located in the first region and its bottom passes through the body region, the second trench is located in the second region, and the third trench is located in the third region and its bottom passes through the body region, and a gate dielectric layer is respectively disposed in the first trench and the third trench;

[0008] a first metal plug, a second metal plug, and a third metal plug, wherein the first metal plug is located in the first trench and its top portion extends to the first interlayer dielectric layer, the second metal plug is located in the second trench and its top portion extends to the first interlayer dielectric layer, and the third metal plug is located in the third trench and its top portion extends to the first interlayer dielectric layer;

[0009] a second interlayer dielectric layer located on the first interlayer dielectric layer, the second interlayer dielectric layer covering the first metal plug, and the second interlayer dielectric layer having a first opening and a second opening in regions corresponding to the second metal plug and the third metal plug, respectively;

[0010] A second electrode layer and a gate are spaced apart and arranged on the second interlayer dielectric layer. The second electrode layer is connected to the second metal plug through the first opening, and the gate is connected to the third metal plug through the second opening.

[0011] The power semiconductor device provided by the present invention has at least one of the following advantages: since the first and third trenches are respectively filled with metal to form the first metal plug and the third metal plug, due to the low resistance of the metal, the reaction is faster when the alternating signal occurs, which can effectively reduce the switching time; compared with the prior art of using doped polysilicon to fill the trench, the first and third metal plugs have better conductivity, greatly reduced resistance, and no carrier offset and depletion effects will occur when a bias voltage is applied; the process cost of doped polysilicon deposition is high, and the equipment maintenance cost is high. The present application does not need to use a polysilicon deposition process to fill the trench; the trenches in the device are filled with metal, which has stable withstand voltage, low charge, fast response speed, low resistance, and faster reaction when the alternating signal occurs, which can effectively reduce the switching time; the first interlayer dielectric layer provided on the surface of the semiconductor substrate can be used as a hard mask (Hard A mask is formed to define the positions of the first, second, and third trenches. This allows for self-alignment of the photolithography layer when forming the first / third trenches and the second trench, reduces processing difficulty and reliance on high-precision photolithography equipment, and avoids significant impacts on device performance due to overlay deviation.

[0012] Another aspect of the present invention provides a method for fabricating a power semiconductor device, comprising: forming a body region in a semiconductor substrate, forming a doped region in the body region, and forming a first interlayer dielectric layer covering the semiconductor substrate, wherein the body region includes a first region, a second region, and a third region; the first interlayer dielectric layer is provided with a first precursor trench corresponding to the first region, a second precursor trench corresponding to the second region, and a third precursor trench corresponding to the third region;

[0013] forming a first photoresist pattern on the first interlayer dielectric layer, wherein the first photoresist pattern has a first photoresist opening and a second photoresist opening in regions corresponding to the first precursor trench and the third precursor trench, respectively;

[0014] Using the first photoresist pattern and the first interlayer dielectric layer as masks, etching the semiconductor substrate and removing the first photoresist pattern to form a first trench and a third trench passing through the body region, respectively;

[0015] forming a gate dielectric layer on the inner wall of the first trench and the inner wall of the third trench;

[0016] Etching the body region corresponding to the second precursor trench to form a second trench passing through the doped region;

[0017] forming a first metal plug, a second metal plug, and a third metal plug in the first trench, the second trench, and the third trench respectively;

[0018] forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer has a first opening and a second opening in regions corresponding to the second metal plug and the third metal plug, respectively;

[0019] forming a second electrode layer and a gate spaced apart on the second interlayer dielectric layer, wherein the second electrode layer is connected to the second metal plug through the first opening, and the gate is connected to the third metal plug through the second opening;

[0020] A first electrode layer is formed on a side of the semiconductor substrate away from the first interlayer dielectric layer.

[0021] The power semiconductor device prepared by this method can be the power semiconductor device described above, and thus, the method can have all the features and advantages of the power semiconductor device described above, which will not be repeated here. In general, the method has at least one of the following advantages: the first groove and the third groove can be formed simultaneously by one lithography, which helps the subsequent lithography to achieve self-alignment and improve the yield, does not require the use of two KrF lithography passes, and avoids the overlay accuracy deviation caused by the two KrF lithography passes, and greatly reduces the cost; at the same time, the first interlayer dielectric layer and the first photoresist pattern are used as masks to achieve self-aligned etching to form the first groove and the third groove, which reduces the requirements for the lithography machine and improves the redundancy of the overlay; uses self-aligned etching to form the second groove, which reduces the requirements for the lithography machine and improves the redundancy of the overlay; does not require the pursuit of overly precise alignment and positioning, and does not require the use of KrF light source lithography equipment, which greatly reduces the processing difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 shows a schematic structural diagram of a power semiconductor device according to an embodiment of the present invention;

[0023] Figure 2 shows a schematic structural diagram of a power semiconductor device according to another embodiment of the present invention;

[0024] Figure 3 A schematic diagram showing the working principle of a power semiconductor device according to an embodiment of the present invention is shown;

[0025] Figure 4 shows a schematic structural diagram of a power semiconductor device according to an embodiment of the present invention;

[0026] Figure 5 shows a schematic structural diagram of a power semiconductor device according to another embodiment of the present invention;

[0027] Figure 6-8 , 10-12, and 14-18 respectively show partial structural schematic diagrams of a power semiconductor device according to yet another embodiment of the present invention;

[0028] Figure 9 、 Figure 13 and Figure 19 A partial top view of a power semiconductor device during fabrication according to an embodiment of the present invention is shown.

[0029] Description of reference numerals:

[0030] 100: First electrode layer; 200: Semiconductor substrate; 210: Substrate; 220: Epitaxial layer; 400: Body region; 500: Doped region; 610: First interlayer dielectric layer; 620: Second interlayer dielectric layer; 11: First trench; 12: Second trench; 13: Third trench; 14: First precursor trench; 15: Second precursor trench; 16: Third precursor trench; 20: Gate dielectric layer; 31: First metal plug; 32: Second metal plug; 33: Third metal plug; 34: First metal layer; 35: Second metal layer; 36: Accommodating cavity; 37: Third metal layer; 40: Channel region; 50: Contact layer; 61: First photoresist pattern; 62: Second photoresist pattern; 700: Second electrode layer; 800: Gate. DETAILED DESCRIPTION

[0031] In order to make the technical solutions and advantages of the embodiments of the present application more clear, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless there is a conflict.

[0032] The formation of doped regions often requires the use of the gate as a self-aligned mask. Most doping and high-temperature processes must be performed after the gate is formed. While metal is an ideal gate material, its compatibility with doping and high-temperature thermal processes is poor, and the patterning accuracy of metal layers is generally poor. Therefore, as technology nodes move downward, metal is rarely used as a gate material. In contrast, polysilicon is widely used as a gate material in device manufacturing. In particular, polysilicon is commonly used to fill the gate trenches of traditional submicron and deep submicron nodes to allow the gate material to subsequently form the necessary self-aligned doping and maintain stable performance during high-temperature processes. However, the semiconductor properties of polysilicon gates cannot match those of metal, which affects device performance. Furthermore, the process cost of doping polysilicon is high, as is the equipment maintenance. Therefore, the application of metal in the fabrication of trench-gate devices has become a hurdle that the field is striving to overcome.

[0033] Furthermore, the current UMOSFET manufacturing process requires high-end photolithography equipment with two KrF light sources (e.g., 248nm wavelength), one for processing the trench and one for processing the contact area. Therefore, the anti-reflective coating, photoresist, specialty gases, and other consumables required for KrF photolithography equipment are different from those used for ordinary i-line light sources (e.g., 365nm), increasing manufacturing costs. Furthermore, the two KrF photolithography passes need to be precisely aligned; otherwise, device function and performance degradation, such as threshold voltage dispersion and decreased avalanche withstand capability, will result. In summary, if a UMOSFET structure and manufacturing method with reliable process technology, balanced device performance, and ease of fabrication can be developed, this will largely resolve the aforementioned issues.

[0034] To address at least one of the above problems, in one aspect, the present invention provides a power semiconductor device. According to an embodiment of the present invention, the power semiconductor device may be a power semiconductor device with a trench gate, such as a trench gate MOSFET.

[0035] According to an embodiment of the present invention, referring to Figure 1 The power semiconductor device comprises: a first electrode layer 100, a semiconductor substrate 200 and a first interlayer dielectric layer 610 stacked in sequence. The semiconductor substrate 200 is provided with a body region 400, which extends from the surface of the semiconductor substrate 200 away from the first electrode layer 100 to the inside of the semiconductor substrate 200; the body region 400 is provided with a doping region 500; the power semiconductor device further comprises: a first trench 11, a second trench 12, and a third trench 13 (the first to third trenches are referred to as Figure 8 、 Figure 10-13As shown), the gate dielectric layer 20, the first metal plug 31, the second metal plug 32, the third metal plug 33, the second interlayer dielectric layer 620, the second electrode layer 700 and the gate 800.

[0036] According to an embodiment of the present invention, the body region 400 includes a first region, a second region, and a third region. The first trench 11 is located in the first region, and its bottom extends through the body region 400. That is, the first trench 11 extends from the surface of the body region 400 to the point where it extends through the body region 400, and the bottom of the first trench 11 is located in the semiconductor substrate 200. The second trench 12 is located in the second region and extends into the body region 400. That is, the bottom of the second trench 12 is located within the body region 400. The third trench 13 is located in the third region, and its bottom extends through the body region 400. That is, the third trench 13 extends from the surface of the body region 400 to the point where it extends through the body region 400, and the bottom of the third trench 13 is located in the semiconductor substrate 200. Gate dielectric layers 20 are disposed on the inner walls of the first trench 11 and the third trench 13, respectively. That is, the gate dielectric layers 20 are disposed on the sidewalls and bottoms of the first trench 11 and the third trench 13. The first metal plug 31 is located in the first trench 11 and its top is located in the first interlayer dielectric layer 610; the second metal plug 32 is located in the second trench 12 and its top is located in the first interlayer dielectric layer 610; the third metal plug 33 is located in the third trench 13 and its top is located in the first interlayer dielectric layer 610.

[0037] A second interlayer dielectric layer 620, located on the first interlayer dielectric layer 610, covers the first metal plug 31. The second interlayer dielectric layer 620 has a first opening and a second opening in the regions corresponding to the second metal plug 32 and the third metal plug 33, respectively. A second electrode layer 700 and a gate 800 are spaced apart and disposed on the second interlayer dielectric layer 620. The second electrode layer 700 is connected to the second metal plug 32 via the first opening, and the gate 800 is connected to the third metal plug 33 via the second opening.

[0038] Thus, the power semiconductor device has at least one of the following advantages: the first trench 11 and the third trench 13 are filled with metal to form a first metal plug 31 and a third metal plug 33, respectively. The metal has low resistance and responds faster to alternating signals, effectively reducing switching time. Compared with the prior art method of filling the trenches with doped polysilicon, the device has better conductivity and significantly lower resistance, and does not cause carrier displacement and depletion when a bias voltage is applied. The process cost of doped polysilicon deposition is high, and the equipment maintenance cost is high. The present application does not require the use of a polysilicon deposition process to fill the trenches. The trenches in the device are filled with metal, which has stable withstand voltage, low charge, fast response speed, low resistance, and faster response to alternating signals, effectively reducing switching time. In addition, the power semiconductor device uses the first interlayer dielectric layer 610 covering the semiconductor substrate 200 as a hard mask, so only one KrF lithography pass can be used, saving process costs. Through layout and process settings, self-alignment of two photolithography layers with high precision requirements is achieved, reducing the probability of defects and improving reliability.

[0039] For ease of understanding, the working principle of the power semiconductor device and the principle of achieving the above technical effects are explained in detail below:

[0040] refer to Figure 2-3 as well as Figure 19 In the power semiconductor device, the third metal plug 33 is connected to the gate 800 (Gate), the second metal plug 32 is connected to the second electrode layer 700 (for example, the source Source), and the first metal plug 31 is spaced from the second metal plug 32 and the third metal plug 33. Figure 19In the top view, the smallest rectangle in the area where the gate 800 is located represents the second opening of the second interlayer dielectric layer 620 connected to the third metal plug, and the smallest rectangles in the area where the second electrode layer 700 (source) is located respectively represent the first opening of the second interlayer dielectric layer 620 connected to the second metal plug 32, that is, the first trench 11 is connected to the third trench 13, and the first metal plug 31 located in the first trench 11 is electrically connected to the third metal plug 33 located in the third trench 13. Therefore, when a potential is applied to the gate 800, a potential is also applied to the third metal plug 33 and the first metal plug 31 connected to the gate 800. The region of the body region 400 adjacent to the first metal plug 31 and extending from the doped region 500 to the semiconductor substrate 200 is defined as the channel region 40 (which is spaced apart from the second metal plug 32). The first metal plug 31, the gate dielectric layer 20 in the first trench 11, and the channel region 40 constitute a MOSFET capacitor structure. When the first metal plug 31 is at a high potential, the channel region 40 is inverted. The inverted channel region 40 connects the doped region 500 with the semiconductor substrate 200, ultimately achieving conduction between the first electrode layer 100 and the second electrode layer 700. That is, after the channel region 40 is inverted, the first electrode layer 100 serving as the drain passes through the semiconductor substrate 200, the channel region 40, the doped region 500, and the second metal plug 32 in sequence, and finally achieves conduction with the source. When the potential disappears, the inversion channel region 40 also disappears, and the channel region 40 restores its original characteristics, shutting off the doped region 500 and the semiconductor substrate 200. The body diode formed by the body region 400 and the semiconductor substrate 200 is reversely cut off, disconnecting the first electrode layer 100 from the second electrode layer 700. The semiconductor substrate 200 and the doped region 500 have the same doping type (e.g., both are N-type doped), while the body region 400 and the semiconductor substrate 200 have opposite doping types (e.g., the body region 400 is P-type doped). When the channel region 40 is inverted (e.g., N-type after inversion), the semiconductor substrate 200 and the doped region 500 are conductive, thereby conductively connecting the first electrode layer 100 to the second electrode layer 700. Correspondingly, when the channel region 40 is not inverted (e.g., still P-type doped), the first electrode layer 100 and the second electrode layer 700 are disconnected.

[0041] The current VDMOS (hereinafter referred to as UMOS) with a U-shaped trench has a complex process, and the trench is filled with doped polysilicon, which will cause problems such as slow response speed, increased switching time, and high manufacturing cost. However, the power semiconductor device in this application uses metal filling in the trench to form a first metal plug 31 and a third metal plug 33. The metal has low resistance and responds faster to alternating signals, which can effectively reduce switching time. Compared with the prior art of using doped polysilicon to fill the trench, it has better conductivity and significantly reduced resistance. When a bias voltage is applied, there will be no carrier displacement and depletion effects. This application does not require the use of a polysilicon deposition process to fill the trench, eliminating a polysilicon deposition process, reducing process costs, and reducing high equipment maintenance costs. The trench in this device is filled with metal, which has stable voltage resistance, low gate charge, fast response speed, and faster response to alternating signals, which can effectively reduce switching time.

[0042] Furthermore, the existing UMOS manufacturing process requires the use of high-precision KrF lithography equipment to achieve high overlay accuracy by forming the first / third trenches and the second trench separately. However, the technical solution of this patent utilizes the first interlayer dielectric layer 610 as a hard mask, requiring only one KrF lithography pass, saving process costs and reducing processing difficulty. Through layout and process settings, self-alignment of the two high-precision lithography layers is achieved, reducing the probability of defects and improving reliability.

[0043] The following describes in detail the various structures of the power semiconductor device according to a specific embodiment of the present invention:

[0044] According to an embodiment of the present invention, the semiconductor substrate 200 may specifically include a stacked substrate 210 and an epitaxial layer 220. The epitaxial layer 220 includes a body region 400, and the body region includes a doped region 500. The semiconductor substrate 200 is of a first doping type. Specifically, the substrate 210, the epitaxial layer 220, and the doped region 500 are of the first doping type, and the body region 400 is of a second doping type, where the first doping type is opposite to the second doping type. For example, the substrate 210, the epitaxial layer 220, and the doped region 500 are each N-type doped (e.g., doped with phosphorus or arsenic), and the body region 400 is P-type doped (e.g., doped with boron).

[0045] According to an embodiment of the present invention, the doping concentration of the substrate 210 is greater than the doping concentration of the epitaxial layer 220. For example, the substrate 210 may be an N+ substrate and the epitaxial layer 220 may be an N- epitaxial layer. According to a specific embodiment of the present invention, the thickness, resistivity, and crystal orientation of the substrate 210 and the epitaxial layer 220 are not particularly limited. Those skilled in the art may select them according to their needs. For example, a resistivity <0.02Ω / cm, <100> A phosphorus-doped substrate 210 having a crystal orientation and a resistivity greater than 0.1 Ω / cm and a thickness greater than 2 μm is used as the epitaxial layer 220. More specifically, the substrate 210 can be a semiconductor substrate such as Si, GaAs, SiC, or GaN, and the epitaxial layer 220 can be formed on one side (generally referred to as the front side) of the substrate 210 using various known epitaxial processes such as chemical vapor deposition (CVD) and molecular beam epitaxy.

[0046] According to the embodiment of the present invention, the thickness, resistivity, and formation method of the body region 400 are not particularly limited, and those skilled in the art can select them according to their needs. For example, the front surface of the epitaxial layer 220 can be ion-implanted with an ion density of not less than E12 / cm 2 The epitaxial layer 220 is exposed to an amount of P-type ions (eg, boron ions) of an order of magnitude and annealed to form a body region 400 extending to a certain depth within the epitaxial layer 220 toward the substrate 210 .

[0047] According to the embodiment of the present invention, the thickness, resistivity, and formation method of the doped region 500 are not particularly limited, and those skilled in the art can select them according to their needs. For example, the doping concentration (ion implantation dose) of the doped region 500 is greater than the doping concentration of the epitaxial layer 220. For another example, the side of the body region 400 away from the epitaxial layer 220 can be ion implanted with a dose of not less than E15 / cm 2 N-type ions of an order of magnitude are deposited and annealed to form a doped region 500 . The doped region 500 extends to a certain depth in the body region 400 toward the substrate 210 .

[0048] According to an embodiment of the present invention, the thickness, forming material, forming method, etc. of the first interlayer dielectric layer 610 are not particularly limited, and those skilled in the art can make selections based on actual needs. For example, the first interlayer dielectric layer 610 is formed of silicon dioxide or silicon nitride. More specifically, a first insulating layer can be formed on the surface of the epitaxial layer 220 by growth methods such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), thermal oxidation, SOG (spin coating), and then photolithography and etching are performed to form first, second, and third precursor trenches (or openings) corresponding to the first, second, and third trenches, thereby obtaining the first interlayer dielectric layer 610. It should be noted that the size of the first, second, and third trenches is generally 250nm or smaller. During the photolithography process, a KrF photolithography device with a 248nm wavelength light source or other photolithography equipment with a shorter wavelength light source is required. Reference Figure 19 The device adopts a design in which multiple cells are repeated at a certain step distance and finally connected in parallel. The arrangement mode, shape and size of the cell area provided in this application are not particularly limited. For example, it can be a square cell, a strip cell, a diamond cell or a hexagonal cell, etc., which will not be repeated here.

[0049] According to an embodiment of the present invention, the body region 400 includes a first region, a second region and a third region. Specifically, the first region and the second region are located in the main cell region (Main Cell region), wherein the first region corresponds to the first trench 11, and the second region corresponds to the second trench 12; the third region can be a gate region (Gate region), corresponding to the third trench 13. The formation method, width and other characteristics of the above-mentioned grooves are not particularly limited, and only need to meet the above-mentioned requirements. The above-mentioned first trench 11 and the third trench 13 are both U-shaped grooves, and the second trench 12 is used to fill the metal plug 32, and then electrically lead the main cell region. The morphology of the second trench 12 is not particularly limited, such as a U-shaped groove, a V-shaped groove, an inverted trapezoidal groove, etc. The above-mentioned grooves are all formed by etching, and the groove depth can be adjusted by controlling the etching time and etching rate.

[0050] According to an embodiment of the present invention, a gate dielectric layer 20 is formed on the sidewalls and bottom of the first trench 11 and the third trench 13. The gate dielectric layer 20 can be formed by thermal oxidation or CVD deposition. Those skilled in the art can select the thickness of the gate dielectric layer 20 based on the threshold voltage requirements of the device. For example, the thickness of the gate dielectric layer 20 is ≮50 angstroms. Specifically, it can be 100 angstroms, 500 angstroms, or 1000 angstroms.

[0051] In order to further improve the performance of this device, refer to Figure 4The device further includes a contact layer 50, which is located at the bottom of the second trench 12. The contact layer 50 is of the second doping type (e.g., P-type doping), and the doping concentration is greater than the doping concentration of the body region 400. Thus, the on-state voltage drop and contact resistance can be reduced. After the second trench 12 is etched and formed, the contact layer 50 can be ion-implanted into the second trench 12 at a density of not less than E14 / cm 2 The dopant material is activated by annealing to form a contact layer 50 at the bottom of the second trench 12 .

[0052] According to an embodiment of the present invention, the first metal plug 31 is located in the first trench 11 and its top extends to the first interlayer dielectric layer 610. The second metal plug 32 connected to the second electrode layer 700 is located in the second trench 12 and its top extends to the first interlayer dielectric layer 610. The third metal plug 33 connected to the gate 800 is located in the third trench 13 and its top extends to the first interlayer dielectric layer 610. The first metal plug 31 and the third metal plug 32 are electrically connected. Figures 4-5 The first metal plug 31, the second metal plug 32, and the third metal plug 33 each independently include: a first metal layer 34 and a second metal layer 35. The first metal layer 34 covers the gate dielectric layer 20 and extends to the first interlayer dielectric layer 610. The second metal layer 35 is connected to the end of the first metal layer 34 away from the semiconductor substrate 200; wherein the upper surface of the second metal layer 35 is flush with the upper surface of the first interlayer dielectric layer 610; the first metal layer 34 and the second metal layer 35 define a receiving cavity 36, which is a cavity or filled with a third metal layer 37. According to an embodiment of the present invention, the material forming the first metal layer 34 is Ti. The material forming the second metal layer 35 is TiN. The material forming the third metal layer 37 is W. Thus, each metal plug is formed of a combination metal of Ti-TiN-W, wherein Ti can reduce contact resistance, TiN acts as an adhesion layer to increase metal adhesion and a barrier layer to prevent metal diffusion, and W serves as a filler and a conductive layer. Of course, no filler is used, and only T and TiN are used as the conductive layer. The hollow inner cavity formed by each metal plug does not affect the conductivity.

[0053] refer to Figure 2 According to an embodiment of the present invention, the region of the body region 400 adjacent to the first metal plug 31 and extending from the doped region 500 to the semiconductor substrate 200 is defined as the channel region 40. The channel region 40 is located between the first metal plug 31 and the second metal plug 32, adjacent to the gate dielectric layer 20 corresponding to the first metal plug 31, and spaced apart from the second metal plug 32. The functions and effects of the channel region 40 have been described in detail above and will not be repeated here.

[0054] According to an embodiment of the present invention, a second interlayer dielectric layer 620 located on the first interlayer dielectric layer 610 covers the first metal plug 31. The second interlayer dielectric layer 620 has a first opening and a second opening in the regions corresponding to the second metal plug 32 and the third metal plug 33, respectively. The thickness, forming material, and forming method of the second interlayer dielectric layer 620 are not particularly limited and can be selected by those skilled in the art based on actual needs. For example, the second interlayer dielectric layer 620 is formed of silicon dioxide or silicon nitride. More specifically, the second interlayer dielectric layer 620 can be formed in the same manner as the first interlayer dielectric layer 610, which will not be described in detail here. For example, the second interlayer dielectric layer 620 can be formed using a deposition method other than thermal oxidation and then subjected to photolithography and etching. To further improve device performance, the total thickness of the first interlayer dielectric layer 610 and the second interlayer dielectric layer 620 is not less than 2000 angstroms.

[0055] According to an embodiment of the present invention, the lower width of the first opening is greater than or equal to the width of the second trench 12, and the lower width of the second opening is greater than or equal to the width of the third trench 13. That is, the opening of the second trench 12 is located within the orthographic projection of the first opening on the first interlayer dielectric layer 610, and the opening of the third trench 13 is located within the orthographic projection of the second opening on the first interlayer dielectric layer 610. This reduces the precision requirements for the lithography machine and improves overlay redundancy. Furthermore, the upper width of the first opening is greater than or equal to the lower width, and the upper width of the second opening is greater than or equal to the lower width. As a result, the sidewall angles of the first and second openings are less than or equal to 90 degrees, and the sidewalls are inclined or vertical, ensuring sufficient contact area between the second electrode layer 700 and the second metal plug 32, and sufficient contact area between the gate 800 and the third metal plug 33. This facilitates the formation of the second electrode layer 700 at the first opening and the gate 800 at the second opening, and both are less susceptible to breakage, thereby improving device performance.

[0056] According to an embodiment of the present invention, the second electrode layer 700 and the gate 800 are spaced apart and disposed on the second interlayer dielectric layer 620. The second electrode layer 700 is connected to the second metal plug 32 through the first opening, and the gate 800 is connected to the third metal plug 33 through the second opening. The thickness, forming material, and forming method of the second electrode layer 700 and the gate 800 are not particularly limited. For example, a layer of metal can be first formed on the second interlayer dielectric layer 620 and then patterned to form the spaced second electrode layer 700 and the gate 800, wherein the second electrode layer 700 serves as the source electrode. The forming materials of the second electrode layer 700 and the gate 800 can be independently Ti-TiN-AlCu or AlSiCu.

[0057] According to an embodiment of the present invention, the first electrode layer 100 is disposed on a side of the semiconductor substrate 200 away from the first interlayer dielectric layer 610 (i.e., the back side of the semiconductor substrate 200). The first electrode layer 100 serves as a drain. The thickness, material, and formation method of the first electrode layer 100 are not particularly limited. For example, the first electrode layer 100 may be formed by first grinding the back side of the semiconductor substrate 200 and then performing a backside metallization process on the thinned semiconductor substrate 200.

[0058] In order to further improve the performance of the device, the power semiconductor device further includes: a third interlayer dielectric layer, which covers the gate 800 and the second electrode layer 700. Thus, the reliability of the device is further improved.

[0059] In general, this functional semiconductor device has a fast response speed, reduced switching time, low preparation cost, good performance and better stability.

[0060] Another aspect of the present invention provides a method for preparing a power semiconductor device. The following describes the method for preparing a power semiconductor device in detail according to a specific embodiment of the present invention:

[0061] S100: forming a body region in a semiconductor substrate, forming a doped region in the body region, and forming a first interlayer dielectric layer covering the semiconductor substrate.

[0062] refer to Figure 6 In this step, the semiconductor substrate 200 includes a substrate 210 and an epitaxial layer 220 stacked in sequence. The body region 400 is located in the epitaxial layer 220, and the doped region 500 is provided in the body region 400. The thickness, resistivity, materials, and formation methods of the substrate 210, epitaxial layer 220, body region 400, doped region 500, and first interlayer dielectric layer 610 have been described in detail above and will not be repeated here.

[0063] According to an embodiment of the present invention, the body region 400 includes a first region, a second region, and a third region. Specifically, the first region and the second region may be main cell regions (Main Cell regions), and the third region may be a gate 800 region (Gate region). The first interlayer dielectric layer 610 is provided with a first precursor trench 14 corresponding to the first region, a second precursor trench 15 corresponding to the second region, and a third precursor trench 16 corresponding to the third region. The first precursor trench 14, the second precursor trench 15, and the third precursor trench 16 eventually form the first trench 11, the second trench 12, and the third trench 13 in the semiconductor substrate 200 through subsequent processes.

[0064] S200: forming a first photoresist pattern on the first interlayer dielectric layer.

[0065] According to an embodiment of the present invention, referring to Figure 7-9 In this step, the first photoresist pattern 61 has a first photoresist opening and a second photoresist opening in the areas corresponding to the first precursor trench 14 and the third precursor trench 16, respectively. The width of the first photoresist opening is greater than the width of the first precursor trench 14, and the width of the second photoresist opening is greater than the width of the third precursor trench 16. That is, the notch of the first precursor trench 14 is located within the orthographic projection area of ​​the first photoresist opening on the first interlayer dielectric layer 610, and the notch of the third precursor trench 16 is located within the orthographic projection area of ​​the second photoresist opening on the first interlayer dielectric layer 610. The first photoresist pattern 61 covers the second precursor trench 15. Figure 9 for Figure 8 In the corresponding top view, the area not covered by the first photoresist pattern 61 and the first interlayer dielectric layer 610 is the area where the first trench 11 and the third trench 13 are located. As mentioned above, the first trench 11 is connected to the third trench 13, and the first metal plug 31 subsequently formed in the first trench 11 is electrically connected to the third metal plug 33 formed in the third trench 13.

[0066] Thus, the first photoresist pattern 61 is arranged on the first interlayer dielectric layer 610, that is, the first photoresist pattern 61 and the first interlayer dielectric layer 610 serve as a mask together, so the first photoresist opening can be smaller or larger than the notch of the first precursor groove 14, and the second photoresist opening can be larger than the notch of the third precursor groove 16. Even the above-mentioned opening in the first photoresist pattern 61 can be slightly offset, that is, the central axis of the above-mentioned opening in the first photoresist pattern 61 and the notch of the first precursor groove 14 and the notch of the third precursor groove 16 do not necessarily have to be absolutely completely coincident; this reduces the exposure accuracy requirements during the formation of the first photoresist pattern 61, improves the redundancy of the overlay, and also reduces the requirements for the photolithography machine. It should be noted that when the first groove 11 and the third groove 13 are subsequently etched, appropriate etching conditions can be selected to ensure the selectivity of the area to be etched with the first photoresist pattern 61 and the first interlayer dielectric layer 610, so as to achieve self-aligned etching.

[0067] S300 : forming a first trench and a third trench extending into the semiconductor substrate respectively.

[0068] According to an embodiment of the present invention, referring to Figure 10 In this step, the semiconductor substrate 200 corresponding to the first precursor trench 14 and the third precursor trench 16 is etched using the first photoresist pattern 61 and the first interlayer dielectric layer 610 as masks, and the first photoresist pattern 61 is removed to form the first trench 11 and the third trench 13 passing through the body region 400, respectively. According to an embodiment of the present invention, the bottoms of the first trench 11 and the third trench 13 are located in the epitaxial layer 220.

[0069] Thus, the first interlayer dielectric layer 610 is used as a hard mask to form openings corresponding to the first trench 11, the second trench 12, and the third trench 13; subsequently, whether the first trench 11 / third trench 13 or the second trench 12 is formed, a photoresist layer with a photoresist opening larger than the hard mask opening can be used, combined with a preferred etching selectivity to achieve self-aligned etching. In other words, the relative positions and sizes of the first, second, and third trenches depend solely on the first interlayer dielectric layer 610, and are not absolutely dependent on the overlay accuracy and wavelength of the lithography machine. Compared to the prior art, in which the production of trenches and contact holes is heavily dependent on the overlay accuracy and wavelength of the KrF lithography machine, the technical solution provided in this embodiment does not require the use of two KrF lithography passes, and improves the overlay redundancy of the two lithography passes, significantly reducing costs, reducing the probability of defects, and improving yield.

[0070] S400: forming a gate dielectric layer on the inner wall of the first trench and the inner wall of the third trench.

[0071] According to an embodiment of the present invention, referring to Figure 10 In this step, those skilled in the art can select the thickness of the gate dielectric layer 20 based on the threshold voltage requirements of the device. For example, the thickness of the gate dielectric layer 20 is ≮50 angstroms. Specifically, the thickness can be 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, or 500 angstroms.

[0072] S500: etching the body region corresponding to the second precursor trench to form a second trench passing through the doped region.

[0073] According to an embodiment of the present invention, referring to Figure 11-13 In this step, the second trench 12 is formed by the following steps: forming a second photoresist pattern 62 on the first interlayer dielectric layer 610, wherein the second photoresist pattern 62 has a third photoresist opening in the region corresponding to the second precursor trench 15, wherein the width of the third photoresist opening is greater than the width of the second precursor trench 15, that is, the notch of the second precursor trench 15 is located within the orthographic projection region of the third photoresist opening on the first interlayer dielectric layer 610; and etching the body region 400 corresponding to the second precursor trench 15 using the second photoresist pattern 62 as a mask to form the second trench 12. According to an embodiment of the present invention, the depth of the second trench 12 is greater than the thickness of the doped region 500 and less than the thickness of the body region 400. Figure 13 for Figure 12 In the corresponding top view, the area not covered by the second photoresist pattern 62 and the first interlayer dielectric layer 610 is the area where the second trench 12 is located, and the second metal plug 32 will be formed in the second trench 12 later.

[0074] As a result, the third photoresist opening is larger than the notch of the second precursor groove 15, which reduces the requirements for the photolithography machine and improves the redundancy of the overlay. It should be noted that when etching to form the second groove 12, suitable etching conditions can be selected to ensure the selectivity of the area to be etched and the third photoresist pattern and the first interlayer dielectric layer 610, so that self-aligned etching can be achieved. In other words, by using the second photoresist pattern 62 and the first interlayer dielectric layer 610 as a mask, self-aligned etching is achieved to form the second groove 12, which reduces the requirements for the photolithography machine and improves the redundancy of the overlay. The second photoresist pattern 62 does not need to pursue overly precise alignment and positioning, nor does it need to use KrF light source lithography equipment, and the processing difficulty is greatly reduced.

[0075] In order to further improve the performance of the device manufactured by this method, after forming the second trench 12, the method further includes:

[0076] The bottom of the second trench is doped to form a contact layer.

[0077] According to an embodiment of the present invention, referring to Figure 14 In this step, the contact layer 50 is located at the bottom of the second trench 12. After the second trench 12 is etched and formed, the contact layer 50 can be ion-implanted into the second trench 12 at a density of not less than E14 / cm 2 The dopant material is activated by annealing to form a contact layer 50 at the bottom of the second trench 12 .

[0078] S600 : forming a first metal plug, a second metal plug, and a third metal plug in the first trench, the second trench, and the third trench respectively.

[0079] According to an embodiment of the present invention, referring to Figure 15-16 In this step, the first metal plug 31, the second metal plug 32 and the third metal plug 33 are formed by the following steps: a first metal layer 34 is formed on the inner wall of the first trench 11 and the inner wall of the third trench 13 respectively, and the first metal layer 34 covers the gate dielectric layer 20 and extends to the first interlayer dielectric layer 610; a second metal layer 35 is formed at an end of the first metal layer 34 away from the semiconductor substrate 200; wherein the upper surface of the second metal layer 35 is flush with the upper surface of the first interlayer dielectric layer 610; the first metal layer 34 and the second metal layer 35 define a receiving cavity 36.

[0080] According to an embodiment of the present invention, the material forming the first metal layer 34 is Ti. The material forming the second metal layer 35 is TiN. According to an embodiment of the present invention, before forming the second metal layer 35, the method further includes: forming a third metal layer 37 on a side of the first metal layer 34 away from the first interlayer dielectric layer 610.

[0081] Thus, each metal plug is formed of a combination metal of Ti-TiN-W, wherein Ti can reduce contact resistance, TiN acts as an adhesion layer to increase metal adhesion and a barrier layer to prevent metal diffusion, and W serves as a filler and a conductive layer. Of course, no filler is used, and only Ti and TiN are used as conductive layers. The hollow inner cavity formed by each metal plug does not affect conductivity.

[0082] According to a specific embodiment of the present invention, each metal plug can be formed by the following steps: first, a Ti precursor layer and a W precursor layer are formed, and the W is etched back (etch back) so that the upper surface of the W is lower than the upper surface of the first interlayer dielectric layer 610; then, a TiN precursor layer (TiN Cap) is deposited by PVD or CVD to encapsulate the W metal and prevent W diffusion; finally, the TiN precursor layer is etched back or chemically mechanically polished (CMP) to expose the upper surface of the first interlayer dielectric layer 610, and finally, each metal plug is formed. Of course, it is also possible not to fill W, and only a Ti precursor layer needs to be formed first. When TiN is deposited by PVD or CVD, the trench is sealed to form a hollow metal plug structure, and then the Ti-TiN is CMPed to expose the upper surface of the first interlayer dielectric layer 610. The polishing amount of CMP needs to be controlled to prevent damage to the upper surface of the closed metal plug interface.

[0083] S700: forming a second interlayer dielectric layer on the first interlayer dielectric layer.

[0084] According to an embodiment of the present invention, referring to Figure 17 In this step, the second interlayer dielectric layer 620 has a first opening and a second opening in the regions corresponding to the second metal plug 32 and the third metal plug 33, respectively. The total thickness of the first interlayer dielectric layer 610 and the second interlayer dielectric layer 620 is no less than 2000 angstroms. The thickness and forming materials of the second interlayer dielectric layer 620 have been described in detail above and will not be repeated here.

[0085] According to an embodiment of the present invention, the second interlayer dielectric layer 620 is formed by the following steps: a second insulating precursor layer and a third photoresist pattern are sequentially stacked on the first interlayer dielectric layer 610, preferably forming a first opening and a second opening with inclined side walls; using the third photoresist pattern as a mask, the second insulating precursor layer is etched to form the second interlayer dielectric layer 620.

[0086] As a result, the sidewall angles of the first and second openings are less than 90 degrees, forming inclined surfaces. This increases the contact area between the second electrode layer 700 and the second metal plug 32, and the contact area between the gate 800 and the third metal plug 33. This facilitates the formation of the second electrode layer 700 at the first opening and the gate 800 at the second opening, making them less susceptible to breakage and improving device performance. The third photoresist pattern eliminates the need for precise alignment and KrF light source lithography equipment, significantly reducing processing difficulty.

[0087] S800: forming a second electrode layer and a gate electrode spaced apart from each other on the second interlayer dielectric layer.

[0088] According to an embodiment of the present invention, referring to Figure 18 In this step, the second electrode layer is connected to the second metal plug 32 through the first opening, and the gate 800 is connected to the third metal plug 33 through the second opening. The thickness, materials, and formation methods of the second electrode layer 700 and the gate 800 have been described in detail above and will not be repeated here.

[0089] S900: forming a first electrode layer on a side of the semiconductor substrate away from the first interlayer dielectric layer.

[0090] According to an embodiment of the present invention, referring to Figure 4 as well as Figure 19 In this step, the first electrode layer 100 is disposed on the side of the semiconductor substrate 200 away from the first interlayer dielectric layer 610 (i.e., the back side of the semiconductor substrate 200). The thickness, materials, and formation method of the first electrode layer 100 have been described in detail above and will not be repeated here.

[0091] refer to Figure 19 In the figure, the smallest rectangle in the region where gate 800 is located represents the second opening in the second interlayer dielectric layer connected to the third metal plug, and the smallest rectangles in the region where second electrode layer 700 (source) is located represent the first opening in the second interlayer dielectric layer connected to the second metal plug. This device utilizes a design in which multiple cells are repeated at a certain step distance and ultimately connected in parallel. The arrangement, shape, and size of the cell regions provided in this application are not particularly limited. For example, they can be square cells, strip cells, diamond cells, or hexagonal cells, and will not be further described here.

[0092] In general, this method significantly reduces costs, lowers requirements for lithography machines, improves overlay redundancy, and significantly reduces processing difficulty.

[0093] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0094] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A power semiconductor device, characterized in that: include: A first electrode layer, a semiconductor substrate, and a first interlayer dielectric layer are sequentially stacked; A body region is provided in the semiconductor substrate, and a doped region is provided in the body region. The semiconductor substrate and the doped region are of a first doping type, and the body region is of a second doping type, the first doping type being opposite to the second doping type. The body region includes a first region, a second region, and a third region. a first trench, a second trench, and a third trench, wherein the first trench is located in the first region and its bottom passes through the body region, the second trench is located in the second region, and the third trench is located in the third region and its bottom passes through the body region, and a gate dielectric layer is disposed in each of the first trench and the third trench; a first metal plug, a second metal plug, and a third metal plug, wherein the first metal plug is located in the first trench and its top portion extends to the first interlayer dielectric layer, the second metal plug is located in the second trench and its top portion extends to the first interlayer dielectric layer, and the third metal plug is located in the third trench and its top portion extends to the first interlayer dielectric layer; a second interlayer dielectric layer located on the first interlayer dielectric layer, the second interlayer dielectric layer covering the first metal plug, and the second interlayer dielectric layer having a first opening and a second opening in regions corresponding to the second metal plug and the third metal plug, respectively; A second electrode layer and a gate are spaced apart and arranged on the second interlayer dielectric layer. The second electrode layer is connected to the second metal plug through the first opening, and the gate is connected to the third metal plug through the second opening.

2. The power semiconductor device according to claim 1, wherein: The width of the lower end of the first opening is greater than or equal to the width of the second groove, and the width of the lower end of the second opening is greater than or equal to the width of the third groove; The width of the upper end of the first opening is greater than or equal to the width of the lower end, and the width of the upper end of the second opening is greater than or equal to the width of the lower end.

3. The power semiconductor device according to claim 1 or 2, characterized in that: Also includes: A contact layer is located at the bottom of the second trench, the contact layer is of the second doping type, and the doping concentration is greater than the doping concentration of the body region.

4. The power semiconductor device according to claim 1, wherein: The first metal plug, the second metal plug, and the third metal plug each independently include: a first metal layer, the first metal layer covering the gate dielectric layer and extending to the first interlayer dielectric layer; a second metal layer connected to an end of the first metal layer away from the semiconductor substrate; in, The upper surface of the second metal layer is flush with the upper surface of the first interlayer dielectric layer; The first metal layer and the second metal layer define a receiving cavity, and the receiving cavity is a cavity or is filled with a third metal layer.

5. The power semiconductor device according to claim 4, characterized in that: The first metal layer is formed of Ti; the second metal layer is formed of TiN; and the third metal layer is formed of W.

6. A method for preparing a power semiconductor device, characterized in that: include: A body region is formed in a semiconductor substrate, a doped region is formed in the body region, and a first interlayer dielectric layer is formed covering the semiconductor substrate, wherein the body region includes a first region, a second region, and a third region; the first interlayer dielectric layer is provided with a first precursor trench corresponding to the first region, a second precursor trench corresponding to the second region, and a third precursor trench corresponding to the third region; forming a first photoresist pattern on the first interlayer dielectric layer, wherein the first photoresist pattern has a first photoresist opening and a second photoresist opening in regions corresponding to the first precursor trench and the third precursor trench, respectively; Using the first photoresist pattern and the first interlayer dielectric layer as masks, etching the semiconductor substrate and removing the first photoresist pattern to form a first trench and a third trench passing through the body region, respectively; forming a gate dielectric layer on the inner wall of the first trench and the inner wall of the third trench; Etching a body region corresponding to the second precursor trench to form a second trench passing through the doped region; forming a first metal plug, a second metal plug, and a third metal plug in the first trench, the second trench, and the third trench respectively; forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer has a first opening and a second opening in regions corresponding to the second metal plug and the third metal plug, respectively; forming a second electrode layer and a gate spaced apart on the second interlayer dielectric layer, wherein the second electrode layer is connected to the second metal plug through the first opening, and the gate is connected to the third metal plug through the second opening; A first electrode layer is formed on a side of the semiconductor substrate away from the first interlayer dielectric layer.

7. The method according to claim 6, characterized in that The second trench is formed by the following steps: forming a second photoresist pattern on the first interlayer dielectric layer, wherein the second photoresist pattern has a third photoresist opening in an area corresponding to the second precursor trench, wherein a width of the third photoresist opening is greater than a width of the second precursor trench; Using the second photoresist pattern as a mask, the doped region and the body region corresponding to the second precursor trench are etched to form the second trench.

8. The method according to claim 7, characterized in that After forming the second trench, the method further includes: Doping is performed on the bottom of the second trench to form a contact layer.

9. The method according to claim 6, characterized in that The first metal plug, the second metal plug, and the third metal plug are formed by the following steps: forming a first metal layer, wherein the first metal layer covers the gate dielectric layer in the first trench and the third trench and extends to the first interlayer dielectric layer, and the first metal layer covers the sidewall of the second trench and extends to the first interlayer dielectric layer; forming a second metal layer at an end of the first metal layer away from the first electrode layer; in, The upper surface of the second metal layer is flush with the upper surface of the first interlayer dielectric layer; The first metal layer and the second metal layer define a receiving cavity.

10. The method according to claim 9, characterized in that Before forming the second metal layer, the method further includes: A third metal layer is formed on a side of the first metal layer away from the first electrode layer to fill the accommodation cavity.

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