Relocation process using CbA technology

Abstract

This invention discloses a relocation process using CbA technology. This disclosure generally relates to efficiently relocating data within a data storage device. This data can be relocated more efficiently by implementing an error-correcting code (ECC) module in a complementary metal-oxide-semiconductor (CMOS) chip for each memory die within the memory array of the memory device. The ECC decodes the codeword at the memory die. Metadata is then extracted from the decoded codeword and transmitted to the controller of the data storage device. The Flash Translation Layer (FTL) module at the controller then verifies the validity of the data by comparing the received metadata with an FTL table. If the metadata indicates that the data is valid, the data is relocated.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 076,760, filed on September 10, 2020, which is incorporated herein by reference. Background Technology Technical Field

[0003] The implementation scheme disclosed herein generally involves relocating data within a data storage device.

[0004] Description of related fields

[0005] In data storage devices utilizing SSDs, there is no need to maintain a reverse lookup table to indicate whether the contents of each Flash Management Unit (FMU) are valid or invalid. Therefore, during data relocation such as garbage collection, the controller is configured to verify which FMUs are valid and should be copied, and which FMUs are invalid and should not be copied.

[0006] A typical way to validate an LBA is to store it in the header of the FMU. During data relocation, the controller is configured to read all headers and, for each header, look up the LBA stored in the controller in a mapping table. If the mapping table indicates that the known physical location of the LBA matches the location of the FMU header, the LBA is valid, and the data should be relocated. Otherwise, the FMU is invalid, and the data should not be relocated.

[0007] To read the header, the entire FMU header is transferred from the memory device to the controller, where it is then decoded. Because the error correction code (ECC) codeword covers the entire FMU header as a single codeword, a bottleneck is created, negatively impacting device performance.

[0008] Therefore, it is necessary to relocate data within data storage devices more effectively. Summary of the Invention

[0009] This disclosure generally relates to efficiently relocating data within a data storage device. This data relocation can be made more efficient by implementing an error-correcting code (ECC) module in a complementary metal-oxide-semiconductor (CMOS) chip for each memory die within the memory array of the memory device. The ECC decodes the codeword at that memory die. Metadata is then extracted from the decoded codeword and transmitted to the controller of the data storage device. A flash translation layer (FTL) module at the controller then verifies the validity of the data by comparing the received metadata with an FTL table. If the metadata indicates that the data is valid, the data is relocated.

[0010] In one embodiment, a data storage device includes: a controller; and a non-volatile memory device coupled to the controller, wherein the non-volatile memory device includes: at least one memory die; and at least one complementary metal-oxide-semiconductor (CMOS) device coupled to at least one memory die, wherein the CMOS device includes an error correction code (ECC) unit.

[0011] In another embodiment, a data storage device includes: a controller; and a non-volatile memory device coupled to the controller, wherein the non-volatile memory device is configured to: decode data; extract metadata from the decoded data; and transfer the extracted metadata to the controller.

[0012] In another embodiment, a data storage device includes: a controller; and a non-volatile memory device coupled to the controller, wherein the non-volatile memory device includes means for decoding data stored in the non-volatile memory device. Attached Figure Description

[0013] Therefore, a detailed understanding of the foregoing features of this disclosure, a more specific description of this disclosure, and the foregoing brief overview can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should therefore not be considered as limiting its scope, as this disclosure allows for other equally effective embodiments.

[0014] Figure 1 This is a schematic block diagram illustrating a storage system according to one embodiment, wherein the data storage device can be used as a storage device for the host device.

[0015] Figure 2 This is a schematic diagram of a circuit-bounded array architecture according to one implementation scheme.

[0016] Figure 3 This is a schematic diagram of a non-volatile memory device architecture based on one implementation scheme.

[0017] Figure 4 This is a schematic diagram of an array of CMOS (CAA) chips according to one implementation scheme.

[0018] Figure 5 This is a flowchart illustrating a data relocation method according to one implementation scheme.

[0019] Figure 6 This is a flowchart illustrating a data relocation method according to another implementation scheme.

[0020] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the accompanying drawings. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0021] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, consider any combination of the following features and elements (whether or not related to different embodiments) to achieve and practice this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, achieving a particular advantage through a given embodiment is not a limitation of this disclosure. Therefore, the following aspects, features, embodiments, and advantages are illustrative only and should not be considered elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered elements or limitations of the appended claims unless expressly stated in the claims.

[0022] This disclosure generally relates to efficiently relocating data within a data storage device. This data relocation can be made more efficient by implementing an error-correcting code (ECC) module in a complementary metal-oxide-semiconductor (CMOS) chip for each memory die within the memory array of the memory device. The ECC decodes the codeword at that memory die. Metadata is then extracted from the decoded codeword and transmitted to the controller of the data storage device. A flash translation layer (FTL) module at the controller then verifies the validity of the data by comparing the received metadata with an FTL table. If the metadata indicates that the data is valid, the data is relocated.

[0023] Figure 1 This is a schematic block diagram illustrating a storage system 100 according to one embodiment, wherein data storage device 106 can be used as a storage device for host device 104. For example, host device 104 can utilize non-volatile memory (NVM) 110 included in data storage device 106 to store and retrieve data. Host device 104 includes host DRAM 138. In some examples, storage system 100 may include multiple storage devices, such as data storage device 106, that can operate as a storage array. For example, storage system 100 may include multiple data storage devices 106 configured to collectively serve as a low-cost / independent disk (RAID) redundant array of high-capacity storage devices for host device 104.

[0024] Host device 104 stores data to and / or retrieves data from one or more storage devices, such as storage device 106. Figure 1 As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a variety of devices, including computer servers, network attached storage (NAS) units, desktop computers, laptops, tablets, set-top boxes, mobile phones such as so-called "smart" phones, so-called "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending or receiving data from data storage devices.

[0025] Data storage device 106 includes a controller 108, an NVM 110, a power source 111, volatile memory 112, an interface 114, and a write buffer 116. In some examples, data storage device 106 may include components not shown for clarity. Figure 1 Additional components are shown in the diagram. For example, data storage device 106 may include a printed circuit board (PCB) to which components of data storage device 106 are mechanically attached, and the PCB includes conductive traces for electrically interconnecting components of data storage device 106, etc. In some examples, the physical dimensions and connector configuration of data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 3.5” data storage devices (e.g., HDDs or SSDs), 2.5” data storage devices, 1.8” data storage devices, peripheral component interconnects (PCI), PCI expansion (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini cards, MiniPCI, etc.). In some examples, data storage device 106 may be directly coupled (e.g., directly soldered) to the motherboard of host device 104.

[0026] The interface 114 of the data storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. Electrical connections (e.g., the data bus, the control bus, or both) of the interface 114 are electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108, allowing data exchange between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 may also allow the data storage device 106 to receive power from the host device 104. For example, such as Figure 1 As shown, power supply 111 can receive power from host device 104 via interface 114.

[0027] NVM 110 may include multiple memory devices. NVM 110 may be configured to store and / or retrieve data. For example, the memory devices of NVM 110 may receive data and messages instructing memory cells to store data from controller 108. Similarly, the memory devices of NVM 110 may receive messages instructing memory devices to retrieve data from controller 108. In some examples, each memory device in the memory devices may be referred to as a die. In some examples, a single physical chip may include multiple dies (i.e., multiple memory cells). In some examples, each memory device may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0028] In some examples, each memory device of the NVM 110 may include any type of non-volatile memory device, such as flash memory devices, phase-change memory (PCM) devices, resistive random access memory (ReRAM) devices, magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory device.

[0029] NVM 110 may include multiple flash memory devices. The NVM flash memory devices may include NAND- or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistors for each flash memory cell. In the NVM flash memory device, the flash memory device may be divided into multiple dies, each of the multiple dies comprising multiple blocks, which may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define pages within the multiple pages. A corresponding cell in each page of the multiple pages may be electrically connected to a corresponding bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC). Controller 108 may write data to and read data from the NVM flash memory device at the page level and erase data from the NVM flash memory device at the block level.

[0030] Data storage device 106 includes a power source 111 that can provide power to one or more components of the data storage device 106. When operating in standard mode, power source 111 can use power supplied by an external device such as host device 104 to power one or more components. For example, power source 111 can use power received from host device 104 via interface 114 to power one or more components. In some examples, power source 111 may include one or more power storage components configured to supply power to one or more components when operating in a shutdown mode, such as when power is stopped from external devices. In this way, power source 111 can be used as an onboard backup power source. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the amount of electricity that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of one or more power storage components. In other words, as the amount of electricity stored by one or more power storage components increases, the cost and / or size of one or more power storage components also increases.

[0031] The data storage device 106 also includes volatile memory 112, which can be used by the controller 108 to store information. Volatile memory 112 may include one or more volatile memory devices. Figure 1As shown, volatile memory 112 can consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0032] Data storage device 106 includes a controller 108 that can manage one or more operations of data storage device 106. For example, controller 108 can manage reading data from NVM 110 and / or writing data to NVM 110. Furthermore, controller 108 is coupled to buffer 116 via flash bus 118, which facilitates data transfer between controller 108 and buffer 116. In one embodiment, flash bus 118 can facilitate data transfer between NVM 110 and controller 108 and / or between volatile memory 112 and controller 108. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 can initiate a data storage command to store data into NVM 110 and monitor the progress of the data storage command.

[0033] Controller 108 can determine at least one operational characteristic of storage system 100 and store at least one operational characteristic in NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 temporarily stores data associated with the write command in internal memory or write buffer 116 before sending the data to NVM 110. The controller also includes a first flash translation layer (FTL) module 120. The first FTL module 120 may include one or more FTL tables configured to track the location of newly updated data in NVM 110, such that each read command for newly updated data is routed to the appropriate location, ensuring that newly programmed pages of NVM 110 are uniformly distributed across NVM 110 to aid wear leveling, and tracking the location of expired or invalid data, such that one or more pages containing expired or invalid data can be erased in flash management operations such as garbage collection.

[0034] Figure 2This is a schematic diagram of a circuit-bounded array (CbA) architecture 200 according to one embodiment. The CbA architecture 200 includes one or more complementary metal-oxide-semiconductor (CMOS) chips coupled to one or more arrays via one or more interconnect units, wherein these arrays correspond to one or more memory locations of an NVM 110, such as the first die among a plurality of dies of the NVM 110. For illustrative purposes, the CMOS device and associated architecture may be referred to as a CMOS work function (WF) 202. Furthermore, for illustrative purposes, the array and associated architecture may be referred to as an array WF 204.

[0035] In one implementation, CMOS WF 202 is a CMOS on-array (CAA) device. Because the CMOS device is separate from the array WF 204, CMOS logic can be executed faster than previous adaptive methods such as under-array CMOS (CuA). Each of the multiple CMOS CAA devices includes an error correction code (ECC) module. The ECC module can be configured to encode and decode error correction codes for each associated NVM die traveling to and from the associated NVM die.

[0036] Figure 3 This is a schematic diagram of a non-volatile memory device architecture 300 according to one embodiment. Aspects of the non-volatile memory device architecture 300 may be similar to... Figure 2 The CbA architecture 200. For example, each memory die 306A-306E may be an array WF 204, and each CMOS device 302A-302E may be a CMOS WF 202. Each memory die 306A-306E may be an NVM die among a plurality of NVM dies of NVM 110. Each CMOS device among the CMOS devices 302A-302E includes an ECC cell among a plurality of ECC cells 304A-304E. The number of CMOS devices 302A-302E, ECC cells 304A-304E, and memory dies 306A-306E shown is not intended to be limiting, but rather to provide examples of possible implementations. In one implementation, the non-volatile memory device architecture 300 includes “n” CMOS chips, ECC cells, and memory dies, where “n” represents any suitable value, such as about 256. Furthermore, in one implementation, the plurality of CMOS devices 302A-302E may be implemented as a CMOS CAA.

[0037] Because each memory die is coupled to a CMOS device and each CMOS device includes an ECC cell, the non-volatile memory device architecture 300 includes an equal number of memory dies, CMOS devices, and ECC cells. The memory dies and CMOS devices can be arranged vertically in an alternating manner. For example, a first memory die 306A is deposited on top of a first CMOS device 302A, and a second CMOS device 302B is deposited on top of the first memory die 306A. A second memory die 306B is deposited on top of the second CMOS device 302B, and so on.

[0038] Furthermore, each CMOS device is coupled to an adjacent memory die. For example, the first CMOS device 302A is coupled to the first memory die 306A, and the second CMOS device 302B is coupled to the second memory die 306B. Because the first CMOS device 302A is coupled to the first memory die 306A, the logic of the CMOS device 302A manages the programming and reading of data traveling to and from the first memory die 306A.

[0039] For example, refer to Figure 1 When controller 108 receives a write command from host device 104, first FTL module 120 schedules the data associated with the write command to a location in NVM 110. The data associated with the write command is transferred to an associated CMOS device, such as first CMOS device 302A, where a first ECC cell encodes low-density parity-check (LDPC) code and / or parity data. After encoding, the data is programmed into an associated first memory die 306A. For example, the size of the data programmed into first memory die 306A may be approximately 4.5KB, where approximately 4KB of data is associated with the write command, and the remaining approximately 0.5KB of data is associated with metadata such as LDPC code and / or parity data.

[0040] When controller 108 receives a read command from host device 104, first FTL module 120 uses an FTL table to locate relevant data in one or more memory dies 306A-306E. After locating the relevant data using the FTL table, a relevant CMOS device, such as first CMOS device 302A, retrieves the data from a relevant memory die, such as first memory die 306A. Before transmitting the data to controller 108, the data is decoded by a relevant ECC unit, such as first ECC unit 304A. The decoded data is the programmed data minus metadata, resulting in decoded data of approximately 4KB in size. In one embodiment, controller 108 may be configured to compare the decoded data with data stored in the FTL table of first FTL module 120. After confirming that the decoded data matches the data stored in the FTL table of first FTL module 120, controller 108 is configured to relocate the valid data to a different non-volatile memory device, such as second memory die 306B. First FTL module 120 is configured to update the FTL table with the relevant location of the relocated valid data. Examples of the operations described earlier could be data management operations, such as garbage collection.

[0041] Figure 4 This is a schematic diagram of an on-array CMOS (CAA) chip 400 according to one embodiment. The CAA chip 400 can be implemented as... Figure 3 At least one CMOS device among CMOS devices 302A-302E, in which case ECC 404 can be implemented as Figure 3 At least one ECC unit among ECC units 304A-304E. The CAA chip 400 includes a sense amplifier and latch 402 and an ECC unit 404. The sense amplifier and latch 402 can communicate with the ECC unit 404. For example, when a controller (such as...) Figure 1 When the controller 108 receives a read command, it transmits the read command to the appropriate CMOS device (such as the CAA chip 400) via a flash bus (such as flash bus 118). The CAA chip 400 reads one or more associated word lines, where the sense amplifier 406 amplifies the low-power signal representing the bit of the memory cell to a recognizable logic level. The latch 408 latches the desired one or more word lines, where the one or more word lines include either a first data 410A and a first parity 412A or a second data 410B and a second parity 412B.

[0042] Data 410A, 410B and parity checks 412A, 412B are transmitted to ECC 404 as codeword 426. Each codeword 426 includes metadata 420, data 422, and parity check 424. For example, data 410A can be metadata 420 and data 422. ECC encoder 416 can be responsible for encoding the parity check or LDPC code into the received data associated with the host write command. ECC decoder 418 can be responsible for decoding codeword 426 to check for and correct any missing bits. Second FTL module 414 is a local FTL module relative to ECC 404 of CAA chip 400. Second FTL module 414 can have... Figure 1 The first FTL module 120 of the controller 108 has similar functionality. The second FTL module 414 can be configured to extract metadata 420 from codeword 426 and transmit the metadata 420 to... Figure 1 The controller 108.

[0043] For example, during an operation initiated by controller 108, such as garbage collection, controller 108 may generate a read command for a first block in the first memory die 306A of NVM 110. The read command is transmitted to a first CMOS device 302A, which may be a CAA chip 400. The sense amplifier and latch 402 of CAA chip 400 read and amplify the associated data and parity associated with the read command, such as first data 410A and first parity 412A associated with the first data 410A. Latch 408 latches the first data 410A and the first parity 412A into a codeword 426, such as a first codeword. The first codeword is then transmitted to ECC 404, where ECC decoder 418 decodes the first codeword and a second FTL module 414 extracts metadata 420. The second FTL module 414 sends the metadata 420 to controller 108, more specifically, to the first FTL module 120. The first FTL module 120 determines whether data 422 or a portion thereof is valid by verifying the FTL table. The valid portion of data 422 is then encoded by the ECC encoder 416, and the CAA chip 400 writes the valid data into a newly allocated block of the first memory die 306A, where the second FTL module 414 stores the location of the valid data. The ECC encoder 416 can attach a metadata header to the valid data, along with the associated LDPC code and / or parity data.

[0044] Figure 5 This is a flowchart illustrating a data relocation method 500 according to one implementation scheme. See also... Figure 4 This provides context for the data relocation method 500. Figure 4This aspect is not intended to be limiting, but rather to provide examples of possible implementations. At box 502, a CbA chip (such as...) Figure 4 ECC modules (such as CAA chip 400) Figure 1 The ECC 404 decodes the codeword associated with the read command. The data associated with codeword 426 and the corresponding parity check are read and latched by the readout amplifier and latch 402. Codeword 426 is transmitted to the ECC, where the ECC decoder decodes it.

[0045] At box 504, the second FTL module 414 of ECC 404 extracts metadata 420 from codeword 426, where metadata 420 can be stored in the header of codeword 426. At box 506, the extracted metadata 420 is transmitted to the controller, such as... Figure 1 The controller 108. At block 508, the controller's FTL module (such as the first FTL module 120) verifies the metadata 420 against the FTL table to confirm the validity of the data 422. At block 510, the valid data is transferred to the controller and reallocated to a new storage block, such as... Figure 3 The second memory die 306B, wherein the second CMOS device 302B is configured to encode data and store it in the second memory die 306B.

[0046] Figure 6 This is a flowchart illustrating a data relocation method 600 according to another embodiment. Data relocation method 600 differs from data relocation method 500 because method 500 involves relocating data to a newly allocated block in a different die of the NVM 110, while method 600 involves relocating data to a newly allocated block in the same die of the NVM 110. See also... Figure 4 This provides context for the data relocation method 600. Figure 4 The purpose of this is not to impose restrictions, but rather to provide examples of possible implementation schemes.

[0047] At box 602, a CbA chip (such as...) Figure 4 ECC modules (such as CAA chip 400) Figure 1 The ECC 404 decodes the codeword associated with the read command. The data associated with codeword 426 and the corresponding parity check are read and latched by the readout amplifier and latch 402. Codeword 426 is transmitted to the ECC, where the ECC decoder decodes it.

[0048] At box 604, the second FTL module 414 of ECC 404 extracts metadata 420 from codeword 426, where metadata 420 can be stored in the header of codeword 426. At box 606, the extracted metadata 420 is transmitted to the controller, such as... Figure 1 The controller 108. At block 608, the controller's FTL module (such as the first FTL module 120) checks the metadata 420 against the FTL table to confirm the validity of the data 422.

[0049] At block 610, the second FTL module 414 assigns a new LBA to valid data. The valid data, or new codeword, is re-encoded by the ECC encoder 416 with metadata header 420 and parity check 424. At block 612, the CAA chip 400 programs the new codeword to a new physical block address (PBA), where the new PBA is a new allocation block for the same die of the NVM 110 (such as the first memory die 306A). At block 614, the new LBA and PBA of the newly programmed data to the new allocation block are used to update the FTL table of the first FTL module 120.

[0050] By implementing ECC modules in the CMOS chip for each memory die within the memory array of the memory device, data relocation can be achieved more efficiently. Because only the decoded and extracted metadata is transferred to the FTL module before data validity verification, only valid data, except for any metadata indicating the presence of invalid data, moves across the flash bus. This results in more efficient data relocation.

[0051] In one embodiment, a data storage device includes: a controller; and a non-volatile memory device coupled to the controller, wherein the non-volatile memory device includes: at least one memory die; and at least one complementary metal-oxide-semiconductor (CMOS) device coupled to the at least one memory die, wherein the CMOS device includes an error correction code (ECC) unit. The ECC unit includes a flash translation layer (FTL) module, an encoder, and a decoder. The number of CMOS devices is equal to the number of memory dies. The non-volatile memory device is capable of transmitting decoded metadata to the controller. The at least one memory die includes a plurality of memory dies. The at least one CMOS device includes a plurality of CMOS devices. These plurality of memory dies and these plurality of CMOS devices are arranged vertically in an alternating manner. The at least one CMOS device includes at least one sense amplifier and at least one latch. The controller includes a flash translation layer (FTL) module.

[0052] In another embodiment, a data storage device includes: a controller; and a non-volatile memory device coupled to the controller, wherein the non-volatile memory device is configured to: decode data; extract metadata from the decoded data; and transfer the extracted metadata to the controller. The controller is configured to compare the extracted metadata with data stored in a Flash Translation Layer (FTL) table. The non-volatile memory device is further configured to transfer valid data to the controller in response to the comparison. The controller is configured to relocate the valid data to a different non-volatile memory device. The non-volatile memory device is further configured to assign a new logical block address (LBA) to the valid data. The non-volatile memory device is further configured to encode a new codeword with a new metadata header for the new LBA. The non-volatile memory device is further configured to program the new codeword to a new physical block address (PBA). The controller is further configured to update the Flash Translation Layer (FTL) table with the new LBA and the new PBA.

[0053] In another embodiment, a data storage device includes: a controller; and a non-volatile memory device coupled to the controller, wherein the non-volatile memory device includes means for decoding data stored in the non-volatile memory device. The non-volatile memory device includes a first flash translation layer (FTL) module. The controller includes a second FTL module different from the first FTL module. The non-volatile memory device is configured to extract metadata from the decoded data and send the extracted metadata to the controller. The controller is configured to compare the extracted metadata with data stored in a flash translation layer (FTL) table in the controller.

[0054] While the foregoing describes embodiments of this disclosure, other and additional embodiments of this disclosure may be contemplated without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A data storage device, comprising: Controller; and A non-volatile memory device coupled to the controller, wherein the non-volatile memory device is configured to: Decode the data; Extracting metadata from decoded data, and The extracted metadata is transmitted to the controller, and the non-volatile memory device includes: At least one memory die; and At least one complementary metal-oxide-semiconductor (CMOS) device, the at least one CMOS device being coupled to the at least one memory die, wherein the CMOS device includes an error correction code (ECC) unit.

2. The data storage device according to claim 1, wherein the ECC unit includes a flash memory translation layer (FTL) module, an encoder, and a decoder.

3. The data storage device according to claim 1, wherein the number of CMOS devices is equal to the number of memory dies.

4. The data storage device according to claim 1, wherein the at least one memory die comprises a plurality of memory dies, wherein the at least one CMOS device comprises a plurality of CMOS devices, and wherein the plurality of memory dies and the plurality of CMOS devices are arranged vertically in an alternating manner.

5. The data storage device according to claim 1, wherein the at least one CMOS device comprises at least one sense amplifier and at least one latch.

6. The data storage device according to claim 1, wherein the controller includes a flash translation layer (FTL) module.

7. A data storage device, comprising: Controller; and A non-volatile memory device coupled to the controller, wherein the non-volatile memory device is configured to: Decode the data; Extract metadata from the decoded data; as well as The extracted metadata is transmitted to the controller.

8. The data storage device of claim 7, wherein the controller is configured to compare the extracted metadata with data stored in a flash translation layer (FTL) table.

9. The data storage device of claim 8, wherein the non-volatile memory device is further configured to transmit valid data to the controller in response to the comparison.

10. The data storage device of claim 9, wherein the controller is configured to relocate the valid data to a different non-volatile memory device.

11. The data storage device of claim 9, wherein the non-volatile memory device is further configured to assign a new logical block address (LBA) to valid data.

12. The data storage device of claim 11, wherein the non-volatile memory device is further configured to encode new codewords with a new metadata header for a new LBA.

13. The data storage device of claim 12, wherein the non-volatile memory device is further configured to program the new codeword to a new physical block address PBA.

14. The data storage device of claim 13, wherein the controller is further configured to update the flash translation layer FTL table with the new LBA and the new PBA.

15. A data storage device, comprising: Controller; and A non-volatile memory device coupled to the controller, wherein the non-volatile memory device includes: A means for decoding data stored in the non-volatile memory device; A means for extracting metadata from decoded data; and A means for sending the extracted metadata to the controller.

16. The data storage device of claim 15, wherein the non-volatile memory device includes a first flash translation layer (FTL) module.

17. The data storage device of claim 16, wherein the controller includes a second FTL module that is different from the first FTL module.

18. The data storage device of claim 15, wherein the controller is configured to compare the extracted metadata with data stored in a Flash Translation Layer (FTL) table in the controller.

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