Fan-out packaging structure and packaging method

Abstract

The present invention provides a fan-out packaging structure and a packaging method, wherein the fan-out packaging structure comprises a first rewiring layer, a second rewiring layer, a metal connecting column, a semiconductor chip, a packaging layer, a stacked chip package, a passive component, a filling layer and a metal bump. The present invention can integrate a plurality of chips with different functions into one packaging structure, thereby improving the integration of the fan-out packaging structure; through the first rewiring layer, the second rewiring layer and the metal connecting column, a three-dimensional vertical stacking packaging is realized, which can effectively improve the integration of the packaging structure, and can effectively shorten the conduction path, so as to reduce power consumption, increase transmission speed and increase data processing capacity.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a fan-out packaging structure and a packaging method. Background Art

[0002] Lower cost, more reliable, faster and higher density circuits are the goals pursued by integrated circuit packaging. With the advent of the 5G communication and artificial intelligence era, the amount of data that chips used in such related fields need to transmit and process at high speed is large, and the demand for mobile Internet and the Internet of Things is becoming stronger and stronger. The miniaturization and multi-functionality of electronic terminal products have become a major trend in industrial development. How to integrate and package different types of high-density chips together to form a powerful system with low volume and power consumption has become a major challenge in the field of advanced semiconductor chip packaging.

[0003] Among them, fan-out wafer-level packaging (FOWLP) has become one of the more advanced fan-out packaging methods due to its large number of input / output ports (I / O) and good integration flexibility. However, in the existing fan-out packaging technology, due to the limited wiring accuracy, the package body has a large area and high thickness, and there are many problems such as numerous processes and low reliability.

[0004] Therefore, it is necessary to provide a new fan-out packaging structure and packaging method. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a fan-out packaging structure and a packaging method, which are used to solve the problems in the prior art that the packaging volume is difficult to reduce and the packaging integration is low.

[0006] To achieve the above object and other related objects, the present invention provides a fan-out packaging method, comprising the following steps:

[0007] Providing a supporting substrate, and forming a separation layer on the supporting substrate;

[0008] forming a first rewiring layer on the separation layer, wherein the first rewiring layer comprises a first surface in contact with the separation layer and a second surface opposite to the separation layer;

[0009] forming a metal connection column on the second surface of the first re-distribution layer, wherein the metal connection column is electrically connected to the first re-distribution layer;

[0010] Providing a semiconductor chip, wherein the semiconductor chip is located on the second surface of the first rewiring layer, and the back surface of the semiconductor chip is bonded to the first rewiring layer, and the front surface of the semiconductor chip is away from the second surface of the first rewiring layer;

[0011] The first rewiring layer, the metal connecting pillars and the semiconductor chip are encapsulated by using an encapsulation layer, and the metal connecting pillars and the pads of the semiconductor chip are exposed by the encapsulation layer;

[0012] forming a second rewiring layer on the packaging layer, wherein the second rewiring layer comprises a first surface in contact with the packaging layer and a second surface opposite thereto, and the second rewiring layer is electrically connected to the metal connection column and the pad of the semiconductor chip;

[0013] forming a metal bump on the second surface of the second redistribution layer, wherein the metal bump is electrically connected to the second redistribution layer;

[0014] Providing a carrier, and peeling off the supporting substrate to expose the first surface of the first redistribution layer;

[0015] Performing laser etching on the first rewiring layer to expose the metal wiring layer in the first rewiring layer;

[0016] Providing a stacked chip package and a passive component, wherein the stacked chip package and the passive component are located on a first surface of the first redistribution layer, and both the stacked chip package and the passive component are electrically connected to the metal wiring layer exposed in the first redistribution layer;

[0017] Using a filling layer to fill the gap between the stacked chip package and the first rewiring layer;

[0018] Cutting is performed to form a fan-out packaging structure.

[0019] Optionally, after forming the filling layer and before cutting, the method further includes a step of encapsulating the first rewiring layer, the stacked chip package and the passive components with a plastic encapsulation layer.

[0020] Optionally, the stacked chip package includes an ePoP memory.

[0021] Optionally, the passive element includes one or a combination of a resistor, a capacitor and an inductor.

[0022] The present invention also provides a fan-out packaging structure, the fan-out packaging structure comprising:

[0023] A first re-distribution layer, the first re-distribution layer comprising a first surface and a second surface opposite to each other;

[0024] a second redistribution layer, the second redistribution layer comprising a first surface and a second surface opposite to each other;

[0025] A metal connection column, located between the second surface of the first redistribution layer and the first surface of the second redistribution layer, and electrically connected to the first redistribution layer and the second redistribution layer;

[0026] A semiconductor chip is located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, and the back surface of the semiconductor chip is bonded to the first rewiring layer, and the front surface of the semiconductor chip is away from the first rewiring layer and electrically connected to the second rewiring layer;

[0027] A packaging layer, located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, covering the first rewiring layer, the metal connecting pillars and the semiconductor chip;

[0028] A stacked chip package and a passive component are located on a first surface of the first redistribution layer and are electrically connected to the first redistribution layer;

[0029] a filling layer, located between the stacked chip package and the first re-distribution layer, and filling a gap between the stacked chip package and the first re-distribution layer;

[0030] The metal bump is located on the second surface of the second redistribution layer and is electrically connected to the second redistribution layer.

[0031] Optionally, it also includes a plastic packaging layer covering the first rewiring layer, the stacked chip package and the passive components.

[0032] Optionally, the stacked chip package includes an ePoP memory.

[0033] Optionally, the passive element includes one or a combination of a resistor, a capacitor and an inductor.

[0034] Optionally, a thickness of the second rewiring layer is greater than a thickness of the first rewiring layer.

[0035] Optionally, the encapsulation layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer; the filling layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

[0036] As described above, the fan-out packaging structure and packaging method of the present invention can integrate a variety of chips with different functions into one packaging structure, thereby improving the integration of the fan-out packaging structure; through the first rewiring layer, the second rewiring layer and the metal connecting column, a three-dimensional vertical stacking packaging is realized, which can effectively improve the integration of the packaging structure and effectively shorten the conduction path to reduce power consumption, increase transmission speed, and increase data processing capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Shown is a process flow chart for preparing the fan-out packaging structure of the present invention.

[0038] Figures 2 to 18 It is a schematic diagram of the structure presented in each step of the preparation process of the fan-out packaging structure in the present invention, wherein: Fig.16 and Fig.18 Shown are structural schematic diagrams of two different fan-out packaging structures in the present invention.

[0039] Component number description

[0040] 100 Support substrate

[0041] 200 Separation Layer

[0042] 300 First rewiring layer

[0043] 301 dielectric layer

[0044] 302 Metal Wiring Layer

[0045] 400 Metal connecting column

[0046] 500 Semiconductor Chips

[0047] 600 Encapsulation Layer

[0048] 700 Second rewiring layer

[0049] 800 metal bumps

[0050] 900 Carrier

[0051] 110 stacked chip package

[0052] 120 Passive Components

[0053] 130 Filling layer

[0054] 140 Plastic layer DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0057] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0058] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0059] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0060] like Figure 1 As shown, this embodiment provides a fan-out packaging method. This embodiment can integrate multiple chips with different functions into one packaging structure, thereby improving the integration of the fan-out packaging structure; through the first rewiring layer, the second rewiring layer and the metal connecting column, a three-dimensional vertical stacking packaging is realized, which can effectively improve the integration of the packaging structure and effectively shorten the conduction path to reduce power consumption, increase transmission speed, and increase data processing capacity.

[0061] First, see Figure 2 , providing a supporting substrate 100 , and forming a separation layer 200 on the supporting substrate 100 .

[0062] Specifically, the support substrate 100 may include one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate. In the present embodiment, the support substrate 100 is preferably a glass substrate with low cost, and it is easy to form the separation layer 200 on its surface, and it can reduce the difficulty of the subsequent stripping process, but it is not limited to this. The separation layer 200 may include one of a tape and a polymer layer. When the polymer layer is used, the polymer can be applied to the surface of the support substrate 100 by a spin coating process, and then cured and formed by an ultraviolet curing or thermal curing process. In the present embodiment, the separation layer 200 uses an LTHC light-to-heat conversion layer, so that the subsequent steps can heat the LTHC light-to-heat conversion layer based on laser or other methods, so that the support substrate 100 is separated from the LTHC light-to-heat conversion layer, reducing the difficulty of the stripping process and reducing damage.

[0063] Next, see Figure 3-4 , a first rewiring layer 300 is formed on the separation layer 200 , wherein the first rewiring layer 300 includes a first surface in contact with the separation layer 200 and a second surface opposite to the separation layer 200 .

[0064] Specifically, in this embodiment, a dielectric layer 301 is first formed on the surface of the separation layer 200, and then a patterned metal wiring layer 302 is formed. According to process requirements, the steps of forming the dielectric layer 301 and the metal wiring layer 302 can be repeated to increase the conductive path. In this embodiment, only one dielectric layer 301 and one metal wiring layer 302 are included to reduce the thickness of the first rewiring layer 300, but the specific number of layers of the first rewiring layer 300 can be selected according to needs. Among them, the material of the dielectric layer 301 can include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass, and fluorine-containing glass; the material of the metal wiring layer 302 can include one of copper, aluminum, nickel, gold, silver, and titanium.

[0065] Next, see Figure 5 , a metal connection column 400 is formed on the second surface of the first re-distribution layer 300 , and the metal connection column 400 is electrically connected to the first re-distribution layer 300 .

[0066] Specifically, the metal connecting column 400 can be formed by a wire welding process, wherein the wire welding process may include a hot pressing wire welding process, an ultrasonic wire welding process, and a hot pressing ultrasonic wire welding process; the material of the metal connecting column 400 may include one or a combination of Au, Ag, Cu, and Al, and the formation method and material selection of the metal connecting column 400 are not overly restricted here.

[0067] Next, see Figure 6, providing a semiconductor chip 500, wherein the semiconductor chip 500 is located on the second surface of the first rewiring layer 300, and the back surface of the semiconductor chip 500 is bonded to the first rewiring layer 300, and the front surface of the semiconductor chip 500 is away from the second surface of the first rewiring layer 300.

[0068] As an example, the height of the metal connection pillar 400 is greater than the height of the semiconductor chip 500 .

[0069] Specifically, when the height of the metal connecting column 400 is greater than the height of the semiconductor chip 500, the damage to the semiconductor chip 500 can be reduced in the subsequent thinning process. The height of the metal connecting column 400 and the semiconductor chip 500 can also be selected according to the type of the semiconductor chip 500, and no excessive restriction is made here.

[0070] Next, see Figure 7-Figure 8 The first rewiring layer 300 , the metal connecting pillars 400 and the semiconductor chip 500 are encapsulated by an encapsulation layer 600 , and the encapsulation layer 600 exposes the pads of the metal connecting pillars 400 and the semiconductor chip 500 .

[0071] Specifically, the method of forming the encapsulation layer 600 may include one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating, and the material of the encapsulation layer 600 may include one of polyimide, silicone and epoxy resin. After the encapsulation layer 600 is formed, a grinding or polishing method may be used on the top surface of the encapsulation layer 600 to provide a flat top surface of the encapsulation layer 600.

[0072] Next, see Fig. 9 A second rewiring layer 700 is formed on the packaging layer 600, and the second rewiring layer 700 includes a first surface in contact with the packaging layer 600 and a second surface opposite thereto, and the second rewiring layer 700 is electrically connected to the metal connecting column 400 and the pad of the semiconductor chip 500.

[0073] As an example, the thickness of the second rewiring layer 700 is greater than the thickness of the first rewiring layer 300 .

[0074] Specifically, the material, structure, and preparation of the second rewiring layer 700 can refer to the first rewiring layer 300, and will not be repeated here. In this embodiment, since the second rewiring layer 700 has more conductive channels, the thickness of the second rewiring layer 700 is greater than the thickness of the first rewiring layer 300, and the specific sizes of the first rewiring layer 300 and the second rewiring layer 700 are not overly restricted here.

[0075] Next, see Fig.10 , forming a metal bump 800, and the metal bump 800 is electrically connected to the second rewiring layer 700, wherein the metal bump 800 may include one of a copper metal bump, a nickel metal bump, a tin metal bump and a silver metal bump, and the specific type can be selected according to needs.

[0076] Next, see Fig.11 , provide a carrier 900, and peel off the support substrate 100 to expose the first surface of the first rewiring layer 300. Specifically, in this embodiment, since the separation layer 200 adopts the LTHC light-to-heat conversion layer, the support substrate 100 can be separated from the LTHC light-to-heat conversion layer by heating based on laser, but the method of peeling off the support substrate 100 is not limited to this, and can be specifically selected according to the materials of the support substrate 100 and the separation layer 200.

[0077] Next, see Fig.12 , laser etching is performed on the first rewiring layer 300 to expose the metal wiring layer 302 in the first rewiring layer 300 .

[0078] Next, see Figure 13-14 , providing a stacked chip package 110 and a passive component 120, wherein the stacked chip package 110 and the passive component 120 are located on the first surface of the first re-wiring layer 300, and the stacked chip package 110 and the passive component 120 are electrically connected to the metal wiring layer 302 exposed in the first re-wiring layer 300.

[0079] As an example, the stacked chip package 110 includes an ePoP memory.

[0080] As an example, the passive component 120 includes one or a combination of a resistor, a capacitor and an inductor.

[0081] Specifically, in this embodiment, the stacked chip package 110 is an ePoP memory, but is not limited thereto, and other packages may be used as needed. Similarly, the passive component 120 may also be configured as needed, and no excessive restrictions are imposed here.

[0082] Next, see Fig.15 A filling layer 130 is used to fill the gap between the semiconductor chip 500 and the first rewiring layer 300 .

[0083] Specifically, the filling layer 130 may include one of an epoxy resin layer, a polyimide layer, and a silicone layer, so as to fill the gap with the insulating filling layer 130 to strengthen the bonding effect between the semiconductor chip 500 and the first rewiring layer 300, and form a protective layer to prevent water vapor, oxygen, etc. from acting on the semiconductor chip 500 and the first rewiring layer 300. The material of the filling layer 130 is not excessively limited here.

[0084] Finally, see Fig.16 , cut to form a fan-out packaging structure.

[0085] As an example, after forming the filling layer 130 and before cutting, a step of encapsulating the first re-distribution layer 300 , the stacked chip package 110 and the passive component 120 with a plastic encapsulation layer 140 is also included.

[0086] For details, see Fig.17 and Fig.18 The plastic sealing layer 140 includes one of an epoxy resin layer, a polyimide layer and a silicone layer. The specific preparation method can refer to the packaging layer 600, which will not be described here.

[0087] See also Fig.16 The present embodiment further provides a fan-out packaging structure, which can be prepared by the above-mentioned preparation method, but is not limited thereto. In the present embodiment, the fan-out packaging structure is prepared by the above-mentioned preparation method, so the preparation method, material selection, etc. of the fan-out packaging structure are not described in detail here.

[0088] Specifically, the fan-out packaging structure includes a first rewiring layer 300, a second rewiring layer 700, a metal connection column 400, a semiconductor chip 500, a packaging layer 600, a stacked chip package 110, a passive component 120, a filling layer 130 and a metal bump 800. The first rewiring layer 300 includes a first surface and a second surface opposite to each other; the second rewiring layer 700 includes a first surface and a second surface opposite to each other; the metal connection column 400 is located between the second surface of the first rewiring layer 300 and the first surface of the second rewiring layer 700, and is electrically connected to the first rewiring layer 300 and the second rewiring layer 700; the semiconductor chip 500 is located between the second surface of the first rewiring layer 300 and the first surface of the second rewiring layer 700, and the back surface of the semiconductor chip 500 is bonded to the first rewiring layer 300, and the front surface of the semiconductor chip 500 is away from the first rewiring layer 300 and is electrically connected to the second rewiring layer 700; The packaging layer 600 is located between the second surface of the first re-wiring layer 300 and the first surface of the second re-wiring layer 700, covering the first re-wiring layer 300, the metal connecting column 400 and the semiconductor chip 500; the stacked chip package 110 and the passive component 120 are located on the first surface of the first re-wiring layer 300 and are electrically connected to the first re-wiring layer 300; the filling layer 130 is located between the stacked chip package 110 and the first re-wiring layer 300, and fills the gap between the stacked chip package 110 and the first re-wiring layer 300; the metal bump 800 is located on the second surface of the second re-wiring layer 700 and is electrically connected to the second re-wiring layer 700.

[0089] As an example, a plastic encapsulation layer 140 covering the first re-distribution layer 300 , the stacked chip package 110 and the passive component 120 is also included.

[0090] As an example, the stacked chip package 110 includes an ePoP memory.

[0091] As an example, the passive component 120 includes one or a combination of a resistor, a capacitor and an inductor.

[0092] As an example, the thickness of the second rewiring layer 700 is greater than the thickness of the first rewiring layer 300 .

[0093] As an example, the encapsulation layer 600 includes one of an epoxy resin layer, a polyimide layer and a silicone layer; the filling layer 130 includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

[0094] In summary, the fan-out packaging structure and packaging method of the present invention can integrate multiple chips with different functions into one packaging structure, thereby improving the integration of the fan-out packaging structure; through the first rewiring layer, the second rewiring layer and the metal connecting column, a three-dimensional vertical stacking packaging is realized, which can effectively improve the integration of the packaging structure and effectively shorten the conduction path to reduce power consumption, increase transmission speed, and increase data processing capacity.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A fan-out packaging method, characterized in that: The following steps are involved: Providing a supporting substrate, and forming a separation layer on the supporting substrate; forming a first rewiring layer on the separation layer, wherein the first rewiring layer comprises a first surface in contact with the separation layer and a second surface opposite to the separation layer; forming a metal connection column on the second surface of the first re-distribution layer, wherein the metal connection column is electrically connected to the first re-distribution layer; Providing a semiconductor chip, wherein the semiconductor chip is located on the second surface of the first rewiring layer, and the back surface of the semiconductor chip is bonded to the first rewiring layer, and the front surface of the semiconductor chip is away from the second surface of the first rewiring layer; The first rewiring layer, the metal connecting pillars and the semiconductor chip are encapsulated by using an encapsulation layer, and the metal connecting pillars and the pads of the semiconductor chip are exposed by the encapsulation layer; forming a second rewiring layer on the packaging layer, wherein the second rewiring layer comprises a first surface in contact with the packaging layer and a second surface opposite thereto, and the second rewiring layer is electrically connected to the metal connection column and the pad of the semiconductor chip; forming a metal bump on the second surface of the second redistribution layer, wherein the metal bump is electrically connected to the second redistribution layer; Providing a carrier, and peeling off the supporting substrate to expose the first surface of the first redistribution layer; Performing laser etching on the first rewiring layer to expose the metal wiring layer in the first rewiring layer; Providing a stacked chip package and a passive component, wherein the stacked chip package and the passive component are located on a first surface of the first redistribution layer, and both the stacked chip package and the passive component are electrically connected to the metal wiring layer exposed in the first redistribution layer; Using a filling layer to fill the gap between the stacked chip package and the first rewiring layer; Cutting is performed to form a fan-out packaging structure.

2. The fan-out packaging method according to claim 1, characterized in that: After forming the filling layer and before cutting, the method further includes the step of using a plastic packaging layer to encapsulate the first rewiring layer, the stacked chip package and the passive components.

3. The fan-out packaging method according to claim 1, characterized in that: The stacked chip package includes an ePoP memory.

4. The fan-out packaging method according to claim 1, characterized in that: The passive components include one or a combination of resistors, capacitors and inductors.

5. A fan-out packaging structure, characterized in that: The fan-out packaging structure comprises: A first re-distribution layer, the first re-distribution layer comprising a first surface and a second surface opposite to each other; a second redistribution layer, the second redistribution layer comprising a first surface and a second surface opposite to each other; A metal connection column, located between the second surface of the first redistribution layer and the first surface of the second redistribution layer, and electrically connected to the first redistribution layer and the second redistribution layer; A semiconductor chip is located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, and the back surface of the semiconductor chip is bonded to the first rewiring layer, and the front surface of the semiconductor chip is away from the first rewiring layer and electrically connected to the second rewiring layer; A packaging layer, located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, covering the first rewiring layer, the metal connecting pillars and the semiconductor chip; A stacked chip package and a passive component are located on a first surface of the first redistribution layer and are electrically connected to the first redistribution layer; a filling layer, located between the stacked chip package and the first re-distribution layer, and filling a gap between the stacked chip package and the first re-distribution layer; a metal bump, located on the second surface of the second redistribution layer and electrically connected to the second redistribution layer; The passive component includes one or a combination of a resistor, a capacitor and an inductor; the packaging layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

6. The fan-out packaging structure according to claim 5, characterized in that: It also includes a plastic packaging layer covering the first rewiring layer, the stacked chip package and the passive components.

7. The fan-out packaging structure according to claim 5, characterized in that: The stacked chip package includes an ePoP memory.

8. The fan-out packaging structure according to claim 5, characterized in that: The thickness of the second rewiring layer is greater than that of the first rewiring layer.

9. The fan-out packaging structure according to claim 5, characterized in that: The encapsulation layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer; the filling layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

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