Pull-down circuit and chip

Abstract

The present invention discloses a pull-down circuit and chip, wherein the pull-down circuit includes: a MOS transistor NM0, a pull-down resistor R0 connected between the drain of the MOS transistor NM0 and a pull-down node AOUT, and a switch unit connected between the source of the MOS transistor NM0 and ground. In a power-off mode, the MOS transistor NM0 is turned on and the switch unit can control the connection between the source of the MOS transistor NM0 and ground. In a non-power-off mode and when the pull-down node AOUT is in a negative voltage domain, the switch unit can control the disconnection between the source of the MOS transistor NM0 and ground. According to an embodiment of the present invention, the pull-down circuit can control the disconnection and connection between the source of the MOS transistor NM0 and ground through the switch unit, so that when the pull-down node AOUT is in a negative voltage domain in the non-power-off mode, the source of the MOS transistor NM0 is disconnected from the ground, effectively preventing the pull-down node AOUT from being pulled down to ground when the pull-down node AOUT is in a negative voltage domain in the non-power-off mode, thereby meeting application requirements.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a pull-down circuit and a chip. Background Art

[0002] The existing pull-down circuit consists of a resistor and an NMOS transistor, which can pull down the output end of the circuit with a positive output voltage to zero. However, when the output end of the circuit outputs a negative voltage, the NMOS transistor will produce an "inverted" problem, causing it to be pulled down to zero when it does not need to be pulled down to zero. This needs to be avoided in some application scenarios where a negative output voltage is required.

[0003] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0004] The object of the present invention is to provide a pull-down circuit and chip, which can prevent the circuit output from being pulled down to zero even if the circuit output is a negative voltage when it is not necessary to pull the voltage down to zero.

[0005] To achieve the above objectives, an embodiment of the present invention provides a pull-down circuit, comprising: a MOS transistor NM0, a pull-down resistor R0 connected between the drain of the MOS transistor NM0 and a pull-down node AOUT, and a switch unit connected between the source of the MOS transistor NM0 and ground; in a power-off mode, the MOS transistor NM0 is turned on and the switch unit is capable of controlling the connection between the source of the MOS transistor NM0 and ground; in a non-power-off mode and when the pull-down node AOUT is in a negative voltage domain, the switch unit is capable of controlling the disconnection between the source of the MOS transistor NM0 and ground.

[0006] In one or more embodiments of the present invention, the pull-down circuit further includes a first control unit connected to the gate of the MOS transistor NM0 , and the first control unit receives a PWD signal and controls the on and off of the MOS transistor NM0 .

[0007] In one or more embodiments of the present invention, the first control unit includes an inverter INV1 and an inverter INV2, the input end of the inverter INV1 receives the PWD signal, the output end of the inverter INV1 is connected to the input end of the inverter INV2, and the output end of the inverter INV2 is connected to the gate of the MOS transistor NM0.

[0008] In one or more embodiments of the present invention, the inverter INV1 and the inverter INV2 are both connected to a power supply VDD, the voltage of the power supply VDD is ≥0V, and the inverter INV1 and the inverter INV2 are both grounded.

[0009] In one or more embodiments of the present invention, the switch unit includes an NMOS transistor NM1 and a PMOS transistor PM0, the drain of the NMOS transistor NM1 is connected to the source of the PMOS transistor PM0 and is also connected to the source of the MOS transistor NM0, the source of the NMOS transistor NM1 is connected to the drain of the PMOS transistor PM0 and is also grounded; in power-off mode and when the pull-down node AOUT is in a positive voltage domain, the NMOS transistor NM1 and the PMOS transistor PM0 are both turned on; in power-off mode and when the pull-down node AOUT is in a negative voltage domain, the NMOS transistor NM1 is turned off and the PMOS transistor PM0 is turned on.

[0010] In one or more embodiments of the present invention, the pull-down circuit further includes a second control unit connected to the gate of the NMOS transistor NM1 and the gate of the PMOS transistor PM0, the second control unit receives a PWD signal and controls the on and off of the NMOS transistor NM1 and the PMOS transistor PM0.

[0011] In one or more embodiments of the present invention, the second control unit includes a level converter Levelshift, an inverter INV3 and an inverter INV4, one end of the level converter Levelshift receives a PWD signal and the other end is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the gate of the PMOS tube PM0 and the input end of the inverter INV4, and the output end of the inverter INV4 is connected to the gate of the NMOS tube NM1.

[0012] In one or more embodiments of the present invention, the inverter INV3 and the inverter INV4 are connected to the power supply VCC, and the inverter INV3 and the inverter INV4 are connected to the power supply VSS. The voltage of the power supply VCC is ≥0V, and the voltage of the power supply VSS is ≤0V.

[0013] In one or more embodiments of the present invention, the MOS transistor NM0 is a DMOS transistor.

[0014] The present invention further provides a chip, comprising an operational amplifier circuit capable of outputting a positive voltage or a negative voltage, wherein the output end of the operational amplifier circuit is connected to a pull-down node AOUT of the pull-down circuit.

[0015] Compared with the prior art, the pull-down circuit according to the embodiment of the present invention can control the disconnection and connection between the source of the MOS transistor NM0 and the ground through the switching unit, so that in the non-power-off mode and when the pull-down node AOUT is in the negative voltage domain, the source of the MOS transistor NM0 is disconnected from the ground, effectively preventing the pull-down node AOUT from being pulled down to the ground when the pull-down node AOUT is in the negative voltage domain in the non-power-off mode, thereby meeting application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a circuit schematic diagram of a pull-down circuit according to an embodiment of the present invention;

[0017] Figure 2 is a voltage waveform diagram of each end in a positive voltage domain according to an embodiment of the present invention;

[0018] Figure 3 1 is a PWD signal waveform diagram and a corresponding current waveform diagram of the NMOS transistor NM1 and the PMOS transistor PM0 in a positive voltage domain according to an embodiment of the present invention;

[0019] Figure 4 is a voltage waveform diagram of each terminal in a negative voltage domain according to an embodiment of the present invention;

[0020] Figure 5 1 is a PWD signal waveform diagram and a corresponding current waveform diagram of the NMOS transistor NM1 and the PMOS transistor PM0 in a negative voltage domain according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0022] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations such as "include" or "comprising", etc., will be understood to include the stated elements or components but not to exclude other elements or other components.

[0023] Example 1

[0024] like Figure 1As shown, a pull-down circuit includes: a MOS transistor NM0; a pull-down resistor R0 connected between the drain of the MOS transistor NM0 and a pull-down node AOUT; and a switch unit 10 connected between the source of the MOS transistor NM0 and ground. The on / off state of the MOS transistor NM0 is controlled by a first control unit 20. The on / off state of the switch unit 10, the source of the MOS transistor NM0, and ground is controlled by a second control unit 30. In this embodiment, a DMOS transistor is used for the MOS transistor NM0 to take advantage of its high drain-source breakdown voltage. The gate-source voltage of the DMOS transistor can reach 5.5V. The pull-down resistor R0 has a smaller resistance value to provide stronger pull-down capability.

[0025] The pull-down node AOUT can be in a positive voltage domain or a negative voltage domain. In the power-off mode, regardless of whether the pull-down node AOUT is in a positive voltage domain or a negative voltage domain, the MOS transistor NM0 is turned on and the switch unit 10 can control the connection between the source of the MOS transistor NM0 and the ground. In the non-power-off mode (normal working state) and when the pull-down node AOUT is in a negative voltage domain, the switch unit 10 can control the disconnection between the source of the MOS transistor NM0 and the ground. In the non-power-off mode (normal working state) and when the pull-down node AOUT is in a positive voltage domain, the MOS transistor NM0 is turned off.

[0026] In this embodiment, the first control unit 20 is connected to the gate of the MOS transistor NM0. The first control unit 20 receives a PWD signal and controls the on / off state of the MOS transistor NM0. When the PWD signal is "0," it indicates a non-power-off mode. When the PWD signal is "1" (i.e., the power supply VDD voltage), it indicates a power-off mode.

[0027] Specifically, the first control unit 20 includes an inverter INV1 and an inverter INV2. The input of the inverter INV1 receives the PWD signal, the output of the inverter INV1 is connected to the input of the inverter INV2, and the output of the inverter INV2 is connected to the gate of the MOS transistor NM0. The inverters INV1 and INV2 are both connected to the power supply VDD, the voltage of the power supply VDD is ≥ 0V, and the inverters INV1 and INV2 are both grounded. In this embodiment, the voltage of the power supply VDD is ≥ 0V and ≤ 5.5V. The inverters INV1 and INV2 are inverters in the power supply VDD voltage and 0 domain.

[0028] In this embodiment, the switch unit 10 includes an NMOS transistor NM1 and a PMOS transistor PM0. The drain of the NMOS transistor NM1 is connected to the source of the PMOS transistor PM0 and is also connected to the source of the MOS transistor NM0. The source of the NMOS transistor NM1 is connected to the drain of the PMOS transistor PM0 and is also grounded. In the power-off mode and when the pull-down node AOUT is in a positive voltage domain, both the NMOS transistor NM1 and the PMOS transistor PM0 are turned on. In the power-off mode and when the pull-down node AOUT is in a negative voltage domain, the NMOS transistor NM1 is turned off and the PMOS transistor PM0 is turned on.

[0029] The second control unit 30 is connected to the gate of the NMOS transistor NM1 and the gate of the PMOS transistor PM0. The second control unit 30 receives a PWD signal and controls the on / off switching of the NMOS transistor NM1 and the PMOS transistor PM0. A PWD signal of "0" indicates a non-power-down mode, while a PWD signal of "1" (i.e., the power supply VDD voltage) indicates a power-down mode.

[0030] Specifically, the second control unit 30 includes a level shifter, an inverter INV3, and an inverter INV4. One end of the level shifter receives the PWD signal and is connected to the input of inverter INV1. The other end is connected to the input of inverter INV3. The output of inverter INV3 is connected to the gate of PMOS transistor PM0 and the input of inverter INV4. The output of inverter INV4 is connected to the gate of NMOS transistor NM1. Inverters INV3 and INV4 are both connected to power supply VCC and power supply VSS. The voltage of power supply VCC is ≥0V and ≤5.5V, and the voltage of power supply VSS is ≤0V and ≥-5.5V. Inverters INV3 and INV4 serve as inverters for the power supply VCC and power supply VSS voltage domains. The level shifter is used for conversion from the VDD domain to the VCC domain.

[0031] like Figure 2 and Figure 3 As shown, at this time, the pull-down node AOUT is in the positive voltage domain. When the PWD signal is "0", after passing through the inverter INV1 and the inverter INV2, the NG end (the gate of the MOS tube) is "0", the MOS tube NM0 is turned off, and the pull-down is turned off; when the PWD signal is "1", after passing through the inverter INV1 and the inverter INV2, the NG end (the gate of the MOS tube) is "1", and the MOS tube NM0 is turned on.

[0032] At the same time, after the PWD signal passes through the level shift converter and inverters INV3 and INV4, the PDP terminal (the gate of the NMOS transistor NM1) is "1" (the power supply VCC voltage domain), and the PDN terminal (the gate of the PMOS transistor PM0) is "0" (the power supply VSS voltage domain). The NMOS transistor NM1 is turned on, the PMOS transistor PM0 is turned on, and the NS terminal (the source of the MOS transistor) is "0", and the pull-down is turned on.

[0033] In the entire process described above, current flows only when the PWD signal switches from "0" to "1". No DC current flows before and after the switching, and no power is consumed.

[0034] like Figure 4 and Figure 5 As shown, the power supply VCC voltage is 0V, the power supply VSS voltage is -5.5V, and the pull-down node AOUT is in a negative voltage domain, such as -5.5V at the pull-down node AOUT.

[0035] When the PWD signal is "0", after passing through inverters INV1 and INV2, the NG terminal (the gate of the MOS transistor) is "0", and the MOS transistor NM0 is still turned on; the PDP terminal (the gate of the NMOS transistor NM1) is the power supply VSS voltage, and the NMOS transistor NM1 is turned off; the PDN terminal (the gate of the PMOS transistor PM0) is the power supply VCC voltage, and the PMOS transistor PM0 is also turned off, so the pull-down is turned off, and the substrate of the NMOS transistor NM1 is connected to the drain, and the substrate of the PMOS transistor PM0 is also connected to the drain, ensuring that there is no static current when the pull-down is turned off, and normal operation is not affected.

[0036] When the PWD signal is "1", after passing through inverters INV1 and INV2, the NG terminal (the gate of the MOS transistor) is "1", and the MOS transistor NM0 is turned on. After the PWD signal passes through the level shift converter and inverters INV3 and INV4, the PDP terminal (the gate of the NMOS transistor NM1) is "1" (the power supply VCC voltage domain), and the PDN terminal (the gate of the PMOS transistor PM0) is "0" (the power supply VSS voltage domain). The NMOS transistor NM1 is turned off, the PMOS transistor PM0 is turned on, the pull-down is turned on, and the NS terminal (the source of the MOS transistor) is pulled to "0", which also ensures that the gate-source voltage of the MOS transistor NM0 (NG-NS<5.5V) is in the safe operating area.

[0037] During the entire process described above, current flows only when the PWD signal switches from "0" to "1". No DC current flows before and after the switching, and no power is consumed.

[0038] Example 2

[0039] This embodiment also provides a chip including an op amp circuit capable of outputting a positive or negative voltage, wherein the output of the op amp circuit is connected to a pull-down node AOUT of a pull-down circuit. The output is pulled down to zero in power-down mode and consumes no power in a non-power-down mode (normal operating mode).

[0040] The foregoing descriptions of specific exemplary embodiments of the present invention are for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many variations and modifications are possible in light of the foregoing teachings. The exemplary embodiments have been selected and described for the purpose of explaining the specific principles of the invention and their practical application, thereby enabling those skilled in the art to realize and utilize a variety of exemplary embodiments of the invention and various options and modifications. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A pull-down circuit, characterized in that: include: A MOS transistor NM0, a pull-down resistor R0 connected between the drain of the MOS transistor NM0 and a pull-down node AOUT, and a switch unit connected between the source of the MOS transistor NM0 and ground; in a power-off mode, the MOS transistor NM0 is turned on and the switch unit can control the connection between the source of the MOS transistor NM0 and the ground; in a non-power-off mode and when the pull-down node AOUT is in a negative voltage domain, the switch unit can control the disconnection between the source of the MOS transistor NM0 and the ground.

2. The pull-down circuit according to claim 1, wherein: The pull-down circuit further includes a first control unit connected to the gate of the MOS transistor NM0 , and the first control unit receives a PWD signal and controls the on and off of the MOS transistor NM0 .

3. The pull-down circuit according to claim 2, wherein: The first control unit includes an inverter INV1 and an inverter INV2. The input end of the inverter INV1 receives a PWD signal. The output end of the inverter INV1 is connected to the input end of the inverter INV2. The output end of the inverter INV2 is connected to the gate of the MOS transistor NM0.

4. The pull-down circuit according to claim 3, wherein: The inverter INV1 and the inverter INV2 are connected to a power supply VDD at the same time, the voltage of the power supply VDD is ≥ 0V, and the inverter INV1 and the inverter INV2 are grounded at the same time.

5. The pull-down circuit according to claim 1, wherein: The switch unit includes an NMOS transistor NM1 and a PMOS transistor PM0. The drain of the NMOS transistor NM1 is connected to the source of the PMOS transistor PM0 and is also connected to the source of the MOS transistor NM0. The source of the NMOS transistor NM1 is connected to the drain of the PMOS transistor PM0 and is also grounded. In the power-off mode and when the pull-down node AOUT is in a positive voltage domain, the NMOS transistor NM1 and the PMOS transistor PM0 are both turned on. In the power-off mode and when the pull-down node AOUT is in a negative voltage domain, the NMOS transistor NM1 is turned off and the PMOS transistor PM0 is turned on.

6. The pull-down circuit according to claim 5, wherein: The pull-down circuit further includes a second control unit connected to the gate of the NMOS transistor NM1 and the gate of the PMOS transistor PM0 , and the second control unit receives a PWD signal and controls the NMOS transistor NM1 and the PMOS transistor PM0 to be turned on and off.

7. The pull-down circuit according to claim 6, wherein: The second control unit includes a level converter Level shift, an inverter INV3 and an inverter INV4. One end of the level converter Level shift receives a PWD signal and the other end is connected to the input end of the inverter INV3. The output end of the inverter INV3 is connected to the gate of the PMOS transistor PM0 and the input end of the inverter INV4. The output end of the inverter INV4 is connected to the gate of the NMOS transistor NM1.

8. The pull-down circuit according to claim 7, wherein: The inverter INV3 and the inverter INV4 are connected to the power supply VCC at the same time. The inverter INV3 and the inverter INV4 are connected to the power supply VSS at the same time. The voltage of the power supply VCC is ≥0V, and the voltage of the power supply VSS is ≤0V.

9. The pull-down circuit according to claim 1, wherein: The MOS transistor NM0 is a DMOS transistor.

10. A chip, characterized in that: It comprises an operational amplifier circuit capable of outputting positive voltage or negative voltage, wherein the output end of the operational amplifier circuit is connected to the pull-down node AOUT of the pull-down circuit according to any one of claims 1 to 9.

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