Methods used in semiconductor processing

Abstract

The embodiments described herein relate to pre-deposition treatment of materials used in metal gates of different transistors on a semiconductor substrate. In one embodiment, the method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form multiple monolayers on the first metal-containing layer and the second metal-containing layer, respectively. The first device and the second device are located on a substrate. The first device includes a first gate structure, and the first gate structure includes a first metal-containing layer. The second device includes a second gate structure, and the second gate structure includes a second metal-containing layer, and the first metal-containing layer is different from the second metal-containing layer. The monolayers on the first metal-containing layer and the second metal-containing layer are exposed to an oxidant to provide a hydroxyl-terminated surface for the monolayers. A third metal-containing layer is then formed on the hydroxyl-terminated surface of the monolayers on the first metal-containing layer and the second metal-containing layer.

Description

[0001] This application is a divisional application of the invention application of the applicant Taiwan Semiconductor Manufacturing Co., Ltd., with an application date of February 1, 2019, an invention name of “Method for Semiconductor Processing” and application number 201910103532.0. Technical Field

[0002] Embodiments of the present invention relate to semiconductor devices, and more particularly to pre-processing work function materials used for different types of metal gates on the same semiconductor substrate. Background Art

[0003] When fabricating field-effect transistors (FETs), such as finFETs, metal gates can be used instead of polysilicon gates to improve device performance. The metal gate formation process involves sequentially forming a gate dielectric layer, a barrier layer, a work function layer, and a metal liner layer within a high-aspect-ratio trench, followed by filling the trench with gate material. The work function layer can be made of different materials for different transistor types, such as p-type FETs or n-type FETs, to fine-tune the transistor's threshold voltage and enhance the device's electrical performance as needed. However, as device dimensions shrink, new challenges arise. Summary of the Invention

[0004] One embodiment of the present invention provides a method for a semiconductor process, comprising: exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form a plurality of monolayers on the first metal-containing layer and the second metal-containing layer, respectively, wherein the first device and the second device are located on a substrate, the first device includes a first gate structure, and the first gate structure includes a first metal-containing layer, the second device includes a second gate structure, and the second gate structure includes a second metal-containing layer, and the first metal-containing layer is different from the second metal-containing layer; exposing the monolayers on the first metal-containing layer and the second metal-containing layer to an oxidant to provide a hydroxyl-terminated surface for the monolayers on the first metal-containing layer and the second metal-containing layer; and forming a third metal-containing layer on the hydroxyl-terminated surface of the monolayers on the first metal-containing layer and the second metal-containing layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A and Figure 1B is a flow chart of an exemplary method for fabricating a semiconductor device in some embodiments.

[0006] Figures 2 to 4 FIG. 1 is a partial perspective view of a semiconductor device at various fabrication stages in some embodiments.

[0007] Figures 5 to 11 1 is a partial cross-sectional view of a semiconductor device at various fabrication stages in some embodiments.

[0008] Figure 12A simplified semiconductor device showing portions of gate structures in three device regions at an intermediate stage of fabrication.

[0009] Figure 13 Shown is a simplified semiconductor device at an intermediate stage of fabrication in some embodiments.

[0010] 14A to 14C Shown are X-ray photoelectron spectra of titanium aluminum carbide deposited on different substrates in some embodiments.

[0011] Description of reference numerals:

[0012] A-A': Section

[0013] T1: First thickness

[0014] T2: Second thickness

[0015] T3: third thickness

[0016] T4, T5, T6: thickness

[0017] 100: Flowchart

[0018] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122: Step 200: Substrate

[0019] 201, 1200, 1300: Semiconductor devices

[0020] 202: Fins

[0021] 206, 240: Interface dielectric layer

[0022] 208: Virtual gate

[0023] 210: Mask

[0024] 212: Virtual gate structure

[0025] 212a, 212b: replacement gate structure

[0026] 213a, 213b, 213c: Source / drain regions

[0027] 214, 230, 1301, 1303, 1305: Grooves

[0028] 216: Quarantine

[0029] 218: Interlayer dielectric layer

[0030] 220: Gate spacer

[0031] 224, 259: upper surface

[0032] 232: Surface

[0033] 234: Etching process

[0034] 242, 1210, 1310: Gate dielectric layer

[0035] 244, 1208, 1308: Work function adjustment layer

[0036] 245: Cover

[0037] 247: Barrier Layer

[0038] 248: Patterned mask structure

[0039] 250a: First device area

[0040] 250b: Second device area

[0041] 251: Single layer

[0042] 252: Bottom anti-reflective coating

[0043] 253: Pretreatment process

[0044] 254: Photoresist

[0045] 255: Metal lining layer

[0046] 257: Gate Metal

[0047] 261, 263: Treated surface

[0048] 265: Hydroxyl terminated

[0049] 270, 272, 1360, 1362, 1364: Illustrations

[0050] 293, 295: Mixed layer

[0051] 1202, 1204, 1206, 1302, 1304, 1306: Device area

[0052] 1212: Metal layer

[0053] 1312: First metal layer

[0054] 1314: Second metal layer

[0055] 1316: Third metal layer DETAILED DESCRIPTION

[0056] The following content provides different embodiments or examples that can implement different structures of the present invention. The embodiments of specific components and arrangements are used to simplify the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes the two being in direct contact, or the two being separated by other additional components rather than in direct contact. In addition, the numbering may be repeated in various examples of the present disclosure, but such repetition is only for simplification and clarity of description and does not mean that the units with the same numbering between different embodiments and / or settings have the same corresponding relationship.

[0057] Additionally, spatially relative terms such as "below," "beneath," "below," "above," "above," or similar terms may be used to simplify describing the relative relationship of one element to another element in a diagram. Spatially relative terms extend to elements used in other orientations and are not limited to the orientation shown. Elements may also be rotated 90° or at other angles, so directional terms are used only to describe the orientation shown in the diagram.

[0058] Embodiments of the present invention generally relate to semiconductor devices, and more particularly to pre-treating work function materials used in different types of metal gates on the same semiconductor substrate. Generally, the pre-treatment passivates the surface of the work function material to produce a single layer, such as aluminum oxide or silicon oxide. The pre-treatment ensures that the layer subsequently deposited on the passivated surface of the work function material has a more consistent thickness across the metal gates of different transistor types, minimizing the impact on the gap filling performance and / or threshold voltage of other layers in the metal gate. Other embodiments include methods for providing different metal layers between a work function adjustment layer and a gate dielectric layer used in different device regions of a field effect transistor (e.g., an n-type field effect transistor or a p-type field effect transistor device) to adjust the multi-threshold voltage of the n-type or p-type device. The different metal layers affect the composition and thickness of the work function adjustment layer and alter the work function value of the work function adjustment layer deposited thereon. Different work function adjustment layers on different substrates can provide different n-type work functions to achieve multi-threshold voltage adjustment without the need for stacking multiple metal layers. This provides more space for metal gate fill.

[0059] The above summarizes some embodiments of the present invention. It will be appreciated that the pre-treatment process can be implemented on planar transistor devices or three-dimensional transistor devices (such as the semiconductor device 201 described in the embodiments of the present invention). Some of the devices described herein include fin field-effect transistors, horizontal all-around gate field-effect transistors, vertical all-around gate field-effect transistors, nanowire channel field-effect transistors, strained semiconductor devices, silicon-on-insulator devices, or other devices where the pre-treatment process can help alleviate issues (such as loading effects and / or substrate-related growth process issues).

[0060] Figure 1A and Figure 1BA flowchart 100 is shown illustrating an exemplary method of fabricating a semiconductor device 201 in various embodiments of the present invention. Figures 2 to 4 It corresponds to Figure 1A and Figure 1B A partial perspective view of a semiconductor device showing various stages of a flow chart, and Figures 5 to 11 It corresponds to Figure 1A and Figure 1B Partial cross-sectional views of a semiconductor device at various stages of the flowchart in FIG. It is noted that flowchart 100 can be used to form any other semiconductor structure not described herein. Persons skilled in the art will appreciate that the figures and descriptions herein do not represent an exhaustive list of processes for forming semiconductor devices and related structures. While the description and figures herein include various steps, the order of these steps is not limited, nor does it imply the presence or absence of intermediate steps. Unless otherwise noted, the order of steps in the figures or descriptions is for illustrative purposes only and does not preclude the possibility that individual steps may be performed simultaneously or with partial, but not complete, overlap.

[0061] The flowchart 100 begins with step 102 of providing a substrate 200 having a dummy gate structure 212 formed on a plurality of fins 202 on the substrate 200, such as Figure 2 As shown. Substrate 200 may be or include a semiconductor base substrate, a semiconductor-on-insulator substrate, or the like, and may be doped (e.g., doped with p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate may include a semiconductor element (e.g., silicon or germanium), a semiconductor compound, a semiconductor alloy, or a combination thereof. Other substrates may also be used.

[0062] Each fin 202 provides an active area, where one or more devices are formed. The method for making the fin 202 performs a suitable process on the substrate 200, including a mask, photolithography, and / or etching process, to form a groove 214 into the substrate 200 and retain a fin (such as the fin 202) extending upward from the substrate 200. The fin 202 can be patterned by any suitable method. For example, the patterning method of the fin 202 can use one or more photolithography processes, including double patterning or multiple patterning processes. Generally speaking, the double patterning or multiple patterning process includes photolithography and self-alignment processes, which can produce a pattern spacing that is smaller than the pattern spacing obtained by using a single direct photolithography process. For example, some embodiments form a sacrificial layer on the substrate and pattern the sacrificial layer using a photolithography process. Using a self-alignment process, spacers can be formed along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the retained spacers can be used to pattern the fin 202 and form the groove 214.

[0063] An insulating material, such as an oxide (e.g., silicon oxide), a nitride, or the like, or a combination thereof, may then be deposited into the trenches 214 using a suitable deposition technique. Other insulating materials formed using any acceptable process may also be used. An acceptable etching process may be used to recess the insulating material to form isolation regions 216. Due to the recessed insulating material, the fins 202 may protrude upward from between adjacent isolation regions 216.

[0064] Isolation region 216 can separate semiconductor device 201 into various device regions. In the example shown, semiconductor device 201 includes a first device region 250a and a second device region 250b. One or more devices can be formed in first device region 250a, and one or more devices can be formed in second device region 250b. For example, each of first device region 250a and second device region 250b can include a certain type of device (e.g., a p-type device or an n-type device), and the device characteristics in each first device region 250a and second device region 250b can differ. In some embodiments, semiconductor device 201 can be a multi-threshold voltage integrated circuit device used for delay or power optimization. In these examples, the devices in the first device region 250a and the second device region 250b can be n-type ultra-low threshold voltage devices, n-type low threshold voltage devices, n-type standard voltage devices, n-type high threshold voltage devices, p-type ultra-low threshold voltage devices, p-type low threshold voltage devices, p-type standard threshold voltage devices, p-type high threshold voltage devices, or any combination thereof. For example, an n-type device (e.g., an n-type FinFET device) can be located in the first device region 250a and can be an n-type standard threshold voltage device, while another n-type device can be located in the second device region 250b and can be an n-type ultra-low threshold voltage device. However, it will be understood that one of ordinary skill in the art can employ any type of device in the device region and any number of metal gates, each including various types of work function adjustment layers (as described below) and / or combinations of layers, to achieve a desired multiple threshold voltages.

[0065] A dummy gate structure 212 is then formed on the fin 202. The dummy gate structures 212 each include an interfacial dielectric layer 206, a dummy gate 208, and a mask 210. The interfacial dielectric layer 206, the dummy gate 208, and the mask 210 used in the dummy gate structure 212 can be formed by sequentially forming individual layers and then patterning these layers into the dummy gate structure 212. For example, the layer used for the interfacial dielectric layer 206 can include or be silicon oxide, silicon nitride, the like, or a multi-layer thereof, and can be formed by thermal growth and / or chemical growth on the fin 202, or by conformal deposition (such as plasma-enhanced chemical vapor deposition, atomic layer deposition, or any suitable deposition technique). The layer used for the dummy gate 208 can include or be silicon (such as polysilicon) or another material, and can be deposited by chemical vapor deposition, physical vapor deposition, or any suitable deposition technique. The layer used for the mask 210 may include or be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof, and may be deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any other suitable deposition technique. The layer used for the mask 210, the dummy gate 208, and the interfacial dielectric layer 206 may then be patterned to form the mask 210, the dummy gate 208, and the interfacial dielectric layer 206 for each dummy gate structure 212. The patterning may be performed using photolithography and one or more etching processes.

[0066] Step 104 forms a gate spacer 220 along the sidewalls of the dummy gate structure 212 (such as the sidewalls of the interfacial dielectric layer 206, the dummy gate 208, and the mask 210), and the gate spacer 220 is formed on the fin 202. For example, the gate spacer 220 may be formed by conformally depositing one or more layers for the gate spacer 220, rather than isotropically etching one or more layers. The one or more layers for the gate spacer 220 may contain a material that is different from the material for the dummy gate structure 212. In one embodiment, the gate spacer 220 may include or be a dielectric material such as silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, the like, multiple layers thereof, or a combination thereof, and may be deposited by chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. An anisotropic etching process such as reactive ion etching, neutral beam etching, or any suitable etching process may then be performed to remove a portion of the spacer layer and form the gate spacer 220, such as Figure 3 shown.

[0067] After forming the gate spacers 220, source / drain regions 213a and 213b may be formed in the fin 202. In some examples, a recess may be etched into the fin 202 using the dummy gate structure 212 as a mask, so that the recess is formed on both sides of the dummy gate structure 212. Epitaxial material may then be epitaxially grown in the recess to form the source / drain regions 213a and 213b. In additional or other embodiments, the source / drain regions 213a and 213b may be formed by implanting dopants into the fin 202 and / or the epitaxial source / drain regions, and the implantation method may use the dummy gate structure 212 as a mask, so that the source / drain regions are formed on both sides of the dummy gate structure 212.

[0068] An interlayer dielectric layer 218 may then be formed on the substrate 200 and the gate spacer 220. In some embodiments, the semiconductor device 201 may also include a contact etch stop layer (not shown) below the interlayer dielectric layer 218 and on the substrate 200 and the gate spacer 220. The contact etch stop layer may include or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or a combination thereof, and may be deposited by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or any other suitable deposition technique. The interlayer dielectric layer 218 may include tetraethoxysilane oxide, silicon oxide, a low dielectric constant material (a material having a dielectric constant lower than that of silicon oxide, such as silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, organosilicate glass, silicon oxycarbide, spin-on glass, spin-on oxide, carbon silicon material, a compound thereof, a composite thereof, the like, or a combination thereof. The deposition method of the interlayer dielectric layer 218 may be spin coating, chemical vapor deposition, flowable chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, or any suitable deposition technique. A chemical mechanical planarization process may then be performed to planarize the interlayer dielectric layer 218 and remove the dummy gate structure 212 to define an upper surface 224 that is substantially coplanar with the upper surface of the dummy gate 208 of the gate structure 212, such as Figure 3 shown.

[0069] In step 106, one or more etching processes are used to remove the dummy gate structure 212. Once the dummy gate structure 212 is removed, a trench 230 is formed to expose at least a portion of the surface 232 of the isolation region 216 (see FIG. Figure 4) and the channel surface of the fin 202. The groove 230 allows a gate structure such as a replacement gate structure to be formed therein. In some examples, an etching process is used to remove the dummy gate 208 exposed by the upper surface 224 of the interlayer dielectric layer 218, and then a different etching process is used to remove the interface dielectric layer 206. The etching process may include suitable wet etching, dry (plasma) etching, and / or other suitable processes. For example, the dry etching process may use a chlorine-containing gas, a fluorine-containing gas, other etching gases, or a combination of the above. The wet etching solution may include ammonium hydroxide, hydrofluoric acid or diluted hydrofluoric acid, deionized water, tetramethylammonium hydroxide, other suitable wet etching solutions, or a combination of the above. Thus, a groove 230 is formed between the gate spacers 220 (where the dummy gate structure 212 is removed), and the channel area of ​​the fin 202 is exposed through the groove 230.

[0070] Figures 5 to 11 It is a cross-sectional view of a semiconductor device at a subsequent manufacturing stage. Figures 5 to 11 The cross-sectional view corresponds to Figure 4 The cross section AA′ is along the fin 202 and is generally perpendicular to the longitudinal direction of the groove 230 .

[0071] Step 108 forms layers for replacement gate structures 212a and 212b for the first device region 250a and the second device region 250b in the trench 230 (i.e., where the dummy gate structure 212 is removed). In the embodiment shown, the layers for replacement gate structures 212a and 212b include an interfacial dielectric layer 240, a gate dielectric layer 242, a cap layer 245, and an optional barrier layer 247, which are sequentially formed in the trench 230 between the gate spacers 220 in the first device region 250a and the second device region 250b, as shown in FIG. Figure 5 As shown. An interfacial dielectric layer 240 is formed on the sidewalls and top of the fin 202 along the channel region, which is defined below the replacement gate structure and between the source / drain regions. For example, the interfacial dielectric layer 240 can be an oxide (such as silicon oxide) formed by thermal or chemical oxidation of the fin 202, a nitride (such as silicon nitride), and / or any suitable dielectric layer formed by chemical vapor deposition, atomic layer deposition, molecular beam deposition, or any other suitable deposition technique.

[0072] The gate dielectric layer 242 may be conformally deposited in the trench 230 on the interfacial dielectric layer 240, on the sidewalls of the gate spacer 220, and on the upper surface of the interlayer dielectric layer 218 and the contact etch stop layer (if used). The gate dielectric layer 242 may include or may be silicon oxide, silicon nitride, a high-k dielectric material, multiple layers thereof, or other suitable dielectric materials. The high-k dielectric material may have a dielectric constant greater than approximately 4.0 (e.g., approximately 7.0) and may include a metal oxide or metal silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, or lead, multiple layers thereof, or combinations thereof. The gate dielectric layer 242 may be deposited by atomic layer deposition, plasma-enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique.

[0073] A capping layer 245 and a barrier layer 247 may then be conformally deposited on the gate dielectric layer 242. The capping layer 245 and barrier layer 247 may comprise tantalum and / or titanium nitrides, silicides, carbonitrides, and / or aluminum nitrides; tungsten nitrides, carbonitrides, and / or carbides; or the like, or a combination thereof, and may be deposited by atomic layer deposition, plasma-enhanced chemical vapor deposition, molecular beam deposition, or another deposition technique. In some examples, the capping layer 245 (e.g., a titanium nitride layer) is conformally formed on the gate dielectric layer 242, and the barrier layer 247 (e.g., a tantalum nitride layer) is conformally formed on the capping layer 245. In some examples, the barrier layer 247 may be a work function adjustment layer or a portion thereof. In some examples, the barrier layer 247 may be omitted. Although the capping layer 245 and the barrier layer 247 are each shown as a single layer in the figures, it should be understood that one or more barrier layers and / or capping layers may be implemented in any desired order, depending on the desired application and threshold voltage of the device.

[0074] After forming the gate dielectric layer 242, the cap layer 245, and the barrier layer 247, a work function adjustment layer 244 may be conformably formed on the barrier layer 247. The work function adjustment layer 224 may be a single layer of material or multiple layers of different materials. Although the work function adjustment layer 244 in the drawings is a single layer, it should be understood that the work function adjustment layer 244 may include one or more layers of work function materials, depending on the application and threshold voltage required by the device. Figure 6 In the illustrated embodiment, the work function layer 244 is a work function layer formed in the first device region 250 a and the second device region 250 b .

[0075] The work function value is related to the material composition of the work function adjustment layer 244. The material of the work function adjustment layer 244 is selected to adjust its work function value so as to achieve the desired threshold voltage of the device to be formed in the respective region. Suitable examples of work function materials for p-type devices include titanium aluminum nitride, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, tungsten carbonitride, other suitable materials with a work function between 4.8 eV and 5.2 eV, or any combination thereof. Suitable examples of work function materials for n-type devices include titanium, aluminum, tantalum aluminum, tantalum aluminum carbide, titanium aluminum carbide, titanium aluminum oxide, hafnium aluminum, titanium aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable materials with a work function between 3.9 eV and 4.3 eV, or any combination thereof. In some embodiments, the work function adjusting layer 244 for a p-type field effect transistor comprises separate layers of titanium aluminum nitride and titanium nitride, while the work function adjusting layer 244 for an n-type field effect transistor comprises separate layers of titanium aluminum carbide and titanium aluminum oxide. In some examples, the work function adjusting layer 244 for an n-type field effect transistor comprises separate layers of titanium aluminum carbide and titanium nitride. Any of the materials described herein can be deposited in any desired order.

[0076] The work function adjustment layer 224 can be deposited by atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam deposition, and / or any other suitable process. In one example described herein, the work function adjustment layer 244 is formed using an atomic layer deposition process at a temperature between approximately 200° C. and 600° C. The thickness of the work function adjustment layer 244 can be varied and adjusted by varying parameters during the atomic layer deposition process, such as the number of deposition cycles, the number of precursor pulses, the pulse frequency, the substrate temperature, the pressure, and the like. It should be understood that a variety of work function adjustment layer deposition, patterning, and etching steps can be performed to produce a multi-threshold voltage device.

[0077] Step 110 is to place the patterned mask structure 248 on the second device region 250b of the semiconductor device 201 of the substrate 200, as shown in FIG. Figure 6 As shown, the patterned mask structure 248 overfills the trench 230 and covers the exposed surface of the second device region 250b. The patterned mask structure protects the field-effect transistors in the second device region 250b from damage during the etching / patterning process and exposes the first device region 250a of the semiconductor device 201 for subsequent processes such as etching. In some embodiments, the patterned mask structure 248 may include a photoresist 254 patterned by a photolithography process and may further include a bottom anti-reflective coating 252 filling the trench 230 in the second device region 250b.

[0078] Step 112 is to perform an etching process to remove the work function adjustment layer 244 not covered by the patterned mask structure 248 from the trench 230 of the field effect transistor in the first device region 250a. Figure 6 As shown. Once the work function adjustment layer 244 is removed, the barrier layer in the trench 230 of the field effect transistor in the first device area 250a is exposed. The etching process may be a wet etching process, which may immerse or soak the substrate 200 in an etching solution. In other embodiments or additional embodiments, a dry process such as a gas phase or plasma process may be used to remove the work function adjustment layer 244 in the first device area 250a. In some embodiments, a combination of wet and dry processes may be used to remove the work function adjustment layer 244 from the desired area. In some examples, the method of removing the work function adjustment layer 244 from the trench 230 uses a wet process, such as immersing or soaking the substrate in an etching solution in a wet tank. In this example, the etching solution may be an alkaline, neutral, or acidic solution with a pH value within a predetermined range, depending on the type of material of the work function adjustment layer 244 to be removed.

[0079] Although the work function adjusting layer 244 is shown as a single layer in the figures, the work function adjusting layer 244 may include multiple layers of different materials, as described above. Therefore, it is understood that in some examples, the etching process 234 removes one or more of the multiple layers in the work function adjusting layer 244, while one or more of the multiple layers in the work function adjusting layer 244 remain after the etching process 234.

[0080] Step 114: After removing the work function adjustment layer 244 from the trench 230 of the field effect transistor in the first device region 250a, the patterned mask structure 248 is removed from the second device region 250b. Figure 7 The patterned mask structure 248 may be removed by any suitable process, such as photoresist stripping or ashing.

[0081] Figure 7 The semiconductor device 201 at an intermediate stage of the manufacturing process is shown, which exposes the barrier layer 247 in the trench 230 of the field effect transistor in the first device area 250a and the work function adjustment layer 244 in the trench 230 of the field effect transistor in the second device area 250b. In the other examples described above, the work function adjustment layer 244 in the trench 230 of the field effect transistor in the first device area 250a and the work function adjustment layer 244 in the trench 230 of the field effect transistor in the second device area 250b are exposed, and the work function adjustment layer 244 in the first device area 250a and the second device area 250b can be different materials. Although Figures 8A to 11The subsequent descriptions may refer to the barrier layer 247 in the trench 230 of the field effect transistor in the first device area 250a and the work function adjustment layer 244 in the trench 230 of the field effect transistor in the second device area 250b; ordinary technicians in this technical field should understand that these descriptions can be implemented in different layers (such as different layers with different materials) of the work function adjustment layer 244 in different device areas (such as the first device area 250a and the second device area 250b).

[0082] Since the work function adjustment layer is exposed to an external environment after deposition, the surface of the barrier layer 247 and / or the surface of the work function adjustment layer 244 may be oxidized. For example, the semiconductor device may be transferred ex-situ to another process chamber (e.g., an etching chamber) in a process system for processing (e.g., removal of the work function adjustment layer). The barrier layer 247 and the work function adjustment layer 244 (which may contain a transition metal such as tantalum, titanium, or the like) tend to have a hydrogen-terminated surface after exposure to an external environment such as the atmosphere. However, compared to a hydroxyl-terminated surface, the barrier layer 247 and the work function adjustment layer 244 having a hydrogen-terminated surface are less reactive toward a subsequent atomic layer deposition metal liner layer, thereby affecting the growth rate of the subsequent atomic layer deposition metal liner layer.

[0083] Various embodiments include an in-situ pretreatment or pre-deposition process that includes immersing a barrier layer and / or work function tuning layer in a reactant to provide a treated surface for the barrier layer and / or work function tuning layer prior to depositing a metal liner layer using an atomic layer deposition process. The treated surface has a monolayer of reactants formed thereon. The oxide monolayer oxidizes upon exposure to an external environment (e.g., the atmosphere) or an oxidizing agent, capping the reactant monolayer with hydroxyl groups that are reactive with subsequent atomic layer deposition used to form the metal liner layer. Due to the pretreatment process, the work function of the subsequently deposited metal liner layer can be independent of the quality of the underlying surface (e.g., the underlying work function tuning layer having an oxidized surface layer). Furthermore, the growth rate of the subsequently deposited metal liner layer is independent of variations in the substrate surface (e.g., the surface of the barrier layer or work function layer) that may affect the growth rate and thickness of the subsequently deposited metal liner layer. The pretreated barrier layer and / or work function tuning layer provides a consistent treated starting surface for subsequent atomic layer deposition of the metal liner layer. In this way, the loading effect of subsequent atomic layer deposition caused by substrate-related growth can be alleviated.

[0084] Step 116 performs a pretreatment process 253 to immerse the respective layers exposed in the trenches 230 of the field effect transistor in the first device region 250a and the second device region 250b in a reactant. For the exposed layers, the pretreatment process 253 provides treated surfaces 261 and 263 having a single layer 251 of reactants formed thereon, such as Figure 8A and Figure 8BAs shown. When the monolayer of reactants is later exposed to an environment such as air or an oxidant, the monolayer of reactants is oxidized to form a hydroxyl-terminated surface. The term "immersion" may refer to introducing a precursor into a chamber and closing the inlet and exhaust ports for a predetermined period of time (e.g., 2 seconds to 5 minutes) to allow the substrate surface to absorb or react with the precursor. The term "pretreatment" may be interchangeable with the terms "surface treatment," "pre-deposition treatment," "pre-deposition immersion," "immersion treatment," or "pre-immersion."

[0085] In various embodiments, the reactants include aluminum-based precursors or silicon-based precursors. Exemplary aluminum-based precursors may include, but are not limited to, trimethylaluminum, triethylaluminum, dimethylethylamine alane, dimethylaluminum hydride, tri-tert-butylaluminum, triisobutylaluminum, trimethylamine alane, triethylamine alane, any suitable aluminum-containing organometallic precursor, or any combination thereof. Exemplary silicon-based precursors may include, but are not limited to, silanes or organosilanes. Silanes may include silane, disilane, trisilane, butasilane, or any combination thereof. The organosilane may include a compound having the formula R y Si x H (2x+2 -y), wherein R is independently methyl, ethyl, propyl, or butyl. The organosilane may be methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, tris(dimethylamino)silane, or any combination thereof. In some examples, the silicon-based precursor may be carbon-free.

[0086] On silicon-based substrates and aluminum-based substrates, the thickness of the metal liner layer (e.g., titanium nitride) deposited after 20 ALD cycles, 40 ALD cycles, or 90 ALD cycles is substantially the same, so aluminum-based precursors and silicon-based precursors can be selected. Thus, by providing or passivating the surface of different layers of the field effect transistor with a single layer 251 of aluminum or silicon, the metal liner layer (e.g., titanium nitride) deposited by subsequent ALD can be formed at the same growth rate (and therefore have the same thickness).

[0087] The pretreatment process 253 may be performed using a chemical vapor deposition process such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced cyclic chemical vapor deposition, pulsed chemical vapor deposition, or any other suitable process such as an implantation process. In some embodiments, the pretreatment process is performed using an atomic layer deposition immersion process. During the atomic layer deposition immersion process, the semiconductor device 201 is heated to a temperature above the condensation temperature of the reactant (e.g., an aluminum-based or silicon-based precursor) but below the thermal decomposition temperature of the reactant. The semiconductor device 201 is then exposed, immersed, or soaked in the reactant, causing the surface of the layer exposed in the trench 230 of the field effect transistor in the first device area 250a and the trench 230 of the field effect transistor in the second device area 250b to absorb the reactant and react with the reactant. The reactant forms a monolayer 251 on the treated surfaces 261 and 263. The semiconductor device 201 is then exposed to the atmosphere or an oxidant to spontaneously form a native oxide (e.g., aluminum oxide or silicon oxide) on the monolayer of the reactant. Figure 8A and Figure 8B Insets 270 and 272 are partial enlarged views of a monolayer 251 of a reactant having hydroxyl end caps 265, respectively, formed on the barrier layer 247 and the work function adjustment layer 244. Figure 8A and Figure 8B In the examples shown, R refers to an aluminum or silicon containing species.

[0088] In some examples, an atomic layer deposition (ALD) immersion process is used to form a monolayer of aluminum oxide on the barrier layer 247 of the field effect transistor in the first device region 250a and on the work function adjustment layer 244 of the field effect transistor in the second device region 250b. The ALD immersion process is initially performed by setting the temperature of the semiconductor device 201 in the process chamber to between about 20°C and about 130°C, such as between about 60°C and about 100°C. An aluminum-based precursor (such as trimethylaluminum or triethylaluminum as described above) can be introduced into the process chamber to immerse or soak the semiconductor device 201 in the aluminum-based precursor. The flow rate of the trimethylaluminum or triethylaluminum into the process chamber can be between about 50 sccm and about 8000 sccm, such as between about 300 sccm and about 5000 sccm, for example, between about 500 sccm and about 2000 sccm. The semiconductor device 201 may be immersed or soaked in trimethylaluminum or triethylaluminum for a period of time ranging from about 1 second to about 300 seconds to form a monolayer of aluminum on the surface of the barrier layer 247 and the work function adjustment layer 244. The time of immersion may be adjusted to obtain a desired amount of aluminum oxide on and / or in the exposed layer. In some examples, the semiconductor device 201 is immersed in trimethylaluminum or triethylaluminum for a period of time ranging from about 10 seconds to about 60 seconds. In some examples, the semiconductor device 201 is immersed in trimethylaluminum or triethylaluminum for a period of time ranging from about 5 seconds to about 20 seconds. In some examples, the semiconductor device 201 is immersed in trimethylaluminum or triethylaluminum for a period of time ranging from about 30 seconds to about 120 seconds. In some embodiments, the semiconductor device 201 is immersed in triethylaluminum at a flow rate of 600 sccm for a period of time ranging from about 30 seconds to about 80 seconds. The thickness of the monolayer of aluminum may be between about to about between, for example, between to about between, for example, between about to about After trimethylaluminum or triethylaluminum is adsorbed on the surface of barrier layer 247 or the surface of work function adjustment layer 244, the atomic layer deposition control system interrupts the flow of trimethylaluminum or triethylaluminum to the process chamber. Semiconductor device 201 is then transferred to another process chamber for deposition of subsequent metal layers. As semiconductor device 201 leaves the process chamber, vacuum is broken and an oxidant is introduced into the aluminum monolayer, causing the aluminum monolayer to transform into an aluminum oxide monolayer.

[0089] In one example, a monolayer of silicon oxide is formed on the barrier layer 247 of the field effect transistor in the first device region 250a and on the work function adjustment layer 244 of the field effect transistor in the second device region 250b. The formation method can be an atomic layer deposition immersion process. The atomic layer deposition immersion process can initially set the temperature of the semiconductor device 201 in the process chamber to between about 20°C and about 130°C, such as between about 60°C and about 100°C. A silicon-containing precursor, such as the aforementioned silane or disilane, can be introduced into the process chamber, thereby immersing or bathing the semiconductor device 201 in the silicon-containing precursor. The flow rate of the silane or disilane into the process chamber is between about 50 sccm and about 8000 sccm, such as between about 300 sccm and about 5000 sccm, or between about 500 sccm and about 2000 sccm. The semiconductor device 201 may be immersed or soaked in silane or disilane for between about 1 second and about 300 seconds to form a monolayer of silicon on the surface of the barrier layer 247 and the work function adjustment layer 244. In some examples, the semiconductor device 201 is immersed in silane or disilane for between about 10 seconds and about 60 seconds. In some examples, the semiconductor device 201 is immersed in silane or disilane for between about 5 seconds and about 20 seconds. In some examples, the semiconductor device 201 is immersed in silane or disilane for between about 30 seconds and about 120 seconds. In one embodiment, the semiconductor device is immersed in silane for between about 15 seconds and about 120 seconds. In another embodiment, the semiconductor device 201 is immersed in disilane for between about 15 seconds and about 60 seconds. The thickness of the monolayer of silicon may be between about to about between, for example, between to about between, or for example between about to about After silane or disilane is absorbed onto the surface of barrier layer 247 and the surface of work function adjustment layer 244, the atomic layer deposition control system interrupts the flow of silane or disilane to the process chamber. Semiconductor device 201 is then transferred to another process chamber for deposition of subsequent metal layers. Upon exiting the process chamber, vacuum is broken, directing an oxidant toward the silicon monolayer, converting the silicon monolayer into a silicon oxide monolayer.

[0090] In other or additional embodiments, the atomic layer deposition process may utilize two or more reactants to produce aluminum oxide or silicon oxide. In this example, the semiconductor device 201 is then exposed to pulses of the two or more reactants alternately to perform a pretreatment process, with the pulses separated by steps of evacuating and / or purging the process chamber.

[0091] In some examples, after a monolayer of a first reactant (e.g., an aluminum-based precursor or a silicon-based precursor) is absorbed on the exposed surface of each layer in the trenches of the field-effect transistors in the first device region 250a and the second device region 250b, the semiconductor device 201 is exposed to a second reactant (e.g., vapor-phase water or other oxidizing agent). Upon exposure to the second reactant, available molecules of the first reactant absorb and react with the second reactant to form a monolayer of aluminum oxide or silicon oxide. This process can be repeated to form a monolayer on the surface layer until the desired thickness is achieved.

[0092] In some examples, an atomic layer deposition process is used to form a monolayer of aluminum oxide on the barrier layer 247 of the field-effect transistor in the first device region 250a and on the work function adjustment layer 244 of the field-effect transistor in the second device region 250b. The atomic layer deposition process is initially performed by setting the temperature of the semiconductor device 201 in the process chamber to between about 20°C and about 500°C, such as between about 250°C and about 500°C. A first reactant, such as trimethylaluminum or triethylaluminum, is pulsed into the process chamber to immerse or soak the semiconductor device 201 in the trimethylaluminum or triethylaluminum. The flow rate of the trimethylaluminum or triethylaluminum into the process chamber is between about 10 sccm and about 6000 sccm, such as between about 100 sccm and about 3000 sccm, for example, between about 100 sccm and about 3000 sccm. The immersion time for forming the aluminum layer on the surfaces of the barrier layer 247 and the work function adjustment layer 244 can be between about 1 second and about 300 seconds. For example, the immersion time may be between about 1 second and about 180 seconds. In some examples, the immersion time may be between about 5 seconds and about 120 seconds. In some examples, the immersion time may be between about 30 seconds and about 60 seconds. After pulsing the first reactant, vacuum is evacuated and / or a purge gas such as an inert gas is delivered. The inert gas may be any suitable inert gas such as argon, helium, neon, or any combination thereof. The flow rate of the inert gas into the process chamber may be between about 100 sccm and about 10,000 sccm, for example, between about 1,000 sccm and about 6,000 sccm. The vacuum and / or purge gas may remove any residual trimethylaluminum, triethylaluminum, or byproducts from the process chamber. After vacuuming and / or purging, a second reactant such as water, ozone, hydrogen peroxide, or any suitable oxidant is pulsed into the process chamber. One or more second reactant molecules may bond to the aluminum layer to form a monolayer-scale aluminum oxide layer. The flow rate of the second reactant into the process chamber may be between about 10 sccm and about 8000 sccm, such as between about 300 sccm and about 5000 sccm, or, for example, between about 500 sccm and about 2000 sccm. The process chamber may be evacuated and / or purged again to remove byproducts from the process chamber. These steps may be repeated, such as in a continuous cycle, until the aluminum oxide on the surfaces of the barrier layer 247 and the work function adjustment layer 244 accumulates to a desired thickness. For example, the thickness of the aluminum oxide may be between about to about between, for example, between to about between 2 and 30 Å, depending on the atomic layer deposition cycle.

[0093] In some examples, an atomic layer deposition process is used to form a monolayer of silicon oxide on the barrier layer 247 of the field-effect transistor in the first device region 250a and on the work function adjustment layer 244 of the field-effect transistor in the second device region 250b. The atomic layer deposition process is initially performed by setting the temperature of the semiconductor device 201 in the process chamber to between approximately 20°C and approximately 500°C, such as between approximately 200°C and approximately 500°C. A first reactant, such as the aforementioned silane or disilane, is pulsed into the process chamber, immersing or soaking the semiconductor device 201 in the silane or disilane. The flow rate of the silane or disilane into the process chamber is between approximately 10 sccm and approximately 3000 sccm, such as between approximately 300 sccm and approximately 1000 sccm. The pulse duration for forming the silicon layer on the surfaces of the barrier layer 247 and the work function adjustment layer 244 can be between approximately 1 second and approximately 300 seconds. For example, the pulse duration can be between approximately 10 seconds and approximately 60 seconds. In some examples, the pulse time may be between about 5 seconds and about 90 seconds. In some examples, the pulse time may be between about 30 seconds and about 120 seconds. After the first reactant is pulsed, vacuum is evacuated and / or a purge gas such as an inert gas is delivered. The inert gas may be any suitable inert gas such as argon, helium, neon, or any combination thereof. The flow rate of the inert gas into the process chamber may be between about 100 sccm and about 6000 sccm, for example, between about 1000 sccm and about 3000 sccm. The vacuum and / or purge gas can remove any residual silane, disilane, or by-products from the process chamber. After vacuum and / or purge, a second reactant such as water, ozone, hydrogen peroxide, or any suitable oxidant is delivered to the process chamber in a pulsed manner. One or more second reactant molecules can bond to the silicon layer to form a monolayer-scale silicon oxide layer. The pulse time of the second reactant may be between about 1 second and about 300 seconds. For example, the pulse time may be between about 10 seconds and about 60 seconds. In some examples, the pulse time may be between about 5 seconds and about 90 seconds. In some examples, the pulse time may be between about 30 seconds and about 120 seconds. The flow rate of the second reactant into the process chamber may be between about 10 sccm and about 8000 sccm, such as between about 300 sccm and about 5000 sccm, or for example between about 500 sccm and about 2000 sccm. Vacuuming and / or purging may be performed again to remove residual second reactant and byproducts from the process chamber. These steps may be repeated as a continuous cycle until the silicon oxide on the surface of the barrier layer 247 and the work function adjustment layer 244 accumulates to a desired thickness. For example, the thickness of the silicon oxide may be between about to about between, for example, between to about In between, depending on the atomic layer deposition cycle.

[0094] In this example, after the pre-treatment process 253, the field effect transistor is covered or passivated with a single layer of aluminum oxide or silicon oxide, and the layers exposed to the pre-treatment process 253 (such as the barrier layer 247 and the work function adjustment layer 244). The single layer of aluminum oxide or silicon oxide is thin (for example, less than ), thereby minimizing the impact on the gap filling performance and / or threshold voltage of other layers in the trench 230. When the semiconductor device 201 leaves the process chamber for subsequent atomic layer deposition of a metal layer, the monolayer of aluminum oxide or silicon oxide is exposed to air, which can further terminate the primary dangling bonds with hydroxyl groups, which can react significantly during the subsequent atomic layer deposition to form a metal liner layer. Therefore, the growth rate of the subsequently deposited metal liner layer can be independent of changes in the substrate surface (such as the barrier layer 247 or the work function adjustment layer 244). Conversely, the pre-treated barrier layer and the work function adjustment layer can provide the same surface for the subsequent atomic layer deposition of the metal liner layer. In this way, the loading effect of the subsequent atomic layer deposition caused by substrate-related growth can be alleviated.

[0095] In step 118, after treating the surfaces of the exposed layers (e.g., the barrier layer in the trench 230 of the field effect transistor in the first device region 250a and the work function adjustment layer 244 in the trench 230 of the field effect transistor in the second device region 250b), a metal liner layer 255 is conformally deposited in the trench 230 (e.g., on the treated surface 261 of the barrier layer 247 and the treated surface 263 of the work function adjustment layer 244). Figure 9 As shown. For example, the metal liner layer 255 can be made of a material similar to that of the cap layer 245. For example, the metal liner layer 255 can be or include tantalum and / or titanium nitrides, silicon nitrides, carbonitrides, and / or aluminum nitrides; tungsten nitrides, carbonitrides, and / or carbides; the like; or combinations thereof. In some examples, the metal liner layer 255 is titanium nitride. In some examples, the metal liner layer 255 is tantalum nitride. In some examples, the metal liner layer 255 is titanium oxynitride. In some examples, the metal liner layer 255 is tantalum oxynitride. Although the metal liner layer 255 is shown as a single layer in the figures, it is contemplated that the metal liner layer 255 may include one or more of the other layers described herein. The metal liner layer 255 and any other layers deposited on the treated surfaces 261 and 263 may also be used to set the work function value of the gate metal 257. In some examples, the metal liner layer 255 is deposited by atomic layer deposition. In other examples, the metal liner layer 255 can be deposited by plasma enhanced chemical vapor deposition, molecular beam deposition, or any other deposition technique.

[0096] In some embodiments, when forming the metal liner layer 255 , oxygen in the single layer 251 may react with a precursor used to form the metal liner layer 255 to form a mixed layer between the metal liner layer 255 and the single layer 251 (eg, aluminum oxide or silicon oxide).

[0097] Due to the pretreatment process 253, the growth rate of the metal liner layer 255 formed by atomic layer deposition on the barrier layer 247 and the work function adjustment layer 244 is almost the same because the field effect transistors in the first device region 250a and the field effect transistors in the second device region 250b have the same starting surface (e.g., treated surfaces 261 and 263 having a single layer of aluminum oxide or silicon oxide). As a result, the metal liner layer 255 can have a consistent thickness on the barrier layer 247 and the work function adjustment layer 244. In addition, because the single layer of aluminum oxide or silicon oxide has hydroxyl termini 265, it can promote reaction with one or more precursors used in the atomic layer deposition to form the metal liner layer 255, thereby improving the growth time of the metal liner layer 255 on the barrier layer 247 and the work function adjustment layer 244 during atomic layer deposition. For example, immersing a barrier layer, such as tantalum nitride, in triethylaluminum (at a flow rate of 600 sccm) for 15 seconds increased the thickness of a metal liner layer, such as titanium nitride, by approximately 46% compared to a barrier layer not immersed in triethylaluminum. Immersing a barrier layer, such as tantalum nitride, in triethylaluminum (at a flow rate of 600 sccm) for 10 seconds increased the thickness of a metal liner layer, such as titanium nitride, by approximately 40% compared to a barrier layer not immersed in triethylaluminum. Immersing a barrier layer, such as tantalum nitride, in triethylaluminum (at a flow rate of 600 sccm) for 5 seconds increased the thickness of a metal liner layer, such as titanium nitride, by approximately 32% compared to a barrier layer not immersed in triethylaluminum. Similar growth patterns were observed on the work function adjustment layer. These observations indicate that the use of an aluminum-based pre-immersion process enhances the growth of a metal liner layer during atomic layer deposition on treated surfaces 261 and 263. Therefore, in some embodiments, after depositing the metal liner layer 255 , the metal liner layer 255 is located on a single layer of aluminum oxide or silicon oxide.

[0098] In step 120, after forming a metal liner layer 255 on the processed surfaces 261 and 263, a gate metal 257 is formed on the metal liner layer 255 and filled into the trench 230 defined in the interlayer dielectric layer 218 to replace the gate structures 212a and 212b. The gate metal 257 may extend beyond the trench 230 to a predetermined thickness, such as Figure 10As shown. In various embodiments, gate metal 257 may be or include a conductive material such as aluminum, copper, titanium, tantalum, aluminum titanium, titanium aluminum nitride, titanium nitride, tantalum nitride, aluminum tantalum, nickel silicide, cobalt silicide, tantalum carbide, tantalum silicon nitride, tungsten, tungsten nitride, molybdenum nitride, platinum, ruthenium, other suitable conductive materials, or combinations thereof. In some examples, gate metal 257 is tungsten. Gate metal 257 may be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, electroplating, atomic layer deposition, and / or other suitable processes.

[0099] Step 122 may include performing a planarization process (e.g., chemical mechanical planarization) to planarize the upper surface of the semiconductor device 201. The planarization process may remove the gate metal 257, the metal liner layer 255, the single layer 251, the barrier layer 247, the cap layer 245, the work function adjustment layer 244, and the gate dielectric layer 242 above the upper surface of the interlayer dielectric layer 218. Figure 11 Once the planarization process is completed, the upper surface 259 of the interlayer dielectric layer 218 is exposed.

[0100] The semiconductor device 201 fabricated according to flowchart 100 may be subjected to subsequent processing to form various structures and regions. For example, subsequent processing may form multiple layers of various contacts / vias / lines and interconnect structures (e.g., metal layers and interlayer or intermetallic dielectric layers) on substrate 200 including semiconductor device 201, which are configured to connect various structures to form functional circuits (which may include one or more devices such as one or more semiconductor devices 201). The various interconnect structures may be made of various conductive materials, such as copper, tungsten, and / or silicide. In one example, a damascene process and / or a dual damascene process may be used to form a copper-related multilayer interconnect structure. Furthermore, additional processing steps may be performed before, during, or after flowchart 100, and some of the aforementioned steps may be replaced or omitted depending on the application.

[0101] The various embodiments described above can alleviate substrate-related loading by pre-treating the exposed surface of the barrier layer and / or work function adjustment layer to provide a common starting surface for subsequent atomic layer deposition. The substrate-dependent growth characteristics of the work function layer can be used to adjust the threshold voltage of an n-type field effect transistor (NFET) or p-type field effect transistor (PFET) device to achieve multiple threshold voltages. In some multi-threshold voltage metal gates, the semiconductor device may include two or more device regions, each of which may include a p-type device or an n-type device. Figure 12A simplified semiconductor device 1200 is shown at an intermediate stage of fabrication, along with portions of gate structures in three device regions 1202, 1204, and 1206. Each device region includes an n-type device. Each n-type device in device regions 1202, 1204, and 1206 has a work function adjusting layer 1208 on a gate dielectric layer 1210. A metal layer 1212, such as a work function adjusting layer for p-type devices (e.g., titanium nitride, tantalum nitride, titanium aluminum nitride, or titanium silicon nitride), is typically formed between the work function adjusting layer 1208 and the gate dielectric layer 1210 and has varying thicknesses to influence the work function of the metal gate. Figure 12 In the example shown, metal layer 1212 in device region 1202 has a first thickness T1; metal layer 1212 in device region 1204 has a second thickness T2, which is greater than first thickness T1; and metal layer 1212 in device region 1206 has a third thickness T3, which is greater than second thickness T2. Because the work function of a metal gate depends in part on the conductivity of metal layer 1212, providing the same metal layer 1212 with different thicknesses can effectively vary and differentiate the work functions of different metal gates in device regions 1202, 1204, and 1206. However, as the size of FinFET devices decreases, using different film thicknesses to adjust multiple threshold voltages may be impractical because the space available for metal layers may be reduced or limited.

[0102] Various embodiments described herein adjust multiple threshold voltages for n-type or p-type devices without forming a multilayer film stack between a work function tuning layer and a gate dielectric layer. Instead, by providing different metal layers between the work function tuning layer and the gate dielectric layer for n-type or p-type devices, the metal gate work function can be adjusted for different device regions. Because the growth behavior of some work function materials is highly substrate-dependent, the composition and thickness of the work function tuning layer in different device regions can be modified by varying the metal layers underlying the work function tuning layer. Figure 13 A simplified semiconductor device 1300 is shown at an intermediate stage of the process in some embodiments. The semiconductor device 1300 may be a multi-threshold voltage integrated circuit device, such as the semiconductor device 201 described above. For clarity, only a portion of the gate structures shown in illustrations 1360, 1362, and 1364 will be discussed. Other elements of the semiconductor device 1300, such as the source / drain regions 213a, 213b, and 213c, the gate spacer 220, the isolation region 216, the fin 202, and the interlayer dielectric layer 218, etc., may be referred to in conjunction with FIG. Figure 5 The semiconductor device 201 described above.

[0103] In one embodiment, semiconductor device 1300 has three device regions 1302, 1304, and 1306, each of which includes n-type devices. Similar to semiconductor device 201 described above, the n-type devices in device regions 1302, 1304, and 1306 can be n-type low threshold voltage devices, n-type standard threshold voltage devices, or n-type high threshold voltage devices, depending on the application. While the devices described here are n-type devices, it should be understood that the concepts can also be applied to p-type devices, such as p-type fin field-effect transistor devices. Each n-type device in device regions 1302, 1304, and 1306 has a work function adjustment layer 1308 on a gate dielectric layer 1310. Similar to the work function adjustment layer 244 described above, suitable examples of the work function adjustment layer 1308 may include titanium, aluminum, tantalum aluminum, tantalum aluminum carbide, titanium aluminum carbide, titanium aluminum oxide, hafnium aluminum, titanium aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, or other suitable materials with a work function between 3.9 eV and 4.3 eV. In one embodiment, the work function adjustment layer 1308 is titanium aluminum carbide. Similar to the gate dielectric layer 242, the gate dielectric layer 1310 may include or be silicon oxide, silicon nitride, a high-k dielectric material, multiple layers thereof, or other suitable dielectric materials. In some embodiments, the gate dielectric layer 1310 may be a metal oxide or metal silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, or lead, multiple layers thereof, or combinations thereof.

[0104] A first metal layer 1312, a second metal layer 1314, and a third metal layer 1316 are provided between the gate dielectric layer 1310 and the work function adjustment layer 1308 in the respective device regions 1302, 1304, and 1306 to adjust the work function value used by the metal gate. The first metal layer 1312, the second metal layer 1314, and the third metal layer 1316 can be titanium nitride, tantalum nitride, titanium aluminum nitride, titanium silicon nitride, a composite containing metal nitrides (such as titanium nitride-silicon nitride), or any suitable metal such as the metals used for the cap layer 245 and the barrier layer 247 described above. In one embodiment, the thickness T4 of the first metal layer 1312, the thickness T5 of the second metal layer 1314, and the thickness T6 of the third metal layer 1316 are substantially the same, for example, about In some examples, thickness T4, thickness T5, and thickness T6 may each be between about to about between, for example, between to about Between. Figure 12Depending on the semiconductor device 1200 (forming the same metal layer 1212 of different thicknesses for adjusting the multi-threshold voltage of an n-type field-effect transistor), the chemical structures of the first metal layer 1312, the second metal layer 1314, and the third metal layer 1316 may differ. In one embodiment, the first metal layer 1312 in the device region 1302 is titanium nitride, the second metal layer 1314 in the device region 1304 is tantalum nitride, and the third metal layer 1316 in the device region 1306 is titanium nitride-silicon nitride. Because the growth behavior of the work function adjustment layer 1308, such as titanium aluminum carbide, is highly substrate-dependent (i.e., the composition and thickness of the titanium aluminum carbide are substrate-dependent), using different metal layers in the respective device regions 1302, 1304, and 1306 results in different titanium aluminum carbide layer thicknesses and properties, thereby changing the work function value of the work function adjustment layer 1308. In some embodiments, the difference between the thickness of titanium aluminum carbide on titanium nitride-silicon nitride and the thickness of titanium aluminum carbide on tantalum nitride may be between about 12% and about 15%, while the difference between the thickness of titanium aluminum carbide on titanium nitride and the thickness of titanium aluminum carbide on tantalum nitride may be between about 28% and about 39%.

[0105] 14A to 14C Shown is the X-ray photoelectron spectrum of the main components of titanium aluminum carbide deposited on titanium nitride-silicon nitride, tantalum nitride, and titanium nitride substrates. In the accompanying figure, the measured photoelectron intensity is marked in arbitrary units (AU), which has a functional relationship with the binding energy. X-ray photoelectron spectroscopy uses X-rays to eject electrons from atomic nuclei present on the surface of titanium aluminum carbide. The kinetic energy of these electrons is measured to obtain the electron binding energy of the atoms of interest (such as aluminum, carbon, and silicon). The temperature at which titanium aluminum carbide is deposited on titanium nitride-silicon nitride, tantalum nitride, and titanium nitride substrates is between about 350°C and about 420°C, and the pressure of the deposition chamber is between about 1 Torr and about 20 Torr. Figure 14A The aluminum spectrum (Al, 2p) in the sample measures the peak of electrons emitted from the 2p shell of aluminum atoms. Titanium aluminum carbide deposited on titanium nitride exhibits the highest aluminum spectrum signal (subtracting a background spectrum of approximately 1.8 from the measured spectrum of approximately 4.7), while titanium aluminum carbide deposited on tantalum nitride and titanium aluminum carbide deposited on titanium nitride-silicon nitride exhibit lower aluminum spectrum signals. This indicates that more aluminum is measured in the titanium aluminum carbide when deposited on the titanium nitride substrate. Therefore, titanium aluminum carbide on a titanium nitride substrate may have more positive charge carriers than titanium aluminum carbide on tantalum nitride or titanium nitride-silicon nitride due to the higher aluminum concentration in the titanium aluminum carbide.

[0106] right Figure 14BThe carbon spectrum (C, 1s) in the TEM image measures the peak of electrons emitted from the 1s shell of carbon atoms. Titanium aluminum carbide deposited on titanium nitride shows the highest carbon spectrum signal (subtracting a background spectrum of approximately 4 from the measured spectrum of approximately 7.3), while titanium aluminum carbide deposited on tantalum nitride and titanium aluminum carbide deposited on titanium nitride-silicon nitride show lower carbon spectrum signals, indicating that more carbon is measured in titanium aluminum carbide when deposited on titanium nitride.

[0107] right Figure 14C The silicon spectrum (Si, 2p) in the tantalum nitride (TAN) layer measures the peak of electrons emitted from the 2p shell of silicon atoms. Titanium aluminum carbide deposited on tantalum nitride exhibits the highest silicon spectrum signal (subtracting a background spectrum of approximately 2.7 from the measured spectrum of approximately 4.5), while titanium aluminum carbide deposited on titanium nitride exhibits the lowest silicon spectrum signal. This indicates that more silicon is measured in the TAN layer when deposited on TAN. The higher silicon intensity in the TAN layer indicates that the TAN layer on TAN is thinner than the TAN layer on titanium nitride, as the silicon signal from the underlying fin (e.g., fin 202) is easier to detect.

[0108] 14A to 14C X-ray photoelectron spectroscopy indicates that different substrates produce titanium aluminum carbide with varying film thicknesses and properties. Therefore, using different metal layers in the device regions 1302, 1304, and 1306 can form titanium aluminum carbide with varying film thicknesses and properties. Different titanium aluminum carbide films on different substrates can provide different n-type work functions for adjusting multiple threshold voltages without the need for stacking multiple metal layers. This provides more space for the device's metal gate or other suitable work function adjustment layers.

[0109] The process of forming different metal layers in respective device regions 1302, 1304, and 1306 is as follows. After forming a gate dielectric layer 1310 in the trenches 1301, 1303, and 1305 between the gate spacers in the device regions 1302, 1304, and 1306, a first metal layer 1312, such as titanium nitride, is formed on the gate dielectric layer 1310 in the trenches 1301, 1303, and 1305 in the device regions 1302, 1304, and 1306. A patterned mask (such as the patterned mask structure 248 described above) can then be positioned over the device region 1302 of the semiconductor device 1300. The patterned mask overfills the trenches and covers the exposed surface of the device region 1302, exposing the device regions 1304 and 1306 for subsequent processes, such as etching. One or more etching processes may then be performed to selectively remove the first metal layer 1312 from the trenches in the device regions 1304 and 1306 , while retaining the first metal layer 1312 in the trenches in the device region 1302 .

[0110] Next, a second metal layer 1314, such as tantalum nitride, is formed in the trenches of device regions 1302, 1304, and 1306. Similarly, a patterned mask is deposited over device region 1304 of semiconductor device 1300. One or more etching processes may then be performed to selectively remove second metal layer 1314 from the trenches of device regions 1302 and 1306, while retaining second metal layer 1314 in the trenches of device region 1304. A third metal layer 1316, such as titanium nitride-silicon nitride, is then formed in the trenches of device regions 1302, 1304, and 1306. A patterned mask is deposited over device region 1306 of semiconductor device 1300. Next, one or more etching processes may be performed to selectively remove third metal layer 1316 from the trenches of device regions 1302 and 1304, while retaining third metal layer 1316 in the trenches of device region 1306. In this manner, a first metal layer 1312 (e.g., titanium nitride) can be formed in the device region 1302 between the gate dielectric layer 1310 and the work function adjustment layer 1308, a second metal layer 1314 (e.g., tantalum nitride) can be formed in the device region 1304 between the gate dielectric layer 1310 and the work function adjustment layer 1308, and a third metal layer 1316 (e.g., titanium nitride-silicon nitride) can be formed in the device region 1306 between the gate dielectric layer 1310 and the work function adjustment layer 1308. The above method can vary the composition and thickness of the work function adjustment layer 1308 (e.g., titanium aluminum carbide) to adjust the multi-threshold voltage as needed.

[0111] After forming the work function adjustment layer 1308 on the first metal layer 1312, the second metal layer 1314, and the third metal layer 1316 in the respective device regions 1302, 1304, and 1306, a process is performed on the semiconductor device 1300 to form a metal liner layer and a gate metal, such as with Figures 9 to 11 The semiconductor device 1300 may be subjected to subsequent processing to form various structures or regions required for a functional integrated device, such as multiple layers of contacts / vias / lines and interconnect structures.

[0112] Various embodiments described herein may provide various advantages. It should be understood that not all advantages are necessarily described herein, that any embodiment need not possess a particular advantage, and that other embodiments may provide different advantages. For example, embodiments described herein include methods and structures associated with a pre-deposition treatment process, including immersing a specific layer (e.g., a work function adjustment layer, a barrier layer, a capping layer, other suitable metal layer, or the like) deposited in a trench of a field effect transistor (e.g., for a standard threshold voltage device) or a trench of another field effect transistor (e.g., for an ultra-low threshold voltage device) in a reactant to provide a treated surface, followed by deposition of a subsequent metal liner layer on the treated surface of the specific layer. In various embodiments, the pre-deposition treatment process forms a monolayer of the reactant on the treated surface. The monolayer of the reactant can be exposed to an external environment or any suitable oxidant for oxidation. Other advantages include providing different metal layers between the work function adjustment layer and the gate dielectric layer to adjust multiple threshold voltages for use in n-type or p-type devices, which can be used in different device regions of a field effect transistor, such as an n-type field effect transistor or a p-type field effect transistor. Different metal layers affect the composition and thickness of the work function tuning layer, thereby varying the work function of the layer deposited thereon. Differentiating the work function tuning layer (e.g., titanium aluminum carbide) on different substrates can provide different n-type work functions for multi-threshold voltage adjustment without the need for stacking multiple metal layers. This allows for more space to accommodate the device's metal gate or other suitable work function tuning layer.

[0113] In one embodiment, a method for semiconductor processing is provided. The method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form a plurality of monolayers on the first metal-containing layer and the second metal-containing layer, respectively, wherein the first device and the second device are located on a substrate, the first device includes a first gate structure including the first metal-containing layer, the second device includes a second gate structure including the second metal-containing layer, and the first metal-containing layer and the second metal-containing layer are different. The method also includes exposing the monolayers on the first metal-containing layer and the second metal-containing layer to an oxidant to provide a hydroxyl-terminated surface for the monolayers on the first metal-containing layer and the second metal-containing layer; and forming a third metal-containing layer on the hydroxyl-terminated surface of the monolayers on the first metal-containing layer and the second metal-containing layer.

[0114] In some embodiments, the reactant comprises an aluminum-based precursor, and the aluminum-based precursor comprises trimethylaluminum, triethylaluminum, dimethylethylaminoalane, dimethylaluminum hydride, tri-tert-butylaluminum, triisobutylaluminum, trimethylaminoalane, triethylaminoalane, an aluminum-containing organometallic precursor, or a combination thereof.

[0115] In some embodiments, the single layer on the first metal-containing layer and the second metal-containing layer is aluminum oxide.

[0116] In some embodiments, the first device and the second device are different types of devices, including an n-type ultra-low threshold voltage device, an n-type low threshold voltage device, an n-type standard voltage device, an n-type high threshold voltage device, a p-type ultra-low threshold voltage device, a p-type low threshold voltage device, a p-type standard threshold voltage device, or a p-type high threshold voltage device.

[0117] In some embodiments, the first metal-containing layer is tantalum nitride and the third metal-containing layer is titanium nitride.

[0118] In some embodiments, the second metal-containing layer includes titanium aluminum carbide or titanium aluminum oxide.

[0119] In some embodiments, the reactant includes a silicon-containing precursor, and the silicon-containing precursor includes silane, disilane, trisilane, butasilane, or combinations thereof.

[0120] In some embodiments, the single layer on the first metal-containing layer and the second metal-containing layer is silicon oxide.

[0121] In some embodiments, the first metal-containing layer and the single layer on the second metal-containing layer are formed by an atomic layer deposition process, and the third metal-containing layer is formed by an atomic layer deposition process.

[0122] Another embodiment provides a semiconductor device. The semiconductor device includes a substrate; and a first device having a first gate structure on the substrate. The first gate structure includes a gate dielectric layer on the substrate; a barrier layer on the gate dielectric layer; a single layer of aluminum oxide or silicon oxide on the barrier layer; a metal liner layer on the single layer of aluminum oxide or silicon oxide on the barrier layer; and a gate metal on the metal liner layer.

[0123] In some embodiments, the semiconductor device further includes a second device having a second gate structure on the substrate. The second gate structure includes: a gate dielectric layer on the substrate; a barrier layer on the gate dielectric layer; a work function adjustment layer on the barrier layer; a single layer of aluminum oxide or silicon oxide on the work function adjustment layer; a metal liner layer on the single layer of aluminum oxide or silicon oxide on the work function adjustment layer; and a gate metal on the metal liner layer.

[0124] In some embodiments, the work function adjustment layer and the barrier layer are made of different materials.

[0125] In some embodiments, the first device and the second device are different types of devices, including an n-type ultra-low threshold voltage device, an n-type low threshold voltage device, an n-type standard voltage device, an n-type high threshold voltage device, a p-type ultra-low threshold voltage device, a p-type low threshold voltage device, a p-type standard threshold voltage device, or a p-type high threshold voltage device.

[0126] Another embodiment provides a method. The method includes forming a gate dielectric layer in a first trench and a second trench, the first trench and the second trench each being defined in a dielectric structure and intersecting a fin on a substrate; forming a first metal layer on the gate dielectric layer in the first trench; forming a second metal layer on the gate dielectric layer in the second trench, wherein the first metal layer and the second metal layer have different chemical compositions; forming a work function adjustment layer directly on the first metal layer in the first trench and the second metal layer in the second trench, wherein the work function adjustment layer thickness on the first metal layer is different from the work function adjustment layer thickness on the second metal layer; and forming gates on the work function adjustment layer in the first trench and the second trench.

[0127] In some embodiments, the method also includes forming a gate dielectric layer in a third trench, and the third trench is defined in the gate structure and intersects with the fin on the substrate; forming a third metal layer on the gate dielectric layer in the third trench, wherein the chemical composition of the third metal layer, the first metal layer, and the second metal layer are different; directly forming a work function adjustment layer on the third metal layer in the third trench, and the work function adjustment layer thickness on the third metal layer, the work function adjustment layer thickness on the first metal layer, and the work function adjustment layer thickness on the second metal layer are different; and forming a gate on the work function adjustment layer in the third trench.

[0128] In some embodiments, the work function adjusting layer includes tantalum aluminum, tantalum aluminum carbide, titanium aluminum carbide, titanium aluminum oxide, hafnium aluminum, titanium aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof.

[0129] In some embodiments, the work function adjusting layer is titanium aluminum carbide.

[0130] In some embodiments, the first metal layer, the second metal layer, and the third metal layer each include titanium nitride, tantalum nitride, titanium aluminum nitride, titanium silicon nitride, or titanium nitride-silicon nitride.

[0131] In some embodiments, the first metal layer is titanium nitride, the second metal layer is tantalum nitride, and the third metal layer is titanium nitride-silicon nitride.

[0132] In some embodiments, the first metal layer, the second metal layer, and the third metal layer have substantially the same thickness.

[0133] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, replacements, or modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A method for semiconductor processing, comprising: forming a gate dielectric layer in a first trench and a second trench, wherein the first trench and the second trench are each defined in a dielectric structure and intersect a fin on a substrate; forming a first metal layer on the gate dielectric layer in the first trench; forming a second metal layer on the gate dielectric layer in the second trench, wherein the chemical compositions of the first metal layer and the second metal layer are different from each other; directly forming a work function adjustment layer on the first metal layer in the first trench and the second metal layer in the second trench, wherein a thickness of the work function adjustment layer on the first metal layer is different from a thickness of the work function adjustment layer on the second metal layer; as well as A plurality of gates are formed on the work function adjustment layer in the first trench and the second trench, respectively, wherein a difference between a thickness of the work function adjustment layer in the first trench and a thickness of the work function adjustment layer in the second trench is between 28% and 39%.

2. The method for semiconductor processing according to claim 1, further comprising: forming the gate dielectric layer in a third trench defined in the dielectric structure and intersecting the fin on the substrate; forming a third metal layer on the gate dielectric layer in the third trench, wherein the third metal layer has a different chemical composition from the first metal layer and the second metal layer; directly forming the work function adjustment layer on the third metal layer in the third trench, wherein a thickness of the work function adjustment layer on the third metal layer is different from a thickness of the work function adjustment layer on the first metal layer and a thickness of the work function adjustment layer on the second metal layer; and A gate is formed on the work function adjustment layer in the third trench.

3. The method for semiconductor processing according to claim 2, wherein the work function adjustment layer comprises tantalum aluminum, tantalum aluminum carbide, titanium aluminum carbide, titanium aluminum oxide, hafnium aluminum, titanium aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or a combination thereof. 4 . The semiconductor process method according to claim 3 , wherein the work function adjustment layer is titanium aluminum carbide.

5. The method for semiconductor processing according to claim 2, wherein the first metal layer, the second metal layer, and the third metal layer each comprise titanium nitride, tantalum nitride, titanium aluminum nitride, titanium silicon nitride, or titanium nitride-silicon nitride. 6 . The method for semiconductor processing as claimed in claim 5 , wherein the first metal layer is titanium nitride, the second metal layer is tantalum nitride, and the third metal layer is titanium nitride-silicon nitride. 7 . The semiconductor process method according to claim 2 , wherein the first metal layer, the second metal layer, and the third metal layer have the same thickness.

8. The method for semiconductor process as claimed in claim 1, wherein the thickness of the first metal layer and the second metal layer is between to between. 9 . The method for semiconductor processing according to claim 1 , wherein the work function adjusting layer comprises titanium aluminum carbide, and wherein an aluminum concentration of the work function adjusting layer in the first trench is different from an aluminum concentration of the work function adjusting layer in the second trench.

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