Rewiring structure and method for forming the same

Abstract

The present invention discloses a redistribution structure and a method for forming the same, wherein the redistribution structure comprises: a first redistribution layer. The first redistribution layer comprises a dielectric layer; at least one conductor structure located in the dielectric layer, the at least one conductor structure having a width L; and at least one dummy structure located next to the at least one conductor structure and in the dielectric layer, the dummy structure having a width D, wherein there is a gap width S between the dummy structure and the at least one conductor structure, and the flatness DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1-(h / T)]×100%, h refers to the difference between the highest height and the lowest height of the top surface of the dielectric layer; and T refers to the thickness of the at least one conductor structure.

Description

Technical Field

[0001] The present invention relates to several packages and manufacturing methods thereof, and in particular to several redistribution structures and forming methods thereof. Background Art

[0002] The redistribution layer (RDL) is a key part of the package. However, after the metal traces of the redistribution layer are formed, the dielectric layer coated on the metal traces will cause the surface of the dielectric layer to be uneven (topography) due to the pattern factors of the metal traces, causing the pattern of the metal traces on the upper layer to fail in the process and cause electrical loss of the metal traces on the upper layer. Summary of the invention

[0003] The present invention is directed to a redistribution layer, which can improve the flatness of a dielectric layer after coating, and can also improve the process yield of an upper metal wiring and reduce the electrical loss of the upper metal wiring.

[0004] According to an embodiment of the present invention, a redistribution structure is proposed, characterized in that it includes: a first redistribution layer. The first redistribution layer includes: a dielectric layer; at least one conductor structure located in the dielectric layer, the at least one conductor structure having a width L; and at least one dummy structure located next to the at least one conductor structure and in the dielectric layer, the dummy structure having a width D, wherein there is a gap width S between the dummy structure and the at least one conductor structure, and the flatness DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1-(h / T)]×100%, h refers to the difference between the highest height and the lowest height of the top surface of the dielectric layer; and T refers to the thickness of the at least one conductor structure.

[0005] According to an embodiment of the present invention, a method for forming a redistribution structure is also proposed, which is characterized by comprising: forming a first redistribution layer. The formation of the first redistribution layer includes forming at least one conductor structure; forming at least one dummy structure next to the at least one conductor structure according to the thickness T and width L of the at least one conductor structure; and coating a dielectric layer between and on the at least one conductor structure and the at least one dummy structure, so that the flatness DOP of the first redistribution layer is greater than or equal to 95% through the formation of the at least one dummy structure, wherein DOP=[1-(h / T)]×100%, h refers to the difference between the highest height and the lowest height of the top surface of the dielectric layer; and T refers to the thickness of the at least one conductor structure.

[0006] Based on the above, the embodiments of the present invention improve the flatness of the dielectric layer after coating by adding a dummy structure around the conductor structure of the redistribution layer, while improving the process yield of the upper conductor structure and reducing the electrical loss of the upper conductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0008] Figures 1A to 1C They are respectively cross-sectional schematic diagrams of a redistribution structure according to an embodiment of the present invention;

[0009] FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C as well as FIG. 5A to FIG. 5C They are top views of several redistribution structures according to embodiments of the present invention;

[0010] Figure 6 , Figure 7 They are cross-sectional schematic diagrams of two redistribution structures according to embodiments of the present invention;

[0011] Figure 8 , Fig.13 , Fig.18 They are cross-sectional schematic diagrams of two redistribution structures and an under-bump metallization structure according to embodiments of the present invention;

[0012] Figures 9 to 12 , Figures 14 to 17 as well as Figures 19 to 22 They are top views of several redistribution structures and under-bump metallization structures according to embodiments of the present invention;

[0013] Fig.23 and Fig.24 A manufacturing flow chart of a redistribution structure and an under-bump metallization structure according to an embodiment of the present invention;

[0014] FIG. 25A to FIG. 25H is a cross-sectional view of a process of a method for manufacturing a packaging structure according to an embodiment of the present invention;

[0015] Fig.26 FIG. 4 is a graph showing the relationship between the flatness of the redistribution layer and the insertion loss according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and description to represent the same or similar parts. Ranges referred to herein are inclusive of their endpoint values, e.g., "1 / 2 to 12 / 1" means between 1 / 2 and 12 / 1, and includes both 1 / 2 and 12 / 1 endpoint values.

[0017] Reference Figure 1A , Figure 2A , Figure 3A , Figure 4A and Figure 5A , an embodiment of the present invention proposes a redistribution layer RDL1. Figure 2A , Figure 3A , Figure 4A and Figure 5A The cross section of line I-I' is as follows Figure 1A As shown. The redistribution layer RDL1 is located on the substrate 10, and the conductor structure CV2 above the redistribution layer RDL1 is a key pattern. The key pattern is, for example, a high-frequency signal line. The substrate 10 is, for example, a carrier. The redistribution layer RDL1 includes at least one conductor structure CV1, at least one dummy structure DY1, and a dielectric layer PM1. Figure 1A In the illustrated embodiment, the redistribution layer RDL1 including a conductor structure CV1, a plurality of dummy structures DY1, and a dielectric layer PM1 is used for illustration, but the present invention is not limited thereto. In another embodiment, the redistribution layer RDL1 includes a plurality of conductor structures CV1, a plurality of dummy structures DY1, and a dielectric layer PM1. In yet another embodiment, the redistribution layer RDL1 includes a plurality of conductor structures CV1, a dummy structure DY1, and a dielectric layer PM1.

[0018] The conductor structure CV1 may also be referred to as a conductor feature, which is a circuit with actual functions. The conductor structure CV1 may include a trace, which is located on the substrate 10. The conductor structure CV1 may be electrically connected to a subsequently formed component or to another conductor structure CV1. The dummy structure DY1 is disposed between the plurality of conductor structures CV1. The dummy structure DY1 is floating and electrically insulated from the conductor structure CV1. The conductor structure CV1 has a width L1. The width L1 is, for example, a critical dimension of the conductor structure CV1. The conductor structure CV1 includes copper or a copper-aluminum alloy.

[0019] The dummy structure DY1 is a conductor material, and therefore can also be called a dummy conductor structure. The material of the dummy structure DY1 can be the same as or different from the material of the conductor structure CV1. The dummy structure DY1 can be formed simultaneously with the conductor structure CV1, or can be formed separately. The dummy structure DY1 includes copper or copper-aluminum alloy. The dummy structure DY1 has a width D1. The width D1 of the dummy structure DY1 is, for example, 1 / 10 to 1 of the width L1 of the conductor structure CV1. There is a gap width S1 between the dummy structure DY1 and the conductor structure CV1 and between the dummy structures DY1. The dielectric layer PM1 can be formed after the conductor structure CV1 and the dummy structure DY1 are formed. The dielectric layer PM1 covers between the conductor structure CV1 and the dummy structure DY1 and on the surface thereof. The dielectric layer PM1 includes a polymer. In some embodiments, the higher the molecular weight and viscosity coefficient of the dielectric layer PM1, the lower the flatness of the dielectric layer PM1. Therefore, the dielectric layer PM1 can also be used by selecting a suitable molecular weight and viscosity coefficient of the dielectric layer PM1. The dielectric layer PM1 is, for example, photosensitive polyimide (Photosensitive PI; PSPI), polyimide (polyimide), polybenzoxazole (PBO) and benzocyclobutene (BCB). The dielectric layer PM1 is a coating layer that has not been subjected to a planarization process (for example, a chemical mechanical polishing process). The dielectric layer PM1 is formed by, for example, a spin coating method. After the coating layer is formed, a curing process may be performed to form the dielectric layer PM1. The ratio of the thickness T1 of the conductor structure CV1 to the thickness H1 of the dielectric layer PM1 is, for example, 1:1.1 to 1:1.6. The thickness H1 of the dielectric layer PM1 refers to the distance between the lowest height of the bottom surface of the dielectric layer PM1 and the lowest height of the top surface of the dielectric layer PM1.

[0020] In some embodiments, the ratio L1 / S1 of the width L1 of the conductor structure CV1 to the gap width S1 is 1 / 2 to 12 / 1. In other embodiments, the ratio L1 / S1 of the width L1 of the conductor structure CV1 to the gap width S1 is 1 / 2 to 10 / 1. The ratio L1 / D1 of the width L1 of the conductor structure CV1 to the width D1 of the dummy structure DY1 is, for example, between 1 and 10. By controlling the thickness T1 of the conductor structure CV1 and the dummy structure DY1 and the ratios L1 / S1 and L1 / D1, the flatness (degree of planarization) DOP1 of the redistribution layer RDL1 of the present invention can be greater than or equal to 95%. The flatness DOP1 is defined as follows:

[0021] DOP1=[1-(h1 / T1)]×100%

[0022] h1 refers to the difference between the highest height and the lowest height of the top surface of the dielectric layer PM1; and

[0023] T1 refers to the thickness of the conductor structure CV1.

[0024] In terms of process, after forming the conductor structure CV1 and the dummy structure DY1 of the redistribution layer RDL1, the thickness T1 of the conductor structure CV1 can be measured. Then, the dielectric layer PM1 is formed. Thereafter, the dielectric layer PM1 can be measured to obtain H1 and the height difference h1. The flatness DOP1 can be calculated based on the obtained thickness T1 and the height difference h1. When h1 is larger, the flatness DOP1 is smaller, indicating that the top surface of the redistribution layer RDL1 is more uneven and the insertion loss is greater. When h1 is smaller, the flatness DOP1 is larger, indicating that the top surface of the redistribution layer RDL1 is more flat and the insertion loss is smaller. When DOP1 is greater than or equal to 95%, the electrical loss can be reduced to within the design requirements.

[0025] In addition, the larger the width L1 of the conductor structure CV1, the larger the range of the ratio L1 / D1 that can make the flatness DOP1 reach 95%. The smaller the width L1 of the conductor structure CV1, the smaller the range of the ratio L1 / D1 that can make the flatness DOP1 reach 95%. For example, for a conductor structure with a thickness of 1 to 4 microns and a width L greater than 100 microns, L1 / D1 can be controlled in the range of 1 / 1 to 10 / 1 to make the flatness DOP1 reach 95%; and for a conductor structure with a thickness of 1 to 4 microns but a width L of 10 to 20 microns, L1 / D1 must be controlled in the range of 1~2 / 1 to make the flatness DOP1 reach 95%.

[0026] When the width L1 of the conductor structure CV1 is smaller, the ratio L1 / S1 reaches a smaller value to make the flatness DOP1 reach 95%. When the width L1 of the conductor structure CV1 is larger, the ratio L1 / S1 must be larger to make the flatness DOP1 reach 95%. For example, for a conductor structure with a thickness of 4 to 8 microns and a width L between 10 and 20 microns, the ratio L1 / S1 is greater than or equal to 2 to make the flatness DOP reach 95%; and for a conductor structure with a thickness of 4 to 8 microns and a width L greater than 100 microns, the ratio L / S must be greater than or equal to 10 to make the flatness DOP reach 95%.

[0027] In some embodiments, a dummy structure DY1 is arranged around each conductor structure CV1. The size and density of the dummy structures DY1 around the conductor structures CV1 in different regions may be the same or different. For example, the size and / or density of the dummy structures DY1 arranged around the conductor structure CV1 in the critical area (with large flatness DOP) are smaller than and / or greater than the size and / or density of the small dummy structures DY1 arranged around the conductor structure CV1 in the non-critical area (with small flatness DOP). In other embodiments, the dummy structures DY1 are arranged around part of the conductor structure CV1, while no dummy structures are arranged around the conductor structure CV1 in another part. For example, a dummy structure DY1 may be arranged around the conductor structure CV1 in the critical area, while no dummy structure DY1 may be arranged around the conductor structure CV1 in the non-critical area. In other words, the flatness DOP1 of the non-critical area may be less than or equal to the flatness DOP1 of the critical area. The critical area is, for example, an area that has an impact on the conductor structure CV2 (for example, electrical loss). The non-critical area is, for example, an area that has no impact on the conductor structure CV2.

[0028] Figure 2A , Figure 3A , Figure 4A and Figure 5A The cross section of line I-I' is as follows Figure 1A See Figure 1A , Figure 2A , Figure 3A , Figure 4A and Figure 5A The shapes of the dummy structures DY1 include square, circular, polygonal, long strip and combinations thereof. The dummy structures DY1 in the redistribution layer RDL1 may have a single shape or multiple shapes. In addition, the sizes and lengths of the dummy structures DY1 may be the same or different. Figure 2A , Figure 3A , Figure 4A and Figure 5A In the embodiment, the dummy structures DY1 are arranged in an array or in parallel with each other, and the dummy structures DY1 have a single shape and are square, circular, polygonal and strip-shaped.

[0029] The width D1 of the dummy structure DY1 may be the same or different. In some embodiments, the redistribution layer RDL1 has a dummy structure DY1 of a single width D1. In other embodiments, the redistribution layer RDL1 has two or more dummy structures DY1 of width D1. For example, the width D1 of the dummy structure DY1 of the redistribution layer RDL1 at a location where the flatness requirement is lower may be greater than the width D1 of the dummy structure DY1 of the redistribution layer RDL1 at a location where the flatness requirement is higher. The width D1 of the dummy structure DY1 is, for example, less than 40 microns, for example, between 10 microns and 40 microns, or less than 10 microns.

[0030] The dummy structure DY1 can be disposed between the conductor structures CV1 with a fixed gap width S1 or with multiple gap widths S1. In some embodiments, there is a single gap width S1 between the dummy structure DY1 and the conductor structure CV1 of the redistribution layer RDL1. In other embodiments, there are two or more gap widths S1 between the dummy structure DY1 and the conductor structure CV1 of the redistribution layer RDL1.

[0031] In the embodiment where the redistribution layer RDL1 has a dummy structure DY1 of a single width D1, the dummy structure DY1 is arranged with a fixed gap width S1. The smaller the width D1 of the dummy structure DY1, the more dummy structures DY1 can be arranged, the more evenly the distribution of the dummy structures is, the greater the flatness DOP1 is, the smaller the surface fluctuation of the redistribution layer RDL1 is, and the surface is relatively flat. Conversely, the larger the width D1 of the dummy structure DY1 is, the smaller the flatness DOP1 is, the greater the fluctuation of the redistribution layer RDL1 is, and the surface is relatively uneven.

[0032] In an embodiment in which the redistribution layer RDL1 has a dummy structure DY1 of a single width D1, the dummy structure DY1 is set with a fixed gap width S1. The smaller the gap width S1, the more dummy structures DY1 can be set, the more evenly the distribution of the dummy structures is, the smaller the ups and downs of the applied dielectric layer PM1 are, and the greater the flatness DOP1 is. Conversely, the larger the gap width S1, the greater the ups and downs of the applied dielectric layer PM1 are, and the smaller the flatness DOP1 is. The gap width S1 between the dummy structure DY1 and the conductor structure CV1 is, for example, less than 80 microns, for example, between 5 microns and 40 microns. When the gap width S1 is greater than 40 microns, the improvement in the flatness of the redistribution layer RDL1 becomes very limited.

[0033] By setting the dummy structure DY1 and controlling the ratio L1 / S1 and the ratio L1 / D1, the flatness DOP1 of the redistribution layer RDL1 can be improved from 60% to more than 75%, for example, 75% to 95%, or even higher.

[0034] The embodiment of the present invention can be used in a rewiring structure composed of multiple rewiring layers. In the rewiring structure, a dummy structure can be set in one or more of the rewiring layers, or a dummy structure can be set in each rewiring layer. Figure 1B and Figure 1C shown.

[0035] Please refer to Figure 1B , the redistribution structure RDLS is located on the substrate 10. The redistribution structure RDLS includes a redistribution layer RDL1 and a redistribution layer RDL2. The conductor structure CV3 above the redistribution layer RDL2 is a key pattern. The key pattern is, for example, a high-frequency signal line.

[0036] The flatness DOP1 of the redistribution layer RDL1 may be less than or equal to 95%, for example, 65% or lower. In some examples, the structure and formation method of the redistribution layer RDL1 may be, for example, the redistribution layer RDL1 having at least one conductor structure CV1, at least one dummy structure DY1 and a dielectric layer PM1 as described in the above-mentioned embodiments. In other examples, the structure of the redistribution layer RDL1 may include the conductor structure CV1 but not the dummy structure DY1. In the present embodiment, the redistribution layer RDL1 is illustrated as having the conductor structure CV1, the dummy structure DY1 and the dielectric layer PM1.

[0037] After the redistribution layer RDL1 is formed, the dielectric layer PM1 is directly formed with the redistribution layer RDL2 without additional planarization process. The structure of the redistribution layer RDL2 may be similar to or different from that of the redistribution layer RDL1.

[0038] The redistribution layer RDL2 includes at least one conductor structure CV2, at least one dummy structure DY2 and a dielectric layer PM2. Figure 1B In the illustrated embodiment, a redistribution layer RDL2 including a conductor structure CV2, a plurality of dummy structures DY2, and a dielectric layer PM2 is used for illustration, but the present invention is not limited thereto. In another embodiment, the redistribution layer RDL2 includes a plurality of conductor structures CV2 and a dielectric layer PM2. In yet another embodiment, the redistribution layer RDL2 includes a plurality of conductor structures CV2, a dummy structure DY2, and a dielectric layer PM2.

[0039] The conductor structure CV2 includes a trace, which is located on the dielectric layer PM1. The conductor structure CV2 also includes a through hole (not shown), which penetrates the dielectric layer PM1 and connects the trace of the conductor structure CV2 with the trace of the conductor structure CV1. The dummy structure DY2 is arranged around the conductor structure CV2. The dummy structure DY2 is floating and electrically insulated from the trace in the conductor structure CV2, and is electrically insulated from the trace of the conductor structure CV1 or subsequently formed components. The conductor structure CV2 has a width L2. The width L2 is, for example, a critical dimension of the conductor structure CV2. The dummy structure DY2 has a width D2. There is a gap width S2 between the dummy structure DY2 and the conductor structure CV2 and between the dummy structures DY2. In other embodiments, the redistribution layer RDL2 may not include multiple dummy structures DY2, such as Figure 7 As shown, it will be described in detail later.

[0040] The dielectric layer PM2 covers between the conductor structure CV2 and the dummy structure DY2 and on the surface thereof. The dielectric layer PM2 includes a polymer, such as photosensitive polyimide (PSPI), polyimide, polybenzoxazole (PBO) and benzocyclobutene (BCB). The dielectric layer PM2 is a coating layer that has not been subjected to a planarization process (such as a chemical mechanical polishing process). The dielectric layer PM2 is formed by, for example, a spin coating method. The ratio of the thickness T2 of the conductor structure CV2 to the thickness H2 of the dielectric layer PM2 is, for example, 1:1.1 to 1:1.6. The thickness H2 of the dielectric layer PM2 refers to the distance between the lowest height of the bottom surface of the dielectric layer PM2 and the lowest height of the top surface of the dielectric layer PM2.

[0041] The flatness DOP2 of the redistribution layer RDL2 of the embodiment of the present invention may be greater than or equal to 95%. The flatness DOP2 of the redistribution layer RDL2 is defined as follows:

[0042] DOP2=[1-(h2 / T2)]×100%

[0043] h2 refers to the difference between the highest height and the lowest height of the top surface of the dielectric layer PM2; and

[0044] T2 refers to the thickness of the conductor structure CV2.

[0045] The shape, size, and arrangement of the dummy structure DY2 may be similar to those of the dummy structure DY1 , and will not be described in detail herein.

[0046] The width D2 of the dummy structure DY2 may be equal to the width L2 of the conductor structure CV2, but is not limited thereto. The ratio L2 / D2 of the width L2 of the conductor structure CV2 to the width D2 of the dummy structure DY2 is, for example, between 1 and 10. The larger the width L2 of the conductor structure CV2, the larger the range of the ratio L2 / D2 for the flatness DOP2 to reach 95%. The smaller the width L2 of the conductor structure CV2, the smaller the range of the ratio L2 / D2 for the flatness DOP2 to reach 95%.

[0047] The ratio L2 / S2 of the width L2 of the conductor structure CV2 to the gap width S2 is, for example, 1 / 2 to 12 / 1. In other embodiments, the ratio L2 / S2 of the width L2 of the conductor structure CV2 to the gap width S2 is 1 / 2 to 10 / 1. When the width L2 of the conductor structure CV2 is smaller, the ratio L2 / S2 reaches a smaller value above which the flatness DOP2 can reach 95%. When the width L2 of the conductor structure CV2 is larger, the ratio L2 / S2 must have a larger value to make the flatness DOP2 reach 95%.

[0048] In some embodiments, by providing the dummy structure DY2, the flatness DOP1 of the redistribution layer RDL2 can be increased from 60% to more than 75%, for example, 75% to 95%, or even higher. The flatness DOP2 of the redistribution layer RDL2 can be equal to or higher than the flatness DOP1 of the redistribution layer RDL1.

[0049] In addition, Figure 1B In the embodiment, the conductor structure CV2 and the conductor structure CV1 completely overlap in the longitudinal direction. The dummy structure DY2 partially overlaps with the dummy structure DY1. The conductor structure CV2 does not overlap with the dummy structure DY1. The dummy structure DY2 does not overlap with the conductor structure CV1. However, the embodiments of the present invention are not limited thereto. The extension directions of the conductor structure CV2 and the conductor structure CV1 may be the same or different, and may completely overlap, partially overlap, or not overlap in the longitudinal direction. The dummy structure DY2 and the dummy structure DY1 may completely overlap, partially overlap, or not overlap in the longitudinal direction. The conductor structure CV2 and the dummy structure DY1 may completely overlap, partially overlap, or not overlap in the longitudinal direction. The dummy structure DY2 and the conductor structure CV1 may completely overlap, partially overlap, or not overlap in the longitudinal direction. Figure 2B , Figure 3B , Figure 4B , Figure 5B Several embodiments are shown to illustrate various redistribution structures RDLS.

[0050] Please refer to Figure 2B , Figure 3B , Figure 4B , Figure 5B, the conductor structures CV1 and CV2 of the redistribution layers RDL1 and RDL2 of the embodiment of the present invention extend in different directions and partially overlap in the longitudinal direction. The dummy structure DY2 and the dummy structure DY1 may partially overlap or not overlap in the longitudinal direction. The conductor structure CV2 and the dummy structure DY1 do not overlap in the longitudinal direction. The dummy structure DY2 and the conductor structure CV1 completely overlap in the longitudinal direction.

[0051] In the embodiment, the dummy structures DY1 and DY2 are in the shape of a square block, a circle, a polygon and a strip, respectively. Figure 2B , Figure 3B , Figure 4B , Figure 5B As shown. The dummy structure DY1 and the dummy structure DY2 have a single shape or multiple shapes respectively. The shapes of the dummy structure DY1 and the dummy structure DY2 can be the same or different. The size of the dummy structure DY2 is smaller than the size of the dummy structure DY1, but not limited thereto. The width of the dummy structure DY1 is equal to that of the conductor structure CV1, and the width of the dummy structure DY2 is equal to that of the conductor structure CV2, but not limited thereto.

[0052] The ratio of the width L1 of the conductor structure CV1 to the gap width S1 and the ratio of the width L2 of the conductor structure CV2 to the gap width S2 are 1 / 2 to 12 / 1. In other embodiments, the ratio of the width L1 of the conductor structure CV1 to the gap width S1 and the ratio of the width L2 of the conductor structure CV2 to the gap width S2 are 1 / 2 to 10 / 1. The flatness DOP1 and the flatness DOP2 of the redistribution layers RDL1 and RDL2 may be greater than 75%, or even 95%, or more.

[0053] Disposing the dummy structures DY1 and DY2 around the conductor structures CV1 and CV2 respectively can make the redistribution layers RDL1 and RDL2 have a flat top surface, which is helpful for the RDL3 process, improves the process yield, and makes the conductor structure CV3 as a high-frequency signal transmission line have good electrical properties.

[0054] Reference Figure 1C In some embodiments, the redistribution structure RDLS includes redistribution layers RDL1, RDL2, and RDL3. The redistribution layer RDL3 is located on the redistribution layer RDL2. The conductor structure CV4 above the redistribution layer RDL3 is a key pattern. The key pattern is, for example, a high-frequency signal line.

[0055] The flatness DOP1 and DOP2 of the redistribution layers RDL1 and RDL2 may be less than or equal to 95%, for example, 65% or lower. In some embodiments, the structure and formation method of the redistribution layers RDL1 and RDL2 may be, for example, the redistribution layer RDL1 having at least one conductor structure CV1, at least one dummy structure DY1 and a dielectric layer PM1 as described in the above embodiments, and the redistribution layer RDL2 having at least one conductor structure CV2, at least one dummy structure DY2 and a dielectric layer PM2. In other embodiments, the structure of the redistribution layer RDL1 may include the conductor structure CV1 but not the dummy structure DY1; the structure of the redistribution layer RDL2 may also include the conductor structure CV2 but not the dummy structure DY2. In the present embodiment, it is explained that the redistribution layer RDL1 has a conductor structure CV1, a plurality of dummy structures DY1 and a dielectric layer PM1, and the redistribution layer RDL2 has a conductor structure CV2, a plurality of dummy structures DY2 and a dielectric layer PM2.

[0056] After the redistribution layer RDL2 is formed, the dielectric layer PM2 is not subjected to an additional planarization process, and the redistribution layer RDL3 is directly formed on the dielectric layer PM2. The structure of the redistribution layer RDL3 may be similar to or different from that of the redistribution layer RDL2.

[0057] The redistribution layer RDL3 includes at least one conductor structure CV3, at least one dummy structure DY3 and a dielectric layer PM3. Figure 1C In the illustrated embodiment, the redistribution layer RDL3 includes a conductor structure CV3, a plurality of dummy structures DY3 and a dielectric layer PM3, but the present invention is not limited thereto. In another embodiment, the redistribution layer RDL3 includes a plurality of conductor structures CV3, a plurality of dummy structures DY3 and a dielectric layer PM3.

[0058] The conductor structure CV3 includes a trace, which is located on the dielectric layer PM2. The conductor structure CV3 also includes a through hole (not shown), which penetrates the dielectric layer PM2 and connects the trace of the conductor structure CV3 with the trace of the conductor structure CV2. The dummy structure DY3 is arranged around the conductor structure CV3. The dummy structure DY3 is floating, electrically insulated from the trace in the conductor structure CV3, and electrically insulated from the trace of the conductor structure CV2 or the subsequently formed components. The conductor structure CV3 has a width L3. The width L3 is, for example, a critical dimension of the conductor structure CV3. The dummy structure DY3 has a width D3. There is a gap width S3 between the dummy structure DY3 and the conductor structure CV3 and between the dummy structures DY3. In other embodiments, the redistribution layer RDL3 does not include multiple dummy structures DY3 (not shown).

[0059] The dielectric layer PM3 covers between the conductor structure CV3 and the dummy structure DY3 and on the surface thereof. The material and formation method of the dielectric layer PM3 may be the same as or different from those of the dielectric layer PM2. The dielectric layer PM3 is a coating layer that has not been subjected to a planarization process (e.g., a chemical mechanical polishing process). The ratio of the thickness T3 of the conductor structure CV3 to the thickness H3 of the dielectric layer PM3 is, for example, 1:1.1 to 1:1.6. The thickness H3 of the dielectric layer PM3 refers to the distance between the lowest height of the bottom surface of the dielectric layer PM3 and the lowest height of the top surface of the dielectric layer PM3.

[0060] Similarly, the thickness H3 of the dielectric layer PM3, the difference h3 between the highest height and the lowest height of the top surface of the dielectric layer PM3, and the height T3 of the conductor structure CV3 can be obtained by measurement, and then the flatness DOP3 of the redistribution layer RDL3 can be obtained. The flatness DOP3 of the redistribution layer RDL3 is defined as follows:

[0061] DOP3=[1-(h3 / T3)]×100%

[0062] h3 refers to the difference between the highest height and the lowest height of the top surface of the dielectric layer PM3; and

[0063] T3 refers to the thickness of the conductor structure CV3.

[0064] The flatness DOP3 of the redistribution layer RDL3 may be the same as or different from the flatness DOP1 of the redistribution layer RDL1, and may also be the same as or different from the flatness DOP2 of the redistribution layer RDL2. In some embodiments, the flatness DOP3 is greater than or equal to the flatness DOP2 or DOP1. For example, the flatness DOP1 and the flatness DOP2 are less than 75%, and the flatness DOP3 is 95% or greater than 95%.

[0065] The following reference Figure 2C , Figure 3C , Figure 4C , Figure 5C , several embodiments are given to illustrate various redistribution structures RDLS.

[0066] Reference Figure 2C , Figure 3C , Figure 4C , Figure 5CIn some embodiments, the chip will be arranged on the redistribution layer RDL3. Considering the problem of electrical transmission, the high-frequency signal transmission line is designed above the redistribution layer RDL3 to shorten the distance between the high-frequency signal transmission line and the chip. That is, the conductor structure CV4 (not shown) above the redistribution layer RDL3 is a key pattern. The key pattern described here may refer to the layer or structure below it must have sufficient flatness. Since the setting of the dummy structures DY1 and DY2 can make the redistribution layer RDL2 have sufficient flatness, the redistribution layer RDL3 does not need to be configured with the dummy structure DY3, and the conductor structure CV3 can be arbitrarily configured according to design requirements, so the conductor structure CV3 is not drawn in this example.

[0067] In some embodiments, the conductor structures CV1, CV2, and CV3 are all in the shape of long strips. The widths of the conductor structures CV1, CV2, and CV3 may be the same or different. The extension directions of the conductor structures CV1, CV2, and CV3 may be the same or different, and may completely overlap, partially overlap, or not overlap in the longitudinal direction. The dummy structure DY2 may completely overlap, partially overlap, or not overlap with the dummy structure DY1 in the longitudinal direction. The conductor structure CV3 may completely overlap, partially overlap, or not overlap with the dummy structure DY2 in the longitudinal direction.

[0068] If the dummy structures DY1 and / or DY2 are not provided, the redistribution layers RDL1 and RDL2 will have excessive fluctuations in height due to the too low flatness DOP1 and DOP2, making the RDL3 process difficult to carry out, causing problems in process yield, or causing problems with the electrical properties of the conductor structure CV3.

[0069] In the above embodiments, the dummy structures DY1 and DY2 are respectively provided on the redistribution layers RDL1 and RDL2. However, the dummy structures DY1 or DY2 may be selectively provided on the redistribution layers RDL1 or RDL2. Figure 6 and Figure 7 shown.

[0070] Reference Figure 6 In some embodiments, a dummy structure DY2 is provided in the redistribution layer RDL2, while a dummy structure DY1 is not provided in the redistribution layer RDL1, as long as the flatness DOP2 of the redistribution layer RDL2 where the conductor structure CV3 serving as a key pattern (such as a high-frequency signal transmission line) lands can reach the required level (such as 95%).

[0071] Reference Figure 7In other embodiments, a dummy structure DY1 is provided in the redistribution layer RDL1, while a dummy structure DY2 is not provided in the redistribution layer RDL2, as long as the flatness of the redistribution layer RDL2 where the conductor structure CV3 of the key pattern (such as a high-frequency signal transmission line) lands can reach the required level (such as 95%).

[0072] In addition, in the above embodiments, the dummy structure is disposed in the rewiring structure. In other embodiments, a dummy structure may also be disposed in the under bump metallization structure UBM below the rewiring structure, such as Figure 8 , Fig.13 and Fig.18 shown.

[0073] Reference Figure 8 , Fig.13 and Fig.18 The redistribution structure RDLS includes redistribution layers RDL1, RDL2 and RDL3. The conductor structure CV3 of the redistribution layer RDL3 is a key pattern, for example, a high-frequency signal transmission line. In addition to the conductor structure CV0 and the dielectric layer PM0, the under-bump metallization layer structure UBM under the redistribution layer RDL1 also includes a dummy structure DY0.

[0074] The under bump metallization structure UBM includes at least one conductor structure CV0, at least one dummy structure DY0 and a dielectric layer PM0. Figure 8 , 13 In the embodiment shown in FIG. 18 , an under bump metallization structure UBM including a conductor structure CV0, a ​​plurality of dummy structures DY0, and a dielectric layer PM0 is used for illustration, but the present invention is not limited thereto. In another embodiment, the under bump metallization structure UBM includes a plurality of conductor structures CV0 and a dielectric layer PM0. In yet another embodiment, the under bump metallization structure UBM includes a plurality of conductor structures CV0, a ​​dummy structure DY0, and a dielectric layer PM0.

[0075] The conductor structure CV0 is located on the substrate 10. The conductor structure CV0 is, for example, a copper pillar. The dummy structure DY0 is disposed between the plurality of conductor structures CV0. The dummy structure DY0 is floating, electrically insulated from the conductor structure CV0, and electrically insulated from the conductor structure CV1 formed subsequently. The conductor structure CV0 has a width L0. The width L0 is, for example, a critical dimension of the conductor structure CV0. The dummy structure DY0 has a width D0. There is a gap width S0 between the dummy structure DY0 and the conductor structure CV0 and between the dummy structures DY0.

[0076] The dielectric layer PM0 covers between the conductor structure CV0 and the dummy structure DY0 and on the surface thereof. The dielectric layer PM0 includes a polymer, such as photosensitive polyimide (PSPI), polyimide, polybenzoxazole (PBO), and benzocyclobutene (BCB). The dielectric layer PM0 is a coating layer that has not been subjected to a planarization process (such as a chemical mechanical polishing process). The dielectric layer PM0 is formed by, for example, a spin coating method.

[0077] The flatness DOP0 of the redistribution layer under bump metallization structure UBM of the embodiment of the present invention may be greater than or equal to 95%. The flatness DOP0 is defined as follows:

[0078] DOP0=[1-(h0 / T0)]×100%

[0079] h0 refers to the difference between the highest height and the lowest height of the top surface of the dielectric layer PM0; and

[0080] T0 refers to the height of the conductor structure CV0.

[0081] In some embodiments, the ratio of the width L0 of the conductor structure CV0 to the gap width S0 is 1 / 2 to 12 / 1. In other embodiments, the ratio of the width L0 of the conductor structure CV0 to the gap width S0 is 1 / 2 to 10 / 1. In this embodiment, by setting the dummy structure DY0, the flatness DOP0 of the under-bump metal layer structure UBM can be increased from 60% to more than 75%, for example, 75% to 95%, or even higher. The flatness DOP0 of the under-bump metal layer structure UBM can be the same as or different from the flatness DOP1 of the redistribution layer RDL1 or the flatness DOP2 of the redistribution layer RDL2. In some embodiments, the flatness DOP0 is greater than or equal to the flatness DOP1 or the flatness DOP2. In other embodiments, the flatness DOP0 is less than or equal to the flatness DOP1 or the flatness DOP2.

[0082] The dummy structure DY0 may have a single shape or multiple shapes. The shape of the dummy structure DY0 is a square block, a polygon, a dot, or a strip, respectively. Figures 9 to 12 , Figures 14 to 17 as well as Figures 19 to 22 shown.

[0083] The width L0 of the dummy structure DY0 may be equal to the width of the conductor structure CV0, but is not limited thereto. The widths L0 of the dummy structures DY0 may be the same or different. The ratio L0 / D0 of the width L0 of the conductor structure CV0 to the width D0 of the dummy structure DY0 is, for example, between 1 and 10.

[0084] In some embodiments, the dummy structure DY0 of the under bump metallurgy structure UBM has a single width L0. In other embodiments, the under bump metallurgy structure UBM has dummy structures DY0 of two or more widths D0. The dummy structure DY0 can be disposed between the conductor structure CV0 with a fixed gap width S0 or with multiple gap widths S0. In some embodiments, there is a single gap width S0 between the dummy structure DY0 of the under bump metallurgy structure UBM and the conductor structure CV0. In other embodiments, there are two or more gap widths S0 between the dummy structure DY0 of the under bump metallurgy structure UBM and the conductor structure CV0. In some embodiments, the ratio of the width L0 of the conductor structure CV0 to the gap width S0 is 1 / 2 to 12 / 1. In other embodiments, the ratio of the width L0 of the dummy structure DY0 to the gap width S0 is 1 / 2 to 10 / 1.

[0085] When the width L0 of the conductor structure CV0 is larger, the range of the ratio L0 / D0 that can make the flatness DOP0 reach 95% is larger. The smaller the width L0 of the conductor structure CV0 is, the smaller the range of the ratio L0 / D0 that can make the flatness DOP0 reach 95%. When the width L0 of the conductor structure CV0 is smaller, the ratio L0 / S0 reaches a smaller value to make the flatness DOP0 reach 95%. When the width L0 of the conductor structure CV0 is larger, the ratio L0 / S0 must have a larger value to make the flatness DOP0 reach 95%.

[0086] In the embodiment of the present invention, by providing the dummy structure DY0 , the flatness DOP0 of the under bump metallurgy structure UBM can be improved from 60% to more than 75%, for example, 75% to 95%, or even higher.

[0087] The under bump metallization structure UBM may be covered with only a single redistribution layer (not shown) or a redistribution structure RDLS having multiple redistribution layers, such as Figures 8 to 22 shown.

[0088] Reference Figure 8 , Fig.13 and Fig.18 The redistribution structure RDLS above the under bump metallization structure UBM includes redistribution layers RDL1, RDL2 and RDL3.

[0089] exist Figure 8The under bump metallization layer structure UBM in the embodiment includes a plurality of conductor structures CV0, a ​​dummy structure DY0 and a dielectric layer PM0. The redistribution layer RDL1 includes a plurality of conductor structures CV1, a dummy structure DY1 and a dielectric layer PM1. The redistribution layer RDL2 includes a plurality of conductor structures CV2, a dummy structure DY2 and a dielectric layer PM2. The redistribution layer RDL3 includes a plurality of conductor structures CV3 and a dielectric layer PM3.

[0090] Reference Figure 8 , the conductor structures CV0, CV1, CV2, and CV3 of the under-bump metal layer structure UBM and the redistribution layers RDL1, RDL2, and RDL3 are, for example, all in the shape of long strips. The width L0 of the conductor structure CV0 may be the same as or different from the widths L1, L2, and L3 of CV1, CV2, and CV3. The extension direction of the conductor structure CV0 may be the same as or different from the extension direction of CV1, CV2, and CV3. The conductor structure CV0 and the conductor structure CV1 completely overlap in the longitudinal direction. The dummy structure DY0 completely overlaps with the dummy structure DY1. The conductor structure CV0 does not overlap with the dummy structure DY1. The dummy structure DY0 does not overlap with the conductor structure CV1. However, the embodiments of the present invention are not limited thereto. The extension directions of the conductor structure CV0 and the conductor structure CV1 may be the same or different, and may completely overlap, partially overlap, or not overlap in the longitudinal direction. The dummy structure DY0 and the dummy structure DY1 may completely overlap, partially overlap, or not overlap in the longitudinal direction. The conductor structure CV0 and the dummy structure DY1 may completely overlap, partially overlap, or not overlap in the longitudinal direction. The dummy structure DY0 and the conductor structure CV1 may completely overlap, partially overlap, or not overlap in the longitudinal direction. Figures 9 to 12 Several embodiments are shown to illustrate various redistribution structures RDLS.

[0091] exist Figures 9 to 12 In the embodiment of the present invention, the dummy structures DY0 and DY1 are respectively in the shape of a square block, a circle, a polygon and a strip. The dummy structures DY0 and DY1 have a single shape respectively, but are not limited thereto. The width D1 of the dummy structure DY1 is less than the width D0 of the dummy structure DY0, but are not limited thereto. The width of the dummy structure DY0 is equal to that of the conductor structure CV0, and the width of the dummy structure DY1 is equal to that of the conductor structure CV1, but are not limited thereto. The positions of the dummy structures DY0 and DY1 may completely overlap, partially overlap or not overlap. Similarly, the positions of the dummy structures DY0 and the conductor structure CV1 may completely overlap, partially overlap or not overlap.

[0092] In this example, by setting up the dummy structures DY0 and DY1, the redistribution layer RDL2 can achieve the required flatness. Therefore, the redistribution layer RDL2 does not need to set up the dummy structure DY2 and the conductor structures CV2 and CV3 of the redistribution layers RDL2 and RDL3 can be arranged at any position according to the design or need. Figures 9 to 12 The redistribution layers RDL2 and RDL3 are not shown.

[0093] The flatness DOP0 of the under bump metallurgy structure UBM, the flatness DOP1 of the redistribution layer RDL1, and the flatness DOP2 of the redistribution layer RDL2 can reach 95% or more. The flatness DOP3 of the redistribution layer RDL3 can be greater than 75%, or even reach 95% or more.

[0094] Reference Fig.13 In other embodiments, the redistribution layer RDL2 does not have the dummy structure DY2. By providing the dummy structure DY0 of the under bump metallization structure UBM and the dummy structure DY1 of the redistribution layer RDL1, the redistribution layer RDL2 can have a high flatness DOP2, so that the conductor structure CV3 of the redistribution layer RDL3 can be formed on the flat redistribution layer RDL2. Fig.14 , Fig.15 , Fig.16 and Fig.17 Several embodiments are shown to illustrate various redistribution structures RDLS.

[0095] Please refer to Fig.14 , Fig.15 , Fig.16 and Fig.17 The conductor structures CV0 and CV1 of the under-bump metallization structure UBM and the redistribution layer RDL1 are both in the shape of long strips, but extend in different directions and partially overlap. The width L0 of the conductor structure CV0 and the width L1 of CV1 can be the same or different. Figures 14 to 17 In the embodiment of the present invention, the shapes and widths of the dummy structures DY0 and DY1 can be referred to in the above reference. Figures 9 to 12 In this example, by setting the dummy structures DY0 and DY1, the redistribution layer RDL2 can achieve the required flatness. Therefore, the redistribution layer RDL2 does not need to be provided with the dummy structure DY2, and the conductor structures CV2 and CV3 of the redistribution layers RDL2 and RDL3 can be arranged at any position according to the design or need. Figures 14 to 17 The redistribution layers RDL2 and RDL3 are not shown.

[0096] The flatness DOP0 of the under bump metallurgy structure UBM and the flatness DOP1 of the redistribution layer RDL1 can reach 95% or more, and the flatness DOP2 of the redistribution layer RDL2 and the flatness DOP3 of the redistribution layer RDL3 can be greater than 75%, or even reach 95% or more.

[0097] Reference Fig.18 In some embodiments, the redistribution layer RDL1 does not include a dummy structure. By providing dummy structures DY0 and DY2 in the under bump metallization structure UBM and the redistribution layer RDL2, the redistribution layer RDL2 can have a high flatness DOP2, so that the conductor structure CV3 of the redistribution layer RDL3 can be formed on the redistribution layer RDL2 with high flatness. Therefore, the dummy structure DY1 may not be provided around the conductor structure CV1 of the redistribution layer RDL1. Figures 19 to 22 Several embodiments are shown to illustrate various redistribution structures RDLS.

[0098] Reference Figures 19 to 22 The conductor structures CV0, CV1, and CV2 of the under-bump metallization structure UBM and the redistribution layers RDL1 and RDL2 are all in the shape of long strips. The widths of the conductor structures CV0, CV2, and CV1 may be the same or different. Figures 19 to 22 In the embodiment, the extension directions of the conductor structures CV0, CV1, and CV2 can be the same or different. The extension direction of the conductor structure CV0 is different from the extension direction of the conductor structures CV1 and CV2, and partially overlaps with the conductor structures CV1 and CV2. The conductor structure CV2 has the same extension direction as CV1, and partially overlaps with it.

[0099] exist Figures 19 to 22 In the embodiment of the present invention, the dummy structures DY0 and DY2 are respectively in the shape of a square, a circle, a polygon and a strip. The dummy structures DY0 and DY2 respectively have a single shape, but are not limited thereto. The size of the dummy structure DY2 is smaller than the size of the dummy structure DY0, but is not limited thereto. The width of the dummy structure DY0 may be equal to that of the conductor structure CV0, and the width of the dummy structure DY2 may be equal to that of the conductor structure CV2, but are not limited thereto. The positions of the dummy structure DY0 and the dummy structure DY2 may completely overlap, partially overlap or not overlap. Similarly, the positions of the dummy structure DY0 and the conductor structure CV2 may completely overlap, partially overlap or not overlap. The positions of the dummy structure DY0 and the conductor structure CV1 may completely overlap, partially overlap or not overlap. In Figures 19 to 22 In the figure, the positions of the dummy structure DY0 and the dummy structure DY2 may completely overlap or partially overlap. The positions of the dummy structure DY0 and the conductor structure CV2 do not overlap. The positions of the dummy structure DY0 and the conductor structure CV1 partially overlap, but this is not limited to this. To avoid the drawing being too complicated, Figures 19 to 22The redistribution layer RDL3 is not shown.

[0100] The flatness DOP0 of the under-bump metal layer structure UBM, the flatness DOP1 of the redistribution layer RDL1, and the flatness DOP2 of the redistribution layer RDL2 can reach 95% or more. The flatness DOP3 of the redistribution layer RDL3 can be greater than 75%, or even reach 95%, or more. In this example, by setting up the dummy structures DY0 and DY2, the redistribution layer RDL2 can already achieve the required flatness. Therefore, the redistribution layer RDL1 does not need to set up the dummy structure DY1, and the conductor structures CV2 and CV3 of the redistribution layers RDL2 and RDL3 can be configured at any position according to the design or need. Therefore, in Figures 19 to 22 The redistribution layer RDL3 is not shown.

[0101] In some embodiments, the above-mentioned under bump metallurgy structure UBM and the redistribution structure RDLS are independent components. In other embodiments, the above-mentioned under bump metallurgy structure UBM can also be regarded as a part of the redistribution structure RDLS.

[0102] Fig.23 and Fig.24 For a manufacturing flow chart of a redistribution structure and an under-bump metallization structure according to an embodiment of the present invention, please refer to Fig.23 In step S10, the method for manufacturing the redistribution layer and the metal layer under the ball according to the embodiment of the present invention can first design the metal layer structure UBM under the bump and the conductor structure of each layer of the redistribution layer according to actual needs. Step S12, confirm the position of the key pattern. The key pattern is, for example, a high-frequency signal line set in the redistribution layer RDL3. Step S14, confirm the thickness, line width and gap width of each conductor structure under the key pattern, such as the thickness, line width and gap width of the metal layer structure UBM under the bump, RDL1, and RDL2. Step S16, confirm the thickness of each dielectric layer and the viscosity coefficient of its material.

[0103] Step S20, setting a dummy structure of the under bump metallurgy structure UBM. When setting the dummy structure of the under bump metallurgy structure UBM, the size (such as width, length, diameter) of the dummy structure, the gap width between the dummy structure and the conductor structure, and the gap width between the dummy structures are set.

[0104] In step S22 , the process parameters of each layer are brought into the simulation structure to simulate the electrical properties of the key pattern.

[0105] If the electrical properties of the key pattern simulated in step S22 meet the requirements, the drawings of the under bump metallization layer structures UBM, RDL1, RDL2 and RDL3 can be directly produced without setting dummy structures in the redistribution layers RDL1, RDL2 or RDL3, as described in step S24.

[0106] If the electrical properties of the key pattern simulated in step S22 do not meet the requirements, step S30 or step S40 is performed, or step S20 is returned to. Returning to step S20, the dummy structures can be set with dummy structures of different widths and different gap widths.

[0107] In some embodiments, steps S20 to S24 may be omitted, and step S30 or step S40 may be performed directly after step S16.

[0108] Step S30, setting the dummy structure of the redistribution layer RDL1. When setting the dummy structure of RDL1, the size (such as width, length, diameter) of the dummy structure, the gap width between the dummy structure and the conductor structure, and the gap width between the dummy structures are set.

[0109] Step S32 , bringing the process parameters of each layer into the simulation structure to simulate the electrical properties of the key pattern.

[0110] If the electrical properties of the key pattern simulated in step S32 meet the requirements, the drawings of the under bump metallurgy structures UBM, RDL1, RDL2 and RDL3 can be directly produced without setting up dummy structures in the redistribution layers RDL2 or RDL3, as described in step S34.

[0111] If the electrical properties of the key pattern simulated in step S32 do not meet the requirements, step S40 is performed, or step S20 or step S30 is returned to step S20 or S30. Returning to step S20 or S30, the dummy structures can be set with different widths of dummy structures and different gap widths.

[0112] Step S40, setting the dummy structure of RDL2. When setting the dummy structure of RDL2, it includes setting the size (such as width, length, diameter) of the dummy structure, the gap width between the dummy structure and the conductor structure, and the gap width between the dummy structures.

[0113] In step S42, the process parameters of each layer are brought into the simulation structure to simulate the electrical properties of the key pattern.

[0114] If the electrical properties of the key pattern simulated in step S42 meet the requirements, the drawings of the under bump metallurgy structures UBM, RDL1, RDL2 and RDL3 can be directly produced without setting up dummy structures in the redistribution layer RDL3, as described in step S44.

[0115] If the electrical properties of the key pattern simulated in step S42 do not meet the requirements, the process returns to step S20 , S30 or S40 to set up dummy structures with different widths and different gap widths.

[0116] Reference Fig.24 After the drawing is produced, step S52 is performed to transfer the pattern of the drawing to a photomask, and then step S54 is performed to transfer the pattern of the photomask to the photoresist layer. Then, step S56 is performed to transfer the pattern of the patterned photoresist layer to the conductor layer through an etching process to form a conductor structure and a dummy structure. These steps can be combined with FIG. 25A to FIG. 25H To explain it.

[0117] FIG. 25A to FIG. 25H It is a cross-sectional view of a process of a method for manufacturing a packaging structure according to an embodiment of the present invention.

[0118] Please refer to Fig.25A , a release layer 12 is first formed on the substrate 10, and then an under-bump metallization structure UBM is formed. The under-bump metallization structure UBM includes a conductor structure CV0, a ​​dummy structure DY0, and a dielectric layer PM0. The conductor structure CV0 and the dummy structure DY0 are not electrically connected. The conductor structure CV0 and the dummy structure DY0 can be arranged according to Fig.24 The dielectric layer PM0 is formed after the conductor structure CV0 and the dummy structure DY0 are formed.

[0119] Please refer to Fig.25B and 25C , patterning the unplanarized dielectric layer PM0 to define a through-hole opening (not shown). Afterwards, a conductor structure CV1 and a dummy structure DY1 are formed on the dielectric layer PM0 and in the through-hole opening, and then the dielectric layer PM1 is formed. The conductor structure CV1, the dummy structure DY1 and the dielectric layer PM1 form a redistribution layer RDL1. The conductor structure CV1 includes a trace T1 and a through-hole V1. The trace t1 of the conductor structure CV1 is electrically connected to the conductor structure CV0 through the through-hole v1. The dummy structure DY1 is disposed around the conductor structure CV1. The dummy structure DY1 is floating, electrically insulated from the conductor structure CV1 and CV0, and electrically insulated from the dummy structure DY0. The conductor structure CV1 and the dummy structure DY1 can be arranged according to Fig.24 The dielectric layer PM1 is formed after the conductor structure CV1 and the dummy structure DY1 are formed to cover the conductor structure CV1 and the dummy structure DY1.

[0120] Please refer to Figures 25D to 25G, redistribution layers RDL2 and RDL3 are formed according to the method of redistribution layer RDL1. Redistribution layer RDL2 includes conductor structure CV2 and dummy structure DY2 which are not electrically connected to each other and dielectric layer PM2. Conductor structure CV2 includes trace t2 and through hole v2. Trace t2 of conductor structure CV2 is electrically connected to conductor structure CV1 through through hole v2. Dummy structure DY2 is arranged around conductor structure CV2. Dummy structure DY2 is floating and electrically insulated from conductor structure CV2 and CV1. Dielectric layer PM2 covers conductor structure CV2 and dummy structure DY2. Redistribution layer RDL3 includes conductor structure CV3 and dielectric layer PM3. Conductor structure CV3 includes trace t3 and through hole v3. Trace t3 of conductor structure CV3 is electrically connected to conductor structure CV2 through through hole v3. Dielectric layer PM3 covers conductor structure CV3.

[0121] Please refer to Fig.25H The dielectric layer PM3 that has not been planarized is patterned to define the location of the through hole opening. Then, a connection terminal 14 is formed on the dielectric layer PM0 and in the through hole opening. Thereafter, the connection terminal 14 is bonded to the tube die 16.

[0122] In this embodiment, the flatness DOP0 of the under bump metallization structure UBM, the flatness DOP1 of the redistribution layer RDL1, and the flatness DOP2 of the redistribution layer RDL2 can reach 95% or more. Therefore, the conductor structure CV3 of the redistribution layer RDL3 can be formed on the redistribution layer RDL2 having high flatness.

[0123] Simulation Example 1

[0124] Simulate the impact of the flatness DOP of various redistribution layers (RDL) on the electrical properties of the upper layer routing. The results are as follows Fig.26 As shown. Fig.26 The results show that as DOP decreases, the insertion loss increases significantly. When DOP exceeds 95%, the electrical loss can be reduced to within the design requirements.

[0125] Simulation Example 2

[0126] Square or strip copper conductor structures with a thickness of 10 μm and a width of L were used as dummy structures of the redistribution layer RDL, and the dummy structures were arranged into arrays with a gap width S of 1 times and 2 times the width L. Afterwards, a PSPI dielectric layer with a thickness of 1.1 to 1.6 times the thickness of the conductor structure was coated to simulate the flatness DOP of the redistribution layer RDL, and the results are shown in Table 1.

[0127] Table 1

[0128]

[0129] Simulation Comparison Example 1

[0130] A PSPI dielectric layer with a thickness ranging from 1.1 to 1.6 times the thickness of the conductor structure is coated on a single copper conductor structure of different widths to simulate the flatness DOP of the redistribution layer RDL. The results are shown in Table 2.

[0131] Table 2

[0132]

[0133] The results in Tables 1 and 2 show that the smaller the width of the copper conductor structure, the greater the flatness DOP. However, the flatness DOP of the copper pad with a width of 10μm still cannot reach 95%. The flatness DOP of the redistribution layer RDL with multiple dummy structures is greater than the flatness DOP of the redistribution layer RDL with only a single dummy structure. The flatness DOP of the redistribution layer RDL with a ratio of the width L of the dummy structure to the gap width S of 1:1 is greater than the flatness DOP of the redistribution layer RDL with a ratio of the width L of the dummy structure to the gap width S of 1:2. In addition, the flatness DOP of the redistribution layer RDL with a square dummy structure is slightly greater than the flatness DOP of the redistribution layer RDL with a long strip dummy structure.

[0134] Simulation Example 3

[0135] Square copper conductor structures with different widths L are used as dummy structures and arranged into arrays with different gap widths S. Afterwards, a PSPI dielectric layer with a thickness of 1.1 to 1.6 times the thickness of the conductor structure is coated to simulate the flatness DOP of the redistribution layer RDL. The results are shown in Table 3.

[0136] Table 3

[0137]

[0138]

[0139]

[0140] The results in Table 3 show that when the width of the dummy structure is the same, the smaller the width of the gap, the higher the density of the dummy structure and the greater the flatness DOP. For example, in the case where the width of the dummy structure is 10 microns, the width of the gap changes from 20 microns to 5 microns, and the flatness DOP increases from 86.9% to 99.4%.

[0141] Furthermore, for a dummy structure with a width of 10 microns, the ratio L / S is controlled at 1, and the flatness DOP can reach 95.9%. For a dummy structure with a width of 20 microns, the ratio L / S is controlled at 1, and the flatness DOP can reach 83.3%. For a dummy structure with a width of 40 microns, the ratio L / S is controlled at 1, and the flatness DOP is only 59.8%. In other words, the flatness DOP obtained by a dummy structure with a small width will be greater than the flatness DOP obtained by a dummy structure with a large width. A dummy structure with a small width can obtain a relatively large flatness DOP with a small ratio L / S, and a dummy structure with a large width must have a larger ratio L / S to obtain the same flatness DOP.

[0142] Simulation Example 4

[0143] Copper with different thicknesses and different widths L is used as the conductor structure of RDL, and a dummy structure is set around the conductor structure with different gap widths S. After that, a PSPI dielectric layer with a thickness of 1.1 to 1.6 times the thickness of the conductor structure is coated. The ratio L / S of the conductor structure width L to the gap width S and the ratio range of the conductor structure width L to the dummy structure width D required for the simulated flatness DOP to be 95% are shown in Table 4.

[0144] Table 4

[0145]

[0146] The results in Table 4 show that for a conductor structure with a thickness of 1 to 8 microns, or even greater than 8 microns, the flatness DOP can reach 95% by controlling the ratio of the conductor structure width L to the gap width S to be greater than 1 / 2.

[0147] Furthermore, for conductor structures with a width greater than 100 microns, the ratio L / S of conductor structures with a thickness of 1 to 4 microns is controlled to be greater than or equal to 8, and the flatness DOP of the redistribution layer RDL can reach 95%; while the ratio L / S of conductor structures with a thickness greater than or equal to 8 microns must be controlled to be greater than or equal to 12, and the flatness DOP of the redistribution layer RDL can reach 95%. Compared with conductor structures with a small thickness, conductor structures with a large thickness must have a larger ratio L / S, and the redistribution layer RDL can have the same flatness.

[0148] In addition, for conductor structures of the same thickness, the larger the width L of the conductor structure, the larger the ratio L / S must be to achieve a flatness DOP of 95%. For example, for a conductor structure with a thickness of 4 to 8 microns and a width L less than 10 microns, a ratio L / S greater than or equal to 3 / 2 can achieve a flatness DOP of 95%; and for a conductor structure with a thickness of 4 to 8 microns and a width L greater than 100 microns, a ratio L / S must be greater than or equal to 10 / 1 to achieve a flatness DOP of 95%.

[0149] For a conductor structure with a thickness of 1 to 8 microns, or even greater than 8 microns, the ratio of the width L of the conductor structure to the width D of the dummy structure is controlled between 1:1 and 10:1, and the flatness DOP can reach 95%.

[0150] In addition, compared with a conductor structure with the same thickness but a smaller width L, a conductor structure with a larger width L has a ratio L / D within a wider range, which can make the flatness DOP reach 95%. Compared with a conductor structure with the same thickness but a larger width L, the range of the ratio L / D of the conductor structure with a smaller width L must be reduced to make the flatness DOP reach 95%. In other words, the larger the conductor structure width L, the larger the range of the ratio L / D that can make the flatness DOP reach 95%.

[0151] For example, for a conductor structure with a thickness of 4 to 8 microns and a width L greater than 100 microns, the flatness DOP can reach 95% by controlling the ratio L / D in the range of 1 / 1 to 10 / 1; and for a conductor structure with a thickness of 4 to 8 microns but a width L less than 10 microns, the ratio L / D must be controlled at 1 to achieve a flatness DOP of 95%.

[0152] Simulation Example 5

[0153] A copper with a thickness T1 of 9 μm and a width L1 of 10 μm is used as the conductor structure CV1 of the RDL, and a copper with a width D1 of 10 μm is set around the conductor structure with a gap width S1 of 10 μm to serve as a dummy structure DY1 of the RDL1. Thereafter, a PSPI dielectric layer PM1 with a thickness of 1.1 to 1.6 times the thickness of the conductor structure CV1 is coated to form a redistribution layer RDL1. Thereafter, a redistribution layer RDL2 is formed on the redistribution layer RDL1. The conductor structure CV2 of RDL2 is a copper with a thickness T2 of 5 μm, a width L2 of 5 μm, and a gap width S2 of 3 μm. The dielectric layer PM2 is a PSPI with a thickness of 1.1 to 1.6 times the thickness of the conductor structure CV2. Thereafter, a redistribution layer RDL3 is formed on RDL2. The conductor structure CV3 of RDL3 is a copper with a thickness T3 of 2 μm, a width L3 of 2 μm, and a gap width S3 of 2 μm. The dielectric layer PM3 is PSPI 1.1 to 1.6 times the thickness of the conductor structure CV3 .

[0154] Simulation Comparison Example 2

[0155] RDL1 , RDL2 and RDL3 of the second simulation comparison example are similar to DL1 , RDL2 and RDL3 of the fifth simulation example, but RDL1 does not include the dummy structure DY1 .

[0156] The results show that in the simulation comparison example 2, the flatness of the redistribution layer RDL1 without the dummy structure DY1 is 60%. In the simulation example 5, the flatness of the redistribution layer RDL1 including the dummy structure DY1 can reach 95%. This means that the setting of the dummy structure DY1 helps to improve the flatness of the redistribution layer RDL1.

[0157] An embodiment of the present invention adds a dummy structure around the conductor structure of the redistribution layer and controls the width of the dummy structure and the width of the gap between the dummy structure and the conductor structure, thereby improving the process yield of the upper conductor structure and reducing the electrical loss of the upper conductor structure.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A rewiring structure, characterized in that: include: The first redistribution layer includes: Dielectric layer; at least one conductor structure located in the dielectric layer, the at least one conductor structure having a width L; and at least one dummy structure, located beside the at least one conductor structure and in the dielectric layer, and the dummy structure has a width D, There is a gap width S between the at least one dummy structure and the at least one conductor structure, and the flatness DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1-(h / T)]×100% h refers to the difference between the highest height and the lowest height of the top surface of the dielectric layer; and T is the thickness of the at least one conductor structure, The at least one dummy structure includes a plurality of dummy structures, and a density of the plurality of dummy structures in a region of the first redistribution layer with a large flatness DOP is greater than a density of the plurality of dummy structures in a region of the first redistribution layer with a small flatness DOP. 2 . The redistribution structure according to claim 1 , wherein a ratio L / S of the width L to the gap width S is 1 / 2 to 12 / 1. 3 . The redistribution structure according to claim 1 , wherein a ratio L / S of the width L to the gap width S is 1 / 2 to 10 / 1. 4 . The redistribution structure according to claim 1 , wherein a ratio L / D of the width L to the width D of the dummy structure is 1 / 1 to 10 / 1. 5 . The redistribution structure according to claim 1 , wherein the width D of the plurality of dummy structures in the region of the first redistribution layer having a large flatness DOP is smaller than the width D of the plurality of dummy structures in the region of the first redistribution layer having a small flatness DOP. 6 . The redistribution structure according to claim 1 , further comprising a second redistribution layer, wherein a flatness of the second redistribution layer is less than or equal to the flatness DOP of the first redistribution layer. 7 . The redistribution structure according to claim 1 , wherein the at least one conductor structure comprises a plurality of conductor structures, and the at least one dummy structure is disposed between the plurality of conductor structures. 8 . The rewiring structure according to claim 1 , further comprising an under bump metallurgy (UBM) structure located below the first rewiring layer, wherein a flatness of the under bump metallurgy (UBM) structure is less than or equal to a DOP of the first rewiring layer.

9. A method for forming a redistribution structure, characterized in that: include: Forming a first redistribution layer, comprising: forming at least one conductor structure; According to the thickness T and the width L of the at least one conductor structure, forming at least one dummy structure next to the at least one conductor structure; and A dielectric layer is coated between and on the at least one conductor structure and the at least one dummy structure, and the at least one dummy structure is formed so that the flatness DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1-(h / T)]×100% h refers to the difference between the highest height and the lowest height of the top surface of the dielectric layer; and T refers to the thickness of the at least one conductor structure, The at least one dummy structure includes a plurality of dummy structures, and a density of the plurality of dummy structures in a region of the first redistribution layer with a large flatness DOP is greater than a density of the plurality of dummy structures in a region of the first redistribution layer with a small flatness DOP. 10 . The method for forming a redistribution structure according to claim 9 , wherein a gap width S is provided between the at least one dummy structure and the at least one conductor structure, and a ratio L / S of the width L to the gap width S is 1 / 2 to 12 / 1. 11 . The method for forming a redistribution structure according to claim 10 , wherein when the width L of the at least one conductor structure is larger, the ratio L / S is larger so that the flatness DOP reaches 95%. 12 . The method for forming a redistribution structure according to claim 9 , wherein a ratio L / D of the width L of the at least one conductor structure to the width D of the at least one dummy structure is 1 / 1 to 10 / 1. 13 . The method for forming a redistribution structure according to claim 12 , wherein the greater the width L of the at least one conductor structure, the greater the range of the ratio L / D for achieving 95% of the flatness DOP.

14. The method for forming a redistribution structure according to claim 9, further comprising: A second redistribution layer is formed before forming the first redistribution layer, and a flatness of the second redistribution layer is less than or equal to a flatness DOP of the first redistribution layer.

15. The method for forming a redistribution structure according to claim 9, further comprising: An under bump metallurgy structure is formed before forming the first redistribution layer, and a flatness of the under bump metallurgy structure is less than or equal to the flatness DOP of the first redistribution layer. 16 . The method for forming a redistribution structure according to claim 9 , wherein the smaller the width D of the plurality of dummy structures is, the larger the flatness DOP of the first redistribution layer is. 17 . The method for forming a redistribution structure according to claim 9 , wherein the higher the density of the plurality of dummy structures is, the greater the DOP of the first redistribution layer is.

18. The method for forming a redistribution structure according to claim 9, wherein a width D of the plurality of dummy structures in an area of ​​the first redistribution layer with a large flatness DOP is smaller than a width D of the plurality of dummy structures in an area of ​​the first redistribution layer with a small flatness DOP.

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