Circuit substrate and preparation method thereof and insulated gate bipolar transistor module

Abstract

The present application relates to a circuit substrate, a preparation method, and an insulated gate bipolar transistor module. The insulated gate bipolar transistor module includes a circuit substrate and a power chip, a solder layer is provided between the circuit substrate and the power chip, the circuit substrate includes a first heat-conducting layer, a second heat-conducting layer, and a third heat-conducting layer stacked in sequence in a direction away from the power chip, and the power chip is connected to the first heat-conducting layer via the solder layer; a first heat diffusion angle is formed between the solder layer and the first heat-conducting layer, and a second heat diffusion angle is formed between the second heat-conducting layer and the third heat-conducting layer; the first heat diffusion angle is greater than the second heat diffusion angle, and the thickness of the first heat-conducting layer is greater than the thickness of the third heat-conducting layer; or the first heat diffusion angle is less than the second heat diffusion angle, and the thickness of the first heat-conducting layer is less than the thickness of the third heat-conducting layer. The configuration of the present application improves the heat dissipation effect of the insulated gate bipolar transistor module and reduces the probability of relaxation or even cracking of each layer of material.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a circuit substrate and a preparation method thereof, and an insulated gate bipolar transistor module. Background Art

[0002] Thermal degradation of insulated gate bipolar transistor (IGBT) modules is caused by fatigue damage due to thermal stress. Factors contributing to module degradation include electrical, thermal, and mechanical factors. Thermal degradation primarily results from the gradual accumulation of internal fatigue and the combined effects of external operating conditions. This in turn leads to electrical degradation due to electrical shifts and mechanical degradation due to stress in the solder layer, which causes cracks. Therefore, studying the thermal degradation mechanisms of IGBT modules is of great significance.

[0003] The IGBT module includes a copper-clad ceramic substrate (Direct Bonding Copper, DBC for short). Typically, the DBC substrate includes a ceramic layer and copper layers arranged on both sides of the ceramic layer. The copper layers on both sides of the ceramic layer have the same thickness. Under long-term or high-frequency use, the DBC has a poor heat dissipation effect, which affects the heat dissipation effect of the IGBT module. Summary of the Invention

[0004] The purpose of the present application is to provide a circuit substrate and a preparation method thereof, and an insulated gate bipolar transistor module to solve the problem of poor heat dissipation effect of the circuit substrate and the insulated gate bipolar transistor module.

[0005] To this end, a first aspect includes a circuit substrate and a power chip, a solder layer is arranged between the circuit substrate and the power chip, the circuit substrate includes a first heat-conducting layer, a second heat-conducting layer and a third heat-conducting layer stacked in sequence in a direction away from the power chip, and the power chip is connected to the first heat-conducting layer through the solder layer; a first heat diffusion angle is formed between the solder layer and the first heat-conducting layer, and a second heat diffusion angle is formed between the second heat-conducting layer and the third heat-conducting layer; wherein the first heat diffusion angle is greater than the second heat diffusion angle, and the thickness of the first heat-conducting layer is greater than the thickness of the third heat-conducting layer; or the first heat diffusion angle is less than the second heat diffusion angle, and the thickness of the first heat-conducting layer is less than the thickness of the third heat-conducting layer.

[0006] In one possible implementation, the second heat-conducting layer includes a first substrate and a second substrate stacked and spaced apart, the third heat-conducting layer includes a third substrate and a fourth substrate stacked and spaced apart, and the first substrate, the third substrate, the second substrate, and the fourth substrate are stacked in sequence along the direction of the first heat-conducting layer away from the power chip; the second heat diffusion angle is formed between the first substrate and the third substrate, and the second heat diffusion angle is formed between the second substrate and the fourth substrate.

[0007] In one possible implementation, the thermal conductivity of the first substrate is equal to the thermal conductivity of the second substrate, the thermal conductivity of the third substrate, the thermal conductivity of the fourth substrate, and the thermal conductivity of the first thermal conductive layer are the same, and the thermal conductivity of the solder layer is greater than or less than the thermal conductivity of the first substrate.

[0008] In one possible implementation, the first heat diffusion angle is greater than the second heat diffusion angle, the sum of the thicknesses of the circuit substrates is 0.8 mm-1.2 mm, the sum of the thicknesses of the first substrate and the second substrate is 1 / 7 of the circuit substrate, and the sum of the thicknesses of the first heat conductive layer, the third substrate, and the fourth substrate is 6 / 7 of the circuit substrate.

[0009] In one possible implementation, the material of the first thermal conductive layer, the third substrate, and the fourth substrate includes copper; and / or the material of the first substrate and the second substrate includes ceramic; and / or the material of the power chip includes silicon; and / or the material of the solder layer includes lead and tin.

[0010] In a possible implementation, a cooling plate is further included, and the cooling plate is disposed on a side of the circuit substrate away from the power chip.

[0011] In a second aspect, an embodiment of the present application provides a circuit substrate for electrically connecting to a power chip of an insulated gate bipolar transistor module, the circuit substrate comprising a first thermally conductive layer, a second thermally conductive layer, and a third thermally conductive layer arranged in a direction away from the power chip, the power chip being connected to the first thermally conductive layer via a solder layer; a first thermal diffusion angle is formed between the solder layer and the first thermally conductive layer, and a second thermal diffusion angle is formed between the second thermally conductive layer and the third thermally conductive layer; wherein the first thermal diffusion angle is greater than the second thermal diffusion angle, and the thickness of the first thermally conductive layer is greater than the thickness of the third thermally conductive layer; or the first thermal diffusion angle is less than the second thermal diffusion angle, and the thickness of the first thermally conductive layer is less than the thickness of the third thermally conductive layer.

[0012] In one possible implementation, the second heat-conducting layer includes a first substrate and a second substrate stacked and spaced apart, the third heat-conducting layer includes a third substrate and a fourth substrate stacked and spaced apart, the first substrate, the third substrate, the second substrate, and the fourth substrate are stacked in sequence along the direction of the first heat-conducting layer away from the power chip; the second heat diffusion angle is formed between the first substrate and the third substrate, and the second heat diffusion angle is formed between the second substrate and the fourth substrate.

[0013] In a third aspect, an embodiment of the present application provides a method for preparing a circuit substrate, comprising using an alkaline solution to clean the oily components on the surfaces of the first thermal conductive layer and the third thermal conductive layer, and using an acidic solution to clean the oxide layer on the surfaces of the first thermal conductive layer and the third thermal conductive layer; using an alkaline solution to clean the surface of the second thermal conductive layer; stacking the first thermal conductive layer, the second thermal conductive layer and the third thermal conductive layer in sequence to form a substrate assembly; and placing the substrate assembly on a supporting plate for sintering.

[0014] In one possible implementation, the second heat-conducting layer includes a first substrate and a second substrate that are stacked and spaced apart, and the third heat-conducting layer includes a third substrate and a fourth substrate that are stacked and spaced apart. The first substrate, the third substrate, the second substrate, and the fourth substrate are stacked in sequence along the direction of the first heat-conducting layer away from the power chip, and the first heat-conducting layer, the first substrate, the third substrate, the second substrate, and the fourth substrate are stacked in sequence to form a substrate assembly.

[0015] According to an embodiment of the present application, an insulated gate bipolar transistor module is provided, which includes a circuit substrate and a power chip. A solder layer is provided between the circuit substrate and the power chip. The circuit substrate includes a first thermal conductive layer, a second thermal conductive layer, and a third thermal conductive layer stacked in a direction away from the power chip. The power chip is connected to the first thermal conductive layer via the solder layer. A first thermal diffusion angle is formed between the solder layer and the first thermal conductive layer, and a second thermal diffusion angle is formed between the second thermal conductive layer and the third thermal conductive layer. When the first thermal diffusion angle is greater than the second thermal diffusion angle, the thickness of the first thermal conductive layer is greater than the thickness of the third thermal conductive layer; or when the first thermal diffusion angle is less than the second thermal diffusion angle, the thickness of the first thermal conductive layer is less than the thickness of the third thermal conductive layer. The present application adjusts the thickness of the first thermal conductive layer and the thickness of the third thermal conductive layer by setting the first thermal diffusion angle and the second thermal diffusion angle. Compared with the prior art insulated gate bipolar transistor module settings, the settings of the present application improve the heat dissipation effect of the insulated gate bipolar transistor module and reduce the probability of relaxation or even cracking of each layer of material. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive work. In addition, in the drawings, the same reference numerals are used for the same components, and the drawings are not drawn according to the actual scale.

[0017] Figure 1 A partial structural schematic diagram of an insulated gate bipolar transistor module provided by an embodiment is shown.

[0018] Description of reference numerals:

[0019] 1. Circuit substrate; 11. First heat-conducting layer; 12. Second heat-conducting layer; 121. First substrate; 122. Second substrate; 13. Third heat-conducting layer; 131. Third substrate; 132. Fourth substrate; 2. Power chip; 3. Solder layer. DETAILED DESCRIPTION

[0020] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] like Figure 1 , Figure 1 A partial structural diagram of an insulated gate bipolar transistor module provided in an embodiment is shown. The embodiment of the present application provides an insulated gate bipolar transistor module, an insulated gate bipolar transistor (IGBT) module.

[0022] IGBT modules inevitably experience wear when subjected to stress. Thermal analysis of IGBT modules shows that each material layer has varying thermal conductivity, subjecting each layer to varying degrees of thermal stress. Thermal stress can accelerate material degradation. In reality, any material will experience some degree of thermal damage at any temperature. For most materials, thermal fatigue accumulates rapidly at high temperatures, and the degree of thermal fatigue depends on the accumulation of temperature-related thermal damage intensity over time. Without a time limit, any temperature is unsafe, indicating that any material will continuously fatigue and degrade under the influence of temperature. Under variable-current operating conditions, IGBT modules are subject to continuous high-temperature and shock thermal damage, making them a typical thermal fatigue device. Under real-world operating conditions, the environmental stresses to which IGBT modules are subjected vary randomly, and the power intensity stress also varies cyclically. Consequently, module losses and chip junction temperatures vary.

[0023] The IGBT module includes a circuit substrate 1 and a power chip 2 , with a solder layer 3 provided between the circuit substrate 1 and the power chip 2 .

[0024] The circuit substrate 1 may be a direct bonding copper (DBC) substrate. The circuit substrate 1 includes a first thermally conductive layer 11, a second thermally conductive layer 12, and a third thermally conductive layer 13 stacked in sequence in a direction away from the power chip 2. The power chip 2 is connected to the first thermally conductive layer 11 via a solder layer 3. A first thermal diffusion angle is formed between the solder layer 3 and the first thermally conductive layer 11, and a second thermal diffusion angle is formed between the second thermally conductive layer 12 and the third thermally conductive layer 13. The first thermal diffusion angle is greater than the second thermal diffusion angle, and the thickness of the first thermally conductive layer 11 is greater than the thickness of the third thermally conductive layer 13. Alternatively, the first thermal diffusion angle is less than the second thermal diffusion angle, and the thickness of the first thermally conductive layer 11 is less than the thickness of the third thermally conductive layer 13.

[0025] It's important to understand that heat transfer affecting the IGBT module can occur both vertically and horizontally. Vertical heat dissipation is determined by thermal resistance, which is determined by the surface area and thickness of the heat dissipation structure. Compared to conventional IGBT modules, the surface area and thickness of the IGBT module in this application remain virtually unchanged, thus maintaining no vertical heat transfer. Lateral heat transfer is measured by the heat diffusion angle, primarily expressed as the heat diffusion area S.

[0026] Ignoring the thermal diffusion angle between the power chip 2 and the solder layer 3, the thermal diffusion area S of the IGBT module is calculated as y1tanα1+dtanα2+y2tanα3. A larger thermal diffusion area S improves lateral heat conduction. Here, y1 is the thickness of the first thermal conductive layer 11; d is the thickness of the second thermal conductive layer 12; y2 is the thickness of the third thermal conductive layer 13; and α is the thermal diffusion angle. The thermal diffusion angle α is calculated using the formula: α = arctan(k1 / k2) (0 < α < 90), where k1 and k2 represent the thermal expansion coefficients of the previous thermal conductive layer and the current material layer, respectively. For example, the first thermal diffusion angle α1 = arctan(thermal expansion coefficient of solder layer 3 / thermal expansion coefficient of first thermal conductive layer 11), the second thermal diffusion angle α2 = arctan(thermal expansion coefficient of second thermal conductive layer 12 / thermal expansion coefficient of third thermal conductive layer 13), and the third thermal diffusion angle α3 = arctan(thermal expansion coefficient of first thermal conductive layer 11 / thermal expansion coefficient of second thermal conductive layer 12).

[0027] The first thermal diffusion angle α1 is greater than the second thermal diffusion angle α2; during use, heat conduction occurs between the power chip 2 and the solder layer 3, heat conduction occurs between the solder layer 3 and the first thermal conductive layer 11, heat conduction occurs between the first thermal conductive layer 11 and the second thermal conductive layer 12, and heat conduction occurs between the second thermal conductive layer 12 and the third thermal conductive layer 13. When the thicknesses of the first thermal conductive layer 11, the second thermal conductive layer 12, and the third thermal conductive layer 13 remain unchanged, the first thermal diffusion angle α1 is greater than the second thermal diffusion angle α2. Compared to when the first thermal diffusion angle α1 is less than or equal to the second thermal diffusion angle α2, heat transfer from the power chip 2 to the first thermal conductive layer 11 is better, thereby increasing the heat transfer rate from the power chip 2 to the circuit substrate 1, improving the heat dissipation effect of the IGBT module, and reducing the probability of relaxation or even cracking of the various layers of material in this application.

[0028] Furthermore, the first thermal diffusion angle α1 is greater than the second thermal diffusion angle α2, and the thickness of the first thermal conductive layer 11 is greater than the thickness of the third thermal conductive layer 13. According to the calculation formula of the thermal diffusion area S of the IGBT module, compared with the case where the thickness of the first thermal conductive layer 11 is less than or equal to the thickness of the third thermal conductive layer 13, the present application improves the heat dissipation effect of the power chip 2, the solder layer 3 and the circuit substrate 1, that is, improves the heat dissipation effect of the IGBT module.

[0029] Furthermore, the first thermal diffusion angle α1 is smaller than the second thermal diffusion angle α2, and the thickness of the first thermal conductive layer 11 is smaller than the thickness of the third thermal conductive layer 13. According to the calculation formula of the thermal diffusion area S of the IGBT module, compared with the case where the thickness of the first thermal conductive layer 11 is greater than or equal to the thickness of the third thermal conductive layer 13, the present application improves the heat dissipation effect of the power chip 2, the solder layer 3 and the circuit substrate 1, that is, improves the heat dissipation effect of the IGBT module.

[0030] In one embodiment, in an optional example, the second heat-conducting layer 12 includes a first substrate 121 and a second substrate 122 stacked and spaced apart, and the third heat-conducting layer 13 includes a third substrate 131 and a fourth substrate 132 stacked and spaced apart, and the first substrate 121, the third substrate 131, the second substrate 122 and the fourth substrate 132 are stacked in sequence along the direction of the first heat-conducting layer 11 away from the power chip 2; the second heat diffusion angle is formed between the first substrate 121 and the third substrate 131, and the second heat diffusion angle is formed between the second substrate 122 and the fourth substrate 132.

[0031] The sum of the thicknesses of the second thermally conductive layer 12 is equal to the sum of the thicknesses of the first and second substrates 121, 122. The sum of the thicknesses of the third thermally conductive layer 13 is equal to the sum of the thicknesses of the third and fourth substrates 131, 132. The first and second substrates 121, 122 are spaced apart, while the third and fourth substrates 131, 132 are spaced apart. That is, the third substrate 131 is disposed between the first and second substrates 121, 122, and the second substrate 122 is disposed between the third and fourth substrates 131, 132. Because a second heat diffusion angle is formed between the second and third thermally conductive layers 12, 13, the second heat diffusion angle is formed between the first and third substrates 121, 131, and the second heat diffusion angle is also formed between the second and fourth substrates 122, 132.

[0032] In one embodiment, the thermal conductivity of the first substrate 121 is equal to the thermal conductivity of the second substrate 122, the thermal conductivity of the third substrate 131, the thermal conductivity of the fourth substrate 132 and the thermal conductivity of the first thermal conductive layer 11 are the same, and the thermal conductivity of the solder layer 3 is greater than or less than the thermal conductivity of the first substrate 121.

[0033] According to the calculation formula for the thermal diffusion angle α: α = arctan(k1 / k2) (0 < α < 90), where k1 and k2 represent the thermal expansion coefficients of the previous heat-conducting layer and the current material layer, respectively, the first thermal diffusion angle α1, the second thermal diffusion angle α2, and the third thermal diffusion angle α3 are calculated. The first thermal diffusion angle α1 is greater than the second thermal diffusion angle α2. When the thermal conductivity of the solder layer 3 is greater than the thermal conductivity of the first substrate 121, the first thermal diffusion angle α1 is greater than the second thermal diffusion angle. When the thermal conductivity of the solder layer 3 is less than the thermal conductivity of the first substrate 121, the first thermal diffusion angle α1 is less than the second thermal diffusion angle α2.

[0034] In one embodiment, when the first heat diffusion angle is greater than the second heat diffusion angle, the total thickness of the circuit substrate 1 is 0.8 mm to 1.2 mm, the thickness of the first substrate 121 and the second substrate 122 is 1 / 7 of the thickness of the circuit substrate 1, and the total thickness of the first thermal conductive layer 11, the third substrate 131, and the fourth substrate 132 is 6 / 7 of the thickness of the circuit substrate 1. The total thickness of the circuit substrate 1 of the present application is the same as the total thickness of the circuit substrate 1 in the prior art; therefore, the total thickness of the first thermal conductive layer 11, the second thermal conductive layer 12, and the third thermal conductive layer 13 is the same as the total thickness of the circuit substrate 1 in the prior art. When the total thickness of the circuit substrate 1 is 1 mm, the thickness of the first substrate 121 and the second substrate 122 is 1 / 7 mm, and the total thickness of the first thermal conductive layer 11, the third substrate 131, and the fourth substrate 132 is 6 / 7 mm.

[0035] In one embodiment, the material of the first thermal conductive layer 11, the third substrate 131 and the fourth substrate 132 includes copper; and / or, the material of the first substrate 121 and the second substrate 122 includes ceramic; and / or, the material of the power chip 2 includes silicon; and / or, the material of the solder layer 3 includes lead and tin.

[0036] It should be understood that the first thermally conductive layer 11, the third substrate 131, and the fourth substrate 132 are conductive layers. The first thermally conductive layer 11 is used for connecting external parts, such as power chips and pins. The first thermally conductive layer 11 can be made of a conductive metal material, such as copper, copper-manganese alloy, copper-zinc alloy, copper-aluminum alloy, copper-magnesium alloy, copper-zirconium alloy, or copper-nickel-magnesium alloy. The first substrate 121 and the second substrate 122 are insulating layers, and can be made of ceramic materials, such as aluminum oxide, aluminum nitride, beryllium oxide, or silicon carbide. The material of the power chip 2 can be selected from single crystal silicon, quartz, or graphite. The material of the solder layer 3 can be a mixture of lead and tin in any proportion.

[0037] In one example, copper is used as the material for the first and third thermally conductive layers 11 and 13. Copper has an extremely high current-carrying capacity, which can reduce the size of the intercepting medium and increase power capacity. The second thermally conductive layer 12 is typically made of ceramic, particularly aluminum nitride. Aluminum nitride is non-toxic, has a moderate dielectric constant, and a thermal conductivity significantly higher than that of aluminum oxide and beryllium oxide. Its coefficient of thermal expansion is similar to that of silicon. Various silicon chips and high-power devices can be directly attached to aluminum nitride substrates without the use of additional transition layers. While this material is relatively costly, it currently holds promise for application in circuit substrate technology.

[0038] The material of the first heat conducting layer 11, the third substrate 131 and the fourth substrate 132 is copper, that is, the thermal expansion coefficient of the first heat conducting layer 11, the third substrate 131 and the fourth substrate 132 is 17.5*10 -6m / K; the first substrate 121 and the second substrate 122 are made of ceramic and have a thermal expansion coefficient of 7*10 -6 m / K; the power chip 2 is a silicon plate and has a thermal expansion coefficient of 3*10 -6 m / K, solder 3 is a mixture of lead and tin and has a thermal expansion coefficient of 28*10 -6 m / K. According to the calculation formula of the thermal diffusion angle, the first thermal diffusion angle α1 is 58 degrees, the second thermal diffusion angle α2 is 22 degrees, and the third thermal diffusion angle α3 is 68 degrees, that is, the first thermal diffusion angle α1 is greater than the second thermal diffusion angle α2.

[0039] In an example, the thickness of the first substrate 121 and the second substrate 122 are equal to 1 / 14 mm, the sum of the thickness of the first substrate 121 and the second substrate 122 is 1 / 7 mm, the thickness of the third substrate 131 and the fourth substrate 132 are both 1 / 7 mm, the sum of the thickness of the third substrate 131 and the fourth substrate 132 is 2 / 7 mm, and the thickness of the first thermal conductive layer 11 is 4 / 7 mm. After calculation, it is found that the heat diffusion area S of the present application is equal to y1tanα1+dtanα2+y2tanα3, which is equal to 64.418. Compared with the heat diffusion area of 23.927 in the prior art, the IGBT module of the present application has a larger lateral heat diffusion area and higher heat dissipation efficiency.

[0040] The areas of the first heat-conducting layer 11 and the third heat-conducting layer 13 are both smaller than the area of the second heat-conducting layer 12, that is, the areas of the first heat-conducting layer 11, the third substrate 131, and the fourth substrate 132 are all smaller than the area of the first substrate 121 or the area of the second substrate 122. When the first substrate 121, the third substrate 131, the second substrate 122, and the fourth substrate 132 are stacked in sequence along the direction of the first heat-conducting layer 11 away from the power chip 2, that is, the first heat-conducting layer 11 and the third heat-conducting layer 13 are arranged in a cross-arrangement, compared with the case where the areas of the first heat-conducting layer 11, the third heat-conducting layer 13, and the second heat-conducting layer 12 are the same, the present application further improves the heat dissipation effect of the IGBT module.

[0041] In an optional example, the IGBT module further includes a cooling plate, which is disposed on a side of the circuit substrate 1 away from the power chip 2. The cooling plate can be made of insulating material to transfer heat from the circuit substrate 1 and improve the heat dissipation effect of the circuit substrate 1.

[0042] like Figure 1In an optional example, a method for preparing a circuit substrate 1 includes using an alkaline solution to clean the oily components on the surfaces of the first thermal conductive layer 11 and the third thermal conductive layer 13, and using an acidic solution to clean the oxide layer on the surfaces of the first thermal conductive layer 11 and the third thermal conductive layer 13; using an alkaline solution to clean the surface of the second thermal conductive layer 12; stacking the first thermal conductive layer 11, the second thermal conductive layer 12 and the third thermal conductive layer 13 in sequence to form a substrate assembly; and placing the substrate assembly on a support plate for sintering.

[0043] It should be understood that during the preparation process, the first heat conducting layer 11 and the third heat conducting layer 13 may be cleaned simultaneously.

[0044] Cleaning the first heat-conducting layer 11 and the third heat-conducting layer 13 includes two steps. The first step is to treat the first heat-conducting layer 11 and the third heat-conducting layer 13 with an alkaline solution. The first heat-conducting layer 11 and the third heat-conducting layer 13 can be immersed in the alkaline solution or wiped to clean the grease on the surface of the first heat-conducting layer 11 and the third heat-conducting layer 13. Commonly used alkaline solutions can be used, such as sodium hydroxide solution or other alkaline solutions. The second step is to clean the grease on the surface of the first heat-conducting layer 11 and the third heat-conducting layer 13 with an acidic solution. The first heat-conducting layer 11 and the third heat-conducting layer 13 can be immersed in the acidic solution or wiped to clean the oxide layer on the surface of the first heat-conducting layer 11 and the third heat-conducting layer 13. Commonly used acidic solutions can be used, such as hydrochloric acid solution or other acidic solutions.

[0045] When cleaning the second heat-conducting layer 12 , the second heat-conducting layer 12 may be immersed in an acidic solution or the surface of the second heat-conducting layer 12 may be cleaned by wiping.

[0046] After the first heat-conducting layer 11 , the second heat-conducting layer 12 and the third heat-conducting layer 13 are cleaned, they are stacked to form a substrate assembly, and then the substrate assembly is placed on a setter plate for sintering.

[0047] After sintering, the circuit substrate 1 is formed, and the first heat-conducting layer 11, the second heat-conducting layer 12 and the third heat-conducting layer 13 have sufficient adhesion strength. The adhesion strength of the first heat-conducting layer 11, the second heat-conducting layer 12 and the third heat-conducting layer 13 in the circuit substrate 1 with good connection is close to the level of thick film metallization.

[0048] In an optional example, the second thermal conductive layer 12 includes a first substrate 121 and a second substrate 122 stacked and spaced apart, and the third thermal conductive layer 13 includes a third substrate 131 and a fourth substrate 132 stacked and spaced apart. The first substrate 121, the third substrate 131, the second substrate 122 and the fourth substrate 132 are stacked in sequence along the direction of the first thermal conductive layer 11 away from the power chip 2, and the first substrate 121, the third substrate 131, the second substrate 122 and the fourth substrate 132 are stacked in sequence to form a substrate assembly.

[0049] It should be understood that when assembling the substrate assembly, the first substrate 121 and the second substrate 122 in the second thermally conductive layer 12 must be spaced apart, and the third substrate 131 and the fourth substrate 132 in the third thermally conductive layer 13 must be spaced apart. That is, the stacking order is first thermally conductive layer 11, second thermally conductive layer 12, and third thermally conductive layer 13. When preparing the IGBT module, the power chip 2 is soldered to the side of the first thermally conductive layer 11 facing away from the second thermally conductive layer 12 via the solder layer 3.

[0050] It should be noted that references in this specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not.

[0051] It should be readily understood that “on,” “above,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers therebetween, and “above” or “over” includes not only the meaning of “above” or “over,” but also includes “above” or “over” with no intervening features or layers therebetween (i.e., directly on something).

[0052] Additionally, spatially relative terms, such as "below," "beneath," "beneath," "above," and the like, may be used herein for ease of description to describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0053] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An insulated gate bipolar transistor module, characterized in that: The invention comprises a circuit substrate and a power chip, wherein a solder layer is provided between the circuit substrate and the power chip, the circuit substrate comprises a first heat-conducting layer, a second heat-conducting layer, and a third heat-conducting layer stacked in sequence in a direction away from the power chip, and the power chip is connected to the first heat-conducting layer through the solder layer; A first heat diffusion angle is formed between the solder layer and the first heat conducting layer, and a second heat diffusion angle is formed between the second heat conducting layer and the third heat conducting layer; The first heat diffusion angle is greater than the second heat diffusion angle, and the thickness of the first heat conducting layer is greater than the thickness of the third heat conducting layer; or the first heat diffusion angle is less than the second heat diffusion angle, and the thickness of the first heat conducting layer is less than the thickness of the third heat conducting layer.

2. The insulated gate bipolar transistor module according to claim 1, wherein: The second heat-conducting layer includes a first substrate and a second substrate stacked and spaced apart, and the third heat-conducting layer includes a third substrate and a fourth substrate stacked and spaced apart, wherein the first substrate, the third substrate, the second substrate, and the fourth substrate are stacked in sequence along the direction of the first heat-conducting layer away from the power chip; The second heat diffusion angle is formed between the first substrate and the third substrate, and the second heat diffusion angle is formed between the second substrate and the fourth substrate.

3. The insulated gate bipolar transistor module according to claim 2, wherein: The thermal conductivity of the first substrate is equal to that of the second substrate, the thermal conductivity of the third substrate, the thermal conductivity of the fourth substrate and the thermal conductivity of the first thermal conductive layer are the same, and the thermal conductivity of the solder layer is greater than or less than that of the first substrate.

4. The insulated gate bipolar transistor module according to claim 2, wherein: The first heat diffusion angle is greater than the second heat diffusion angle, the sum of the thicknesses of the circuit substrates is 0.8 mm-1.2 mm, the sum of the thicknesses of the first substrate and the second substrate is 1 / 7 of the circuit substrate, and the sum of the thicknesses of the first heat conductive layer, the third substrate and the fourth substrate is 6 / 7 of the circuit substrate.

5. The insulated gate bipolar transistor module according to claim 2, wherein: The first heat-conducting layer, the third substrate, and the fourth substrate are made of copper; And / or, the material of the first substrate and the second substrate includes ceramic; And / or, the material of the power chip includes silicon; And / or, the material of the solder layer includes lead and tin.

6. The insulated gate bipolar transistor module according to claim 1, wherein: It also includes a cooling plate, which is arranged on a side of the circuit substrate away from the power chip.

7. A circuit substrate for electrically connecting to a power chip of an insulated gate bipolar transistor module, characterized in that: The circuit substrate comprises a first heat-conducting layer, a second heat-conducting layer and a third heat-conducting layer arranged in a direction away from the power chip, and the power chip is connected to the first heat-conducting layer through a solder layer; A first heat diffusion angle is formed between the solder layer and the first heat conducting layer, and a second heat diffusion angle is formed between the second heat conducting layer and the third heat conducting layer; The first heat diffusion angle is greater than the second heat diffusion angle, and the thickness of the first heat conducting layer is greater than the thickness of the third heat conducting layer; or the first heat diffusion angle is less than the second heat diffusion angle, and the thickness of the first heat conducting layer is less than the thickness of the third heat conducting layer.

8. The circuit substrate according to claim 7, wherein: The second heat-conducting layer includes a first substrate and a second substrate stacked and spaced apart, and the third heat-conducting layer includes a third substrate and a fourth substrate stacked and spaced apart, wherein the first substrate, the third substrate, the second substrate, and the fourth substrate are stacked in sequence along the direction of the first heat-conducting layer away from the power chip; The second heat diffusion angle is formed between the first substrate and the third substrate, and the second heat diffusion angle is formed between the second substrate and the fourth substrate.

9. A method for preparing a circuit substrate according to claim 7 or 8, characterized in that: include: Cleaning the oily components on the surfaces of the first heat conducting layer and the third heat conducting layer with an alkaline solution, and cleaning the oxide layers on the surfaces of the first heat conducting layer and the third heat conducting layer with an acidic solution; Cleaning the surface of the second heat-conducting layer with an alkaline solution; stacking the first heat-conducting layer, the second heat-conducting layer and the third heat-conducting layer in sequence to form a substrate assembly; The substrate assembly is placed on a setter plate for sintering.

10. The method for preparing a circuit substrate according to claim 9, wherein: The second heat-conducting layer includes a first substrate and a second substrate that are stacked and spaced apart, and the third heat-conducting layer includes a third substrate and a fourth substrate that are stacked and spaced apart. The first substrate, the third substrate, the second substrate, and the fourth substrate are stacked in sequence along the direction of the first heat-conducting layer away from the power chip. The first heat-conducting layer, the first substrate, the third substrate, the second substrate, and the fourth substrate are stacked in sequence and bonded to form a substrate assembly.

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