Floating-gate split-gate flash memory device and its manufacturing method

Abstract

The present invention discloses a floating gate split-gate flash memory device, wherein the first gate structure comprises a floating gate dielectric layer, a floating gate polysilicon layer, an inter-polysilicon dielectric layer and a control gate polysilicon layer. The outer side surface of the first inner side wall defines the outer side surface of the first gate structure, the inner side surface of the first inner side wall defines the inner side surfaces of the inter-polysilicon dielectric layer and the control gate polysilicon layer, and the inner side surfaces of the floating gate dielectric layer and the floating gate polysilicon layer are self-aligned and defined by the second inner side wall of the inner side surface of the first inner side wall. The second gate structure is self-aligned and formed on the inner side surface of the first gate structure. The lightly doped drain region and the outer pocket injection region are both self-aligned with the outer side surface of the first gate structure. The inner pocket injection region is self-aligned with the inner side surface of the control gate polysilicon layer. The source-drain injection region is self-aligned with the outer side wall of the outer side surface of the first gate structure. The present invention also discloses a method for manufacturing a floating gate split-gate flash memory device. The present invention can reduce the short channel effect of the device and simultaneously improve the withstand voltage of the source-drain junction.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a floating gate split gate flash memory device. The present invention also relates to a method for manufacturing the floating gate split gate flash memory device. Background Art

[0002] like Figure 1 , which is a schematic diagram of the structure of a device unit structure of an existing floating gate split-gate flash memory device; Figure 1 The device cell structure shown is a 2-bit NORD type flash memory cell. Taking an N-type device as an example, the device cell structure of an existing floating gate split gate flash memory device includes:

[0003] The first gate structure formed on the P-type doped semiconductor substrate 101 includes a floating gate dielectric layer 102, a floating gate polysilicon layer 103, an inter-polysilicon dielectric layer 104 and a control gate polysilicon layer 105 which are stacked in sequence.

[0004] A first inner sidewall 106 is formed on the top of the control gate polysilicon layer 105, the inner side surfaces of the control gate polysilicon layer 105 and the inter-polysilicon dielectric layer 104 are self-aligned and defined by the inner side surfaces of the first inner sidewall 106, the outer side surfaces of the control gate polysilicon layer 105, the inter-polysilicon dielectric layer 104, the floating gate polysilicon layer 103 and the floating gate dielectric layer 102 are self-aligned and defined by the outer side surfaces of the first inner sidewall 106, and the outer side surfaces of the first inner sidewall 106, the control gate polysilicon layer 105, the inter-polysilicon dielectric layer 104, the floating gate polysilicon layer 103 and the floating gate dielectric layer 102 are superimposed to form the outer side surface of the first gate structure.

[0005] The second inner sidewall 108 is self-alignedly formed on the inner side surfaces of the inter-polysilicon dielectric layer 104, the control gate polysilicon layer 105 and the first inner sidewall 106, the inner side surfaces of the floating gate polysilicon layer 103 and the floating gate dielectric layer 102 are self-alignedly defined by the inner side surfaces of the second inner sidewall 108, and the inner side surfaces of the second inner sidewall 108, the floating gate polysilicon layer 103 and the floating gate dielectric layer 102 are superimposed to form the inner side surface of the first gate structure.

[0006] An outer wall 113 is formed on the outer side of the first gate structure.

[0007] The second gate structure is formed on the semiconductor substrate 101 within the inner side surface of the first gate structure in a self-aligned manner, and the second gate structure includes a select gate dielectric layer 109 and a select gate polysilicon layer 110 stacked in sequence.

[0008] Figure 1In the embodiment, a protective dielectric layer 111 is further formed on the surface of the select gate polysilicon 110 .

[0009] Also formed in the semiconductor substrate 101 are an N-type lightly doped drain region (LDD) 112 , an N-type heavily doped source / drain injection region 114 , a threshold voltage adjustment region 115 of a selection transistor, and a threshold voltage adjustment region 107 of a floating gate storage transistor.

[0010] The lightly doped drain region 112 is self-aligned with the outer side surface of the first gate structure.

[0011] The source / drain implantation region 114 and the outer side surface of the outer sidewall 113 are self-aligned.

[0012] The threshold voltage adjustment region 115 of the selection transistor and the inner side surface of the floating gate polysilicon layer 103 are self-aligned.

[0013] Since the device unit structure is a 2-bit NORD type structure, the device unit structure includes two first gate structures and one second gate structure. The lightly doped drain region 112 and the source-drain injection region 114 both include two symmetrical ones, and the channel region is located between the two source-drain injection regions 114. The first gate structure and the second gate structure perform segmented control on the channel region. The threshold voltage adjustment region 107 of the floating gate storage tube is self-aligned with the outer side surfaces of the two first gate structures.

[0014] As the size of the device unit structure shrinks, the short channel effect of the device becomes more serious, the control ability of the control gate becomes weaker and weaker, the threshold voltage of the cell decreases, and the leakage current increases.

[0015] An effective method to control the short channel effect of the device is to reduce the doping dose and ion implantation energy of the N-type LDD of the cell and add P-type pocket ion implantation. However, Flash cell devices are different from CMOS devices. The source and drain of the device are the bit lines of the cell, which require high voltage. High pocket doping and shallow LDD junctions are not allowed. How to solve the contradiction between suppressing the short channel effect and ensuring that the bit line can withstand high voltage is the technical problem to be solved by the present invention. Summary of the invention

[0016] The technical problem to be solved by the present invention is to provide a floating gate split gate flash memory device, which can reduce the short channel effect of the device and at the same time improve the withstand voltage of the source-drain junction so as to achieve high voltage resistance of the bit line. To this end, the present invention also provides a method for manufacturing a floating gate split gate flash memory device.

[0017] In order to solve the above technical problems, the device unit structure of the floating gate split-gate flash memory device provided by the present invention comprises:

[0018] The first gate structure formed on the semiconductor substrate doped with the second conductivity type includes a floating gate dielectric layer, a floating gate polysilicon layer, an inter-polysilicon dielectric layer and a control gate polysilicon layer stacked in sequence.

[0019] A first inner sidewall is formed on the top of the control gate polysilicon layer, the inner side surfaces of the control gate polysilicon layer and the inter-polysilicon dielectric layer are defined by self-alignment of the inner side surface of the first inner sidewall, the outer side surfaces of the control gate polysilicon layer, the inter-polysilicon dielectric layer, the floating gate polysilicon layer and the floating gate dielectric layer are defined by self-alignment of the outer side surface of the first inner sidewall, and the outer side surfaces of the first inner sidewall, the control gate polysilicon layer, the inter-polysilicon dielectric layer, the floating gate polysilicon layer and the floating gate dielectric layer are superimposed to form the outer side surface of the first gate structure.

[0020] The second inner sidewall is self-aligned and formed on the inner side surfaces of the inter-polysilicon dielectric layer, the control gate polysilicon layer and the first inner sidewall, the inner side surfaces of the floating gate polysilicon layer and the floating gate dielectric layer are self-aligned and defined by the inner side surfaces of the second inner sidewall, and the inner side surfaces of the second inner sidewall, the floating gate polysilicon layer and the floating gate dielectric layer are superimposed to form the inner side surface of the first gate structure.

[0021] An outer sidewall is formed on the outer side of the first gate structure.

[0022] The second gate structure is formed on the semiconductor substrate within the inner side of the first gate structure in a self-aligned manner, and the second gate structure includes a select gate dielectric layer and a select gate polysilicon layer stacked in sequence.

[0023] A lightly doped drain region of the first conductivity type, an outer pocket injection region doped with the second conductivity type, an inner pocket injection region doped with the second conductivity type, and a heavily doped source and drain injection region of the first conductivity type are also formed in the semiconductor substrate.

[0024] The lightly doped drain region is self-aligned with an outer side surface of the first gate structure.

[0025] The outer pocket implant region is self-aligned with an outer side surface of the first gate structure.

[0026] The inner pocket implantation region and the inner side surface of the control gate polysilicon layer are self-aligned.

[0027] The source / drain injection region and the outer side surface of the outer side wall are self-aligned.

[0028] The source-drain injection region is connected to a bit line.

[0029] The first gate structure and the second gate structure perform segmented control on the channel region, and a short channel effect control structure is formed by the lightly doped drain region, the outer pocket injection region and the inner pocket injection region.

[0030] The PN junction formed between the outer pocket injection region and the source-drain injection region serves as a voltage-withstanding structure for the bit line voltage.

[0031] The doping dose of the outer pocket injection region is less than the doping dose of the inner pocket injection region, and the total dose of the doping dose of the outer pocket injection region and the doping dose of the inner pocket injection region is used to ensure that the requirements for short channel effect control are met; the doping dose of the outer pocket injection region is reduced to meet the withstand voltage requirements at the source and drain injection regions.

[0032] A further improvement is that the doping concentration of the inner pocket injection region has the characteristic of gradually decreasing from the surface of the semiconductor substrate downwards.

[0033] A first groove is formed in the bottom area of ​​the second gate structure by etching the semiconductor material of the semiconductor substrate. The first groove is self-aligned with the inner side surface of the first gate structure. The depth of the first groove is less than the depth of the inner pocket injection region, so that the contact position between the selection gate dielectric layer of the second gate structure and the inner pocket injection region is located below the surface of the semiconductor substrate. The inner pocket injection region located below the first groove is used as the threshold voltage adjustment region of the selection tube so that the threshold voltage of the selection tube meets the requirements.

[0034] A further improvement is that the threshold voltage adjustment region of the selection tube is composed of a first injection region doped with a first conductive type superimposed on the inner pocket injection region, the first injection region and the inner side surface of the first gate structure are self-aligned, the net doping of the overlapping region of the first injection region and the inner pocket injection region is the second conductive type, and the first injection region reduces the surface concentration of the inner pocket injection region to meet the threshold voltage requirement of the selection tube.

[0035] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0036] A further improvement is that the device unit structure is a 2-bit NORD type structure, and the device unit structure includes two first gate structures and one second gate structure.

[0037] The second gate structure is formed in a self-aligned manner between inner side surfaces of two first gate structures.

[0038] The lightly doped drain region is formed in the semiconductor substrate at the outer side surfaces of the two first gate structures in a self-aligned manner.

[0039] The two source-drain implantation regions are formed in the semiconductor substrate at the outer side surfaces of the outer sidewalls of the two first gate structures in a self-aligned manner.

[0040] The inner pocket implantation region is formed in a self-aligned manner between inner side surfaces of the control gate polysilicon layers of the two first gate structures.

[0041] A further improvement is that the inter-polysilicon dielectric layer is an ONO layer.

[0042] A further improvement is that a well region doped with a second conductivity type is also formed on the semiconductor substrate, and the lightly doped drain region, the outer pocket injection region, the inner pocket injection region and the source and drain injection region are all formed in the surface area of ​​the well region.

[0043] A further improvement is that a second threshold voltage adjustment region doped with a second conductive type is also formed in the semiconductor substrate aligned with the outer side surfaces of the two first gate structures, and the second threshold voltage adjustment region is used to adjust the threshold voltage of the floating gate storage tube and achieve anti-punch-through, and the threshold voltage of the floating gate storage tube is determined by the coverage of the second threshold voltage adjustment region at the bottom by the floating gate polysilicon layer through the floating gate dielectric layer.

[0044] A further improvement is that the device unit structure is an N-type structure, the first conductivity type is N-type, and the second conductivity type is P-type.

[0045] In order to solve the above technical problems, in the manufacturing method of the floating gate split-gate flash memory device provided by the present invention, the step of forming the device unit structure includes:

[0046] Step 1: forming a floating gate dielectric layer, a floating gate polysilicon layer, an inter-polysilicon dielectric layer and a control gate polysilicon layer in sequence on the surface of the semiconductor substrate doped with the second conductivity type.

[0047] Step 2: forming a hard mask layer, and patterning and etching the hard mask layer to form a first opening.

[0048] Step three: forming a first inner wall on the inner side of the first opening.

[0049] Step 4: etching the control gate polysilicon layer and the inter-polysilicon dielectric layer in sequence with the inner side surface of the first inner sidewall as a self-alignment condition to form the inner sidewalls of the control gate polysilicon layer and the inter-polysilicon dielectric layer.

[0050] Step 5: With the inner side surface of the control gate polysilicon layer as a self-aligned condition, a first pocket implantation of the second conductive type doping is performed to form an inner pocket implantation region. The first pocket implantation is an angled implantation.

[0051] Step six: forming a second inner sidewall by self-alignment on the inner side surfaces of the inter-polysilicon dielectric layer, the control gate polysilicon layer, and the first inner sidewall.

[0052] Step seven, etching the floating gate polysilicon layer and the floating gate dielectric layer with the inner side surface of the second inner sidewall as a self-alignment condition to form the inner side surfaces of the floating gate polysilicon layer and the floating gate dielectric layer; the inner side surfaces of the second inner sidewall, the floating gate polysilicon layer and the floating gate dielectric layer are superimposed to form the inner side surface of the first gate structure.

[0053] Step eight: forming a second gate structure on the semiconductor substrate within the inner side surface of the first gate structure by self-alignment, wherein the second gate structure includes a select gate dielectric layer and a select gate polysilicon layer stacked in sequence.

[0054] Step nine: removing the hard mask layer to expose the outer side surface of the first inner sidewall.

[0055] Step ten, taking the outer side surface of the first inner sidewall as a self-alignment condition, the control gate polysilicon layer, the inter-polysilicon dielectric layer, the floating gate polysilicon layer and the floating gate dielectric layer are sequentially etched to form the outer side surfaces of the control gate polysilicon layer, the inter-polysilicon dielectric layer, the floating gate polysilicon layer and the floating gate dielectric layer, and the outer side surfaces of the first inner sidewall, the control gate polysilicon layer, the inter-polysilicon dielectric layer, the floating gate polysilicon layer and the floating gate dielectric layer are superimposed to form the outer side surface of the first gate structure.

[0056] Step 11: Performing lightly doped drain implantation of a first conductivity type lightly doped with the outer side surface of the first gate structure as a self-alignment condition to form a lightly doped drain region.

[0057] Step 12: Perform a second pocket implantation of the second conductive type doping under a self-aligned condition on the outer side surface of the first gate structure to form an outer pocket implantation region. The second pocket implantation is an angled implantation.

[0058] Step 13: forming an outer wall on the outer side of the outer side surface of the first gate structure by self-alignment.

[0059] Step 14: Using the outer side surface of the outer wall as a self-alignment condition, perform a second source and drain implantation with heavy doping of the conductive type to form a source and drain implantation region.

[0060] The source and drain implantation regions are connected to the bit lines.

[0061] The first gate structure and the second gate structure perform segmented control on the channel region, and a short channel effect control structure is formed by the lightly doped drain region, the outer pocket injection region and the inner pocket injection region.

[0062] The PN junction formed between the outer pocket injection region and the source-drain injection region serves as a voltage-withstanding structure for the bit line voltage.

[0063] The doping dose of the outer pocket injection region is less than the doping dose of the inner pocket injection region, and the total dose of the doping dose of the outer pocket injection region and the doping dose of the inner pocket injection region is used to ensure that the requirements for short channel effect control are met; the doping dose of the outer pocket injection region is reduced to meet the withstand voltage requirements at the source and drain injection regions.

[0064] A further improvement is that the doping concentration of the inner pocket injection region has the characteristic of gradually decreasing from the surface of the semiconductor substrate downwards;

[0065] After step 7 is completed and before step 8 of growing the select gate dielectric layer is performed, the following steps are further included:

[0066] The semiconductor material of the semiconductor substrate is continuously etched to form a first groove using the inner side surface of the first gate structure as a self-alignment condition.

[0067] The depth of the first groove is less than the depth of the inner pocket injection region, so that the contact position between the selection gate dielectric layer of the second gate structure and the inner pocket injection region is located below the surface of the semiconductor substrate. The inner pocket injection region located below the first groove is used as the threshold voltage adjustment region of the selection tube so that the threshold voltage of the selection tube meets the requirements.

[0068] A further improvement is that after step 7 is completed and before step 8 of growing the select gate dielectric layer is performed, the method further includes:

[0069] Ions of the first conductive type doping are implanted using the inner side surface of the first gate structure as a self-alignment condition to form a first implantation region.

[0070] The threshold voltage adjustment region of the selection tube is composed of a first injection region doped with a first conductive type superimposed on the inner pocket injection region, the net doping of the overlapping region of the first injection region and the inner pocket injection region is the second conductive type, and the first injection region reduces the surface concentration of the inner pocket injection region to meet the threshold voltage requirement of the selection tube.

[0071] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0072] A further improvement is that the device unit structure is a 2-bit NORD type structure, and the device unit structure includes two first gate structures and one second gate structure.

[0073] The first opening defines a region between two outer side surfaces of the first gate structures.

[0074] The second gate structure is formed in a self-aligned manner between inner side surfaces of two first gate structures.

[0075] The lightly doped drain region is formed in the semiconductor substrate at the outer side surfaces of the two first gate structures in a self-aligned manner.

[0076] The two source-drain implantation regions are formed in the semiconductor substrate at the outer side surfaces of the outer sidewalls of the two first gate structures in a self-aligned manner.

[0077] The inner pocket implantation region is formed in a self-aligned manner between inner side surfaces of the control gate polysilicon layers of the two first gate structures.

[0078] A further improvement is that the inter-polysilicon dielectric layer is an ONO layer.

[0079] A further improvement is that a well region doped with a second conductivity type is also formed on the semiconductor substrate, and the lightly doped drain region, the outer pocket injection region, the inner pocket injection region and the source and drain injection region are all formed in the surface area of ​​the well region.

[0080] A further improvement is that, after the first opening is formed in step 2 and before step 3, the method further includes:

[0081] Ions doped with a second conductive type are implanted using the hard mask layer as a mask to form a second threshold voltage adjustment region, wherein the second threshold voltage adjustment region is used to adjust the threshold voltage of the floating gate storage tube and achieve anti-punch-through, and the threshold voltage of the floating gate storage tube is determined by the coverage of the second threshold voltage adjustment region at the bottom by the floating gate polysilicon layer through the floating gate dielectric layer.

[0082] A further improvement is that the device unit structure is an N-type structure, the first conductivity type is N-type, and the second conductivity type is P-type.

[0083] A further improvement is that the injection dose of the first pocket injection is less than 1e13cm -2 The injection dose of the second pocket injection is greater than 1e13cm -2 .

[0084] The present invention makes a special arrangement for the pocket injection area of ​​the device unit structure of the floating gate split gate flash memory device, that is, the pocket injection area is divided into an outer pocket injection area and an inner pocket injection area, wherein the formation process of the outer pocket injection area is the same as that of the prior art and adopts the same self-alignment condition as the lightly doped drain area, while the inner pocket injection area is self-aligned with the inner side surface of the control gate polysilicon layer, and under the condition that the channel area includes the outer pocket injection area and the inner pocket injection area, due to the increase of the second conductive type doping impurities in the channel area, the short channel effect will be reduced. On this basis, that is, on the basis of ensuring that the requirements of the short channel effect are met, the doping concentration of the outer pocket injection area can be reduced, so that the voltage resistance of the PN junction, that is, the source-drain junction, of the source-drain injection area will increase, the source-drain injection area of ​​the device unit structure of the floating gate split gate flash memory device will be connected to the bit line, the bit line will be connected to a high voltage, when the voltage resistance of the source-drain junction increases, the high voltage applied to the bit line will increase, so the high voltage resistance of the bit line will increase. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0086] Figure 1 It is a structural schematic diagram of a device unit structure of an existing floating gate split-gate flash memory device;

[0087] Figure 2 It is a structural schematic diagram of a device unit structure of a floating gate split-gate flash memory device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0088] like Figure 2 , which is a schematic diagram of a device unit structure of a floating gate split gate flash memory device according to an embodiment of the present invention. The device unit structure of a floating gate split gate flash memory device according to an embodiment of the present invention includes:

[0089] The first gate structure formed on the semiconductor substrate 301 doped with the second conductivity type includes a floating gate dielectric layer 302, a floating gate polysilicon layer 303, an inter-polysilicon dielectric layer 304 and a control gate polysilicon layer 305 stacked in sequence.

[0090] A first inner sidewall 306 is formed on the top of the control gate polysilicon layer 305, and the inner side surfaces of the control gate polysilicon layer 305 and the inter-polysilicon dielectric layer 304 are self-aligned and defined by the inner side surfaces of the first inner sidewall 306. The outer side surfaces of the control gate polysilicon layer 305, the inter-polysilicon dielectric layer 304, the floating gate polysilicon layer 303 and the floating gate dielectric layer 302 are self-aligned and defined by the outer side surfaces of the first inner sidewall 306. The outer side surfaces of the first inner sidewall 306, the control gate polysilicon layer 305, the inter-polysilicon dielectric layer 304, the floating gate polysilicon layer 303 and the floating gate dielectric layer 302 are superimposed to form the outer side surface of the first gate structure.

[0091] The second inner sidewall 308 is self-alignedly formed on the inner side surfaces of the inter-polysilicon dielectric layer 304, the control gate polysilicon layer 305 and the first inner sidewall 306, the inner side surfaces of the floating gate polysilicon layer 303 and the floating gate dielectric layer 302 are self-alignedly defined by the inner side surfaces of the second inner sidewall 308, and the inner side surfaces of the second inner sidewall 308, the floating gate polysilicon layer 303 and the floating gate dielectric layer 302 are superimposed to form the inner side surface of the first gate structure.

[0092] An outer wall 313 is formed on the outer side of the first gate structure.

[0093] The second gate structure is formed on the semiconductor substrate 301 within the inner side surface of the first gate structure in a self-aligned manner, and the second gate structure includes a select gate dielectric layer 309 and a select gate polysilicon layer 310 stacked in sequence.

[0094] Figure 2 In the embodiment, a protective dielectric layer 311 is further formed on the surface of the select gate polysilicon 310 .

[0095] Also formed in the semiconductor substrate 301 are a lightly doped drain region 312 of the first conductivity type, an outer pocket injection region 201 doped with the second conductivity type, an inner pocket injection region 202 doped with the second conductivity type, and a heavily doped source and drain injection region 314 of the first conductivity type.

[0096] The lightly doped drain region 312 is self-aligned with the outer side surface of the first gate structure.

[0097] The outer pocket implantation region 201 is self-aligned with the outer side surface of the first gate structure.

[0098] The inner pocket implantation region 202 and the inner side surface of the control gate polysilicon layer 305 are self-aligned.

[0099] The source / drain implantation region 314 and the outer side surface of the outer sidewall 313 are self-aligned.

[0100] The source-drain implantation region 314 is connected to the bit line.

[0101] The first gate structure and the second gate structure perform segmented control on the channel region, and a short channel effect control structure is formed by the lightly doped drain region 312 , the outer pocket injection region 201 , and the inner pocket injection region 202 .

[0102] The PN junction formed between the outer pocket injection region 201 and the source-drain injection region 314 serves as a voltage-withstanding structure for the bit line voltage.

[0103] The doping dose of the outer pocket injection region 201 is less than the doping dose of the inner pocket injection region 202, and the total dose of the doping dose of the outer pocket injection region 201 and the doping dose of the inner pocket injection region 202 ensures that the requirements for short channel effect control are met; the doping dose of the outer pocket injection region 201 is reduced to meet the withstand voltage requirements at the source and drain injection region 314.

[0104] In the embodiment of the present invention, the doping concentration of the inner pocket implantation region 202 has the characteristic of gradually decreasing from the surface of the semiconductor substrate 301 downwards.

[0105] A first groove 203 formed by etching the semiconductor material of the semiconductor substrate 301 is formed in the bottom region of the second gate structure, the first groove 203 is self-aligned with the inner side surface of the first gate structure, the depth of the first groove 203 is less than the depth of the inner pocket injection region 202, so that the contact position between the selection gate dielectric layer 309 of the second gate structure and the inner pocket injection region 202 is located below the surface of the semiconductor substrate 301, and the inner pocket injection region 202 located below the first groove 203 is used as the threshold voltage adjustment region of the selection tube, so that the threshold voltage of the selection tube meets the requirements. In other embodiments, it can also be: the threshold voltage adjustment region of the selection tube is composed of a first injection region doped with a first conductive type superimposed on the inner pocket injection region 202, the first injection region is self-aligned with the inner side surface of the first gate structure, the net doping of the superimposed region of the first injection region and the inner pocket injection region 202 is the second conductive type, and the first injection region reduces the surface concentration of the inner pocket injection region 202 to meet the threshold voltage requirement of the selection tube.

[0106] In the embodiment of the present invention, the semiconductor substrate 301 includes a silicon substrate.

[0107] The device unit structure is a 2-bit NORD type structure, and the device unit structure includes two first gate structures and one second gate structure.

[0108] The second gate structure is formed in a self-aligned manner between inner side surfaces of two first gate structures.

[0109] The lightly doped drain region 312 is formed in the semiconductor substrate 301 at the outer side surfaces of the two first gate structures in a self-aligned manner.

[0110] The two source-drain implantation regions 314 are formed in the semiconductor substrate 301 at the outer side surfaces of the outer sidewalls 313 of the two first gate structures in a self-aligned manner.

[0111] The inner pocket implantation region 202 is formed in a self-aligned manner between the inner side surfaces of the control gate polysilicon layer 305 of the two first gate structures.

[0112] The inter-polysilicon dielectric layer 304 is an ONO layer.

[0113] A well region doped with the second conductivity type is also formed on the semiconductor substrate 301, and the lightly doped drain region 312, the outer pocket injection region 201, the inner pocket injection region 202 and the source-drain injection region 314 are all formed in the surface area of ​​the well region.

[0114] A second threshold voltage adjustment region 307 doped with a second conductive type is also formed in the semiconductor substrate 301 aligned with the outer side surfaces of the two first gate structures. The second threshold voltage adjustment region 307 is used to adjust the threshold voltage of the floating gate storage tube and achieve anti-punch-through. The threshold voltage of the floating gate storage tube is determined by the covering of the second threshold voltage adjustment region 307 at the bottom by the floating gate polysilicon layer 303 through the floating gate dielectric layer 302.

[0115] Since the pocket implantation in the outer pocket implantation area 201 and the inner pocket implantation area 202 is performed by angled ion implantation, preferably, the implantation dose of the pocket implantation in the outer pocket implantation area 201 is less than 1e13 cm -2 The injection dose of the inner pocket injection area 202 is greater than 1e13cm -2 .

[0116] In the embodiment of the present invention, the device unit structure is an N-type structure, the first conductivity type is N-type, and the second conductivity type is P-type. The control gate polysilicon layer 305, the floating gate dielectric layer 302, and the select gate polysilicon layer 310 are all N-type doped. In other embodiments, the device unit structure can also be a P-type structure, the first conductivity type is P-type, and the second conductivity type is N-type.

[0117] The embodiment of the present invention makes a special arrangement for the pocket injection area of ​​the device unit structure of the floating gate split-gate flash memory device, that is, the pocket injection area is divided into an outer pocket injection area 201 and an inner pocket injection area 202, wherein the formation process of the outer pocket injection area 201 is the same as that of the prior art and adopts the same self-alignment conditions as the lightly doped drain area 312, while the inner pocket injection area 202 is self-aligned with the inner side surface of the control gate polysilicon layer 305. Under the condition that the channel area includes the outer pocket injection area 201 and the inner pocket injection area 202, the short channel effect will be reduced due to the increase of the second conductive type doping impurities in the channel area. On this basis, that is, on the basis of ensuring that the requirements of the short channel effect are met, the doping concentration of the outer pocket injection area 201 can be reduced, so that the voltage resistance of the PN junction, i.e. the source-drain junction, of the source-drain injection area 314 will increase, and the source-drain injection area 314 of the device unit structure of the floating gate split-gate flash memory device will be connected to the bit line, and the bit line will be connected to a high voltage. When the voltage resistance of the source-drain junction increases, the high voltage applied to the bit line will increase, and therefore the ability of the bit line to withstand high voltage will increase.

[0118] In the method for manufacturing a floating gate split-gate flash memory device according to an embodiment of the present invention, the step of forming a device unit structure includes:

[0119] Step 1: forming a floating gate dielectric layer 302, a floating gate polysilicon layer 303, an inter-polysilicon dielectric layer 304 and a control gate polysilicon layer 305 in sequence on the surface of the semiconductor substrate 301 doped with the second conductivity type.

[0120] In the method of the embodiment of the present invention, the semiconductor substrate 301 includes a silicon substrate.

[0121] The inter-polysilicon dielectric layer 304 is an ONO layer.

[0122] Step 2: forming a hard mask layer (not shown), and patterning and etching the hard mask layer to form a first opening.

[0123] Step three: forming a first inner wall 306 on the inner side of the first opening.

[0124] Step 4: The control gate polysilicon layer 305 and the inter-polysilicon dielectric layer 304 are sequentially etched with the inner side surface of the first inner sidewall 306 as a self-alignment condition to form the inner sidewalls of the control gate polysilicon layer 305 and the inter-polysilicon dielectric layer 304 .

[0125] Step 5: With the inner side surface of the control gate polysilicon layer 305 as a self-aligned condition, a first pocket implantation of the second conductive type doping is performed to form an inner pocket implantation region 202. The first pocket implantation is an angled implantation.

[0126] Step six: forming a second inner sidewall 308 on the inner side surfaces of the inter-polysilicon dielectric layer 304 , the control gate polysilicon layer 305 and the first inner sidewall 306 by self-alignment.

[0127] Step seven, etching the floating gate polysilicon layer 303 and the floating gate dielectric layer 302 with the inner side surface of the second inner sidewall 308 as a self-alignment condition to form the inner side surfaces of the floating gate polysilicon layer 303 and the floating gate dielectric layer 302; the inner side surfaces of the second inner sidewall 308, the floating gate polysilicon layer 303 and the floating gate dielectric layer 302 are superimposed to form the inner side surface of the first gate structure.

[0128] The doping concentration of the inner pocket injection region 202 has the characteristic of gradually decreasing from the surface of the semiconductor substrate 301 downwards;

[0129] After step 7 is completed and before the subsequent step 8 of growing the selection gate dielectric layer 309 is performed, the following steps are also included:

[0130] The semiconductor material of the semiconductor substrate 301 is further etched with the inner side surface of the first gate structure as a self-alignment condition to form a first groove 203 .

[0131] The depth of the first groove 203 is less than the depth of the inner pocket injection region 202, so that the contact position between the selection gate dielectric layer 309 of the second gate structure and the inner pocket injection region 202 is located below the surface of the semiconductor substrate 301, and the inner pocket injection region 202 located below the first groove 203 is used as the threshold voltage adjustment region of the selection tube so that the threshold voltage of the selection tube meets the requirements.

[0132] In other embodiments, after step 7 is completed and before the growth of the select gate dielectric layer 309 in step 8 is performed, the following steps may also be included:

[0133] Ions of the first conductive type doping are implanted using the inner side surface of the first gate structure as a self-alignment condition to form a first implantation region.

[0134] The threshold voltage adjustment region of the selection tube is composed of a first injection region doped with a first conductive type superimposed on the inner pocket injection region 202, and the net doping of the overlapping region of the first injection region and the inner pocket injection region 202 is the second conductive type. The first injection region reduces the surface concentration of the inner pocket injection region 202 to meet the threshold voltage requirement of the selection tube.

[0135] Step eight: forming a second gate structure on the semiconductor substrate 301 within the inner side surface of the first gate structure by self-alignment, wherein the second gate structure includes a select gate dielectric layer 309 and a select gate polysilicon layer 310 stacked in sequence.

[0136] Step nine: remove the hard mask layer to expose the outer side surface of the first inner sidewall 306 .

[0137] Step ten, taking the outer side surface of the first inner sidewall 306 as a self-alignment condition, the control gate polysilicon layer 305, the inter-polysilicon dielectric layer 304, the floating gate polysilicon layer 303 and the floating gate dielectric layer 302 are etched in sequence to form the outer side surfaces of the control gate polysilicon layer 305, the inter-polysilicon dielectric layer 304, the floating gate polysilicon layer 303 and the floating gate dielectric layer 302, and the outer side surfaces of the first inner sidewall 306, the control gate polysilicon layer 305, the inter-polysilicon dielectric layer 304, the floating gate polysilicon layer 303 and the floating gate dielectric layer 302 are stacked to form the outer side surface of the first gate structure.

[0138] Step 11: Perform lightly doped drain implantation of the first conductivity type lightly doped with the outer side surface of the first gate structure as a self-alignment condition to form a lightly doped drain region 312 .

[0139] Step 12: Perform a second pocket implantation of the second conductive type doping under a self-aligned condition on the outer side surface of the first gate structure to form an outer pocket implantation region 201. The second pocket implantation is an angled implantation.

[0140] Step 13: forming an outer wall 313 on the outer side of the outer side surface of the first gate structure by self-alignment.

[0141] Step 14: Using the outer side surface of the outer wall 313 as a self-alignment condition, perform a second source and drain implantation with heavily doped conductive type to form a source and drain implantation region 314 .

[0142] The source-drain implantation region 314 is connected to the bit line.

[0143] The first gate structure and the second gate structure perform segmented control on the channel region, and a short channel effect control structure is formed by the lightly doped drain region 312 , the outer pocket injection region 201 , and the inner pocket injection region 202 .

[0144] The PN junction formed between the outer pocket injection region 201 and the source-drain injection region 314 serves as a voltage-withstanding structure for the bit line voltage.

[0145] The doping dose of the outer pocket injection region 201 is less than the doping dose of the inner pocket injection region 202, and the total dose of the doping dose of the outer pocket injection region 201 and the doping dose of the inner pocket injection region 202 ensures that the requirements for short channel effect control are met; the doping dose of the outer pocket injection region 201 is reduced to meet the withstand voltage requirements at the source and drain injection region 314.

[0146] In the method of the embodiment of the present invention, the injection dose of the first pocket injection is less than 1e13cm -2 The injection dose of the second pocket injection is greater than 1e13cm -2 .

[0147] The device unit structure is a 2-bit NORD type structure, and the device unit structure includes two first gate structures and one second gate structure.

[0148] The first opening defines a region between two outer side surfaces of the first gate structures.

[0149] The second gate structure is formed in a self-aligned manner between inner side surfaces of two first gate structures.

[0150] The lightly doped drain region 312 is formed in the semiconductor substrate 301 at the outer side surfaces of the two first gate structures in a self-aligned manner.

[0151] The two source-drain implantation regions 314 are formed in the semiconductor substrate 301 at the outer side surfaces of the outer sidewalls 313 of the two first gate structures in a self-aligned manner.

[0152] The inner pocket implantation region 202 is formed in a self-aligned manner between the inner side surfaces of the control gate polysilicon layer 305 of the two first gate structures.

[0153] A well region doped with the second conductivity type is also formed on the semiconductor substrate 301, and the lightly doped drain region 312, the outer pocket injection region 201, the inner pocket injection region 202 and the source-drain injection region 314 are all formed in the surface area of ​​the well region.

[0154] After the first opening is formed in step 2 and before step 3, the method further includes:

[0155] The second conductive type doped ions are implanted using the hard mask layer as a mask to form a second threshold voltage adjustment area 307. The second threshold voltage adjustment area 307 is used to adjust the threshold voltage of the floating gate storage tube and achieve anti-punch-through. The threshold voltage of the floating gate storage tube is determined by the covering of the second threshold voltage adjustment area 307 at the bottom by the floating gate polysilicon layer 303 through the floating gate dielectric layer 302.

[0156] In the embodiment of the present invention, the device unit structure is an N-type structure, the first conductivity type is N-type, and the second conductivity type is P-type. The control gate polysilicon layer 305, the floating gate dielectric layer 302, and the select gate polysilicon layer 310 are all N-type doped. In other embodiment methods, the device unit structure can also be a P-type structure, the first conductivity type is P-type, and the second conductivity type is N-type.

[0157] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A floating gate split-gate flash memory device, characterized in that: The device unit structure includes: A first gate structure formed on a semiconductor substrate doped with a second conductivity type includes a floating gate dielectric layer, a floating gate polysilicon layer, an inter-polysilicon dielectric layer, and a control gate polysilicon layer stacked in sequence; A first inner sidewall is formed on the top of the control gate polysilicon layer, the inner side surfaces of the control gate polysilicon layer and the inter-polysilicon dielectric layer are self-aligned and defined by the inner side surface of the first inner sidewall, the outer side surfaces of the control gate polysilicon layer, the inter-polysilicon dielectric layer, the floating gate polysilicon layer and the floating gate dielectric layer are self-aligned and defined by the outer side surface of the first inner sidewall, and the outer side surfaces of the first inner sidewall, the control gate polysilicon layer, the inter-polysilicon dielectric layer, the floating gate polysilicon layer and the floating gate dielectric layer are superimposed to form the outer side surface of the first gate structure; The second inner sidewall is self-aligned and formed on the inner side surfaces of the inter-polysilicon dielectric layer, the control gate polysilicon layer and the first inner sidewall, the inner side surfaces of the floating gate polysilicon layer and the floating gate dielectric layer are self-aligned and defined by the inner side surfaces of the second inner sidewall, and the inner side surfaces of the second inner sidewall, the floating gate polysilicon layer and the floating gate dielectric layer are superimposed to form the inner side surface of the first gate structure; An outer wall is formed on the outer side of the first gate structure; A second gate structure is self-alignedly formed on the semiconductor substrate within the inner side of the first gate structure, and the second gate structure includes a select gate dielectric layer and a select gate polysilicon layer stacked in sequence; A lightly doped drain region of the first conductivity type, an outer pocket injection region doped with the second conductivity type, an inner pocket injection region doped with the second conductivity type, and a heavily doped source and drain injection region of the first conductivity type are also formed in the semiconductor substrate; The lightly doped drain region is self-aligned with the outer side surface of the first gate structure; The outer pocket injection region is self-aligned with the outer side surface of the first gate structure; The inner pocket implantation region and the inner side surface of the control gate polysilicon layer are self-aligned; The source-drain injection region and the outer side surface of the outer side wall are self-aligned; The source-drain injection region is connected to the bit line; The first gate structure and the second gate structure perform segmented control on the channel region, and the lightly doped drain region, the outer pocket injection region and the inner pocket injection region form a short channel effect control structure; The PN junction formed between the outer pocket injection region and the source-drain injection region serves as a withstand voltage structure for the bit line voltage; The doping dose of the outer pocket injection region is less than the doping dose of the inner pocket injection region, and the total dose of the doping dose of the outer pocket injection region and the doping dose of the inner pocket injection region is used to ensure that the requirements for short channel effect control are met; the doping dose of the outer pocket injection region is reduced to meet the withstand voltage requirements at the source and drain injection regions.

2. The floating gate split-gate flash memory device according to claim 1, characterized in that: The doping concentration of the inner pocket injection region has the characteristic of gradually decreasing from the surface of the semiconductor substrate downwards; A first groove is formed in the bottom area of ​​the second gate structure by etching the semiconductor material of the semiconductor substrate. The first groove is self-aligned with the inner side surface of the first gate structure. The depth of the first groove is less than the depth of the inner pocket injection region, so that the contact position between the selection gate dielectric layer of the second gate structure and the inner pocket injection region is located below the surface of the semiconductor substrate. The inner pocket injection region located below the first groove is used as the threshold voltage adjustment region of the selection tube so that the threshold voltage of the selection tube meets the requirements.

3. The floating gate split-gate flash memory device according to claim 1, wherein: The threshold voltage adjustment region of the selection tube is composed of a first injection region doped with a first conductive type superimposed on the inner pocket injection region, the first injection region and the inner side surface of the first gate structure are self-aligned, the net doping of the overlapping region of the first injection region and the inner pocket injection region is the second conductive type, and the first injection region reduces the surface concentration of the inner pocket injection region to meet the threshold voltage requirement of the selection tube.

4. The floating gate split-gate flash memory device according to claim 1, 2 or 3, characterized in that: The semiconductor substrate includes a silicon substrate.

5. The floating gate split-gate flash memory device according to claim 4, characterized in that: The device unit structure is a 2-bit NORD type structure, and the device unit structure includes two first gate structures and one second gate structure; The second gate structure is formed in a self-aligned manner between the inner side surfaces of the two first gate structures; The lightly doped drain region is self-alignedly formed in the semiconductor substrate at the outer side surfaces of the two first gate structures; The two source-drain implantation regions are self-aligned and formed in the semiconductor substrate at the outer side surfaces of the outer side walls of the two first gate structures; The inner pocket implantation region is formed in a self-aligned manner between inner side surfaces of the control gate polysilicon layers of the two first gate structures.

6. The floating gate split-gate flash memory device according to claim 5, characterized in that: The inter-polysilicon dielectric layer is an ONO layer.

7. The floating gate split-gate flash memory device according to claim 5, characterized in that: A well region doped with a second conductivity type is also formed on the semiconductor substrate; The lightly doped drain region, the outer pocket injection region, the inner pocket injection region and the source-drain injection region are all formed in the surface region of the well region.

8. The floating gate split-gate flash memory device according to claim 7, characterized in that: A second threshold voltage adjustment region doped with a second conductive type is also formed in the semiconductor substrate aligned with the outer side surfaces of the two first gate structures. The second threshold voltage adjustment region is used to adjust the threshold voltage of the floating gate storage tube and achieve anti-punch-through. The threshold voltage of the floating gate storage tube is determined by the coverage of the second threshold voltage adjustment region at the bottom by the floating gate polysilicon layer through the floating gate dielectric layer.

9. The floating gate split-gate flash memory device according to claim 8, characterized in that: The device unit structure is an N-type structure, the first conductivity type is N-type, and the second conductivity type is P-type.

10. A method for manufacturing a floating gate split-gate flash memory device, characterized in that: The steps of forming the device unit structure include: Step 1: forming a floating gate dielectric layer, a floating gate polysilicon layer, an inter-polysilicon dielectric layer and a control gate polysilicon layer in sequence on the surface of the semiconductor substrate doped with the second conductivity type; Step 2: forming a hard mask layer, and patterning and etching the hard mask layer to form a first opening; Step 3: forming a first inner wall on the inner side of the first opening; Step 4: etching the control gate polysilicon layer and the inter-polysilicon dielectric layer in sequence with the inner side surface of the first inner sidewall as a self-alignment condition to form the inner sidewalls of the control gate polysilicon layer and the inter-polysilicon dielectric layer; Step 5: With the inner side surface of the control gate polysilicon layer as a self-alignment condition, a first pocket implantation of a second conductive type doping is performed to form an inner pocket implantation region, wherein the first pocket implantation is an angled implantation; Step six, forming a second inner sidewall by self-alignment on the inner side surface of the inter-polysilicon dielectric layer, the control gate polysilicon layer and the first inner sidewall; Step 7: etching the floating gate polysilicon layer and the floating gate dielectric layer with the inner side surface of the second inner sidewall as a self-alignment condition to form the inner side surfaces of the floating gate polysilicon layer and the floating gate dielectric layer; the inner side surfaces of the second inner sidewall, the floating gate polysilicon layer and the floating gate dielectric layer are superimposed to form the inner side surface of the first gate structure; Step eight, forming a second gate structure on the semiconductor substrate within the inner side surface of the first gate structure by self-alignment, wherein the second gate structure includes a select gate dielectric layer and a select gate polysilicon layer stacked in sequence; Step nine, removing the hard mask layer to expose the outer side surface of the first inner sidewall; Step ten, taking the outer side surface of the first inner sidewall as a self-alignment condition, sequentially etching the control gate polysilicon layer, the inter-polysilicon dielectric layer, the floating gate polysilicon layer and the floating gate dielectric layer to form the outer side surfaces of the control gate polysilicon layer, the inter-polysilicon dielectric layer, the floating gate polysilicon layer and the floating gate dielectric layer, and the outer side surfaces of the first inner sidewall, the control gate polysilicon layer, the inter-polysilicon dielectric layer, the floating gate polysilicon layer and the floating gate dielectric layer are superimposed to form the outer side surface of the first gate structure; Step 11: performing lightly doped drain implantation of a first conductivity type lightly doped with the outer side surface of the first gate structure as a self-alignment condition to form a lightly doped drain region; Step 12: Perform a second pocket implantation of a second conductive type doping with the outer side surface of the first gate structure as a self-aligned condition to form an outer pocket implantation region; the second pocket implantation is an angled implantation; Step 13, forming an outer wall by self-alignment outside the outer side surface of the first gate structure; Step 14: performing a second source-drain implantation with heavy conductive type doping under the self-alignment condition to form a source-drain implantation region; The source-drain injection region is connected to the bit line; The first gate structure and the second gate structure perform segmented control on the channel region, and the lightly doped drain region, the outer pocket injection region and the inner pocket injection region form a short channel effect control structure; The PN junction formed between the outer pocket injection region and the source-drain injection region serves as a withstand voltage structure for the bit line voltage; The doping dose of the outer pocket injection region is less than the doping dose of the inner pocket injection region, and the total dose of the doping dose of the outer pocket injection region and the doping dose of the inner pocket injection region is used to ensure that the requirements for short channel effect control are met; the doping dose of the outer pocket injection region is reduced to meet the withstand voltage requirements at the source and drain injection regions.

11. The method for manufacturing a floating gate split-gate flash memory device according to claim 10, characterized in that: The doping concentration of the inner pocket injection region has the characteristic of gradually decreasing from the surface of the semiconductor substrate downwards; After step 7 is completed and before step 8 of growing the select gate dielectric layer is performed, the following steps are further included: Continue etching the semiconductor material of the semiconductor substrate to form a first groove using the inner side surface of the first gate structure as a self-alignment condition; The depth of the first groove is less than the depth of the inner pocket injection region, so that the contact position between the selection gate dielectric layer of the second gate structure and the inner pocket injection region is located below the surface of the semiconductor substrate. The inner pocket injection region located below the first groove is used as the threshold voltage adjustment region of the selection tube so that the threshold voltage of the selection tube meets the requirements.

12. The method for manufacturing a floating gate split-gate flash memory device according to claim 10, wherein: After step 7 is completed and before step 8 of growing the select gate dielectric layer is performed, the following steps are further included: Performing ion implantation of a first conductive type doping with the inner side surface of the first gate structure as a self-alignment condition to form a first implantation region; The threshold voltage adjustment region of the selection tube is composed of a first injection region doped with a first conductive type superimposed on the inner pocket injection region, the net doping of the overlapping region of the first injection region and the inner pocket injection region is the second conductive type, and the first injection region reduces the surface concentration of the inner pocket injection region to meet the threshold voltage requirement of the selection tube.

13. The method for manufacturing a floating gate split-gate flash memory device according to claim 10, 11 or 12, characterized in that: The semiconductor substrate includes a silicon substrate.

14. The method for manufacturing a floating gate split-gate flash memory device according to claim 13, wherein: The device unit structure is a 2-bit NORD type structure, and the device unit structure includes two first gate structures and one second gate structure; The first opening defines a region between two outer side surfaces of the first gate structures; The second gate structure is formed in a self-aligned manner between the inner side surfaces of the two first gate structures; The lightly doped drain region is self-alignedly formed in the semiconductor substrate at the outer side surfaces of the two first gate structures; The two source-drain implantation regions are self-aligned and formed in the semiconductor substrate at the outer side surfaces of the outer side walls of the two first gate structures; The inner pocket implantation region is formed in a self-aligned manner between inner side surfaces of the control gate polysilicon layers of the two first gate structures.

15. The method for manufacturing a floating gate split-gate flash memory device according to claim 14, wherein: The inter-polysilicon dielectric layer is an ONO layer.

16. The method for manufacturing a floating gate split-gate flash memory device according to claim 14, wherein: A well region doped with a second conductivity type is also formed on the semiconductor substrate; The lightly doped drain region, the outer pocket injection region, the inner pocket injection region and the source-drain injection region are all formed in the surface region of the well region.

17. The method for manufacturing a floating gate split-gate flash memory device according to claim 16, wherein: After the first opening is formed in step 2 and before step 3, the method further includes: Ions doped with a second conductive type are implanted using the hard mask layer as a mask to form a second threshold voltage adjustment region, wherein the second threshold voltage adjustment region is used to adjust the threshold voltage of the floating gate storage tube and achieve anti-punch-through, and the threshold voltage of the floating gate storage tube is determined by the coverage of the second threshold voltage adjustment region at the bottom by the floating gate polysilicon layer through the floating gate dielectric layer.

18. The method for manufacturing a floating gate split-gate flash memory device according to claim 17, wherein: The device unit structure is an N-type structure, the first conductivity type is N-type, and the second conductivity type is P-type.

19. The method for manufacturing a floating gate split-gate flash memory device according to claim 16, wherein: The injection dose of the first pocket injection is less than 1e13cm -2 The injection dose of the second pocket injection is greater than 1e13cm -2 .

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