Data cyclic shift device, method, chip, computer equipment and storage medium

Abstract

The present disclosure provides a data cyclic shift device, method, chip, computer equipment and storage medium, including: a processor, a memory and a multi-level cyclic shift network, the multi-level cyclic shift network includes multiple cyclic shifters; the memory is used to store the mapping relationship between each predetermined cyclic shift parameter and the control vector; the control vector is determined based on the target level, target position and cyclic shift parameter of each cyclic shifter in the multi-level cyclic shift network; the processor is used to determine the target input data and extract the control vector matching the cyclic shift parameter from the memory; the target input data and the extracted control vector are input to the multi-level cyclic shift network, and the data cyclic shift result is determined based on the target output data and the cyclic shift parameter output by the multi-level cyclic shift network; the multi-level cyclic shift network is used to perform a cyclic shift operation on the target input data based on each cyclic shifter.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data cyclic shift device, method, chip, computer equipment and storage medium. Background Art

[0002] With the continuous development of integrated circuits, cyclic shift networks are widely used in various chips to perform cyclic shift operations on data.

[0003] In practical applications, in addition to the need to perform cyclic shift operations on data of various lengths, it is often necessary to process the cyclic shifted data accordingly according to different usage scenarios so that the obtained cyclic shift results meet the needs of different scenarios. Therefore, how to set up a configurable cyclic shift network that is compatible with different application scenarios has become one of the urgent problems to be solved. Summary of the invention

[0004] The embodiments of the present disclosure at least provide a data cyclic shift device, method, chip, computer equipment and storage medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a data cyclic shift device, comprising: a processor, a memory, and a multi-level cyclic shift network, wherein the multi-level cyclic shift network comprises a plurality of cyclic shifters; wherein:

[0006] The memory is used to store a predetermined mapping relationship between each cyclic shift parameter and a control vector; the control vector is predetermined based on the target level of each cyclic shifter in the multi-level cyclic shift network, the target position in the target level, and the cyclic shift parameter;

[0007] The processor is configured to, after acquiring the data to be cyclically shifted and the cyclic shift parameters, determine the target input data based on the cyclic shift parameters and the data to be cyclically shifted, and extract a control vector matching the cyclic shift parameters from the memory; input the target input data and the extracted control vector into the multi-level cyclic shift network, and determine the data cyclic shift result based on the target output data output by the multi-level cyclic shift network and the cyclic shift parameters;

[0008] The multi-level cyclic shift network is used to perform a cyclic shift operation on the target input data based on each cyclic shifter.

[0009] In one possible implementation, the cyclic shift parameter includes a shift value, and at least one of the following: a shift direction, a shift delay, a minimum shift unit, and the number of input terminals of the multi-level cyclic shift network, wherein the minimum shift unit represents the number of unit processing bits when the multi-level cyclic shift network performs a shift operation.

[0010] In this way, by setting the minimum shift unit, the multi-level cyclic shift network can perform cyclic shift operations on to-be-cyclic-shifted data of different lengths.

[0011] In a possible implementation manner, the processor is specifically used to determine the total number of bits of target cyclic shift data input to each input end of the multi-level cyclic shift network based on the minimum shift unit and the number of input ends of the multi-level cyclic shift network; when it is detected that the total number of bits of the target cyclic shift data is different from the number of bits of the data to be cyclically shifted, determine the target cyclic shift data input to each input end of the multi-level cyclic shift network based on the data to be cyclically shifted, the minimum shift unit and the number of input ends of the multi-level cyclic shift network.

[0012] In one possible implementation, the processor is specifically used to fill the data to be cyclically shifted with padding data when it is detected that the number of bits of the data to be cyclically shifted is less than the total number of bits, so as to obtain target cyclically shifted data with a number of data bits equal to the total number of bits; and determine the target cyclically shifted data input to each input end of the multi-level cyclic shift network based on the target cyclic data and the number of input ends of the multi-level cyclic shift network.

[0013] In this way, by using padding data to pad the data to be cyclically shifted, the cyclic shift problem of the data to be cyclically shifted with an arbitrary data length can be solved.

[0014] In a possible implementation manner, the processor is specifically configured to input the target cyclic shift data to corresponding input ends respectively; and input the control vectors corresponding to the cyclic shift parameters to corresponding cyclic shifters respectively;

[0015] Each of the cyclic shifters in the multi-level cyclic shift network is used to perform cyclic shift processing on the target cyclic shift data according to the control vector to obtain the target output data.

[0016] In a possible implementation manner, the processor is further configured to, when detecting that the target output data includes padding data, delete the padding data to obtain a data cyclic shift result after deleting the padding data.

[0017] In this way, by deleting the padding data, the accuracy of the final data cyclic shift result can be ensured.

[0018] In a possible implementation manner, the processor is specifically configured to, when detecting that the minimum shift unit is not a preset value, rearrange the target output data based on the shift value and the minimum shift unit to obtain the data cyclic shift result.

[0019] In this way, by performing a rearrangement operation on the target output data, the accuracy of the data cyclic shift result finally obtained can be ensured, thereby effectively solving the cyclic shift problem when the data cyclic shift is performed using the minimum shift unit.

[0020] In a possible implementation manner, the processor is further configured to add a delay to the data in the data cyclic shift result according to the shift delay, so as to adjust the timing of the data in the data cyclic shift result.

[0021] In this way, by adding a delay, the timing of the data to be cyclically shifted can be adjusted to adapt to application scenarios with different timing requirements, effectively avoiding metastable problems caused by timing violations (i.e., timing not meeting preset requirements) in application scenarios such as chips.

[0022] In a possible implementation manner, the cyclic shifter is composed of at least one cyclic shift switch;

[0023] The control vector for controlling each cyclic shifter to perform a cyclic shift operation is determined according to the following method:

[0024] For any of the cyclic shift switches in each cyclic shifter, when it is detected that mod[mod(k-1, 2n-1)-V, 2n)]≥2n-1 is satisfied, setting the switch state of the cyclic shift switch to the first state; and

[0025] When it is detected that mod[mod(k-1, 2n-1)-V, 2n)]<2n-1, the switch state of the cyclic shift switch is set to the second state;

[0026] Wherein, V is the shift value, n and k represent the target level of the cyclic shift switch in the multi-level cyclic shift network and the target position in the target level, respectively, and mod represents a modulo operation.

[0027] In a second aspect, an embodiment of the present disclosure provides a data cyclic shift method, including:

[0028] Obtaining data to be cyclically shifted and cyclic shift parameters;

[0029] Determining target input data based on the cyclic shift parameter and the data to be cyclically shifted;

[0030] Inputting the target input data and the obtained corresponding control vector into a multi-level cyclic shift network to obtain target output data output by the multi-level cyclic shift network; wherein the multi-level cyclic shift network comprises a plurality of cyclic shifters, and the control vector for controlling each cyclic shifter to perform a cyclic shift operation is predetermined based on the target level of each cyclic shifter in the multi-level cyclic shift network, the target position in the target level, and the cyclic shift parameter;

[0031] A data cyclic shift result is determined based on the target output data and the cyclic shift parameter.

[0032] In a third aspect, an embodiment of the present disclosure further provides a chip, wherein the chip is deployed with a data cyclic shift device as in any possible implementation manner of the first aspect.

[0033] In a fourth aspect, corresponding to the data cyclic shift method in the second aspect, an embodiment of the present disclosure further provides a data cyclic shift device, including:

[0034] An acquisition unit, used for acquiring data to be cyclically shifted and cyclic shift parameters;

[0035] A first determining unit, configured to determine target input data based on the cyclic shift parameter and the data to be cyclically shifted;

[0036] a shift unit, configured to input the target input data and the obtained corresponding control vector into a multi-level cyclic shift network to obtain target output data output by the multi-level cyclic shift network; wherein the multi-level cyclic shift network comprises a plurality of cyclic shifters, and the control vector for controlling each cyclic shifter to perform a cyclic shift operation is predetermined based on the target level of each cyclic shifter in the multi-level cyclic shift network, the target position in the target level, and the cyclic shift parameter;

[0037] The second determining unit is used to determine a data cyclic shift result based on the target output data and the cyclic shift parameter.

[0038] In a fifth aspect, an embodiment of the present disclosure further provides a computer device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processor and the memory communicate via the bus, and the machine-readable instructions are executed by the processor to perform the above-mentioned second aspect; or, comprising: the chip in the third aspect.

[0039] In a sixth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above-mentioned second aspect are executed.

[0040] For a description of the effects of the above-mentioned data cyclic shift method, chip, computer device and storage medium, please refer to the description of the above-mentioned data cyclic shift device, which will not be repeated here.

[0041] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0043] Figure 1 A flow chart of a data cyclic shift method provided by an embodiment of the present disclosure is shown;

[0044] Figure 2 A schematic diagram of a multi-level cyclic shift network in the data cyclic shift method provided in an embodiment of the present disclosure is shown;

[0045] Figure 3 A schematic diagram showing a method for determining a target level and a target position of a cyclic shifter in a multi-level cyclic shift network in a data cyclic shift method provided by an embodiment of the present disclosure is shown;

[0046] Figure 4 A schematic diagram showing a rearrangement operation on the target output data in the data cyclic shift method provided in an embodiment of the present disclosure;

[0047] Figure 5 A schematic diagram of the architecture of a data cyclic shift device provided by an embodiment of the present disclosure is shown;

[0048] Figure 6 A schematic diagram of the architecture of a data cyclic shift device provided by an embodiment of the present disclosure is shown;

[0049] Figure 7 A schematic diagram of the structure of a computer device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0051] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0052] The term "and / or" herein only describes an association relationship, indicating that three relationships may exist. For example, A and / or B may represent the following three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set consisting of A, B, and C.

[0053] Research has found that with the continuous development of integrated circuits, cyclic shift networks are widely used in various chips to perform cyclic shift operations on data. In practical applications, in addition to the need to perform cyclic shift operations on data of various lengths, it is often necessary to process the cyclic shift data accordingly according to different usage scenarios so that the cyclic shift results obtained meet the needs of different scenarios. Therefore, how to set up a configurable cyclic shift network that is compatible with different application scenarios has become one of the problems that need to be solved urgently.

[0054] Based on the above research, the present disclosure provides a data cyclic shift device, method, chip, computer equipment and storage medium, which determines the target input data based on the cyclic shift parameter and the data to be cyclically shifted, and after obtaining the target output result based on the multi-level cyclic shift network, processes the target output data according to the cyclic shift parameter to obtain the data cyclic shift result. In this way, the applicability of using the multi-level cyclic shift network for data cyclic shift operations can be improved, so that the multi-level cyclic shift network can adapt to the data cyclic shift requirements in different application scenarios.

[0055] In practical applications, the cyclic shift network may be a multi-level cyclic shift network. Each layer of the cyclic shift network in the multi-level cyclic shift network may be composed of a plurality of processing elements (PE) in parallel. Each processing element may be composed of a multi-input and multi-output switch. The number of input terminals and output terminals of the processing element is related to the arrangement order of each layer of the cyclic shift network in the multi-level permutation network. The specific structures of the processing elements corresponding to different layers of permutation networks are different. The multi-level cyclic shift network completes the cyclic shift operation of the entire multi-level cyclic shift network through the serial calculation of each layer of the cyclic shift network. The cyclic shift network may be deployed as a hardware unit in a chip during deployment to provide on-chip hardware support for the cyclic shift requirements in the chip, or it may be encapsulated into corresponding hardware and connected to a target chip that needs to perform a cyclic shift operation, so as to perform a cyclic shift operation according to the data to be cyclically shifted and the cyclic shift parameters when a cyclic shift request is received. The purpose of the cyclic shift operation may be, for example, to improve the operation efficiency. As a data processing method, the cyclic shift operation may set different cyclic shift parameters according to different task requirements to meet different task requirements.

[0056] Exemplarily, the circular shift operation can be used in a target algorithm that has circular shift requirements, such as a low-density parity check code (LDPC) decoding algorithm, an image classification function, and related algorithms of a bitset function. In the target algorithm, the data to be processed is subjected to circular shift processing by a circular shift network before performing corresponding operations. Compared with directly performing operations, the complexity of the operations can be reduced, thereby improving the operational efficiency when using the target algorithm and saving computing resources.

[0057] The “circular shifter” in the embodiment of the present disclosure may serve as the above-mentioned operation unit, and the “circular shift switch” in the embodiment of the present disclosure may serve as the switch in the above-mentioned operation unit.

[0058] To facilitate understanding of the present embodiment, a data cyclic shift method disclosed in the embodiment of the present disclosure is first introduced in detail. The execution subject of the data cyclic shift method provided in the embodiment of the present disclosure is generally a computer device with certain computing capabilities, and the computer device includes, for example: a terminal device or a server or other processing device, and the terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a computing device, etc. In some possible implementations, the data cyclic shift method can be implemented by a processor calling a computer-readable instruction stored in a memory.

[0059] See also Figure 1FIG. 1 is a flowchart of a data cyclic shift method provided by an embodiment of the present disclosure, wherein the method comprises steps S101 to S104, wherein:

[0060] S101: Acquire data to be cyclically shifted and cyclic shift parameters.

[0061] S102: Determine target input data based on the cyclic shift parameter and the data to be cyclically shifted.

[0062] S103: Input the target input data and the obtained corresponding control vector into a multi-level cyclic shift network to obtain the target output data output by the multi-level cyclic shift network; wherein the multi-level cyclic shift network includes a plurality of cyclic shifters, and the control vector for controlling each cyclic shifter to perform a cyclic shift operation is predetermined based on the target level of each cyclic shifter in the multi-level cyclic shift network, the target position in the target level, and the cyclic shift parameter.

[0063] S104: Determine a data cyclic shift result based on the target output data and the cyclic shift parameter.

[0064] The following is a detailed description of the above steps.

[0065] For S101, the data to be cyclically shifted and the cyclic shift parameters can be parsed from the cyclic shift request. The requesting party that initiates the cyclic shift request can be a hardware device that establishes a communication connection with the data cyclic shift device. The data to be cyclically shifted represents the initial data that needs to be cyclically shifted. The cyclic shift parameters include a shift value, and at least one of the following: a shift direction, a shift delay, a minimum shift unit, and the number of input terminals of the multi-level cyclic shift network, wherein the minimum shift unit represents the minimum number of bits moved when a cyclic shift operation is completed through the multi-level cyclic shift network (that is, the number of unit processing bits).

[0066] Specifically, the shift direction indicates the direction when performing a data circular shift operation, including left and right, corresponding to a circular shift operation to the left and a circular shift operation to the right, respectively; the shift value indicates the number of bits moved in the shift direction when performing a circular shift operation, for example, a shift value of 1 indicates a circular shift of 1 bit in the shift direction; the shift delay indicates a delay value added to the data to be circularly shifted when performing a data circular shift operation, so as to adjust the timing of the data to be circularly shifted, for example, a delay value of 1 means that the circular shift operation is continued after one clock cycle, and the final circular shift result is 1 more than the circular shift result without delay. There are changes in timing, so that it can adapt to application scenarios with different timing requirements, and effectively avoid metastable problems caused by timing violations (that is, the timing does not meet the preset requirements) in application scenarios such as chips; in some scenarios, the granularity that needs to be shifted is not 1 number, but several numbers, which requires dividing the scattered data into data blocks. For example, if the number of input data is 16, 2 numbers can be set as a data block, and the data blocks are used as units for input in the multi-level cyclic shift network. At this time, the number of input data is the number of input data blocks (8 in this example), and each data block constitutes the smallest unit of cyclic shift.

[0067] S102: Determine target input data based on the cyclic shift parameter and the data to be cyclically shifted.

[0068] Here, the target input data is the data input into the multi-level cyclic shift network. When determining the target input data, the total number of bits of the target cyclic shift data input into each input end of the multi-level cyclic shift network can be determined based on the minimum shift unit and the number of input ends of the multi-level cyclic shift network, and the target input data can be determined based on the relationship between the total number of bits of the target cyclic shift data and the number of bits of the data to be cyclically shifted.

[0069] Specifically, the product of the number of the minimum shift unit and the number of input terminals of the multi-level cyclic shift network is the total number of bits of the target cyclic shift data.

[0070] Exemplarily, taking the minimum shift unit as 5 and the number of input terminals of the multi-level cyclic shift network as 16, the total number of bits of the target cyclic shift data is 80.

[0071] Specifically, when determining the target input data, according to the different relationships between the total number of bits of the target cyclically shifted data and the number of bits of the data to be cyclically shifted, the following situations can be considered:

[0072] Case 1: the total number of bits of the target cyclically shifted data is the same as the number of bits of the data to be cyclically shifted.

[0073] In this case, the data to be cyclically shifted may be segmented based on the minimum shift unit to obtain target cyclically shifted data input to each input end of the multi-level cyclic shift network.

[0074] Exemplarily, the data to be cyclically shifted is a0~a 15 , the minimum shift unit is 4, and the number of input terminals of the multi-level cyclic shift network is 4. The data a0 to a0 to be cyclically shifted can be cyclically shifted according to the minimum shift unit 4. 15 The target cyclic shift data input to the first to fourth input terminals of the multi-level cyclic shift network are respectively a0 to a3, a4 to a7, a8 to a9. 11 、a 12 ~a 15 .

[0075] Case 2: the total number of bits of the target cyclically shifted data is greater than the number of bits of the data to be cyclically shifted.

[0076] At this time, the minimum target shift unit can be determined based on the number of bits of the cyclic shift data and the number of input terminals of the multi-level cyclic shift network, so as to use the minimum target shift unit to update the minimum shift unit, and after the minimum shift unit is updated, the total number of bits of the target cyclic shift data can be re-determined according to the updated minimum shift unit, and the step of determining the target input data can be re-executed.

[0077] Exemplarily, the data to be cyclically shifted is a0~a 71 For example, the input terminals of the multi-level cyclic shift network are A0~A 15 For example, the number of bits of the data to be cyclically shifted is 72, and the number of input terminals of the multi-level cyclic shift network is 16. The number of bits of the data to be cyclically shifted (72) can be divided by the number of input terminals of the multi-level cyclic shift network (16), and the obtained quotient is modulo upward to obtain a final result of 5, so that the corresponding minimum target shift unit can be determined to be 5. The physical meaning represented by this is that at least 5 data to be cyclically shifted need to be input into 1 input terminal of the multi-level cyclic shift network before the multi-level cyclic shift network can be used to complete the cyclic shift operation of the data to be cyclically shifted.

[0078] It should be noted that, when updating the minimum shift unit, using the minimum target shift unit to update the minimum shift unit is only one possible implementation method. In actual applications, any value greater than the minimum target shift unit can be selected to update the minimum shift unit according to needs, and the embodiments of the present disclosure do not limit this.

[0079] Case 3: the total number of bits of the target cyclically shifted data is smaller than the number of bits of the data to be cyclically shifted.

[0080] At this time, padding data may be used to pad the data to be cyclically shifted, so as to obtain target cyclically shifted data whose data bit number is equal to the total bit number.

[0081] Specifically, when the padding data is used to fill the data to be circularly shifted, the padding may be performed on the left side of the data to be circularly shifted (i.e., in front of the data to be circularly shifted), or on the right side of the data to be circularly shifted (i.e., behind the data to be circularly shifted).

[0082] Exemplarily, the data to be cyclically shifted is a0~a 11 For example, the input terminals of the multi-level cyclic shift network are A0~A 15 For example, the number of bits of the data to be cyclically shifted is 12, and the input end of the multi-level cyclic shift network is 16. The data to be cyclically shifted can be padded with padding data 0, and the target cyclically shifted data after padding can be 0, 0, 0, 0, a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a2, a3, a4, a5, a6, a7, a8, a9, a11, a12, a3, a4, a5, a6, a7, a8, a9, a13, a14, a15, a16, a7, a8, a9, a15, a16, a17, a8, a9, a10, a11, a2, a3, a4, a5, a6, a7, a8, a9, a10 10 、a 11 , or a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 、a 11 , 0, 0, 0, 0.

[0083] Furthermore, after obtaining the padded target cyclic shift data, the target cyclic shift data input to each input end of the multi-level cyclic shift network can be determined based on the target cyclic data and the number of input ends of the multi-level cyclic shift network.

[0084] Continuing with the above example, we can determine the filled 0, 0, 0, 0, a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 、a 11 、a 12 , or a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 、a 11 、a 12 , 0, 0, 0, 0 are input to A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A 10 , A 11 , A 12 , A 13 , A 14 , A 15The target circular shift data in .

[0085] S103: Input the target input data and the obtained corresponding control vector into a multi-level cyclic shift network to obtain the target output data output by the multi-level cyclic shift network; wherein the multi-level cyclic shift network includes a plurality of cyclic shifters, and the control vector for controlling each cyclic shifter to perform a cyclic shift operation is predetermined based on the target level of each cyclic shifter in the multi-level cyclic shift network, the target position in the target level, and the cyclic shift parameter.

[0086] Here, the multi-level cyclic shift network can be a banyan network, a butterfly network, etc. The number of layers of the multi-level cyclic shift network and the type and connection method of the cyclic shifters in each layer of the cyclic shift network can be determined based on the number of input terminals of the multi-level cyclic shift network.

[0087] Specifically, assuming that the number of layers of the multi-level cyclic shift network is N, the number of input terminals of the multi-level cyclic shift network is 2 N , from the 1st layer to the Nth layer, the cyclic shifters of the Mth layer (N≥M≥1, where N and M are both positive integers) are composed of 2 M-1 The cyclic shifter is composed of a cyclic shift switch, which is the smallest hardware unit constituting the cyclic shifter. Controlling the cyclic shifter is to control the cyclic shift switch in the cyclic shifter. Each of the cyclic shift switches has two input ends and two output ends. The input end of the cyclic shifter in each layer of the cyclic shift network is connected to the output end of the cyclic shifter at the corresponding position of the previous layer (the input end of the first layer is the input end of the multi-level cyclic shift network), and the output end of the cyclic shifter in each layer of the cyclic shift network is connected to the input end of the cyclic shifter at the corresponding position of the next layer (the output end of the last layer is the output end of the multi-level cyclic shift network). The number of cyclic shifters in the Mth layer is 2 N-M .

[0088] Exemplarily, taking the multi-level cyclic shift network as a banyan network, in the banyan network, in order to enable the input data to complete various cyclic shift requirements and at the same time occupy the least hardware resources, the number of input terminals of the banyan network, the number of layers of the banyan network, the number of cyclic shifters included in each layer, and the number of cyclic shift switches usually have a unique corresponding relationship, that is, in order to complete various cyclic shift operations of a specific number of input data, the minimum number of layers of the banyan network required to be used is fixed, and when the number of layers of the banyan network is the minimum number of layers, the number of cyclic shifters included in each layer, and the number of cyclic shift switches are also fixed, that is, under the premise of meeting various cyclic shift operation requirements, various hardware setting parameters (the number of layers of the banyan network, the number of cyclic shifters included in each layer, and the number of cyclic shift switches) when occupying the least hardware resources are unique.

[0089] Exemplarily, the schematic diagram of the multi-level cyclic shift network can be as follows: Figure 2 As shown, Figure 2 In the embodiment, the number of input terminals of the multi-level cyclic shift network is 16, and the number of layers of the multi-level cyclic shift network is 4. The first to fourth layers are respectively composed of 8, 4, 2, and 1 cyclic shifters. The cyclic shift switches (i.e. Figure 2 The SW in the 1st layer is 1, 2, 4, and 8 respectively. When performing data cyclic shift, the target input data of the first layer input is a0 to a 15 After being processed by the cyclic shift network of the first layer, b0~b 15 ; b0~b 15 Input to the cyclic shift network of the second layer, after being processed by the cyclic shift network of the second layer, c0~c 15 ; c0~c 15 Input to the cyclic shift network of the third layer, after being processed by the cyclic shift network of the third layer, d0~d 15 ; d0~d 15 Input to the 4th layer cyclic shift network, after being processed by the 4th layer cyclic shift network, we get e0~e 15 (i.e., the target output data of the multi-level cyclic shift network).

[0090] Here, when the target input data is input into a multi-level cyclic shift network, the target cyclic shift data input into each input end of the multi-level cyclic shift network can be respectively input into the corresponding input end; and the control vector is respectively input into the corresponding cyclic shifter to instruct the cyclic shifter to perform cyclic shift processing on the target cyclic shift data according to the control vector, thereby obtaining the target output data.

[0091] Specifically, the control vector may be determined based on the target levels of the multi-level cyclic shift network, the target positions in the target levels, and the cyclic shift parameters of the cyclic shifters.

[0092] It should be noted here that the multi-level cyclic shift network can be any one of a banyan network and a butterfly network. Both the banyan network and the butterfly network are constructed by interconnecting cyclic shifters. The calculation methods of the control vectors corresponding to the banyan network and the butterfly network are different. Therefore, even if the network structures of the banyan network and the butterfly network are different, the cyclic shift effect can be achieved by calculating the control vectors corresponding to the banyan network and the butterfly network respectively.

[0093] For example, in Figure 2 Based on the schematic diagram of the multi-level cyclic shift network, in order to highlight Figure 2 The role of each cyclic shift switch in the specific cyclic shift operation, and the schematic diagram of determining the target level and target position of the cyclic shifter in the multi-level cyclic shift network can be as follows Figure 3 As shown, Figure 3 The data to be cyclically shifted is a1~a L After being filled with filling data, the data input to the multi-level cyclic shift network is a1~a 2k , where the cyclic shift switches in the multi-level cyclic shift network are numbered SW k,n , where K≥k≥1, K is the number of cyclic shift switches in each layer of the cyclic shift network; N≥n≥1, N is the number of layers of the multi-layer cyclic shift network, and the relationship between K and N is K=2 N-1 , the target level of any of the cyclic shift switches in the multi-level cyclic shift network and the target position in the target level can be quickly located by numbering.

[0094] Further, taking the banyan network as an example of a multi-level cyclic shift network, according to the network structure characteristics of the banyan network and the cascade relationship between different levels in the multi-level banyan network, for any of the cyclic shift switches, the switch state of the cyclic shift switch can be determined based on the target level, the target position and the shift value corresponding to the cyclic shift switch, and when determining the switch state, a preset judgment formula can be used to judge the target level, the target position and the shift value, and the switch state of the cyclic shift switch can be determined according to the judgment result. In this way, by judging each cyclic shift switch constituting the multi-level cyclic shift network and setting the corresponding switch state according to the judgment result, the cyclic shift operation corresponding to the shift value can be completed through the switch states corresponding to each cyclic shift switch.

[0095] Based on this, when the mapping relationship between the cyclic shift parameter and the control vector is predetermined, it is necessary to first determine the corresponding control vector according to the cyclic shift parameter corresponding to the cyclic shift data. When implementing, it can be detected that the control vector satisfies mod[mod(k-1,2 n-1 )-V, 2 n )]≥2 n-1 When the cyclic shift switch is switched, the switch state of the cyclic shift switch is set to the first state (data exchange is performed, and the data respectively inputted from the two input ends are exchanged and then outputted from the two output ends respectively), wherein V is the shift value, n and k respectively represent the target level of the cyclic shift switch in the multi-level cyclic shift network, and the target position in the target level, mod represents the remainder operation, and mod(a, b) represents the remainder obtained after taking a÷b; otherwise, the switch state of the cyclic shift switch is set to the second state (data exchange is not performed, and the data respectively inputted from the two input ends are directly outputted from the two output ends).

[0096] Furthermore, V here usually refers to the left shift value. If the shift direction is right shift, the right shift bit number can be converted into the left shift bit number and then assigned to V. In one implementation, the data length minus the right shift value is equal to the left shift value.

[0097] It should be noted that, when the minimum shift unit is not 1, the shift value used in the above judgment formula is not the initial shift value in the cyclic shift parameter, but a target shift value re-determined based on the cyclic shift parameter and the minimum shift unit, that is, the target shift value is the shift value used when judging the switching state of the cyclic shift switch according to the judgment formula when the minimum shift unit is not 1.

[0098] For example, taking the shift value as 9 and the minimum shift unit as 2, the shift value used in the judgment formula (that is, the target shift value) is the quotient of 9 divided by 2, which is 4. In order to distinguish it from the initial shift value, the re-determined shift value is called the target shift value.

[0099] For example, Figure 2 Taking a cyclic shift switch in which the data at the input end is a0 and a1 and the data at the output end is b0 and b1 as an example, if the switching state of the switch is the first state, b0 output at the output end is a1, and b1 output is a0. The function of the cyclic shift switch is to swap the order of the input a0 and b0; and if the switching state of the switch is the second state, b0 output at the output end is a0, and b1 output is a1. The function of the cyclic shift switch is to output the input a0 and b0 directly without swapping the order.

[0100] For example, if the number of bits of the data to be cyclically shifted and the number of input terminals of the multi-level cyclic shift network are both 8, then N is 3, K is 4, and when the shift value V is 0, for SW 1,1 , substituting k=1, n=1, V=0 into mod[mod(k-1,2 n-1 )-V, 2 n ) the calculated result is 0, 0 is less than 1, then the SW 1,1 The switch state of is the second state, and the switch states of other cyclic shift switches can be obtained according to the same calculation process. Since the calculation process is similar, the calculation process is not repeated here. According to the above judgment formula, the switch state of each cyclic shift switch is the second state, that is, no data exchange is performed, the final input and output are the same, and no cyclic shift operation is performed; when the shift value V is 1, according to the above judgment formula, the switch numbered SW 1,1 , SW 2,1 , SW 3,1 , SW 4,1 , SW 1,2 , SW 3,2 , SW 1,3 The switch state of the cyclic shift switch with number is the first state, and the switch states of the cyclic shift switches with other numbers are the second state.

[0101] Further, after determining the switch states of the circular shift switches corresponding to the digits of the data to be circularly shifted and the corresponding shift values, the control vectors corresponding to the circular shifters can be determined according to the circular shifters corresponding to the circular shift switches, and the mapping relationship between the number of bits of the data to be circularly shifted, the shift value and the determined control vectors corresponding to the circular shifters can be stored in a memory (for example, in a read-only memory), so that the control vectors corresponding to the circular shifters can be directly determined according to the mapping relationship, the number of bits of the data to be circularly shifted and the shift value during the subsequent circular shift operation, thereby avoiding the problem of large real-time calculation amount and long calculation time caused by real-time determination of the control vectors corresponding to the circular shifters during the circular shift operation; wherein, in the control vector, 1 can be used to indicate that the switch state of the circular shift switch is the first state, and 0 can be used to indicate that the switch state of the circular shift switch is the second state.

[0102] Specifically, for any of the cyclic shifters, the switch states of the cyclic shift switches constituting the cyclic shifter may be arranged in a preset arrangement manner to obtain a control vector corresponding to the cyclic shifter.

[0103] For example, taking the example that the circular shifter A is composed of 4 circular shift switches, and the switch states of each circular shift switch are 1, 1, 0, 0 respectively, after arranging them according to a preset arrangement, the control vector corresponding to the circular shifter A can be obtained as (1, 1, 0, 0).

[0104] Here, it should be noted that the control vector may be predetermined, and may be determined after the cyclic shift parameter is acquired.

[0105] S104: Determine a data cyclic shift result based on the target output data and the cyclic shift parameter.

[0106] Here, it is possible to first detect whether the target output data contains padding data, and if it is detected that the target output data contains padding data, delete the padding data. Then, when determining the data cyclic shift result, it can be divided into the following two cases:

[0107] Case 1: The minimum shift unit is the preset value

[0108] Here, the preset value may be 1, that is, the number of bits when the multi-level cyclic shift network performs a shift operation is 1, and the target output data obtained after deleting the padding data can be used as the data cyclic shift result.

[0109] Case 2: The minimum shift unit is not the preset value

[0110] In this case, since the shift value in the circular shift parameter cannot be achieved by shifting only based on the minimum shift unit (for example, if the shift value is 9 and the minimum shift unit is 4, the shift value 9 cannot be reached no matter how the minimum shift unit is moved), the target output data can be rearranged based on the shift value and the minimum shift unit to obtain the data circular shift result.

[0111] Specifically, the target output data can be rearranged according to the shift value and the remainder of the minimum shift unit. The shift direction in the rearrangement operation is the same as the shift direction in the circular shift parameter. The process of the rearrangement operation can be regarded as a process of setting the minimum shift unit to 1 and re-performing a circular shift with the remainder as the shift number, which will not be elaborated here.

[0112] Exemplarily, a schematic diagram of performing a rearrangement operation on the target output data may be as follows: Figure 4 As shown, Figure 4 In the example, the number of input data to be cyclically shifted is 64, and the input data is a0~a 63 , the shift value is 9, the shift direction is left shift, since the number of input terminals of the multi-level cyclic shift network is 16, the number of network layers of the multi-level cyclic shift network is 4, and the minimum shift unit is 4, then the corresponding target shift value is 2, and the data shift operation is performed according to the target shift value. The cyclic shift results obtained are represented by A as A2, A3, A4, A5, A6, A7, A8, A9, A 10 , A 11 , A 12 , A 13 , A 14 , A 15 , A0, A1, expressed as a8, a9, a 10 、a 11 、a 12 、a 13 、a 14 、a 15 、a 16 、a 17 、a 18 、a 19 、a 20 、a 21 、a 22 、a 23 、a 24 、a 25 、a 26 、a 27 、a 28 、a 29 、a 30 、a 31 、a 32 、a33 、a 34 、a 35 、a 36 、a 37 、a 38 、a 39 、a 40 、a 41 、a 42 、a 43 、a 44 、a 45 、a 46 、a 47 、a 48 、a 49 、a 50 、a 51 、a 52 、a 53 、a 54 、a 55 、a 56 、a 57 、a 58 、a 59 、a 60 、a 61 、a 62 、a 63 , a0, a1, a2, a3, a4, a5, a6, a7, after obtaining the result after the cyclic shift, a Reorder operation (i.e., a rearrangement operation) can be performed according to the shift value 9 and the remainder 1 of the minimum shift unit 4, the rearrangement operation is to perform a cyclic shift again on the result of the cyclic shift according to the remainder 1, the shift direction of the rearrangement operation is the same as the shift direction, both are shifted to the left, and the rearranged results a9, a 10 、a 11 、a 12 、a 13 、a 14 、a 15 、a 16 、a 17 、a 18 、a 19 、a 20 、a 21 、a 22 、a 23 、a 24 、a 25 、a 26 、a 27 、a 28 、a 29 、a 30 、a 31 、a 32 、a 33 、a 34 、a35 、a 36 、a 37 、a 38 、a 39 、a 40 、a 41 、a 42 、a 43 、a 44 、a 45 、a 46 、a 47 、a 48 、a 49 、a 50 、a 51 、a 52 、a 53 、a 54 、a 55 、a 56 、a 57 、a 58 、a 59 、a 60 、a 61 、a 62 、a 63 , a0, a1, a2, a3, a4, a5, a6, a7, a8.

[0113] In a possible implementation manner, a delay may be added to the data in the data cyclic shift result according to the shift delay, so as to adjust the timing of the data in the data cyclic shift result.

[0114] Here, according to the needs of the actual application scenario, a delay can be added after the output of any layer of the cyclic shift network, and the data after the delay is input into the next layer of the cyclic shift network. For example, Figure 2 A delay is added to the output b0 of the first-layer cyclic shift network, and the delayed b0 is input into the second-layer cyclic shift network to continue the cyclic shift operation. For how to add the delay and the effect of the delay, please refer to the above related content, which will not be repeated here.

[0115] It should be noted that when adding delay, branch delay can be added after the output of any layer of cyclic shift network according to the needs of the actual application scenario. The branch delays after the outputs of different layers of cyclic shift networks can be different, as long as the sum of the branch delays added after the outputs of each layer of cyclic shift network is equal to the shift delay in the cyclic shift parameter.

[0116] Exemplarily, taking the shift delay of 3 as an example, a branch delay with a delay value of 1 can be added after the output of the 1st layer cyclic shift network, the 2nd layer cyclic shift network, and the 3rd layer cyclic shift network, respectively, so as to meet the overall shift delay requirements of the multi-level cyclic shift network.

[0117] The data cyclic shift method provided by the embodiment of the present disclosure determines the target input data based on the cyclic shift parameter and the data to be cyclically shifted, and after obtaining the target output result based on the multi-level cyclic shift network, processes the target output data according to the cyclic shift parameter to obtain the data cyclic shift result. In this way, the applicability of using the multi-level cyclic shift network for data cyclic shift operations can be improved, so that the multi-level cyclic shift network can adapt to the data cyclic shift requirements in different application scenarios.

[0118] Based on the same inventive concept, a data cyclic shift device corresponding to the data cyclic shift method is also provided in the embodiment of the present disclosure. Since the principle of solving the problem by the device in the embodiment of the present disclosure is similar to the above-mentioned data cyclic shift method in the embodiment of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0119] See also Figure 5 As shown, it is a schematic diagram of the architecture of a data cyclic shift device provided in an embodiment of the present disclosure, wherein the data cyclic shift device comprises: a processor 51, a memory 52 and a multi-level cyclic shift network 53, wherein the multi-level cyclic shift network comprises a plurality of cyclic shifters; wherein:

[0120] The memory 52 is used to store a predetermined mapping relationship between each cyclic shift parameter and a control vector; the control vector is predetermined based on the target level of each cyclic shifter in the multi-level cyclic shift network, the target position in the target level, and the cyclic shift parameter;

[0121] The processor 51 is configured to, after acquiring the data to be cyclically shifted and the cyclic shift parameters, determine the target input data based on the cyclic shift parameters and the data to be cyclically shifted, and extract a control vector matching the cyclic shift parameters from the memory; input the target input data and the extracted control vector into the multi-level cyclic shift network, and determine the data cyclic shift result based on the target output data output by the multi-level cyclic shift network and the cyclic shift parameters;

[0122] The multi-level cyclic shift network 53 is used to perform a cyclic shift operation on the target input data based on each cyclic shifter.

[0123] In one possible implementation, the cyclic shift parameter includes a shift value, and at least one of the following: a shift direction, a shift delay, a minimum shift unit, and the number of input terminals of the multi-level cyclic shift network, wherein the minimum shift unit represents the number of unit processing bits when the multi-level cyclic shift network performs a shift operation.

[0124] In one possible implementation, the processor 51 is specifically used to determine the total number of bits of target cyclic shift data input to each input end of the multi-level cyclic shift network based on the minimum shift unit and the number of input ends of the multi-level cyclic shift network; when it is detected that the total number of bits of the target cyclic shift data is different from the number of bits of the data to be cyclically shifted, determine the target cyclic shift data input to each input end of the multi-level cyclic shift network based on the data to be cyclically shifted, the minimum shift unit and the number of input ends of the multi-level cyclic shift network.

[0125] In one possible implementation, the processor 51 is specifically configured to, when detecting that the number of bits of the data to be cyclically shifted is less than the total number of bits, fill the data to be cyclically shifted with padding data to obtain target cyclically shifted data with a number of data bits equal to the total number of bits; and determine the target cyclically shifted data input to each input terminal of the multi-level cyclic shift network based on the target cyclic data and the number of input terminals of the multi-level cyclic shift network.

[0126] In a possible implementation manner, the processor 51 is specifically configured to input the target cyclic shift data to corresponding input ends respectively; and input the control vectors corresponding to the cyclic shift parameters to corresponding cyclic shifters respectively;

[0127] Each of the cyclic shifters in the multi-level cyclic shift network is used to perform cyclic shift processing on the target cyclic shift data according to the control vector to obtain the target output data.

[0128] In a possible implementation manner, the processor 51 is further configured to, when detecting that the target output data includes padding data, delete the padding data to obtain a data cyclic shift result after deleting the padding data.

[0129] In a possible implementation manner, the processor 51 is specifically configured to, when detecting that the minimum shift unit is not a preset value, rearrange the target output data based on the shift value and the minimum shift unit to obtain the data cyclic shift result.

[0130] In a possible implementation manner, the processor 51 is further configured to add a delay to the data in the data cyclic shift result according to the shift delay, so as to adjust the timing of the data in the data cyclic shift result.

[0131] Regarding the specific implementation process of the above-mentioned device, reference can be made to the description of the method embodiment, which will not be repeated here.

[0132] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0133] Corresponding to the data cyclic shift method described in the above embodiment, the present disclosure also provides a data cyclic shift device, which is different from Figure 5 The device shown in FIG. 1 is a virtual device corresponding to the data cyclic shift method. Figure 6 FIG. 1 is a schematic diagram of the architecture of a data cyclic shift device provided by an embodiment of the present disclosure, including:

[0134] An acquisition unit 601 is used to acquire data to be cyclically shifted and cyclic shift parameters;

[0135] A first determining unit 602, configured to determine target input data based on the cyclic shift parameter and the data to be cyclically shifted;

[0136] A shift unit 603 is configured to input the target input data and the obtained corresponding control vector into a multi-level cyclic shift network to obtain target output data output by the multi-level cyclic shift network; wherein the multi-level cyclic shift network includes a plurality of cyclic shifters, and the control vector for controlling each cyclic shifter to perform a cyclic shift operation is predetermined based on the target level of each cyclic shifter in the multi-level cyclic shift network, the target position in the target level, and the cyclic shift parameter;

[0137] The second determining unit 604 is configured to determine a data cyclic shift result based on the target output data and the cyclic shift parameter.

[0138] Based on the same technical concept, the embodiment of the present disclosure also provides a computer device. Figure 7 As shown, it is a schematic diagram of the structure of a computer device 700 provided in an embodiment of the present disclosure, including a processor 701, a memory 702, and a bus 703. Among them, the memory 702 is used to store execution instructions, including a memory 7021 and an external memory 7022; the memory 7021 here is also called an internal memory, which is used to temporarily store the operation data in the processor 701, and the data exchanged with the external memory 7022 such as a hard disk. The processor 701 exchanges data with the external memory 7022 through the memory 7021. When the computer device 700 is running, the processor 701 communicates with the memory 702 through the bus 703, so that the processor 701 executes the following instructions:

[0139] Obtaining data to be cyclically shifted and cyclic shift parameters;

[0140] Determining target input data based on the cyclic shift parameter and the data to be cyclically shifted;

[0141] Inputting the target input data and the obtained corresponding control vector into a multi-level cyclic shift network to obtain target output data output by the multi-level cyclic shift network; wherein the multi-level cyclic shift network comprises a plurality of cyclic shifters, and the control vector for controlling each cyclic shifter to perform a cyclic shift operation is predetermined based on the target level of each cyclic shifter in the multi-level cyclic shift network, the target position in the target level, and the cyclic shift parameter;

[0142] A data cyclic shift result is determined based on the target output data and the cyclic shift parameter.

[0143] An embodiment of the present disclosure further provides a chip, wherein the chip is equipped with a data cyclic shift device as described in any embodiment of the present disclosure.

[0144] The embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the data cyclic shift method described in the above method embodiment are executed. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0145] The embodiments of the present disclosure also provide a computer program product, which carries a program code. The instructions included in the program code can be used to execute the steps of the data cyclic shift method described in the above method embodiment. For details, please refer to the above method embodiment, which will not be repeated here.

[0146] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is implemented as a computer storage medium. In another optional embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0147] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0148] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0149] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0150] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0151] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A data cyclic shift device, characterized in that: include: A processor, a memory and a multi-level cyclic shift network, wherein the multi-level cyclic shift network comprises a plurality of cyclic shifters; The cyclic shifter is composed of at least one cyclic shift switch; wherein: The memory is used to store a predetermined mapping relationship between each cyclic shift parameter and a control vector; the control vector is determined based on the target level of each cyclic shifter in the multi-level cyclic shift network, the target position in the target level, and the cyclic shift parameter; The processor is configured to, after acquiring the data to be cyclically shifted and the cyclic shift parameters, determine the target input data based on the cyclic shift parameters and the data to be cyclically shifted, and extract a control vector matching the cyclic shift parameters from the memory; input the target input data and the extracted control vector into the multi-level cyclic shift network, and determine the data cyclic shift result based on the target output data output by the multi-level cyclic shift network and the cyclic shift parameters; The multi-level cyclic shift network is used to perform a cyclic shift operation based on each cyclic shifter on the target input data; The cyclic shift parameter comprises a shift value; The control vector for controlling each cyclic shifter to perform a cyclic shift operation is determined according to the following method: For any of the cyclic shift switches in each cyclic shifter, when it is detected that mod[mod(k-1, 2n-1)-V, 2n)]≥2n-1 is satisfied, setting the switch state of the cyclic shift switch to the first state; and When it is detected that mod[mod(k-1, 2n-1)-V, 2n)]<2n-1, the switch state of the cyclic shift switch is set to the second state; Wherein, V is the shift value, n and k represent the target level of the cyclic shift switch in the multi-level cyclic shift network and the target position in the target level, respectively, and mod represents a modulo operation.

2. The device according to claim 1, characterized in that The cyclic shift parameters also include at least one of the following: shift direction, shift delay, minimum shift unit and the number of input terminals of the multi-level cyclic shift network, wherein the minimum shift unit represents the number of unit processing bits when the multi-level cyclic shift network performs a shift operation.

3. The device according to claim 2, characterized in that The processor is specifically configured to determine the total number of bits of target cyclic shift data input to each input end of the multi-level cyclic shift network based on the minimum shift unit and the number of input ends of the multi-level cyclic shift network; When it is detected that the total number of bits of the target cyclic shift data is different from the number of bits of the data to be cyclic shifted, the target cyclic shift data input to each input end of the multi-level cyclic shift network is determined based on the data to be cyclic shifted, the minimum shift unit and the number of input ends of the multi-level cyclic shift network.

4. The device according to claim 3, characterized in that The processor is specifically configured to fill the data to be cyclically shifted with filling data when detecting that the number of bits of the data to be cyclically shifted is less than the total number of bits, so as to obtain target cyclically shifted data with a number of data bits equal to the total number of bits; Based on the target cyclic shift data and the number of input terminals of the multi-level cyclic shift network, target cyclic shift data input to each input terminal of the multi-level cyclic shift network is determined.

5. The device according to claim 3, characterized in that The processor is specifically configured to input the target cyclic shift data to corresponding input terminals respectively; and input the control vectors corresponding to the cyclic shift parameters to corresponding cyclic shifters respectively; Each of the cyclic shifters in the multi-level cyclic shift network is used to perform cyclic shift processing on the target cyclic shift data according to the control vector to obtain the target output data.

6. The device according to claim 1, characterized in that The processor is further configured to delete the padding data when detecting that the target output data includes padding data, and obtain a data cyclic shift result after deleting the padding data.

7. The device according to any one of claims 2 to 4, characterized in that: The processor is specifically configured to rearrange the target output data based on the shift value and the minimum shift unit to obtain the data cyclic shift result when it is detected that the minimum shift unit is not a preset value.

8. The device according to claim 2, characterized in that The processor is further configured to add a delay to the data in the data cyclic shift result according to the shift delay, so as to adjust the timing of the data in the data cyclic shift result.

9. A data cyclic shift method, characterized in that: include: Obtaining data to be cyclically shifted and cyclic shift parameters; Determining target input data based on the cyclic shift parameter and the data to be cyclically shifted; Inputting the target input data and the obtained corresponding control vector into a multi-level cyclic shift network to obtain target output data output by the multi-level cyclic shift network; wherein the multi-level cyclic shift network comprises a plurality of cyclic shifters, and the cyclic shifter comprises at least one cyclic shift switch; the control vector for controlling each cyclic shifter to perform a cyclic shift operation is predetermined based on the target level of each cyclic shifter in the multi-level cyclic shift network, the target position in the target level, and the cyclic shift parameter; Determining a data cyclic shift result based on the target output data and the cyclic shift parameter; The cyclic shift parameter comprises a shift value; The control vector for controlling each cyclic shifter to perform a cyclic shift operation is determined according to the following method: For any of the cyclic shift switches in each cyclic shifter, when it is detected that mod[mod(k-1, 2n-1)-V, 2n)]≥2n-1 is satisfied, setting the switch state of the cyclic shift switch to the first state; and When it is detected that mod[mod(k-1, 2n-1)-V, 2n)]<2n-1, the switch state of the cyclic shift switch is set to the second state; Wherein, V is the shift value, n and k represent the target level of the cyclic shift switch in the multi-level cyclic shift network and the target position in the target level, respectively, and mod represents a modulo operation.

10. A chip, characterized in that: The chip is equipped with a data cyclic shift device as described in any one of claims 1 to 8.

11. A computer device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processor communicates with the memory via the bus, and when the machine-readable instructions are executed by the processor, the steps of the data cyclic shift method according to claim 9 are performed; Or, comprising: a chip as claimed in claim 10.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data cyclic shift method as claimed in claim 9 are executed.

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