Level Shifters and Digital Isolators

Abstract

The present invention provides a level shifter and a digital isolator, the level shifter also includes a bias current transient enhancement unit and an edge fast response unit; the input signal end is connected to the level shift main unit, the bias current transient enhancement unit and the edge fast response unit; the output end of the bias current transient enhancement unit is connected to the input end of the edge fast response unit, the output end of the edge fast response unit is connected to the output end of the level shift main unit, and the output end of the level shift main unit is used as the output signal end; the bias current transient enhancement unit is used to provide the edge fast response unit with a transient enhanced bias current during the input signal jump process, and the edge fast response unit is used to respond quickly under the action of the bias current to speed up the conversion speed of the output level of the level shift main unit. The problem of slow response of the traditional level shifter when the input signal level suddenly changes is solved.

Description

Technical Field

[0001] The present invention relates to the field of isolators, and in particular to a level shifter and a digital isolator. Background Art

[0002] The main function of the level shifter is to achieve level conversion. In the design of the new generation of electronic circuits, with the introduction of low-voltage logic circuits, there is often a problem of input and output logic incoordination within the circuit system. When two different power supply voltages are cascaded, the problem of level conversion needs to be solved.

[0003] Commonly used level shifters include Figure 1 As shown, it includes two inverted input signal ports Vin_p and Vin_n, two inverted output ports Vout_p and Vout_n, a fourteenth PMOS tube, a fifteenth PMOS tube, a fourteenth NMOS tube and a fifteenth NMOS tube. In practical applications, there are the following deficiencies:

[0004] 1. When the traditional level shifter is working, when the input signal changes suddenly, since the two output port levels control the gates of the fourteenth PMOS tube and the fifteenth PMOS tube, it is difficult for the working states of the two tubes to change quickly, resulting in a slow conversion rate of the level converter;

[0005] 2. If the circuit is expected to work better, the fourteenth NMOS tube and the fifteenth NMOS tube group must have a better ability to transmit current in order to accelerate the level conversion, which requires the fourteenth NMOS tube and the fifteenth NMOS tube to be large-size devices, which will increase power consumption and reduce integration.

[0006] The above two problems limit the applicability of traditional level shifters. Summary of the invention

[0007] The purpose of the embodiments of the present invention is to provide a level shifter, which is used to solve the disadvantage of the level shifter in the prior art that the response speed is slow during level conversion, and can achieve stable level conversion.

[0008] In order to achieve the above-mentioned object, the present invention provides a level shifter, comprising an input signal terminal, an output signal terminal and a level shift main unit, the level shifter further comprising a bias current transient enhancement unit and an edge fast response unit; the input signal terminal is connected to the level shift main unit, the bias current transient enhancement unit and the edge fast response unit; the output terminal of the bias current transient enhancement unit is connected to the input terminal of the edge fast response unit, the output terminal of the edge fast response unit is connected to the output terminal of the level shift main unit, and the output terminal of the level shift main unit serves as the output signal terminal;

[0009] The bias current transient enhancement unit is used to provide a transient enhanced bias current to the edge fast response unit during the input signal jump process, and the edge fast response unit is used to respond quickly under the action of the bias current to speed up the conversion speed of the output level of the level shift main unit. The bias current transient enhancement unit can provide a larger bias current to the edge fast response unit during the signal jump process, improve the response speed of the edge fast response unit, and the edge fast response unit can improve the response speed of the circuit when the input level is converted, further speeding up the level conversion speed of the level shifter.

[0010] Further, the input signal terminal includes a first input signal terminal and a second input signal terminal;

[0011] The first input signal terminal is connected to an inverter, and the output terminal of the inverter serves as a second input signal terminal;

[0012] The first input signal terminal is also connected to the input terminal of the level shift main unit, the input terminal of the bias current transient enhancement unit and the input terminal of the edge fast response unit respectively; the input signal is transmitted to the level shift main unit, the bias current transient enhancement unit and the edge fast response unit through the first input signal terminal;

[0013] The second input signal terminal is connected to the input terminal of the level shift main unit and the input terminal of the edge fast response unit respectively; the inverted input signal output by the inverter is transmitted to the level shift main unit and the edge fast response unit through the second input signal terminal.

[0014] Further, the bias current transient enhancement unit includes: a third capacitor, a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a thirteenth NMOS transistor and a thirteenth PMOS transistor;

[0015] The first input signal terminal is connected to one end of the third capacitor, the other end of the third capacitor is connected to the source of the thirteenth NMOS tube and the source of the first PMOS tube, the gate of the thirteenth NMOS tube is connected to the first bias voltage; the gate of the first PMOS tube is connected to the second bias voltage, the source of the thirteenth PMOS tube is connected to the power supply terminal, the gate and drain of the thirteenth PMOS tube are connected to the drain of the thirteenth NMOS tube, the drain of the second NMOS tube and the gate of the second PMOS tube; the drain and gate of the first NMOS tube are connected to the drain of the first PMOS tube and the gate of the second NMOS tube; the sources of the first NMOS tube and the second NMOS tube are both connected to the ground terminal, and the source of the second PMOS tube is connected to the power supply terminal; the drain of the second PMOS tube outputs the transient enhanced bias current to the edge fast response unit.

[0016] Further, the output signal terminal includes a first output signal terminal and a second output signal terminal;

[0017] The edge fast response unit includes: a first capacitor, a second capacitor, a third NMOS tube, a third PMOS tube, a fourth NMOS tube, a fourth PMOS tube, a fifth NMOS tube, a fifth PMOS tube, a sixth NMOS tube, a sixth PMOS tube, a seventh NMOS tube, a ninth PMOS tube, a tenth NMOS tube, a tenth PMOS tube, an eleventh NMOS tube, an eleventh PMOS tube, a twelfth NMOS tube and a twelfth PMOS tube;

[0018] The output end of the bias current transient enhancement unit is connected to the drain of the third NMOS tube, the gate and drain of the third NMOS tube are connected, the source of the third NMOS tube is connected to the source of the third PMOS tube, the gate and drain of the third PMOS tube are connected to the gate and drain of the fourth NMOS tube, and the source of the fourth NMOS tube is grounded; the gate of the third NMOS tube is connected to the gate of the fifth NMOS tube and the gate of the eleventh NMOS tube, the drain of the fifth NMOS tube is connected to the gate and drain of the fourth PMOS tube and the gate of the sixth PMOS tube; the source of the fourth PMOS tube and the source of the sixth PMOS tube are connected to the power supply; the source of the fifth NMOS tube is connected to the source of the fifth PMOS tube and one end of the first capacitor, and the other end of the first capacitor is connected to the first input signal end; the gate of the fifth PMOS tube is connected to the gate of the third PMOS tube and the gate of the eleventh PMOS tube, the drain of the fifth PMOS tube is connected to the sixth PMOS tube, and the gate of the fifth PMOS tube is connected to the sixth PMOS tube. The drain and gate of the NMOS tube and the gate of the seventh NMOS tube are connected; the source of the sixth NMOS tube and the source of the seventh NMOS tube are both connected to the ground terminal; the drain of the sixth PMOS tube is connected to the drain of the seventh NMOS tube and is connected to the first output signal terminal; the drain of the eleventh PMOS tube is connected to the drain and gate of the twelfth NMOS tube and the gate of the tenth NMOS tube; the source of the tenth NMOS tube and the source of the twelfth NMOS tube are both connected to the ground terminal; the source of the eleventh PMOS tube is connected to the source of the eleventh NMOS tube and one end of the second capacitor, and the other end of the second capacitor is connected to the output end of the inverter; the drain of the eleventh NMOS tube is connected to the gate and drain of the tenth PMOS tube and the gate of the ninth PMOS tube, and the drain of the ninth PMOS tube is connected to the drain of the tenth NMOS tube and is connected to the second output signal terminal; the source of the tenth PMOS tube and the source of the ninth PMOS tube are connected to the power supply terminal.

[0019] Further, the output signal terminal includes a first output signal terminal and a second output signal terminal;

[0020] The level shift main unit includes: a seventh PMOS tube, an eighth NMOS tube, an eighth PMOS tube and a ninth NMOS tube, the gate of the eighth NMOS tube is connected to the first input signal terminal; the source of the eighth NMOS tube is connected to the ground terminal, the drain of the eighth NMOS tube is connected to the drain of the seventh PMOS tube and the gate of the eighth PMOS tube and connected to the first output signal terminal; the source of the seventh PMOS tube and the source of the eighth PMOS tube are connected to the power supply terminal; the gate of the seventh PMOS tube is connected to the drain of the eighth PMOS tube and the drain of the ninth NMOS tube and connected to the second output signal terminal; the gate of the ninth NMOS tube is connected to the output terminal of the inverter, and the source of the ninth NMOS tube is connected to the ground terminal.

[0021] A second aspect of the present invention provides a digital isolator, wherein the digital isolator uses the level shifter.

[0022] Through the above technical solution, the present invention provides a level shifter that can be applied to a digital isolator, which is characterized by a high level conversion speed to adapt to high-speed application scenarios and can provide a stable level conversion function.

[0023] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0025] Figure 1 This is a conventional level shifter circuit diagram;

[0026] Figure 2 is a block diagram of a level shifter circuit provided by one embodiment of the present invention;

[0027] Figure 3 is a detailed circuit diagram of a level shifter provided in one embodiment of the present invention;

[0028] Figure 4 It is a circuit diagram of a bias current transient enhancement unit of a level shifter provided by an embodiment of the present invention;

[0029] Figure 5 The invention is a circuit diagram of a fast edge response unit of a level shifter provided in one embodiment of the present invention.

[0030] Description of Reference Numerals

[0031] MN1-first NMOS tube, MP1-first PMOS tube, MN2-second NMOS tube, MP2-second PMOS tube, MN3-third NMOS tube, MP3-third PMOS tube, MN4-fourth NMOS tube, MP4-fourth PMOS tube, MN5-fifth NMOS tube, MP5-fifth PMOS tube, MN6-sixth NMOS tube, MP6-sixth PMOS tube, MN7-seventh NMOS tube, MP7-seventh PMOS tube, MN8-eighth NMOS tube, MP8-eighth PMOS tube, MN9-ninth NMOS tube, MP9-ninth PMOS tube, MN 10-the tenth NMOS tube, MP10-the tenth PMOS tube, MN11-the eleventh NMOS tube, MP11-the eleventh PMOS tube, MN12-the twelfth NMOS tube, MP12-the twelfth PMOS tube, MN13-the thirteenth NMOS tube, MP13-the thirteenth PMOS tube, MN14-the fourteenth NMOS tube, MP14-the fourteenth PMOS tube, MN15-the fifteenth NMOS tube, MP15-the fifteenth PMOS tube, C1-the first capacitor, C2-the second capacitor, C3-the third capacitor, INV0-inverter, VBN-the first bias voltage, VBP-the second bias voltage. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0033] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0034] Figure 2 FIG. 1 is a block diagram of a level shifter circuit provided by an embodiment of the present invention. Figure 1As shown, the level shifter includes: an input signal terminal, an output signal terminal and a level shift main unit, and the level shifter also includes a bias current transient enhancement unit and an edge fast response unit; the input signal terminal is connected to the level shift main unit, the bias current transient enhancement unit and the edge fast response unit; the output terminal of the bias current transient enhancement unit is connected to the input terminal of the edge fast response unit, the output terminal of the edge fast response unit is connected to the output terminal of the level shift main unit, and the output terminal of the level shift main unit serves as the output signal terminal;

[0035] The bias current transient enhancement unit is used to provide a transient enhanced bias current to the edge fast response unit during the input signal jump process, and the edge fast response unit is used to respond quickly under the action of the bias current to speed up the conversion speed of the output level of the level shift main unit. The bias current transient enhancement unit can provide a larger bias current to the edge fast response unit during the signal jump process, improve the response speed of the edge fast response unit, and the edge fast response unit can improve the response speed of the circuit when the input level is converted, further speeding up the level conversion speed of the level shifter.

[0036] In one embodiment, Figure 3 As shown, the input signal terminal includes a first input signal terminal Vin_p and a second input signal terminal Vin_n;

[0037] The first input signal terminal Vin_p is connected to the inverter, and the output terminal of the inverter INV0 serves as the second input signal terminal Vin_n;

[0038] The first input signal terminal Vin_p is also connected to the input terminal of the level shift main unit, the input terminal of the bias current transient enhancement unit and the input terminal of the edge fast response unit respectively; the input signal is transmitted to the level shift main unit, the bias current transient enhancement unit and the edge fast response unit through the first input signal terminal Vin_p;

[0039] The second input signal terminal Vin_n is connected to the input terminal of the level shift main unit and the input terminal of the edge fast response unit respectively; the inverted input signal output by the inverter is transmitted to the level shift main unit and the edge fast response unit through the second input signal terminal Vin_n

[0040] In one embodiment, Figure 3 and Figure 4 As shown, the bias current transient enhancement unit includes: a third capacitor C3, a first NMOS transistor MN1, a first PMOS transistor MP1, a second NMOS transistor MN2, a second PMOS transistor MP2, a thirteenth NMOS transistor MN13 and a thirteenth PMOS transistor MP13;

[0041] The first input signal terminal Vin_p is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to the source of the thirteenth NMOS tube MN13 and the source of the first PMOS tube MP1, the gate of the thirteenth NMOS tube MN13 is connected to the first bias voltage VBN; the gate of the first PMOS tube MP1 is connected to the second bias voltage VBP, the source of the thirteenth PMOS tube MP13 is connected to the power supply terminal VDD, the gate and drain of the thirteenth PMOS tube MP13 are connected to the drain of the thirteenth NMOS tube MN13, the drain of the second NMOS tube MN2 and the gate of the second PMOS tube MP2; the drain and gate of the first NMOS tube MN1 are connected to the drain of the first PMOS tube MP1 and the gate of the second NMOS tube MN2; the sources of the first NMOS tube MN1 and the second NMOS tube MN2 are both connected to the ground terminal GND, the source of the second PMOS tube MP2 is connected to the power supply terminal VDD; the drain of the second PMOS tube MP2 outputs the transient enhanced bias current Itune to the edge fast response unit.

[0042] In the above embodiment, the transient enhanced bias current Itune output by the bias current transient enhancement unit is copied from the thirteenth PMOS transistor MP13 to the second PMOS transistor MP2, and the current flowing through the thirteenth PMOS transistor MP13 is the sum of the currents flowing through the thirteenth NMOS transistor MN13 and the second NMOS transistor MN2. When the input signal Vin_p jumps from a high level to a low level, the gate-source voltage difference of the thirteenth NMOS tube MN13 increases, so that the current flowing through increases, and then the current flowing through the thirteenth PMOS tube MP13 increases, so the current copied to the second PMOS tube MP2 increases; when the input signal Vin_p jumps from a low level to a high level, the gate-source voltage difference of the first PMOS tube MP1 increases, so that the current flowing through increases, the current flows through the first NMOS tube MN1 and is copied to the second NMOS tube MN2, so that the current of the second NMOS tube MN2 increases, and then the current flowing through the thirteenth PMOS tube MP13 increases, so the current copied to the second PMOS tube MP2 increases; therefore, when the input signal jumps, the bias current transient enhancement unit will quickly increase the bias current Itune.

[0043] In one embodiment, Figure 3 and Figure 5As shown, the edge fast response unit includes: a first capacitor C1, a second capacitor C2, a third NMOS tube MN3, a third PMOS tube MP3, a fourth NMOS tube MN4, a fourth PMOS tube MP4, a fifth NMOS tube MN5, a fifth PMOS tube MP5, a sixth NMOS tube MN6, a sixth PMOS tube MP6, a seventh NMOS tube MN7, a ninth PMOS tube MP9, a tenth NMOS tube MN10, a tenth PMOS tube MP10, an eleventh NMOS tube MN11, an eleventh PMOS tube MP11, a twelfth NMOS tube MN12 and a twelfth PMOS tube MP12;

[0044] The output end of the bias current transient enhancement unit is connected to the drain of the third NMOS tube MN3, the gate and drain of the third NMOS tube MN3 are connected, the source of the third NMOS tube is connected to the source of the third PMOS tube MP3, the gate and drain of the third PMOS tube MP3 are connected to the gate and drain of the fourth NMOS tube MN4, and the source of the fourth NMOS tube MN4 is grounded to the ground terminal GND; the gate of the third NMOS tube MN3 is connected to the gate of the fifth NMOS tube MN5 and the gate of the eleventh NMOS tube MN11, the drain of the fifth NMOS tube MN5 is connected to the fourth PMOS tube MP3, and the gate of the third PMOS tube MP3 is connected to the gate of the fourth NMOS tube MN4. The gate and drain of the fifth PMOS tube MP4 and the gate of the sixth PMOS tube MP6 are connected; the source of the fourth PMOS tube MP4 and the source of the sixth PMOS tube MP6 are connected to the power supply; the source of the fifth NMOS tube MN5 is connected to the source of the fifth PMOS tube MP5 and one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the first input signal terminal Vin_p; the gate of the fifth PMOS tube MP5 is connected to the gate of the third PMOS tube MP3 and the gate of the eleventh PMOS tube MP11, and the drain of the fifth PMOS tube MP5 is connected to the drain of the sixth NMOS tube MN6. The gate and the gate of the seventh NMOS tube MN7 are connected; the source of the sixth NMOS tube MN6 and the source of the seventh NMOS tube MN7 are both connected to the ground terminal GND; the drain of the sixth PMOS tube MP6 is connected to the drain of the seventh NMOS tube MN7 and is connected to the first output signal terminal Vout_p; the drain of the eleventh PMOS tube MP11 is connected to the drain and the gate of the twelfth NMOS tube MN12 and the gate of the tenth NMOS tube MN10; the source of the tenth NMOS tube MN10 and the source of the twelfth NMOS tube MN12 are both connected to the ground terminal GND; The source of the first PMOS tube MP11 is connected to the source of the eleventh NMOS tube MN11 and one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the output end of the inverter INV0; the drain of the eleventh NMOS tube MN11 is connected to the gate and drain of the tenth PMOS tube MP10 and the gate of the ninth PMOS tube MP9, the drain of the ninth PMOS tube MP9 is connected to the drain of the tenth NMOS tube MN10 and connected to the second output signal end; the source of the tenth PMOS tube MP10 and the source of the ninth PMOS tube MP9 are connected to the power supply end VDD.

[0045] In the above embodiment, when the input signal Vin_p jumps from a high level to a low level, that is, the inverted input signal Vin_n jumps from a low level to a high level, at this time, the output signal Vout_p of the first output signal end is initially at a low level and converts to a high level, and the output signal Vout_n of the second output signal end is initially at a high level and converts to a low level. In the process of the jump, the gate-source voltage difference of the fifth NMOS transistor MN5 increases, and the current flowing through the fifth NMOS transistor MN5 increases, so that the drain voltage of the fourth PMOS transistor MP4 decreases, that is, the drain voltage of the sixth PMOS transistor MP6 decreases, thereby making the sixth PMOS transistor MP6 more conductive, and accelerating the pull-up of the output signal Vout_p level; the gate-source voltage difference of the eleventh PMOS transistor MP11 increases, and the current flowing through the twelfth NMOS transistor MN12 increases, so that the drain voltage of the twelfth NMOS transistor MN12 increases, that is, the drain voltage of the tenth NMOS transistor MN10 increases, thereby making the tenth NMOS transistor MN10 more conductive, and accelerating the pull-down of the output signal Vout_n level.

[0046] When the input signal Vin_p jumps from a low level to a high level, that is, the inverted input signal Vin_n jumps from a high level to a low level, at this time, the output signal Vout_p of the first output signal end is initially at a high level and converts to a low level, and the output signal Vout_n of the second output signal end is initially at a low level and converts to a high level. In the process of the jump, the gate-source voltage difference of the fifth PMOS tube MP5 increases, and the current flowing through the fifth PMOS tube MP5 increases, so that the drain voltage of the sixth NMOS tube MN6 increases, that is, the drain voltage of the seventh NMOS tube MN7 increases, and then the seventh NMOS tube MN7 is more conductive, which accelerates the pull-down of the output signal Vout_p level; the gate-source voltage difference of the eleventh NMOS tube MN11 increases, and the current flowing through the eleventh NMOS tube MN11 increases, so that the drain voltage of the tenth PMOS tube MP10 decreases, that is, the drain voltage of the ninth PMOS tube MP9 decreases, and then the ninth PMOS tube MP9 is more conductive, which accelerates the pull-up of the output signal Vout_p level.

[0047] The bias current Itune output by the bias current transient enhancement unit provides a bias current for the fast edge response unit. If the bias current Itune increases, the current copied to the fifth NMOS tube MN5 and the eleventh NMOS tube MN11 through the third NMOS tube MN3 and the current copied to the fifth PMOS tube MP5 and the eleventh PMOS tube MP11 through the third PMOS tube MP3 both increase, which will increase the difference between the gate-source voltage difference of the fifth NMOS tube MN5 and the fifth PMOS tube MP5 and the gate-source voltage difference of the eleventh NMOS tube MN11 and the eleventh PMOS tube MP11, thereby accelerating the response speed of the circuit. Therefore, the bias current transient enhancement unit can provide a larger bias current for the fast edge response unit during the signal jump process, thereby increasing the response speed of the signal edge fast response unit, and further accelerating the level conversion speed of the level shifter.

[0048] In one embodiment, the level shift main unit includes: a seventh PMOS tube MP7, an eighth NMOS tube MN8, an eighth PMOS tube MP8 and a ninth NMOS tube MN9, the gate of the eighth NMOS tube MN8 is connected to the first input signal terminal Vin_p; the source of the eighth NMOS tube MN8 is connected to the ground terminal GND, the drain of the eighth NMOS tube MN8 is connected to the drain of the seventh PMOS tube MP7 and the gate of the eighth PMOS tube MP8 and connected to the first output signal terminal; the source of the seventh PMOS tube MP7 and the source of the eighth PMOS tube MP8 are connected to the power supply terminal VDD; the gate of the seventh PMOS tube MP7 is connected to the drain of the eighth PMOS tube MP8 and the drain of the ninth NMOS tube MN9 and connected to the second output signal terminal; the gate of the ninth NMOS tube MN9 is connected to the output terminal of the inverter INV0; the source of the ninth NMOS tube MN9 is connected to the ground terminal GND.

[0049] In the above embodiment, when the input signal Vin_p jumps from a high level to a low level, that is, the inverted input signal Vin_n jumps from a low level to a high level, the output signal Vout_p of the first output signal end is initially a low level and is converted to a high level; when the input signal Vin_p jumps from a low level to a high level, that is, the inverted input signal Vin_n jumps from a high level to a low level, the output signal Vout_p of the first output signal end is initially a high level and is converted to a low level, and the output signal Vout_n of the second output signal end is initially a low level and is converted to a high level. Since the output signal Vout_p and the output signal Vout_n control the gates of the seventh PMOS tube MP7MP7 and the eighth PMOS tube MP8MP8, when the output signal Vout_p and the output signal Vout_n are accelerated to change under the action of the bias current transient enhancement unit and the edge fast response unit, the level shifter can also increase the level change speed and the conversion speed of the output signal.

[0050] The present application also provides a digital isolator, which uses the level shifter.

[0051] The level shifter provided by the present invention utilizes a fast edge response unit to improve the response speed of the circuit during input level conversion, and utilizes current transient enhancement technology to further accelerate the response speed of the fast edge response unit at the edge of the input signal, thereby solving the problem of slow response of traditional level shifters when the input signal level suddenly changes, and at the same time, stable level conversion can be achieved. The level shifter can be applied to high-speed digital isolators.

[0052] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, the technical scheme of the embodiments of the present invention can be subjected to a variety of simple modifications, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the embodiments of the present invention will not further describe various possible combinations.

[0053] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the embodiments of the present invention, they should also be regarded as the contents disclosed in the embodiments of the present invention.

Claims

1. A level shifter, comprising an input signal terminal, an output signal terminal and a level shift main unit, characterized in that: The level shifter also includes a bias current transient enhancement unit and an edge fast response unit; The input signal terminal is connected to the level shift main unit, the bias current transient enhancement unit and the edge fast response unit; the output terminal of the bias current transient enhancement unit is connected to the input terminal of the edge fast response unit, the output terminal of the edge fast response unit is connected to the output terminal of the level shift main unit, and the output terminal of the level shift main unit serves as the output signal terminal; The bias current transient enhancement unit is used to provide a transient enhanced bias current to the edge fast response unit during the input signal jump process, and the edge fast response unit is used to respond quickly under the action of the bias current to speed up the conversion speed of the output level of the level shift main unit; The input signal terminal includes a first input signal terminal and a second input signal terminal; The first input signal terminal is connected to an inverter, and the output terminal of the inverter serves as a second input signal terminal; The first input signal terminal is also connected to the input terminal of the level shift main unit, the input terminal of the bias current transient enhancement unit and the input terminal of the edge fast response unit respectively; The input signal is transmitted to the level shift main unit, the bias current transient enhancement unit and the edge fast response unit through the first input signal terminal; The second input signal terminal is connected to the input terminal of the level shift main unit and the input terminal of the edge fast response unit respectively; The inverted input signal output by the inverter is transmitted to the level shift main unit and the edge fast response unit through the second input signal terminal.

2. The level shifter according to claim 1, wherein: The bias current transient enhancement unit includes: a third capacitor, a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a thirteenth NMOS transistor and a thirteenth PMOS transistor; The first input signal terminal is connected to one end of the third capacitor, the other end of the third capacitor is connected to the source of the thirteenth NMOS tube and the source of the first PMOS tube, the gate of the thirteenth NMOS tube is connected to the first bias voltage; the gate of the first PMOS tube is connected to the second bias voltage, the source of the thirteenth PMOS tube is connected to the power supply terminal, the gate and drain of the thirteenth PMOS tube are connected to the drain of the thirteenth NMOS tube, the drain of the second NMOS tube and the gate of the second PMOS tube; the drain and gate of the first NMOS tube are connected to the drain of the first PMOS tube and the gate of the second NMOS tube; the sources of the first NMOS tube and the second NMOS tube are both connected to the ground terminal, and the source of the second PMOS tube is connected to the power supply terminal; the drain of the second PMOS tube outputs the transient enhanced bias current to the edge fast response unit.

3. The level shifter according to claim 2, characterized in that: The output signal terminal includes a first output signal terminal and a second output signal terminal; The edge fast response unit includes: a first capacitor, a second capacitor, a third NMOS tube, a third PMOS tube, a fourth NMOS tube, a fourth PMOS tube, a fifth NMOS tube, a fifth PMOS tube, a sixth NMOS tube, a sixth PMOS tube, a seventh NMOS tube, a ninth PMOS tube, a tenth NMOS tube, a tenth PMOS tube, an eleventh NMOS tube, an eleventh PMOS tube, a twelfth NMOS tube and a twelfth PMOS tube; The output end of the bias current transient enhancement unit is connected to the drain of the third NMOS tube, the gate and drain of the third NMOS tube are connected, the source of the third NMOS tube is connected to the source of the third PMOS tube, the gate and drain of the third PMOS tube are connected to the gate and drain of the fourth NMOS tube, and the source of the fourth NMOS tube is grounded; the gate of the third NMOS tube is connected to the gate of the fifth NMOS tube and the gate of the eleventh NMOS tube, the drain of the fifth NMOS tube is connected to the gate and drain of the fourth PMOS tube and the gate of the sixth PMOS tube; the source of the fourth PMOS tube and the source of the sixth PMOS tube are connected to the power supply; the source of the fifth NMOS tube is connected to the source of the fifth PMOS tube and one end of the first capacitor, and the other end of the first capacitor is connected to the first input signal end; the gate of the fifth PMOS tube is connected to the gate of the third PMOS tube and the gate of the eleventh PMOS tube, the drain of the fifth PMOS tube is connected to the sixth PMOS tube, and the gate of the fifth PMOS tube is connected to the sixth PMOS tube. The drain and gate of the NMOS tube and the gate of the seventh NMOS tube are connected; the source of the sixth NMOS tube and the source of the seventh NMOS tube are both connected to the ground terminal; the drain of the sixth PMOS tube is connected to the drain of the seventh NMOS tube and is connected to the first output signal terminal; the drain of the eleventh PMOS tube is connected to the drain and gate of the twelfth NMOS tube and the gate of the tenth NMOS tube; the source of the tenth NMOS tube and the source of the twelfth NMOS tube are both connected to the ground terminal; the source of the eleventh PMOS tube is connected to the source of the eleventh NMOS tube and one end of the second capacitor, and the other end of the second capacitor is connected to the output end of the inverter; the drain of the eleventh NMOS tube is connected to the gate and drain of the tenth PMOS tube and the gate of the ninth PMOS tube, and the drain of the ninth PMOS tube is connected to the drain of the tenth NMOS tube and is connected to the second output signal terminal; the source of the tenth PMOS tube and the source of the ninth PMOS tube are connected to the power supply terminal.

4. The level shifter according to claim 1, wherein: The output signal terminal includes a first output signal terminal and a second output signal terminal; The level shift main unit includes: a seventh PMOS tube, an eighth NMOS tube, an eighth PMOS tube and a ninth NMOS tube, the gate of the eighth NMOS tube is connected to the first input signal terminal; the source of the eighth NMOS tube is connected to the ground terminal, the drain of the eighth NMOS tube is connected to the drain of the seventh PMOS tube and the gate of the eighth PMOS tube and connected to the first output signal terminal; the source of the seventh PMOS tube and the source of the eighth PMOS tube are connected to the power supply terminal; the gate of the seventh PMOS tube is connected to the drain of the eighth PMOS tube and the drain of the ninth NMOS tube and connected to the second output signal terminal; the gate of the ninth NMOS tube is connected to the output terminal of the inverter, and the source of the ninth NMOS tube is connected to the ground terminal.

5. A digital isolator, characterized in that: The digital isolator uses the level shifter according to any one of claims 1 to 4.

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