Compiling for a synchronous processor

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for compiling a latency-insensitive program for a synchronous processor. One of the methods includes receiving an intermediate representation of a program that specifies a plurality of operations to be performed by a plurality of respective components of a synchronous processor, wherein the intermediate representation assigns a respective clock cycle value to each of the plurality of operations at which the operation is scheduled to be performed by the synchronous processor. The intermediate representation is processed to generate a respective update window for each operation in the intermediate representation that requires a hardware configuration update, wherein the update window specifies a range of time during which a configuration update instruction can be executed to effect the hardware configuration update. The configuration update instruction is scheduled to occur during one or more of the update windows and in accordance with configuration constraints of the synchronous processor.

Description

Technical Field

[0001] This specification relates to compiler technology for synchronous integrated circuit accelerators. Background Technology

[0002] Synchronous integrated circuit accelerators are application-specific integrated circuits (ASICs) designed for highly parallel synchronous operations. Parallelism is achieved by integrating many different independent processing elements that can be executed simultaneously. Such devices are well-suited for accelerating inference propagation through neural networks, for example, where each independent processing element performs different multiplications or additions of layer inputs with weights.

[0003] For the sake of brevity, such a device will be referred to as a synchronous processor or synchronous chip in this specification. In practice, such a device can be implemented using multiple silicon wafers (e.g., using die stacks or silicon interposers).

[0004] In this specification, a synchronous processor means that operations performed by independent processing units do not branch, such as in an if / else statement in an imperative program. Instead, operations can be partially or fully scheduled ahead of time. For example, some synchronous processor operations must be scheduled down to the single-cycle level, meaning that each operation of each processing element is assigned to a specific time slot within the execution cycle.

[0005] This complexity makes programming synchronous processors extremely error-prone. For example, a user error that introduces an unexpected delay in a single cycle can lead to incorrect or undefined computational results, which could mean that multiple passes of the same program might produce different results. Summary of the Invention

[0006] This specification describes techniques for compiling programs written for synchronous processors. The techniques described below relate to scheduling data instructions that manipulate data streams on the processor. The techniques also relate to automatically generating and scheduling configuration update instructions executed by the processor's control hardware.

[0007] Specific embodiments of the subject matter described in this specification can be implemented to achieve one or more of the following advantages. The system can automatically generate a fully scheduled intermediate representation for a synchronous processor from a latency-insensitive input program. This significantly reduces human error in synchronous processor programming. Furthermore, the latency-insensitive program can be reused for different hardware configurations without rewriting. The intermediate representation allows for full scheduling of configuration update instructions and provides the compiler with the ability to raise errors when no possible output program exists.

[0008] Details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. Attached Figure Description

[0009] Figure 1 This is a flowchart of an example process for generating an intermediate representation of the input program.

[0010] Figure 2 This is a graphical representation of the example program.

[0011] Figure 3 This is a flowchart of an example process for issuing configuration update instructions for an intermediate representation.

[0012] Figure 4 This is a diagram illustrating the scheduling of configuration update instructions under given constraints of a synchronous processor.

[0013] Figure 5 This is a schematic diagram illustrating an example of a dedicated logic circuit.

[0014] Figure 6 An example of a tile is shown.

[0015] The same reference numerals and names in the various figures indicate the same elements. Detailed Implementation

[0016] Figure 1 This is a flowchart of an example process for generating an intermediate representation of the input program. For convenience, this process will be described as being performed by a system of one or more computers located in one or more locations and appropriately programmed according to this specification.

[0017] The system receives a program (110) specifying the operations to be performed by components of the synchronous processor. Generally, each statement of the program can specify one or more input variables, output variables, and operations. The program does not need to specify delays or timing information regarding when the operations are performed. Instead, the system can then use the variable names to determine the timing constraints for executing the program on the synchronous processor.

[0018] Table 1 lists an example program that multiplies two values ​​read from RAM, adds the result to a third value read from RAM, and then writes the result back to RAM.

[0019]

[0020] Table 1

[0021] Arrow syntax, such as ("<-name-<"), identifies a subroutine that receives on-chip parameters from the right and assigns their on-chip results to the name on the left. In the case of synchronous processors, arrow syntax can be used to refer to a specific hardware component on the processor. In this example, "addr" is used as the input to the entire compound program, as declared in "procaddr->..." in line 1. In this case, "addr" identifies which processor component's RAM is read from in each of the three read operations. For example, the RAM represented by "addr" could be used to compute and store partial sums for use in the next stage of the program.

[0022] It is worth noting that the example program is latency-insensitive, meaning it does not specify any information about component latency or the timing required to execute each operation. This means that, unlike traditional programs, the program in Table 1 does not need to execute statements sequentially. In fact, due to the characteristics of synchronous processors, statements are typically expected to execute in a different order or in parallel.

[0023] The system obtains the corresponding clock delay value (120) for each component of the synchronous processor. The system can maintain a mapping, such as a table, between (1) each operation identified by a keyword or function in the program and (2) the corresponding clock delay value representing the number of clock cycles occupied by each operation on the synchronous processor. This arrangement allows the same latency-insensitive program to be compiled for different underlying hardware designs. This is advantageous because if the design of the underlying hardware changes some component delay values, the same program can still be compiled for the new hardware design.

[0024] The system generates clock timing constraints (130) for executing the program. Clock timing constraints specify when a particular operation must occur relative to other operations. Typically, a value must be read at least one clock cycle before that value is used. For example, a multiplication operation requiring two inputs has such a constraint: both inputs must be read at least one clock cycle before the multiplication operation begins. Therefore, for example, the multiplication operation in row 5 of Table 1 must begin at least one clock cycle after each read operation in rows 3 and 4. Furthermore, consecutive operations should not overlap in time. The system can generate constraints using variable names in the program to determine which operations must occur after other operations.

[0025] Figure 2This is a graphical representation 200 of the example program. Graphical representation 200 corresponds to the example program listed in Table 1. Graphical representation 200 has nodes, each node corresponding to one of the operations in the program. Thus, the graph has a read node 205 representing the read command for line 2, a read node 210 representing the read command for line 3, a read node 215 representing the read command for line 4, a multiplication node 220 representing the multiplication command for line 5, an addition node 225 representing the addition command for line 6, and a write node 230 representing the write command for line 7.

[0026] To generate clock timing constraints, the system can traverse the program, or equivalently, the edges in the graphical representation, to determine dependencies based on variable names. The system can then calculate the required clock delay values ​​for the dependencies between the discovered operations. For example, if the multiplication operation in line 4 takes 4 cycles, the system can generate a constraint that the addition operation in line 5 depends on the output of the multiplication operation and should not begin 4 cycles after the multiplication operation has started.

[0027] To give another example, the addition operation in line 6 depends on the variable x read in line 2. Therefore, there is a dependency between the operation in line 6 and the operation in line 2.

[0028] like Figure 2 As shown, the two read nodes 205 and 210 have a latency of 1 cycle. Read node 215 has a latency of 2 cycles. Multiplication node 220 has a latency of 4 cycles, addition node 225 has a latency of 3 cycles, and write node 230 has a latency of 1 cycle.

[0029] like Figure 1 As shown, the system generates an intermediate representation of the program, which assigns the corresponding clock cycle value to each of the multiple operations (140). The intermediate representation is intermediate in a sense because it is code at a lower level than the user program, but usually not low enough to be directly executed by a synchronous processor.

[0030] The system can generate intermediate representations by starting with any arbitrary operation in the program and then iterating over dependencies and delays. For example, the system can start at read node 210 and assign read operations to be executed at any starting cycle number (e.g., cycle 0).

[0031] The system can then use the dependency between node 210 and node 220, as well as the one-cycle delay of node 210, to allocate subsequent multiplication operations to be executed in cycle 1.

[0032] The system can then examine another dependency of multiplication node 220, namely read node 215. Read node 215 represents reading from expanded RAM with different characteristics than the RAM used for read node 210. Therefore, the latency is different—two cycles instead of one cycle. The system therefore allocates the read operation of read node 215 to be executed two cycles before the multiplication operation of multiplication operation 220.

[0033] This results in a negative period value of -1. However, the values ​​in the intermediate representation only represent the relative period time, so negative values ​​are allowed, and sometimes even expected or unavoidable.

[0034] The system can then check the dependencies of adder node 225 corresponding to the addition operation. The delay between multiplication node 220 and adder node 225 is 4 cycles, so the system schedules the addition operation to be executed 4 cycles after the multiplication operation, for example, in cycle 5.

[0035] The system can then examine another dependency of adder node 225, namely read node 205. Due to the one-cycle delay of read node 205, the system can schedule the read operation to execute one cycle before adder node 225. Therefore, the system assigns a cycle value of 4 to the read operation.

[0036] Finally, the system checks the dependency of adder node 225, which in this example is write node 230 corresponding to the write operation. Due to the 3-cycle delay of adder node 225, the system assigns a cycle value of 8 to the write operation.

[0037] Therefore, the intermediate representation associates the corresponding cycle time value with each operation in the program. The system can use any suitable data structure to store the intermediate representation. For example, the system can store a mapping between (1) the cycle time value and (2) the instruction identifier, nodes in the graph, instruction text, or some other representation of the operation.

[0038] deal with Figure 2 The example intermediate values ​​generated by the graph shown are presented in Table 2:

[0039]

[0040]

[0041] Table 2

[0042] Unlike the original input procedure, the statements in Table 2 do specify the temporal order of the operations to be performed by the synchronous processor. This order of operations is likely to succeed on actual hardware because all scheduling delay information has been automatically generated down to the cycle level.

[0043] In some cases, a correct intermediate representation does not exist for the input program. In such situations, the system may raise an error indicating that the program cannot be compiled correctly. This can happen, for example, when dependencies in the input program form a cycle. It can also occur when the hardware is not fast enough to generate values ​​that are available when needed.

[0044] As another example, any type of operation with multiple inputs derived from the same intermediate value is likely to be malformed. If a value "a" is produced in cycle 0, a value "b" is calculated from "a" after 3 cycles, and a value "c" is calculated from "a" after 2 cycles, and the program attempts to multiply "b" and "c" together without addressing the latency differences, there is no correct way to schedule these operations. Instead, the user might have to add code to pass "c" to the next cycle, for example, by using RAM or a delay register.

[0045] Although the intermediate representation specifies a periodic scheduling for operations to be performed by the synchronous processor, the compiler can issue additional instructions to actually execute the program on the components of the synchronous processor. In particular, the compiler may need to generate configuration update instructions that specify changes to the data paths between the processing components of the synchronous processor. This is especially true when the instructions have polyhedral semantics, meaning that each sequence of instructions may be executed multiple times. Thus, for example, program semantics might specify that a particular read operation should read from a specific register in 10 consecutive iterations, and then from a different specific register in the next 10 iterations.

[0046] In order to switch from one configuration to another, the processor can issue a configuration update instruction that changes the input on the multiplexer in the data path between processor components.

[0047] Figure 3 This is a flowchart of an example process for issuing configuration update instructions to an intermediate representation. For convenience, this process will be described as being performed by a system of one or more computers located in one or more locations and appropriately programmed according to this specification.

[0048] The system processes the intermediate representation to generate a corresponding update window (310) for each operation. The system processes the instructions in the intermediate representation and generates a corresponding update window for each instruction requiring a configuration update, representing the time range within which the corresponding configuration update instruction needs to be executed. In some implementations, if no configuration update instruction is received, the processor will use the same configuration on the next execution of the operation.

[0049] The system acquires one or more configuration constraints (320) of the synchronous processor. One of the natural configuration constraints of the synchronous processor's control hardware is the number of configuration update instructions that can be executed in a single cycle. For example, some synchronous processors may only support executing 1, 2, 4, or 8 configuration update instructions simultaneously.

[0050] Other configuration constraints may include the periods on which configuration instructions can be executed. For example, in some implementations, configuration update instructions can only be executed once every Nth period, for example, where N is 2, 4, or 8.

[0051] Other configuration constraints may include power domain constraints on how many configuration updates can be performed per power domain of a specified processor.

[0052] The system generates and schedules configuration update instructions (330) based on the update window and configuration constraints. Each configuration update instruction can change the behavior of an instruction in different loop iterations. For example, a configuration update instruction can change the register used in a register read operation. As another example, a configuration update instruction can change the arguments of a multiplexer in the data path of a synchronous processor. This may cause downstream operations to use different arguments in subsequent loop iterations. Typically, each configuration update instruction is scheduled to occur within one of the update windows generated from the intermediate representation of the process. The system can use any appropriate constraint solving procedure to schedule all required configuration update instructions within the available update window. An example constraint solving example will now be described.

[0053] Figure 4 This is a diagram illustrating the scheduling of configuration update instructions under the constraints of a given synchronous processor. Figure 4 It features a horizontal timeline, along which the configuration window and update window are illustrated. This is the information the compiler can generate after processing the intermediate representation of the program as described above.

[0054] The configuration window indicates the time range during which a specific instruction will be executed by a processor with a specific configuration. The update window indicates the time range during which the configuration is not important or is ignored for a specific instruction.

[0055] Therefore, the RegFile0Read instruction 452 is shown to have a first update window 412 and a configuration window 415, in which instruction 452 will be executed using a configuration named C1. During configuration window 415, the processor will repeatedly execute instruction 452 once per cycle using configuration C1.

[0056] Similarly, the RegFile1Read instruction 454 is shown with a second update window 422 and a configuration window 425, in which instruction 454 will be executed using a configuration called C2. During configuration window 415, the processor will repeatedly execute instruction 452 once per cycle using configuration C2. It is worth noting that the second update window 422 is much longer than the first update window 412, which means greater flexibility in issuing configuration update instructions for the RegFile1Read instruction 454.

[0057] The multiplication instruction 456 is shown with a first configuration window 432 and a second configuration window 434. During each of these configuration windows, the processor can perform multiple cycles of the multiplication operation instead of repeating the operation performed for a register read instruction as described above. The multiplication instruction has an update window 435. For example, the update window 435 can change the data path to change the operands of the multiplication operation.

[0058] The addition instruction 458 is also shown as having two configuration windows 442 and 444 during which addition operations will be performed for multiple cycles, and two update windows 443 and 445 during which one or more operands of the addition instruction can be changed.

[0059] The compiler can use update windows to determine the scheduling of configuration update instructions that satisfy processor constraints. In this example, assume the constraint is that the processor can only execute configuration update instructions on cycles X, Y, and Z. Furthermore, the processor has an additional constraint that only two configuration update instructions can be executed on a single cycle.

[0060] Period X overlaps with three update windows. Period Y overlaps with one update window. Period Z also overlaps with three update windows. Therefore, the compiler can select at most two of the three overlapping update windows on periods X and Z.

[0061] The compiler can choose any appropriate constraint-solving flow to determine how to schedule the five configuration updates. For example, the compiler can start with the most constrained update window and work towards the least constrained update window. If no solution is found, the compiler can raise an error indicating that the program cannot execute on the processor.

[0062] like Figure 4 As shown, the most constrained update windows are those that overlap with only a single period in period X, period Y, or period Z. There are four such windows that overlap with only a single period: UW 412, UW 435, UW 443, and UW 445.

[0063] Therefore, the compiler can schedule the corresponding configuration update instructions during these update windows. In other words, the compiler can schedule CU0 401 and CU3 404 during period X, and can schedule CU2 403 and CU4 404 during period Z.

[0064] The compiler can then eliminate any cycles that already have two configuration updates, taking into account the remaining update window. Therefore, the compiler can remove cycles X and Z based on further considerations, since both cycles are fully occupied by configuration update instructions.

[0065] The only remaining unallocated update window is UW422, which still overlaps with cycle Y. Therefore, the compiler can schedule CU1 402 during cycle Y, and the process can end since all configuration update instructions have been successfully scheduled.

[0066] However, consider the case where the second update window 422 equals the first update window 412. In this case, the scheduling problem may have no solution because at least three configuration update instructions would be scheduled for period X. In this scenario, the compiler might throw an error indicating that the configuration update could not be successfully scheduled.

[0067] Figure 5 This is a schematic diagram illustrating an example of a special-purpose logic circuit, specifically an ASIC 500. The ASIC 500 includes multiple synchronous processors, which will be referred to as tiles for simplicity. For example, the ASIC 500 includes tiles 502, wherein one or more of tiles 502 include special-purpose circuitry configured to perform synchronous computations (e.g., multiplication and addition operations). Specifically, each tile 502 may include an array of computational units, wherein each unit is configured to perform mathematical operations (see example...). Figure 6 The exemplary tile 200 shown and described herein. In some embodiments, the tiles 502 are arranged in a grid pattern, wherein the tiles 502 are arranged along a first dimension 501 (e.g., rows) and along a second dimension 503 (e.g., columns). For example, in Figure 5 In the example shown, tile 502 is divided into four distinct sections (510a, 510b, 510c, 510d), each containing 288 tiles arranged in a grid of 18 tiles vertically and 16 tiles horizontally. In some implementations, Figure 5 The ASIC 500 shown can be understood as comprising a single pulsed cell array subdivided / arranged into individual tiles, wherein each tile includes a subset / subarray of cells, local memory, and bus lines (see example...). Figure 6 ).

[0068] The ASIC 500 also includes a vector processing unit 504. The vector processing unit 504 includes circuitry configured to receive output from tile 502 and calculate a vector computation output value based on the output received from tile 502. For example, in some embodiments, the vector processing unit 504 includes circuitry (e.g., multiplication circuitry, adder circuitry, shifter, and / or memory) configured to perform an accumulation operation on the output received from tile 502. Alternatively or additionally, the vector processing unit 504 includes circuitry configured to apply a nonlinear function to the output of tile 502. Alternatively or additionally, the vector processing unit 504 generates a normalized value, a pooled value, or both. The vector computation output of the vector processing unit may be stored in one or more tiles. For example, the vector computation output may be stored in memory uniquely associated with tile 502. Alternatively or additionally, the vector computation output of the vector processing unit 504 may be transmitted to circuitry outside the ASIC 500, for example, as the output of a computation. In some implementations, the vector processing unit 504 is segmented such that each segment includes circuitry configured to receive output from a corresponding set of tiles 502 and to calculate vectors based on the received output. For example, in Figure 5 In the example shown, the vector processing unit 504 includes two rows spanning the first dimension 501, each row comprising 32 segments 506 arranged in 32 columns. As explained herein, each segment 506 includes circuitry (e.g., multiplication circuitry, adder circuitry, shifter, and / or memory) configured to perform vector calculations based on outputs (e.g., sums) from the corresponding column of tile 502. The vector processing unit 504 may be positioned in the middle of the grid of tile 502, as... Figure 5 As shown. Other possible arrangements of the vector processing unit 504 are also possible.

[0069] The ASIC 500 also includes a communication interface 508 (e.g., interfaces 508a, 508b). The communication interface 508 includes one or more sets of serializer / deserializer (SerDes) interfaces and general purpose input / output (GPIO) interfaces. The SerDes interfaces are configured to receive instructions (e.g., instructions for operating the controllable bus lines described below) and / or input data for the ASIC 500, and to output data from the ASIC 500 to external circuitry. For example, the SerDes interfaces can be configured to transmit instructions and / or input data at rates of 32Gbps, 56Gbps, or any suitable data rate on one of the sets of SerDes interfaces included in the communication interface 508. The GPIO interfaces are configured to provide an interface for debugging and / or booting. For example, the ASIC 500 can run a bootloader when it is powered on. If the program fails, the administrator can use the GPIO interfaces to debug the root cause of the failure.

[0070] The ASIC 500 further includes multiple controllable bus lines (see example...). Figure 6 The multiple controllable bus lines are configured to transmit data between the communication interface 508, the vector processing unit 504, and the multiple tiles 502. The controllable bus lines include wires extending, for example, along both a first dimension 501 (e.g., rows) and a second dimension 503 (e.g., columns) of the grid. A first subset of the controllable bus lines extending along the first dimension 501 can be configured to extend along a first direction (e.g., towards...). Figure 5 Data is transmitted to the right side. A second subset of the controllable bus lines extending along the first dimension 501 can be configured to transmit data along the second direction (e.g., to the right). Figure 5 Data is transmitted along the left side. A first subset of the controllable bus lines extending along the second dimension 503 can be configured to transmit data along a third direction (e.g., towards the left side). Figure 5 Data is transmitted from the top. A second subset of the controllable bus lines extending along the second dimension 503 can be configured to transmit data along the fourth direction (e.g., to the top). Figure 5 Data is transmitted from the bottom.

[0071] Each controllable bus line includes multiple transmitter elements, such as flip-flops, for transmitting data along the line according to a clock signal. Transmitting data via the controllable bus line may include transferring data from a first transmitter element of the controllable bus line to a second adjacent transmitter element of the controllable bus line in each clock cycle. In some embodiments, data is transmitted via the controllable bus line on the rising or falling edge of a clock cycle. For example, data present on a first transmitter element (e.g., a flip-flop) of the controllable bus line in a first clock cycle may be transmitted to a second transmitter element (e.g., a flip-flop) of the controllable bus line in a second clock cycle. In some embodiments, the transmitter elements may be periodically spaced apart from each other at a fixed distance. For example, in some cases, each controllable bus line includes multiple transmitter elements, with each transmitter element located within or near a corresponding tile 502.

[0072] Each controllable bus line also includes multiple multiplexers and / or demultiplexers. The multiplexers / demultiplexers of the controllable bus line are configured to transfer data between the bus line and components of the ASIC chip 500. For example, the multiplexers / demultiplexers of the controllable bus line may be configured to transfer data to and / or from tile 502, to and / or from vector processing unit 504, or to and / or from communication interface 508. Transferring data between tile 502, vector processing unit 504, and communication interface may include sending control signals to the multiplexers based on the desired data transfer to occur. The control signals may be stored in registers directly coupled to the multiplexers and / or demultiplexers. The values ​​of the control signals can then be determined, for example, what data is transferred from a source (e.g., within tile 502 or memory of vector processing unit 504) to the controllable bus line, or alternatively, what data is transferred from the controllable bus line to a receiving point (e.g., within tile 502 or memory of vector processing unit 504).

[0073] The controllable bus lines are configured for control at the local level, such that each tile, vector processing unit, and / or communication interface includes its own set of control elements for manipulating the controllable bus lines passing through that tile, vector processing unit, and / or communication interface. For example, each tile, 1D vector processing unit, and communication interface may include a corresponding set of transmitter elements, multiplexers, and / or demultiplexers for controlling the transmission of data to and from that tile, 1D vector processing unit, and communication interface.

[0074] To minimize latency associated with the operation of the ASIC chip 500, tiles 502 and vector processing unit 504 can be positioned to reduce the distance data travels between various components. In certain embodiments, both tiles 502 and communication interface 508 can be divided into multiple portions, with both the tile portions and the communication interface portions arranged such that the maximum distance data travels between the tiles and the communication interface is reduced. For example, in some embodiments, a first set of tiles 502 can be arranged in a first portion on a first side of the communication interface 508, and a second set of tiles 502 can be arranged in a second portion on a second side of the communication interface. As a result, the distance from the communication interface to the farthest tile can be halved compared to a configuration where all tiles 502 are arranged in a single portion on one side of the communication interface.

[0075] Alternatively, the tiles can be arranged in different numbers of sections, such as four sections. For example, in Figure 5In the example shown, multiple tiles 502 of the ASIC 500 are arranged in multiple sections 510 (510a, 510b, 510c, 510d). Each section 510 includes a similar number of tiles 502 arranged in a grid pattern (e.g., each section 510 may include 256 tiles arranged in 16 rows and 16 columns). The communication interface 508 is also divided into multiple sections: a first communication interface 508a and a second communication interface 508b arranged on either side of the section 510 containing the tiles 502. The first communication interface 508a can be coupled to the two tile sections 510a and 510c on the left side of the ASIC chip 500 via a controllable bus line. The second communication interface 508b can be coupled to the two tile sections 510b and 510d on the right side of the ASIC chip 500 via a controllable bus line. As a result, the maximum distance data travels to and / or from communication interface 508 (and therefore the associated delay) can be halved compared to an arrangement where only a single communication interface is available. Other coupling arrangements between tile 502 and communication interface 508 may also reduce data latency. The coupling arrangement between tile 502 and communication interface 508 can be programmed by providing control signals to the transmitter elements and multiplexers of the controllable bus line.

[0076] In some implementations, one or more tiles 502 are configured to initiate read and write operations with respect to controllable bus lines and / or other tiles within the ASIC 500 (referred to herein as "control tiles"). The remaining tiles in the ASIC 500 may be configured to perform computations based on input data (e.g., computational layer inference). In some implementations, the control tiles include the same components and configuration as other tiles within the ASIC 500. Control tiles may be added as one or more additional tiles, one or more additional rows, or one or more additional columns to the ASIC 500. For example, for a symmetric grid of tiles 502 (where each tile 502 is configured to perform computations on input data), one or more additional rows of control tiles may be included to handle read and write operations on tiles 502 that perform computations on the input data. For example, each section 510 includes 18 rows of tiles, where the last two rows may include control tiles. In some implementations, providing separate control tiles increases the amount of memory available in the other tiles used for computations. However, as described herein, a separate tile dedicated to providing control is not necessary, and in some cases, a separate control tile is not provided. Instead, each tile can store in its local memory instructions for initiating read and write operations on that tile.

[0077] In addition, although Figure 5Each section 510 shown includes tiles arranged in 18 rows × 16 columns, but the number of tiles 502 and their arrangement within the section may vary. For example, in some cases, section 510 may include an equal number of rows and columns.

[0078] Furthermore, despite Figure 5 The tile 502 is shown as being divided into four parts, but it can also be divided into other different groups. For example, in some embodiments, the tile 502 is divided into two different parts, such as the first part above the vector processing unit 504 (e.g., closer to...). Figure 5 The second part (e.g., closer to the top of the page shown) and below the vector processing unit 504 (e.g., closer to the top of the page) and the second part below the vector processing unit 504. Figure 5 (See bottom of page). In such an arrangement, each section can contain, for example, 576 tiles arranged in a grid consisting of 18 tiles longitudinally (along direction 503) and 32 tiles laterally (along direction 501). Sections can contain other total numbers of tiles and can be arranged in arrays of different sizes. In some cases, the division between sections is described by the hardware features of the ASIC 500. For example, as... Figure 5 As shown, portions 510a and 510b can be separated from portions 510c and 510d by the vector processing unit 504.

[0079] The latency can also be reduced by centering the vector processing unit 504 relative to the tile portion 510. In some embodiments, the first half of the tile 502 is arranged on the first side of the vector processing unit 504, while the second half of the tile 502 is arranged on the second side of the vector processing unit 504.

[0080] For example, in Figure 5 In the illustrated ASIC chip 500, the vector processing unit 504 includes two sections (e.g., two rows), each section including a plurality of segments 506 matching the number of columns of the tile 502. Each segment 506 can be positioned and configured to receive output, such as a summation, from the corresponding column of the tile 502 within the tile section 510. Figure 5In the example shown, tile portions 510a and 510b located on the first side of vector processing unit 504 (e.g., above vector processing unit 504) can be coupled to the top row of segment 506 via a controllable bus line. Tile portions 510c and 510d located on the second side of vector processing unit 504 (e.g., below vector processing unit 504) can be coupled to the bottom row of segment 506 via a controllable bus line. Furthermore, each tile 502 in the first half above processing unit 504 can be located at the same distance from vector processing unit 504 as the corresponding tile 502 in the second half below processing unit 504, such that there is no difference in total delay between the two halves. For example, tile 502 in row i of the first part 510a (where variable i corresponds to row position) can be located at the same distance from vector processing unit 504 as tile 502 in row m-1-i of the second part of the tiles (e.g., part 510c) (where m represents the total number of rows in each part, and it is assumed that the rows in both parts increase in the same direction).

[0081] Compared to an arrangement where the vector processing unit 504 is located at the far end (e.g., bottom) of all tiles 502, configuring the tile portions 510 in this way halves the distance data travels to and / or from the vector processing unit 504 (and therefore the associated delay). For example, the delay associated with receiving an accumulation from portion 510a through a row of tiles 502 can be half the delay associated with receiving an accumulation from portions 510a and 510c through a row of tiles 502. The coupling arrangement of the tiles 502 and the vector processing unit 504 can be programmed by providing control signals to the transmitter elements and multiplexers of the controllable bus line.

[0082] During the operation of the ASIC chip 500, the activation input can be shifted between tiles. For example, the activation input can be shifted along the first dimension 501. In addition, the output of computations performed on tile 502 (e.g., the output of computations performed by a computation array within tile 502) can be shifted between tiles along the second dimension 503.

[0083] In some implementations, the controllable bus lines can be physically hardwired to allow data to skip tiles 502, thereby reducing latency associated with the operation of the ASIC chip 500. For example, the output of a computation performed on the first tile 502 can be shifted along the second dimension 503 of the grid to a second tile 502 at least one tile away from the first tile 502, thus skipping tiles in between. In another example, an activation input from the first tile 502 can be shifted along the first dimension 501 of the grid to a second tile 502 at least one tile away from the first tile 502, thus skipping tiles in between. By skipping at least one tile when shifting activation input or output data, the overall data path length can be reduced, resulting in faster data transmission (e.g., no need to store data at the skipped tiles using clock cycles) and reduced latency.

[0084] In an example implementation, each tile 502 within each column of portion 510a can be configured via a controllable bus line to pass output data to the vector processing unit 504 along the second dimension 503. The tiles 502 within each column can be further configured to pass data to the vector processing unit 504 by skipping the next adjacent tile (e.g., via a physical hardwired controllable bus line between tiles). That is, the tile 502 at position (i,j) = (0,0) in the first portion 510a (where variable i corresponds to the row position and variable j corresponds to the column position) can be hardwired to pass output data to the tile 502 at position (i,j) = (2,0); similarly, the tile 502 at position (i,j) = (2,0) in the first portion 510a can be hardwired to pass output data to the tile 502 at position (i,j) = (4,0), and so on. The last tile that is not skipped (e.g., tile 502 at position (i,j) = (16,0)) passes the output data to the vector processing unit 504. For the portion 510 with 18 rows of tiles, for example... Figure 5 The example shown demonstrates that tile skipping ensures that all tiles within section 510 are at most nine “tile skips” from vector processing unit 504, thereby improving the performance of ASIC chip 500 by halving the data path length and the resulting data latency.

[0085] In another example implementation, each tile 502 within each row of portions 510a, 510c and each row of portions 510b, 510d can be configured via a controllable bus line to pass an activation input along the first dimension 501. For example, some tiles within portions 510a, 510b, 510c, 510d can be configured to pass the activation input toward the center of the grid 500 or to the communication interface 508. Tiles 502 within each row can be further configured to skip adjacent tiles, for example, via hard-wired controllable bus lines between tiles. For example, tile 502 at position (i,j) = (0,0) in part 510a (where variable i corresponds to the row position and variable j corresponds to the column position) can be configured to pass the activation input to tile 502 at position (i,j) = (0,2); similarly, tile 502 at position (i,j) = (0,2) in part 510a can be configured to pass the activation input to tile 502 at position (i,j) = (0,4), and so on. In some cases, the last tile that is not skipped (e.g., tile 502 at position (i,j) = (0,14)) will not pass the activation input to another tile.

[0086] Similarly, skipped tiles can pass activation input in the opposite direction. For example, tile 502 at position (i,j) = (0,15) in the first part 510a (where variable i corresponds to the row position and variable j corresponds to the column position) can be configured to pass activation input to tile 502 at position (i,j) = (0,13); similarly, tile 502 at position (i,j) = (0,13) in the first part 510a can be configured to pass activation input to tile 502 at position (i,j) = (0,11), and so on. In some cases, the last tile that is not skipped (e.g., tile 502 at position (i,j) = (0,1)) will not pass activation input to another tile. By skipping tiles, in some implementations, it is possible to improve the performance of ASIC chip 500 by halving the data path length and the resulting data latency.

[0087] As explained herein, in some embodiments, one or more tiles 502 are dedicated to storing control information. That is, tiles 502 dedicated to storing control information do not participate in calculations on input data such as weight inputs and activation inputs. The control information may include, for example, control data for configuring a controllable bus line during operation of the ASIC chip 500 so that data can move within the ASIC chip 500. The control data may be provided to the controllable bus line in the form of control signals for controlling transmitter elements and multiplexers of the controllable bus line. The control data specifies whether a particular transmitter element of the controllable bus line passes data to the next transmitter element of the controllable bus line to transfer data between tiles according to a predetermined schedule. The control data additionally specifies whether data is transferred from or to the bus line. For example, the control data may include control signals that direct a multiplexer to transfer data from the bus line to memory and / or other circuitry within the tile. In another example, the control data may include control signals that direct a multiplexer to transfer data from memory and / or circuitry within the tile to the bus line. In another example, control data may include control signals that direct the multiplexer to transmit data between the bus line and communication interface 508 and / or between the bus line and vector processing unit 504. Alternatively, as disclosed herein, dedicated control tiles are not used. Instead, in such a case, the control information for that particular tile is stored in the local memory of each tile.

[0088] Figure 6 An example of a tile 600 used in an ASIC chip 500 is illustrated. Each tile 600 includes a local memory 602 and a computation array 604 coupled to the memory 602. The local memory 602 includes physical memory located close to the computation array 604. The computation array 604 includes a plurality of cells 606. Each cell 606 of the computation array 604 includes circuitry configured to perform computations (e.g., multiplication and accumulation operations) based on data inputs to the cell 606 (e.g., activation inputs and weight inputs). Each cell can perform computations (e.g., multiplication and accumulation operations) over one cycle of a clock signal. The computation array 604 may have more rows than columns, more columns than rows, or an equal number of columns and rows. For example, in Figure 6 In the example shown, computation array 604 comprises 64 cells arranged in 8 rows and 8 columns. Other computation array sizes are also possible, such as those with 16, 32, 128, or 256 cells. Each tile can include the same number of cells and / or the same size computation array. The total number of operations that can be performed in parallel for an ASIC chip then depends on the total number of tiles with the same size computation array within the chip. For example, for Figure 5The ASIC chip 500 shown contains approximately 1150 tiles, meaning it can perform approximately 72,000 computations in parallel per cycle. Examples of usable clock speeds include, but are not limited to, 225MHz, 500MHz, 750MHz, 1GHz, 1.25GHz, 1.5GHz, 1.75GHz, or 2GHz. Figure 5 As shown, the computational array 604 for each individual tile is a subset of the larger tile pulsation array.

[0089] The memory 602 included in tile 600 may include, for example, random access memory (RAM), such as SRAM. Other memory may be used instead. Each memory 602 can be configured to store and Figure 5 The total memory associated with the n tiles 502 of the ASIC chip shown is (1 / n). The memory 602 can be provided in single-chip or multi-chip form. For example, Figure 6 The memory 602 shown is provided as four single-port SRAMs, each coupled to the compute array 604. Alternatively, the memory 602 may be provided in a configuration such as two single-port SRAMs or eight single-port SRAMs. After error correction coding, the combined capacity of the memory may be, but is not limited to, 16kB, 32kB, 64kB, or 128kB. By providing the physical memory 602 locally to the compute array, the wiring density of the ASIC 500 can be significantly reduced in some implementations. In alternative configurations where the memory is concentrated within the ASIC 500, in contrast to the local provision described herein, wires may be required for every bit of the memory bandwidth. The total number of wires required to cover each tile of the ASIC 500 would far exceed the available space within the ASIC 100. In contrast, with dedicated memory provided for each tile, the total number required across the ASIC 500 region can be significantly reduced.

[0090] Tile 600 also includes controllable bus lines. These controllable bus lines can be categorized into several different groups. For example, the controllable bus lines may include a first group of general-purpose controllable bus lines 610 configured to transmit data between tiles along each basic direction. That is, the first group of controllable bus lines 610 may include: bus line 610a configured to travel along the first dimension 501 of the tile grid in a first direction (in... Figure 6 Data is transmitted in the direction referred to as "East"; bus line 610b is configured to move along the first dimension 101 of the tile grid towards the second direction (in the direction of the second direction). Figure 6 Data is transmitted in the second direction (referred to as "west"), where the second direction is opposite to the first direction; bus line 610c, which is configured to travel along the second dimension 103 of the tile grid towards a third direction (in Figure 6Data is transmitted (referred to as "North" in the original text); and bus line 610d, which is configured to move along the second dimension 103 of the tile grid towards the fourth direction (in the original text). Figure 6 Data is transmitted via a fourth direction (referred to as "South"), which is opposite to the third direction. The general-purpose bus line 610 can be configured to carry control data, activation input data, data from and / or to the communication interface, data from and / or to the vector processing unit, and data to be stored and / or used by the tile 600 (e.g., weight input). The tile 600 may include one or more control elements 621 (e.g., triggers and multiplexers) for controlling the controllable bus line, thereby routing data to and / or from the tile 600 and / or from the memory 602.

[0091] The controllable bus lines may further include a second set of controllable bus lines, referred to herein as the computing array section and bus line 620. The computing array section and bus line 620 may be configured to carry data output from calculations performed by the computing array 604. For example, bus line 620 may be configured to carry portions and data obtained from rows in the computing array 604, such as... Figure 6 As shown. In this case, the number of bus lines 620 will match the number of rows in array 604. For example, for an 8x8 computing array, there will be 8 partial and bus lines 620, each coupled to the output of the corresponding row in computing array 604. The computing array output bus lines 620 can be further configured to couple to another tile within the ASIC chip, for example, as input to a computing array on another tile within the ASIC chip. For example, the array partial and bus lines 620 of tile 600 can be configured to receive input (e.g., partial and 620a) of a computing array located at least one tile away from tile 600. The output of computing array 604 is then added to the partial and line 620 to produce a new partial and 620b, which can be output from tile 600. The partial and 620b can then be passed to another tile, or alternatively, to a vector processing unit. For example, each bus line 620 can be coupled to a corresponding segment of a vector processing unit (e.g., Figure 5 (Section 506 in the middle).

[0092] Such as about Figure 5 As explained, a controllable bus line may include circuitry such as a transmitter element (e.g., a trigger) configured to allow data to be transmitted along the bus line. In some implementations, each controllable bus line includes a corresponding transmitter element for each tile. (See also: Regarding...) Figure 5To further explain, the controllable bus line may include circuitry such as a multiplexer configured to allow data to be transmitted between different tiles of the ASIC chip, vector processing units, and communication interfaces. The multiplexer can be located anywhere there is a source or destination of data. For example, in some implementations, such as... Figure 6 As shown, control circuitry 621 (e.g., a multiplexer) can be located at the intersections of controllable bus lines (e.g., at the intersection of general-purpose bus lines 610a and 610d, at the intersection of general-purpose bus lines 610a and 610c, at the intersection of general-purpose bus lines 610b and 610d, and / or at the intersection of general-purpose bus lines 610b and 610c). The multiplexer at the bus line intersection can be configured to transmit data between the bus lines at the intersection. Therefore, by appropriate operation of the multiplexer, it is possible to change the direction of data travel on the controllable bus lines. For example, data traveling along the first dimension 101 on general-purpose bus line 610a can be transferred to general-purpose bus line 610d, causing the data to travel instead along the second dimension 103. In some embodiments, the multiplexer can be located near the memory 602 of tile 600 so that data can be transferred to and / or from memory 602.

[0093] Embodiments of the subject matter and functional operation described in this specification may be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed in this specification and their structural equivalents), or in one or more combinations thereof. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory storage medium for execution by a data processing apparatus or for controlling the operation of a data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or one or more combinations thereof. Alternatively or additionally, the program instructions may be encoded on artificially generated propagation signals (e.g., machine-generated electrical, optical, or electromagnetic signals) generated to encode information for transmission to a suitable receiver device, thereby being executed by the data processing apparatus.

[0094] The term "data processing device" refers to data processing hardware and encompasses all kinds of devices, apparatuses, and machines for processing data, including, for example, programmable processors, computers, or multiple processors or computers. The device may also be or further include special-purpose logic circuitry, such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits). In addition to hardware, the device may optionally include code that creates an execution environment for computer programs, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, or one or more combinations thereof.

[0095] A computer program, also referred to or described as a program, software, software application, applet, module, software module, script, or code, can be written in any programming language (including compiled or interpreted languages, or declarative or procedural languages) and can be deployed in any form (including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment). A program may, but does not necessarily, correspond to a file in a file system. A program may be stored as part of a file containing other programs or data (e.g., in one or more scripts within a markup language document), in a single file dedicated to the program in question, or in multiple coordinating files (e.g., in a file storing one or more modules, subroutines, or portions of code). A computer program can be deployed to execute on a single computer or on multiple computers located at a site or distributed across multiple sites and interconnected via a data communication network.

[0096] For a system of one or more computers configured to perform a specific operation or action, this means that the system has software, firmware, hardware, or a combination thereof installed thereon, which, in operation, cause the system to perform the operation or action. For one or more programs configured to perform a specific operation or action, this means that the one or more programs include instructions that, when executed by a data processing device, cause the device to perform the operation or action.

[0097] As used herein, "engine" or "software engine" refers to a software-implemented input / output system that provides an output distinct from the input. An engine can be a coded functional block, such as a library, platform, software development kit ("SDK"), or object. Each engine can be implemented on any suitable type of computing device, such as a server, mobile phone, tablet computer, laptop computer, music player, e-book reader, laptop or desktop computer, PDA, smartphone, or other fixed or portable device, which includes one or more processors and computer-readable media. Furthermore, two or more engines can be implemented on the same computing device or on different computing devices.

[0098] The processes and logic flows described in this specification can be implemented by one or more programmable computers, which execute one or more computer programs to perform functions by manipulating input data and producing outputs. The processes and logic flows can also be implemented by dedicated logic circuitry (e.g., FPGA or ASIC) or by a combination of dedicated logic circuitry and one or more programmable computers.

[0099] A computer suitable for executing computer programs can be based on a general-purpose or special-purpose microprocessor, or both, or any other type of central processing unit (CPU). Typically, the CPU receives instructions and data from read-only memory or random access memory, or both. The basic components of a computer are the CPU for making or executing instructions and one or more memory devices for storing instructions and data. The CPU and memory may be supplemented by or integrated into special-purpose logic circuitry. Typically, a computer will also include, or be operatively coupled to, one or more mass storage devices (e.g., magneto-optical, magneto-optical, or optical disc) for storing data, or transfer data to or to them, or both. However, a computer does not necessarily need to have such devices. Furthermore, a computer can be embedded in another device, such as a mobile phone, personal digital assistant (PDA), mobile audio or video player, game console, GPS receiver, or portable storage device such as a Universal Serial Bus (USB) flash drive, and so on.

[0100] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and storage devices, including, for example: semiconductor storage devices such as EPROM, EEPROM, and flash memory devices; disks such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0101] To provide interaction with the user, embodiments of the subject matter described in this specification can be implemented on a computer having: a display device, such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user; and a keyboard and pointing device, such as a mouse, trackball, or presence-sensitive display or other surface through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including voice input, speech input, or tactile input. Furthermore, the computer can interact with the user by sending and receiving documents to and from the device used by the user; for example, by sending a webpage to a web browser on the user's device in response to a request received from a web browser. Moreover, the computer can interact with the user by sending text messages or other forms of messages to a personal device (e.g., a smartphone), running a messaging application, and receiving response messages from the user as a response.

[0102] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes back-end components (e.g., as a data server), middleware components (e.g., an application server), or front-end components (e.g., a client computer with a graphical user interface, a web browser, or an app through which a user can interact with embodiments of the subject matter described in this specification), or any combination of one or more such back-end components, middleware components, or front-end components. The components of the system can be interconnected via digital data communication (e.g., a communication network) of any form or medium. Examples of communication networks include local area networks (LANs) and wide area networks (WANs), such as the Internet.

[0103] Example 1 is a method comprising:

[0104] The receiving program has an intermediate representation specifying multiple operations to be performed by multiple corresponding components of the synchronization processor, wherein the intermediate representation assigns a corresponding clock cycle value to each of the multiple operations, at which the operation is scheduled to be executed by the synchronization processor;

[0105] The intermediate representation is processed to generate a corresponding update window for each operation in the intermediate representation that requires a hardware configuration update, wherein the update window specifies the time range during which a configuration update instruction can be executed to achieve the hardware configuration update.

[0106] Obtain one or more configuration constraints of the synchronization processor; and

[0107] Configuration update instructions are generated and scheduled, each configuration update instruction occurring during one update window of the update window and in accordance with the configuration constraints of the synchronization processor.

[0108] Example 2 is the method described in Example 1, wherein the configuration constraint includes the maximum number of configuration update instructions that the synchronous processor can execute in a single cycle.

[0109] Example 3 is the method described in Example 2, wherein the configuration constraint includes a limited number of cycles on which configuration update instructions can be executed.

[0110] Example 4 is the method of any one of Examples 1-3, wherein generating and scheduling configuration update instructions from the update window and the configuration constraints includes assigning the configuration update instructions to the update window with the largest constraint before assigning the configuration update instructions to other update windows.

[0111] Example 5 is the method of any one of Examples 1-4, wherein one or more of the configuration update instructions change the register of the read operation.

[0112] Example 6 is the method of any one of Examples 1-5, wherein one or more of the configuration update instructions change the multiplexer arguments in the data path of the synchronization processor.

[0113] Example 7 is a method according to any one of Examples 1-6, wherein the synchronization processor is configured to perform each operation with the same configuration if a configuration update instruction has not yet been issued.

[0114] Example 8 is a method according to any of the foregoing examples, further comprising performing the operation using the synchronization processor and updating the configuration of the synchronization processor according to the configuration update instruction.

[0115] Example 9 is a method comprising:

[0116] A program that receives multiple operations specified to be performed by multiple corresponding components of a synchronization processor;

[0117] For each of the plurality of components, obtain the corresponding clock delay value for each corresponding operation to be performed by the component for the program;

[0118] Based on the corresponding clock delay value for each corresponding operation of the program, clock timing constraints for executing the program are generated; and

[0119] An intermediate representation of the program is generated based on the clock timing constraints, and the intermediate representation assigns the corresponding clock cycle value to each of the plurality of operations.

[0120] Example 10 is the method described in Example 9, wherein the operation further includes:

[0121] The intermediate representation is processed to generate a corresponding update window for each operation in the intermediate representation that requires a hardware configuration update, wherein the update window specifies the time range during which a configuration update instruction can be executed to achieve the hardware configuration update.

[0122] Obtain one or more configuration constraints of the synchronous processor;

[0123] Configuration update instructions are generated and scheduled, each configuration update instruction occurring during one update window of the update window and in accordance with the configuration constraints of the synchronization processor.

[0124] Example 11 is the method described in Example 10, wherein the configuration constraint includes the maximum number of configuration update instructions that the synchronous processor can execute in a single cycle.

[0125] Example 12 is the method described in Example 11, wherein the configuration constraint includes a limited number of cycles on which configuration update instructions can be executed.

[0126] Example 13 is the method described in Example 10, wherein generating and scheduling configuration update instructions from the update window and the configuration constraints includes assigning the configuration update instructions to the update window with the largest constraint before assigning the configuration update instructions to other update windows.

[0127] Example 14 is the method of any one of Examples 9-13, wherein the procedure is delay-insensitive.

[0128] Example 15 is the method described in Example 14, wherein the procedure does not specify the order of operations or the timing between the operations.

[0129] Example 16 is the method described in Example 15, wherein the procedure does not specify delay information for the components of the synchronization processor.

[0130] Example 17 is the method of any one of Examples 9-16, wherein the intermediate representation of the program is capable of assigning a negative clock cycle value to each of the plurality of operations.

[0131] Example 18 is the method of any one of Examples 9-17, wherein the operation further includes generating dependency information between operations based on variables in the input program.

[0132] Example 19 is a system comprising one or more computers and a storage device for storing one or more instructions, which, when executed by the one or more computers, are operable to cause the one or more computers to perform the method described in any of the preceding examples.

[0133] Example 20 is a computer storage medium coded with a computer program, the program including instructions that, when executed by a data processing apparatus, are operable to cause the data processing apparatus to perform the method described in any one of Examples 1 to 18.

[0134] While this specification contains numerous specific details of implementation, these should not be construed as limiting the scope of any invention or the scope of claims, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Certain features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, or even initially claimed in this way, in some cases, one or more features from a claimed combination may be removed from the combination, and the claimed combination may be for sub-combinations or variations thereof.

[0135] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or that all the operations shown be performed to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated into a single software product or packaged into multiple software products.

[0136] Specific embodiments of this subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the actions recited in the claims may be performed in a different order, but the desired result may still be achieved. As an example, the processes depicted in the drawings do not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A compilation method for a synchronous processor, the method comprising: The receiving program has an intermediate representation that specifies multiple operations to be performed by multiple corresponding components of the synchronization processor, wherein the intermediate representation assigns a corresponding clock cycle value to each of the multiple operations, and the operations are scheduled to be executed by the synchronization processor at the corresponding clock cycle value. The intermediate representation is processed to generate a corresponding update window for each operation in the intermediate representation that requires a hardware configuration update, wherein the update window specifies the time range in which a configuration update instruction can be executed to achieve the hardware configuration update. Obtain one or more configuration constraints of the synchronization processor; and Configuration update instructions are generated and scheduled, each occurring within an update window and according to the configuration constraints of the synchronization processor. The synchronous processor is configured to perform each operation with the same configuration if no configuration update instruction has been issued.

2. The method of claim 1, wherein the configuration constraint includes the maximum number of configuration update instructions that the synchronous processor can execute in a single cycle.

3. The method of claim 2, wherein the configuration constraint comprises a finite number of periods on which configuration update instructions can be executed.

4. The method of claim 1, wherein generating and scheduling configuration update instructions from the update window and the configuration constraints includes assigning the configuration update instructions to the update window with the largest constraint before assigning the configuration update instructions to other update windows.

5. The method according to claim 1, wherein one or more of the configuration update instructions modify the registers read from.

6. The method according to claim 1, wherein one or more of the configuration update instructions change the multiplexer arguments in the data path of the synchronization processor.

7. The method of claim 1, further comprising performing the operation using the synchronization processor and updating the configuration of the synchronization processor according to the configuration update instruction.

8. A compilation method for a synchronous processor, the method comprising: A program that receives multiple operations specified to be performed by multiple corresponding components of a synchronization processor; For each of the plurality of components, obtain the corresponding clock delay value for each corresponding operation to be performed by the component for the program; Based on the corresponding clock delay value for each corresponding operation of the program, a clock timing constraint for executing the program is generated; An intermediate representation of the program is generated based on the clock timing constraints. This intermediate representation assigns a corresponding clock cycle value to each of the plurality of operations, which are scheduled to be executed by the synchronous processor at the corresponding clock cycle value. The intermediate representation is processed to generate a corresponding update window for each operation in the intermediate representation that requires a hardware configuration update, wherein the update window specifies the time range in which a configuration update instruction can be executed to achieve the hardware configuration update. Obtain one or more configuration constraints of the synchronization processor; and Configuration update instructions are generated and scheduled, each occurring within an update window and according to the configuration constraints of the synchronization processor. The synchronous processor is configured to perform each operation with the same configuration if no configuration update instruction has been issued.

9. The method of claim 8, wherein the configuration constraint includes the maximum number of configuration update instructions that the synchronous processor can execute in a single cycle.

10. The method of claim 9, wherein the configuration constraint comprises a finite number of periods on which configuration update instructions can be executed.

11. The method of claim 8, wherein generating and scheduling configuration update instructions from the update window and the configuration constraints includes assigning the configuration update instructions to the update window with the largest constraint before assigning the configuration update instructions to other update windows.

12. The method of claim 8, wherein the procedure is latency insensitive.

13. The method of claim 12, wherein the procedure does not specify the order of operations or the timing between the operations.

14. The method of claim 13, wherein the procedure does not specify delay information for the components of the synchronization processor.

15. The method of claim 8, wherein the intermediate representation of the program is capable of assigning negative clock cycle values ​​to each of the plurality of operations.

16. The method of claim 8, wherein the operation further comprises generating dependency information between operations based on variables in the input program.

17. A compilation system for a synchronous processor, the system comprising: One or more computers and a storage device for storing one or more instructions, which, when executed by the one or more computers, are operable to cause the one or more computers to perform the method of any one of claims 1-16.

18. A computer storage medium coded with a computer program, the program comprising instructions that, when executed by a data processing apparatus, are operable to cause the data processing apparatus to perform the method according to any one of claims 1 to 16.

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