A method, device, computer storage medium and terminal for implementing command scheduling

Abstract

The present invention discloses a method, device, computer storage medium and terminal for implementing command scheduling, including: when a dynamic random access memory (DRAM) receives a first command, determining whether there is a first position for inserting the first command in a command queue; when the first position exists, determining whether the first position passes a consistency conflict check; inserting the first command into the first position that passes the consistency conflict check; wherein the first command includes: a read command or a write command. In the embodiment of the present invention, when the command queue is not read and written grouped, a consistency conflict check is performed on the newly received first command and then the insertion process is performed, thereby improving the read and write performance of the system on chip (SOC).

Description

Technical Field

[0001] The present invention relates to, but is not limited to, system-on-chip technology, and in particular to a method, device, computer storage medium, and terminal for implementing command scheduling. Background Art

[0002] As the scale of system on chip (SOC) becomes larger and larger, the number of modules such as central processing unit (CPU) and data processing unit (DPU) integrated inside SOC is also increasing; the efficiency of the system's DRAM cache execution of each module will directly affect the overall performance of SOC.

[0003] The dynamic random access memory (DRAM) controller is the basic component for parsing and processing SOC bus commands. It mainly schedules read and write commands based on read and write classification or queue reordering technology. Among them, the read and write classification, fixed rules and queue scheduling strategies with strong coupling logic in related technologies make the current scheduling strategies more and more complex, with problems such as low flexibility, tight logic coupling and poor compatibility, which has become a major problem in the current DRAM controller design. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present invention provide a method, an apparatus, a computer storage medium and a terminal for implementing command scheduling, which can improve the data reading and writing performance of a system on a chip.

[0006] An embodiment of the present invention provides a method for implementing command scheduling, including:

[0007] When the dynamic random access memory DRAM receives a new first command, it determines whether there is a first position for inserting the first command in the command queue;

[0008] When the first position exists, determining whether the first position passes a consistency conflict check;

[0009] inserting a first command into a first position that passes a consistency conflict check;

[0010] The first command includes: a read command or a write command.

[0011] On the other hand, an embodiment of the present invention further provides a computer storage medium, wherein the computer storage medium stores a computer program, and when the computer program is executed by a processor, the method for implementing command scheduling is implemented.

[0012] In another aspect, an embodiment of the present invention further provides a terminal, comprising: a memory and a processor, wherein the memory stores a computer program; wherein:

[0013] The processor is configured to execute the computer program in the memory;

[0014] When the computer program is executed by the processor, the method for implementing command scheduling as described above is implemented.

[0015] In another aspect, an embodiment of the present invention further provides a device for implementing command scheduling, comprising: a position determination unit, a conflict checking unit and an insertion processing unit; wherein:

[0016] The position determination unit is configured to: upon receiving the first command, determine whether there is a first position for inserting the first command in the command queue;

[0017] The conflict checking unit is configured to: when the first position exists, determine whether the first position passes the consistency conflict check;

[0018] The insertion processing unit is configured to: insert the first command into a first position that passes the consistency conflict check;

[0019] The first command includes: a read command or a write command.

[0020] The technical solution of the present application includes: when a dynamic random access memory (DRAM) receives a first command, determining whether there is a first position for inserting the first command in a command queue; when the first position exists, determining whether the first position passes a consistency conflict check; inserting the first command into the first position that passes the consistency conflict check; wherein the first command includes: a read command or a write command. In the embodiment of the present invention, when the command queue is not read and written grouped, a consistency conflict check is performed on the newly received first command and then the insertion process is performed, thereby improving the read and write performance of the system on chip (SOC).

[0021] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0023] Figure 1 A flowchart of a method for implementing command scheduling according to an embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of a first position of an embodiment of the present invention;

[0025] Figure 3 is a schematic diagram of a first position of another embodiment of the present invention;

[0026] Figure 4 A schematic diagram of a first position of yet another embodiment of the present invention;

[0027] Figure 5 A schematic diagram of inserting a fourth command according to an embodiment of the present invention;

[0028] Figure 6 A schematic diagram of inserting a fourth command according to another embodiment of the present invention;

[0029] Figure 7 A schematic diagram of data caching according to an embodiment of the present invention;

[0030] Figure 8 A schematic diagram of alarm processing according to an embodiment of the present invention;

[0031] Fig. 9 The present invention is a block diagram of a device for implementing command scheduling according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0033] The steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions. Also, although a logical sequence is shown in the flowchart, in some cases, the steps shown or described can be performed in a sequence different from that shown here.

[0034] Figure 1 Flow chart of a method for implementing command scheduling in an embodiment of the present invention, such as Figure 1 As shown, including:

[0035] Step 101: When a dynamic random access memory (DRAM) receives a first command, it determines whether there is a first position for inserting the first command in a command queue;

[0036] In an exemplary embodiment, the first command in the embodiment of the present invention includes a newly received command.

[0037] In an exemplary embodiment, the embodiment of the present invention determines whether there is a first position for inserting a first command in the command queue, including:

[0038] In order from the tail to the head of the command queue, it is determined whether there is a first position for inserting the first command in the command queue.

[0039] Step 102: When the first position exists, determine whether the first position passes the consistency conflict check;

[0040] Step 103: insert the first command into the first position that passes the consistency conflict check;

[0041] The first command includes: a read command or a write command.

[0042] It should be noted that the read commands and write commands in the command queue of the embodiment of the present invention are processed serially, so only one first command is processed in one command scheduling.

[0043] In the embodiment of the present invention, when the command queue is not read and written in groups, a consistency conflict check is performed on the newly received first command and then an insertion process is performed, thereby improving the read and write performance of the system on chip (SOC).

[0044] In an exemplary embodiment, the embodiment of the present invention determines whether there is a first position for inserting a first command in the command queue, including:

[0045] When there is a command that meets the page hit (page hit, accessing the same bank or row) in the command queue, the position after the command that meets the page hit is determined as the first position;

[0046] When there are two commands with a bank conflict in the command queue, the middle position of the two commands with a bank conflict is determined as the first position;

[0047] It should be noted that the two fourth commands with group conflicts should be adjacent commands. Only adjacent commands may have group conflicts.

[0048] When there are two adjacent commands with the same operation type in the command queue, the middle position of the two adjacent commands with the same operation type is determined as the first position;

[0049] The operation types include: read operation and write operation.

[0050] The differences in determining the first position are briefly described below with examples; Figure 2 Schematic diagram of the first position of an embodiment of the present invention, Figure 2As shown in the figure, WR in WR_Bx_Rx_Cx represents a write operation, Bx represents xBank, Rx represents the xth row, and Cx represents the xth column. The above command represents writing the xth row and xth column of xbank; RD in RD_Bx_Rx_Cx represents a read operation. The above command represents reading the xth row and xth column of xbank. Figure 2 The identifiers 1, 2 and 3 respectively represent the first positions of the three commands that meet the Page Hit requirement. The first position of identifier 1 is close to the head of the command queue. When the first command is inserted, the priority of the first position of identifier 1 is greater than the priority of the first position of identifier 2. The priority of the first position of identifier 2 is greater than the priority of the first position of identifier 3. When performing a consistency conflict check, the embodiment of the present invention performs judgment and processing one by one in the order of the above priorities from high to low.

[0051] Figure 3 Schematic diagram of the first position of another embodiment of the present invention, Figure 3 As shown in the figure, identifiers 1, 2 and 3 respectively represent the first positions of three commands when there are two group conflicts; identifier 1 is close to the head of the command queue, and when the first command is inserted, the priority of the first position of identifier 1 is greater than the priority of the first position of identifier 2; the priority of the first position of identifier 2 is greater than the priority of the first position of identifier 3; when performing a consistency conflict check, the embodiment of the present invention performs judgment and processing one by one in the order of the above priorities from high to low.

[0052] Figure 4 FIG. 1 is a schematic diagram of a first position of another embodiment of the present invention, Figure 4 As shown in the figure, identifiers 1, 2 and 3 respectively represent the first positions when there are two adjacent commands with the same operation type; identifier 1 is close to the head of the command queue, and when the first command is inserted, the priority of the first position of identifier 1 is greater than the priority of the first position of identifier 2; the priority of the first position of identifier 2 is greater than the priority of the first position of identifier 3; when performing a consistency conflict check, the embodiment of the present invention performs judgment and processing one by one in the order of the above priorities from high to low.

[0053] In an exemplary example, an embodiment of the present invention may determine the first position only based on the judgment of whether there are commands that meet the page command; in an exemplary example, an embodiment of the present invention may determine the first position only based on the judgment of whether there are two commands with group conflicts; in an exemplary example, an embodiment of the present invention may determine the first position based on the judgment of whether there are two commands with consistent operation types and adjacent to each other. In an exemplary example, an embodiment of the present invention may select two from the judgment of whether there are commands that meet the page command, whether there are two commands with group conflicts, and whether there are two commands with consistent operation types and adjacent to each other, and perform the judgment processing of the first position in sequence according to the order of whether there are commands that meet the page command, whether there are two commands with group conflicts, and whether there are two commands with consistent operation types and adjacent to each other. In an exemplary example, an embodiment of the present invention may perform the judgment processing of the first position one by one according to the judgment of whether there are commands that meet the page command, whether there are two commands with group conflicts, and whether there are two commands with consistent operation types and adjacent to each other.

[0054] In an exemplary embodiment, the embodiment of the present invention determines whether the first position passes the consistency conflict check, including:

[0055] Performing a consistency conflict check between the first command and the second command at the first position in order from the head to the tail of the command queue;

[0056] When the first command and the second command pass the consistency conflict check, determining that the first position passes the consistency conflict check;

[0057] The second command includes: a read command and / or a write command that is immediately adjacent to the first position.

[0058] It should be noted that the consistency conflict check in the embodiment of the present invention is based on the address and read-write attribute definition of the module, and may include: module address conflict and / or read-write conflict; for example, according to the data processing process of the module, the read-write order of the module is preset, so once the read-write order does not meet the preset, it is considered that there is a conflict. In an exemplary instance, the rules for consistency conflicts in the embodiment of the present invention can be set by a person skilled in the art according to the implementation scenario. In an exemplary instance, the modules in the embodiment of the present invention include a central processing unit (CPU), a data processor (DPU) and a display module integrated in the SOC, and other modules that need to read and write data through DRAM; in an exemplary instance, the embodiment of the present invention can distinguish each module in the SOC by a pre-set number, distinguish the commands and addresses of each module based on the number, and then perform a consistency conflict check. When the consistency conflict detection of the embodiment of the present invention determines that there is a consistency conflict, the first position is deleted from the position where the first instruction can be inserted.

[0059] In an exemplary embodiment, the embodiment of the present invention inserts the first command into the first position that passes the consistency conflict check, including:

[0060] The first command is inserted into the first position closest to the head of the command queue and passes the consistency violation check.

[0061] In an exemplary embodiment, the embodiment of the present invention can also insert the first command into other first positions that pass the consistency conflict check. Inserting the first command into the first position that is closest to the head of the command queue and passes the consistency conflict check improves the processing efficiency of the first command and avoids the timing problem (the command received later is inserted before the first command) caused by the insertion position of the subsequent commands.

[0062] In an exemplary embodiment, the method of the embodiment of the present invention further includes:

[0063] When it is determined that there is no first position for inserting the first command in the command queue, the first command is written to the tail of the command queue.

[0064] In the embodiment of the present invention, when the first position does not exist, the order of the command queue is kept unchanged, and the newly added first command is written to the tail of the command queue.

[0065] In an exemplary embodiment, the method of the embodiment of the present invention further includes:

[0066] Setting a timeout threshold for one or more third commands in the command queue;

[0067] When the third command is not executed within the timeout threshold, the third command is inserted into the head of the command queue.

[0068] In an exemplary embodiment, the embodiment of the present invention can be set by a technician according to the system application. For example, the access unique identifier (ID) of the sixth command is a read operation of a display module (Display), and the timeout threshold can be dynamically configured according to the resolution of the Display. The setting of the timeout threshold in the embodiment of the present invention can be understood as a timeout mechanism or an aging mechanism. By setting the timeout threshold, the command with a time limit requirement is avoided from being stuck.

[0069] In an exemplary embodiment, the method of the embodiment of the present invention further includes:

[0070] determining a fourth command in the command queue that can be operated in parallel;

[0071] Inserting more than one fourth command that can be operated in parallel within a first delay interval of a bank conflict of the first fourth command;

[0072] Among them, the fourth command includes: multiple groups (Muti-Bank) commands and / or group (BankGroup) commands; the first fourth command includes: the fourth command close to the head of the command queue; the inserted one or more fourth commands that can be operated in parallel include: other fourth commands that can be operated in parallel except the first fourth command; the cumulative sum of the second delay intervals of the group conflicts of the inserted one or more fourth commands that can be operated in parallel is less than the first delay interval.

[0073] In an exemplary embodiment, an embodiment of the present invention may be used in the usage scenario of the DRAM of the embodiment of the present invention, and set to insert a fixed number of fourth commands that can be operated in parallel within the first delay interval; for example, insert two fourth commands that can be operated in parallel. Directly setting a fixed number can reduce the calculation steps of the cumulative sum of the second delay interval and improve the processing speed. In an exemplary embodiment, an embodiment of the present invention can search for fourth commands that can be operated in parallel in order from head to tail. The fourth commands that can be operated in parallel may include multiple groups, and the embodiment of the present invention performs the above processing for each group of fourth commands separately. In an exemplary embodiment, the one or more inserted fourth commands that can be operated in parallel are fourth commands determined according to the order of the command queue, that is, the order of the inserted fourth command in the command queue is consistent with that before the command is inserted.

[0074] Figure 5 A schematic diagram of inserting a fourth command according to an embodiment of the present invention is shown in FIG. Figure 5 As shown, Figure 5The timing parameters in are parameters defined by the JEDEC standard. In the embodiment of the present invention, the write operation of B4-R3 is hidden in the first delay interval (group conflict period) of the group conflict of B0. In the embodiment of the present invention, based on the isolation operation attribute between group conflicts (the characteristic of requiring a long delay wait), the subsequent read or write commands of other groups that can be operated in parallel are advanced to the first delay interval of the group conflict for execution. The delay of the group conflict is hidden in a parallel manner.

[0075] The processing of inserting the fourth command in the embodiment of the present invention can avoid designing a complex logic mechanism for queue insertion and sorting, and reduce the logic coupling degree of DRAM. In an exemplary instance, when the operation executed by the fourth command in the embodiment of the present invention is a write operation, the first delay interval TCFH of the group conflict of the write operation = tWR + tRP + tRCD; wherein tWR represents the time for write recovery, tRP represents the time for pre-charging, and tRCD represents the activation time. The above time information can be obtained from the Joint Electron Device Engineering Committee JEDEC manual. Correspondingly, the number of multiple groups of write commands inserted in theory = the first delay interval / (data bus (DQ) conflict length (Burst Length) / 2). Here, it should be noted that, when the number of multiple groups of write commands contained in the command queue is less than the calculated number of commands that can be inserted, only the multiple groups of write commands contained in the command queue need to be inserted; Figure 6 A schematic diagram of inserting a fourth command in another embodiment of the present invention is shown in FIG. Figure 6 As shown, Figure 6 The timing parameters in the embodiment of the present invention are parameters defined by the JEDEC standard. Figure 5 Three or more groups of commands are inserted in the first delay interval. Through the insertion processing of parallel operations, the embodiment of the present invention improves the bandwidth utilization of the data bus.

[0076] In an exemplary embodiment, after inserting more than one fourth command that can be operated in parallel, the method of the embodiment of the present invention further includes:

[0077] For each of the more than one fourth commands that can be operated in parallel, respectively perform a consistency conflict check with the fifth command;

[0078] When the fourth command and the fifth command pass the consistency conflict check, data operation is performed according to the fourth command when reading the fourth command;

[0079] When the fourth command and the fifth command fail to pass the consistency conflict check, an activation operation is performed on the fourth command when the fourth command is read;

[0080] The fifth command includes: the first command in the command queue that is arranged after one or more fourth commands that can be operated in parallel.

[0081] In an exemplary embodiment, the method of the embodiment of the present invention further includes:

[0082] When it is determined according to the address information of the command that the addresses of N commands in the command queue are continuous, data at the N+1th address is read, and the read data and address information are cached in a preset cache area;

[0083] When an instruction including the N+1th address is received, cached data is read from the cache area according to the address information.

[0084] The embodiment of the present invention performs continuity judgment on the address of the command, and reads the data of the N+1th address when the addresses of N commands are continuous, thereby realizing pre-reading of data; Figure 7 Schematic diagram of data cache according to an embodiment of the present invention, Figure 7 As shown in the figure, the pre-read address is Bank2-Row1-Col4; the data in the corresponding DRAM address is pre-read and stored in the cache (Buffer) and the address information of the data is recorded; if there is no subsequent write operation to the address, the Buffer is always the latest data, and if a write operation is performed to the address, the write data in the Buffer is updated. If a new read command hits the Buffer, the data is read directly from the Buffer without having to read the data from the DRAM particles.

[0085] It should be noted that the address continuity of the embodiment of the present invention includes: the group and row addresses are the same, and the column addresses are continuous; such as bank1-row1-c1->bank1-row1-c2->bank1-row1-c3->bank1-row1-c4; the value of N is set by the user according to the application scenario of DRAM. The cache depth D can be set by the user according to system performance and application requirements; in an exemplary embodiment, the embodiment of the present invention can be simulated through batch performance testing to determine the reasonable values ​​of D and N so that the system can achieve optimal performance.

[0086] In an exemplary embodiment, the method of the embodiment of the present invention further includes:

[0087] When the data cached in the cache area is not read and updated within a preset time, the data is deleted;

[0088] When the data cached in the cache area is not read within a preset time period but is updated, the data is output to the DRAM and then the data in the cache area output to the DRAM is deleted.

[0089] In an exemplary embodiment, the preset duration of the embodiment of the present invention may be set by those skilled in the art based on experience.

[0090] In an exemplary embodiment, the method of the embodiment of the present invention further includes:

[0091] determining whether the first command is inserted in the first position;

[0092] When the first command is not inserted into the first position, an alarm process is performed.

[0093] The embodiment of the present invention sets a self-check function, and performs an alarm process when a problem including a logic operation error occurs, resulting in the first command not being inserted into the first position; Figure 8 FIG. 1 is a schematic diagram of an alarm processing according to an embodiment of the present invention. Figure 8 As shown, when no other group command is inserted between two group conflicts, alarm processing is performed; in an exemplary instance, the alarm processing performed by an embodiment of the present invention includes: generating an error report based on the fact that the first command is not inserted into the first position, and feeding back the generated error report to the user or a module for automatically processing alarms set in the system through a system message, email or other means; the user or the module for automatically processing alarms executes processing including closing the insertion function according to the received error report.

[0094] The embodiment of the present invention determines the first position where the first command can be inserted, realizes the rearrangement of the command queue, and avoids the read-write conflict through the consistency conflict check; by setting the timeout threshold, the problem of command waiting being too long is avoided. By setting the interval time between the insertion group conflicts of the fourth command that can be operated in parallel, the complexity and coupling of command scheduling are simplified, and the execution efficiency of DRAM is improved. By judging the continuity of the address, data is pre-read, so that less queue resources are used, and better reading efficiency can be achieved in the case of continuous reading; the embodiment of the present invention realizes the real-time discovery of queue scheduling problems through alarm processing, providing a basis for timely adjustment of command scheduling.

[0095] An embodiment of the present invention further provides a computer storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method for implementing command scheduling is implemented.

[0096] The embodiment of the present invention further provides a terminal, comprising: a memory and a processor, wherein a computer program is stored in the memory; wherein:

[0097] The processor is configured to execute the computer program in the memory;

[0098] When the computer program is executed by the processor, the method for implementing command scheduling as described above is implemented.

[0099] Fig. 9 FIG. 1 is a structural block diagram of a device for implementing command scheduling according to an embodiment of the present invention, such as Fig. 9 As shown, it includes: a position determination unit, a conflict checking unit and an insertion processing unit; wherein,

[0100] The position determination unit is configured to: upon receiving the first command, determine whether there is a first position for inserting the first command in the command queue;

[0101] The conflict checking unit is configured to: when the first position exists, determine whether the first position passes the consistency conflict check;

[0102] The insertion processing unit is configured to: insert the first command into a first position that passes the consistency conflict check;

[0103] The first command includes: a read command or a write command.

[0104] In the embodiment of the present invention, when the command queue is not read and written in groups, a consistency conflict check is performed on the newly received first command and then an insertion process is performed, thereby improving the read and write performance of the system on chip (SOC).

[0105] In an exemplary embodiment, the embodiment of the present invention determines that the location unit is set to:

[0106] When there is a command matching the page hit in the command queue, the position after the command matching the page hit is determined as the first position;

[0107] When there are two commands with group conflicts in the command queue, the middle position of the two commands with group conflicts is determined as the first position;

[0108] When there are two adjacent commands with the same operation type in the command queue, the middle position of the two adjacent commands with the same operation type is determined as the first position; wherein the operation type includes: a read operation and a write operation.

[0109] In an exemplary embodiment, the conflict checking unit of the embodiment of the present invention is configured as follows:

[0110] Performing a consistency conflict check between the first command and the second command at the first position in order from the head to the tail of the command queue;

[0111] When the first command and the second command pass the consistency conflict check, determining that the first position passes the consistency conflict check;

[0112] The second command includes: a read command and / or a write command that is immediately adjacent to the first position.

[0113] In an exemplary embodiment, the insertion processing unit of the embodiment of the present invention is configured as follows:

[0114] The first command is inserted into the first position closest to the head of the command queue and passes the consistency violation check.

[0115] In an exemplary embodiment, the insertion processing unit of the embodiment of the present invention is further configured to:

[0116] When the position determining unit determines that there is no first position for inserting the first command in the command queue, the first command is written into the tail of the command queue.

[0117] In an exemplary embodiment, the apparatus of the embodiment of the present invention further includes a timeout processing unit, which is configured to:

[0118] A timeout threshold is set for one or more third commands in the command queue; when the third command is not executed within the timeout threshold, the third command is inserted into the head of the command queue.

[0119] In an exemplary embodiment, the apparatus of the embodiment of the present invention further includes a parallel processing unit, which is configured to:

[0120] Determine a fourth command that can be operated in parallel in the command queue; insert more than one fourth command that can be operated in parallel within a first delay interval of a group conflict of a first fourth command;

[0121] Among them, the fourth command includes: multiple groups of commands and / or group commands; the first fourth command includes: the fourth command close to the head of the command queue; the inserted one or more fourth commands that can be operated in parallel include: other fourth commands that can be operated in parallel except the first fourth command; the cumulative sum of the second delay intervals of the group conflicts of the inserted one or more fourth commands that can be operated in parallel is less than the first delay interval.

[0122] In an exemplary embodiment, the parallel processing unit of the embodiment of the present invention is further configured as follows:

[0123] For each of the more than one fourth commands that can be operated in parallel, respectively perform a consistency conflict check with the fifth command;

[0124] When the fourth command and the fifth command pass the consistency conflict check, data operation is performed according to the fourth command when reading the fourth command;

[0125] When the fourth command and the fifth command fail to pass the consistency conflict check, an activation operation is performed on the fourth command when the fourth command is read;

[0126] The fifth command includes: the first command in the command queue that is arranged after one or more fourth commands that can be operated in parallel.

[0127] In an exemplary embodiment, the apparatus of the embodiment of the present invention further includes a pre-reading unit, which is configured to:

[0128] When it is determined according to the address information of the command that the addresses of N commands in the command queue are continuous, data at the N+1th address is read, and the read data and address information are cached in a preset cache area;

[0129] When an instruction including the N+1th address is received, cached data is read from the cache area according to the address information.

[0130] In an exemplary embodiment, the pre-reading unit of the embodiment of the present invention is further configured to:

[0131] When the data cached in the cache area is not read and updated within a preset time, the data is deleted;

[0132] When the data cached in the cache area is not read within a preset time period but is updated, the data is output to the DRAM and then the data in the cache area output to the DRAM is deleted.

[0133] In an exemplary embodiment, the device of the embodiment of the present invention further includes an alarm unit, which is configured to:

[0134] Determine whether the first command is inserted into the first position; if the first command is not inserted into the first position, perform alarm processing.

[0135] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A method for implementing command scheduling, comprising: When the dynamic random access memory DRAM receives the first command, it determines whether there is a first position for inserting the first command in the command queue; When the first position exists, determining whether the first position passes a consistency conflict check; inserting a first command into a first position that passes a consistency conflict check; Among them, the first command includes: a read command or a write command; the determining whether there is a first position for inserting the first command in the command queue includes: when there is a command that meets the page hit in the command queue, the position after the command that meets the page hit is determined as the first position; when there are two commands with group conflict in the command queue, the middle position of the two commands with group conflict is determined as the first position; when there are two commands with the same operation type and adjacent to each other in the command queue, the middle position of the two commands with the same operation type and adjacent to each other is determined as the first position; the operation types include: read operation and write operation.

2. The method according to claim 1, characterized in that The determining whether the first position passes the consistency conflict check includes: Performing a consistency conflict check between the first command and the second command on the first position in order from the head to the tail of the command queue; When the first command and the second command pass the consistency conflict check, determining that the first position passes the consistency conflict check; The second command includes: a read command and / or a write command that is immediately adjacent to the first position.

3. The method according to claim 1, characterized in that The inserting the first command into the first position that passes the consistency conflict check comprises: The first command is inserted into a first position that is closest to the head of the command queue and passes the consistency conflict check.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: When it is determined that there is no first position for inserting the first command in the command queue, the first command is written to the tail of the command queue.

5. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Setting a timeout threshold for one or more third commands in the command queue; When the third command is not executed within the timeout threshold, the third command is inserted into the head of the command queue.

6. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Determining a fourth command in the command queue that can be operated in parallel; Inserting more than one fourth command that can be operated in parallel within a first delay interval of a group conflict of the first fourth command; Among them, the fourth command includes: multiple groups of commands and / or group commands; the first fourth command includes: the fourth command close to the head of the command queue; the inserted one or more fourth commands that can be operated in parallel include: other fourth commands that can be operated in parallel except the first fourth command; the cumulative sum of the second delay intervals of the group conflicts of the inserted one or more fourth commands that can be operated in parallel is less than the first delay interval.

7. The method according to claim 6, characterized in that After inserting more than one fourth command operable in parallel, the method further comprises: Performing a consistency conflict check on each of the more than one fourth commands that can be operated in parallel with the fifth command; When the fourth command and the fifth command pass the consistency conflict check, performing data operation according to the fourth command when reading the fourth command; When the fourth command and the fifth command fail to pass the consistency conflict check, performing an activation operation on the fourth command when reading the fourth command; The fifth command includes: the first command in the command queue that is arranged after the one or more fourth commands that can be operated in parallel.

8. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: When it is determined according to the address information of the command that the addresses of the N commands in the command queue are continuous, data at the N+1th address is read, and the read data and address information are cached in a preset cache area; When an instruction including the N+1th address is received, cached data is read from the cache area according to the address information.

9. The method according to claim 8, characterized in that The method further comprises: When the data cached in the cache area has not been read and updated within a preset time period, the data is deleted; When the data cached in the cache area is not read within a preset time period but is updated, the data is output to the DRAM and then the data in the cache area output to the DRAM is deleted.

10. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: determining whether the first command is inserted into the first position; When the first command is not inserted into the first position, an alarm process is performed.

11. A computer storage medium, wherein a computer program is stored in the computer storage medium, and when the computer program is executed by a processor, the method for implementing command scheduling as claimed in any one of claims 1 to 10 is implemented.

12. A terminal, comprising: A memory and a processor, wherein the memory stores a computer program; wherein, The processor is configured to execute the computer program in the memory; When the computer program is executed by the processor, the method for implementing command scheduling as described in any one of claims 1 to 10 is implemented.

13. A device for implementing command scheduling, comprising: Determine the position unit, the conflict checking unit and the insertion processing unit; wherein, The position determination unit is configured to: upon receiving the first command, determine whether there is a first position for inserting the first command in the command queue; The conflict checking unit is configured to: when the first position exists, determine whether the first position passes the consistency conflict check; The insertion processing unit is configured to: insert the first command into a first position that passes the consistency conflict check; Among them, the first command includes: a read command or a write command; the determining whether there is a first position for inserting the first command in the command queue includes: when there is a command that meets the page hit in the command queue, the position after the command that meets the page hit is determined as the first position; when there are two commands with group conflict in the command queue, the middle position of the two commands with group conflict is determined as the first position; when there are two commands with the same operation type and adjacent to each other in the command queue, the middle position of the two commands with the same operation type and adjacent to each other is determined as the first position; the operation types include: read operation and write operation.

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