A semiconductor device forming method

Abstract

The application discloses a semiconductor device forming method, which is carried out in a vacuum reaction cavity and comprises the following steps: providing a substrate, which is provided with a dielectric layer and at least one opening, a bottom anti-reflective coating is arranged above the dielectric layer and in the opening, and a photoresist layer is arranged above the bottom anti-reflective coating around the opening; introducing a reaction gas into the vacuum reaction cavity to etch the opening, wherein the reaction gas comprises a first gas and a second gas, the first gas comprises NO, and the second gas comprises CO and / or CO2; and the etching rate of the reaction gas to the bottom anti-reflective coating is greater than the etching rate of the reaction gas to the photoresist layer. The NO / CO reaction gas provided by the application can achieve a selectivity ratio of the BARC and the PR which is equivalent to a basic condition, the etching rate of the BARC is greatly improved, the CD size of the PR is greatly reduced, the oxidation ability of the SiN dielectric layer is reduced, the wafer loss in subsequent wet etching is reduced, and the etching uniformity can also meet the requirements.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a semiconductor device forming method. BACKGROUND

[0002] With the increasing update of the chip industry and the increasing improvement of the technical node, the precision and delicacy of the process and technology are required higher and higher, especially to 3nm and below, the fine process is increasingly prominent, for example, the uniformity of most processes, whether in film deposition or etching, polishing and other processes need very high uniformity. In terms of etching, for example, the process needs precision, low damage or strong etching ability.

[0003] At present, in 3nm and below, the etching of organic material faces great challenges, especially small hole (below 15nm) etching, with very high aspect ratio, the etching ability of the bottom of the small hole is sharply weakened, plus the complexity of the dielectric layer, the density of the photoresist, the small hole etching is subject to multiple considerations, and needs to meet conditions such as low film loss, appropriate dielectric material size, strong organic etching ability and so on. However, the current chemical environment is difficult to meet all these conditions, especially in practical application.

[0004] As shown in the prior art organic etching schematic diagram with high aspect ratio small size structure, the left graph (a) is the initial schematic diagram, after etching, the following problems exist, as shown in the right graph (b), the first problem is that the top dielectric film 11 is lost too much, the second problem is that there is residual organic layer 12 at the bottom, and the main reasons for forming these problems include: reducing the etchant concentration to avoid dielectric film loss, or increasing the etching power to improve the etching rate, so that the photoresist is sputtered into the small hole and / or the dielectric film is lost. Figure 1 SUMMARY

[0005] The purpose of the present application is to solve the problem that the prior art small size etching process cannot simultaneously consider the oxidation resistance of silicon nitride, the shrinkage of CD (critical dimension), and the small hole etching ability, especially cannot meet the uniformity requirement of fine process for 3nm and below small size structure.

[0006] In order to achieve the above purpose, the present application provides a semiconductor device forming method, which is carried out in a vacuum reaction chamber, and the method comprises:

[0007] A substrate is provided, which is provided with a dielectric layer, the dielectric layer comprises at least one opening, a bottom anti-reflective coating is provided above the dielectric layer and in the opening, and a photoresist layer is provided above the bottom anti-reflective coating around the opening; ​

[0008] A reaction gas is introduced into the vacuum reaction chamber, and the opening is etched, the reaction gas comprising a first gas and a second gas, the first gas comprising NO, and the second gas comprising CO and / or CO2, wherein the etching rate of the reaction gas to the bottom anti-reflective coating is greater than the etching rate to the photoresist layer.

[0009] Optionally, the etching rate of the reaction gas to the bottom anti-reflective coating in the opening is greater than the etching rate of the reaction gas to the bottom anti-reflective coating on the dielectric layer.

[0010] Optionally, the aspect ratio of the opening is greater than 4.

[0011] Optionally, the first gas is NO, and the second gas is CO, and the volume ratio of the first gas to the second gas is 1:0.5-1:2.

[0012] Optionally, the first gas is NO, and the second gas is CO, and the volume ratio of the first gas to the second gas is 1:4-4:1.

[0013] Optionally, the selectivity of the reaction gas to the photoresist layer and the bottom anti-reflective layer is greater than 1.

[0014] Optionally, the dielectric layer comprises, but is not limited to, a silicon oxide layer or a silicon nitride layer.

[0015] Optionally, the process conditions of the etching comprise: the pressure in the vacuum reaction chamber is 20mT-120mT, the radio frequency is 50MHz-120MHz, the power is 100W-600W, and the temperature of the lower electrode in the vacuum reaction chamber for carrying the substrate is 15℃-30℃.

[0016] Optionally, the width of the opening of the small-size structure is less than 5nm.

[0017] Optionally, the width of the opening of the small-size structure is less than 15nm.

[0018] The semiconductor device forming method provided by the application uses NO gas mixed with CO and / or CO2 gas as reaction gas to perform small size structure etching. The CO and / or CO2 gas can significantly enhance the etching selectivity of the NO gas (the etching rate of the bottom anti-reflective coating is greater than that of the photoresist layer), improve the CD shrinkage ability of the PR, the oxidation resistance of the wafer, and the etching uniformity can also meet the requirements. Therefore, the etching method provided by the application can meet the requirements of reducing the oxidation ability of silicon nitride, improving the shrinkage ability of CD, and selectively etching small holes, and the etching uniformity is high, which realizes the precision, low damage or strong etching ability of the etching process, and can meet the high requirements of 3nm and below small size structure fine process. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 Prior art etching small size structure before and after state schematic diagram.

[0020] Figure 2 Flow chart of the semiconductor device forming method of the application.

[0021] Figure 3 Etching selectivity results of the reaction gas of the application to the bottom anti-reflective coating (BARC) and the PR layer.

[0022] Figure 4 Etching rate and uniformity experimental results of the reaction gas of the application to the small size structure.

[0023] Figure 5 CD size shrinkage ability experimental results of the reaction gas of the application to the small size structure.

[0024] Figure 6 Oxidation ability experimental results of the reaction gas of the application to the silicon nitride dielectric layer of the wafer. DETAILED DESCRIPTION

[0025] The technical solutions of the application will be described clearly and completely in combination with the drawings. Obviously, the described embodiments are part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0026] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0027] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected; it can be directly connected, or indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0028] The "uniformity" described herein refers to a parameter for measuring the etching capability of the etching process on the entire wafer or the entire batch, or batch to batch, which is expressed by NU(%) = (E max -E min ) / 2E ave , E max represents the maximum etching rate measured, E min represents the minimum etching rate measured, and E ave represents the average etching rate. The smaller the NU(%) is, the better the uniformity is.

[0029] As shown in Figure 2 , the present application provides a semiconductor device forming method, which is carried out in a vacuum reaction chamber, and the method comprises:

[0030] S1, providing a substrate, the substrate is provided with a dielectric layer, the dielectric layer comprises at least one opening, a bottom anti-reflective coating is provided above the dielectric layer and in the opening, and a photoresist layer is provided above the bottom anti-reflective coating around the opening;

[0031] S2, introducing a reaction gas into the vacuum reaction chamber to etch the opening, the reaction gas comprises a first gas and a second gas, the first gas comprises NO, and the second gas comprises CO and / or CO2, wherein the etching rate of the reaction gas on the bottom anti-reflective coating is greater than that on the photoresist layer.

[0032] The etching rate of the reaction gas to the bottom anti-reflective coating in the opening is greater than the etching rate of the reaction gas to the bottom anti-reflective coating on the dielectric layer.

[0033] The method is suitable for small-size structures with a large aspect ratio, for example, the aspect ratio of the opening is greater than 4. In some embodiments, the width of the opening of the small-size structure is less than 15 nm, and in other embodiments, the width of the opening of the small-size structure is less than 5 nm.

[0034] In some embodiments, the first gas is NO, the second gas is CO, and the volume ratio of the first gas to the second gas is 1:0.5-1:2.

[0035] In some embodiments, the first gas is NO, the second gas is CO, and the volume ratio of the first gas to the second gas is 1:4-4:1.

[0036] In some embodiments, the selectivity of the reaction gas to the photoresist layer and the bottom anti-reflective layer is greater than 1.03.

[0037] In some embodiments, the dielectric layer is a silicon oxide layer or a silicon nitride layer.

[0038] Nitric oxide (NO) is commonly used in thin film deposition, furnace tube oxidation and other processes. NO has a very high free radical concentration, so its chemical properties are more active. In etching experiments, it was found that its etching rate was high, comparable to the etching rate of equal amounts of N2 / O2 (same atomic ratio). Because NO has very high activity, its selectivity for etching different organic materials is weak, which reduces its ability to shrink CD. The present application uses CO gas in combination with NO gas as a reaction gas for small-size etching. CO gas is relatively inert and has a weak etching rate. Under appropriate conditions, it can be used as a polymer-producing gas, which complements NO gas and together exhibits some advantages, such as, under the condition of ensuring sufficient etching rate, the introduction of CO can significantly increase the shrinkage ability of CD and reduce the damage to silicon nitride, silicon oxide and other dielectric materials.

[0039] The following respectively compares and analyzes the etching selectivity of the reaction gas configured by the present application to the bottom anti-reflective coating (BARC) and the PR layer, the etching rate and uniformity of the small-size structure, the shrinkage ability of the CD size, and the oxidation ability to the silicon nitride dielectric layer.

[0040] Example 1

[0041] In a vacuum reaction chamber, a substrate is provided, which is provided with a dielectric layer containing at least one opening, a bottom anti-reflective coating (BARC) is provided above the dielectric layer and in the opening, and a photoresist layer (PR) is provided above the bottom anti-reflective coating around the opening.

[0042] The etching selectivity of BARC and PR is tested by mixing 100 units of NO with 0, 50, 100, 150 and 200 units of CO respectively as the reaction gas, i.e., 100NO, 100NO / 50CO, 100NO / 100CO, 100NO / 150CO, 100NO / 200CO experimental groups; the better etching gas in the prior art, 200 units of N2 and 15 units of O2 are mixed as a reference group (200N2 / 15O2); and 50N2 / 50O2, 50N2 / 50O2 / 200CO with equal atomic ratio are used as control groups.

[0043] The experimental results are shown in Table 1. Figure 3 As shown in Table 1, the selectivity of the reference group (200N2 / 15O2) to BARC and PR is 1.02, and the selectivity of the experimental group 100NO is 0.97, i.e., PR is easier to etch; and with the increase of the amount of CO in the experimental group, the selectivity increases accordingly, and when it increases to 200 units, the selectivity reaches 1.02, and the selection effect is equivalent to that of the reference group. The etching rate of the control group with equal atomic ratio of 50N2 / 50O2 and 100NO is slightly improved, but the etching selectivity is still less than 1; even if 200 units of CO are mixed, i.e., the etching gas is 50N2 / 50O2 / 200CO (with the same atomic ratio as 100NO / 200CO), the selectivity is improved, but the improvement is weak, and the selectivity is still less than 1, and PR is easier to etch.

[0044] It can be seen that CO is beneficial to improve the etching selectivity of BARC, and the mixture of NO and CO has an unexpected technical effect, and when a suitable proportion is selected, such as the volume ratio of NO to CO is 1:4-4:1, the etching selectivity of different organic materials is effectively improved. Different etching conditions also have a certain influence on the etching selectivity, and the optional etching process conditions include that the pressure in the vacuum reaction chamber is 20mT-120mT, the radio frequency is 50MHz-120MHz, the power is 100W-600W, and the temperature of the lower electrode in the vacuum reaction chamber for carrying the substrate is 15℃-30℃.

[0045] It should be noted that the etching selectivity is related to the specific organic material to be etched, but the change trend of the etching selectivity is not related to the specific material. For example, when a group of organic materials is selected, the etching selectivity of the reference group is 3:1, and the selectivity of 100NO is about 1:1, almost no selectivity, and as the amount of CO increases, the etching selectivity increases accordingly, and the reaction gas of 100NO / 200CO can achieve the same selectivity effect as the reference group.

[0046] Furthermore, the etching rate of BARC by 100NO / 200CO (2118.7 A / min) is much higher than that of the reference group (200N2 / 1502) (1233.3 A / min), as shown in the leftmost first column chart of FIG. 2. Figure 3 It can be seen that the etching rate of the NO / CO reaction gas provided by the present application is greatly improved compared with the existing basic conditions.

[0047] Example 2

[0048] In a vacuum reaction chamber, a substrate is provided, and the substrate is provided with a dielectric layer, the dielectric layer comprising at least one opening, and a bottom anti-reflective coating (BARC) is provided above the dielectric layer and in the opening, and a photoresist layer (PR) is provided above the bottom anti-reflective coating around the opening.

[0049] 100 units of NO are mixed with 0, 50, 100, 150, and 200 units of CO respectively as reaction gas to perform etching rate and uniformity experiments on the BARC coating, i.e., 100NO, 100NO / 50CO, 100NO / 100CO, 100NO / 150CO, and 100NO / 200CO experimental groups; and 50N2 / 50O2, 50N2 / 50O2 / 200CO with equal atomic ratio are used as a control group.

[0050] The experimental results are shown in FIG. 2. Figure 4 As the amount of CO increases, the etching rate gradually decreases, and the uniformity also decreases (NU% increases): the NU% of the experimental group increases from 2.2 to 4.2 (different processes require different NU%, generally <5% is good), and the etching rate decreases from 2698.3 A / min to 2118.7 A / min, and the reduced etching rate is still much higher than the etching rate under the basic conditions (1233.3 A / min, see FIG. 2). Figure 3 The NU% of the control group increases from 2.8 to 5.0.

[0051] It can be seen that CO has a significant effect on improving the uniformity of NO etching, and in practice, the proportion of CO can be adjusted according to the actual requirement for uniformity. The mixed gas of NO / CO as the reaction gas has strong etching ability, fast etching rate, and good uniformity, and has unexpected technical effects.

[0052] Example 3

[0053] In a vacuum reaction chamber, a substrate is provided, which is provided with a dielectric layer containing at least one opening, a bottom anti-reflective coating is provided above the dielectric layer and in the opening, and a photoresist layer is provided above the bottom anti-reflective coating around the opening.

[0054] The substrate is etched by using different reaction gases, and the same thickness is etched. The reference group is etched by 200N2 / 15O2 for 60s. The control group is etched by 50N2 / 50O2 for 27s and 50N2 / 50O2 / 200CO for 35s, respectively. The experimental group is etched by 100NO for 28s, 100NO / 50CO for 30s, 100NO / 100CO for 32s, 100NO / 150CO for 34s, and 100NO / 200CO for 36s, respectively.

[0055] As shown in Figure 5 After etching of the reference group, the CD size of PR is 87.28nm, and the etching rate is 1314.1A / min. After etching of the experimental group (100NO etching for 28s), the CD size of PR is 88.9nm, and the etching rate is 2698.3A / min. The etching rate is greatly improved, but the critical dimension also increases. With the increase of the amount of CO in the experimental group, the etching rate gradually decreases, and the CD size also gradually decreases. After etching of the experimental group (100NO / 200CO etching for 36s), the CD size of PR is 78.19nm, which is 12% smaller than that without adding CO. According to the results of the control group (50N2 / 50O2 etching for 27s and 50N2 / 50O2 / 200CO etching for 35s) with the same atomic ratio and equal amount, it can be seen that CO also reduces the CD size of PR etched by N2 / O2, but the reduction is not obvious, only 3.8%.

[0056] It can be seen that CO has the effect of shrinking the CD of PR, and the mixing of CO has a significant effect on the CD shrinking ability of NO. The mixed gas of CO and NO as the reaction gas for etching small size structures can effectively reduce the CD size of PR etched by NO, so as to ensure enough time for more etchants to enter the small size for etching. In practice, the flow of CO can also be adjusted according to actual needs to achieve the desired CD shrinking effect.

[0057] Compared with the reference group (200N2 / 15O2), the etching rate of the experimental group 100NO / 200CO is increased by 61%, and the CD size of PR is shrunk by 10.4%.

[0058] Example 4

[0059] Take 6 pieces of SiN wafer (wafer 1, wafer 2, wafer 3, wafer 4, wafer 5, wafer 6), respectively, after 0.5% HF immersion for 60s, the wafer loss is 8.4A, the main loss is the self-oxidized silicon oxide and part of silicon nitride. At this time, there is no silicon oxide on the wafer.

[0060] Control group: After the above treated wafer 1 is immersed in 0.5% HF for 60s, it loses 6.0A again, mainly the loss of silicon nitride.

[0061] Take the above treated wafer 2-6 to test the oxidation ability of different reaction gases to silicon nitride, the results are shown in Figure 6 Generally, the stronger the oxidation ability of the reaction gas, the greater the contribution of the oxidation layer on the surface of the silicon nitride, and the more damage caused by 0.5% HF immersion, the greater the thickness of the loss layer.

[0062] Control group: Put the above treated wafer 2 into the processing chamber, under the conditions of pressure 40mT, radio frequency 60MHz, power 200W, pass 200N2 / 1502 for 90s, so that part of the silicon nitride on the wafer is oxidized to silicon oxide; Then 0.5% HF immersion for 60s, detection found that wafer 2 loss 25.3A.

[0063] Experimental group 1: Put the above treated wafer 3 into the processing chamber, under the conditions of pressure 40mT, radio frequency 60MHz, power 200W, pass 100NO for 41s, so that part of the silicon nitride on the wafer is oxidized to silicon oxide; Then 0.5% HF immersion for 60s, detection found that wafer 3 loss 26.3A.

[0064] Experimental group 2: Put the above treated wafer 4 into the processing chamber, under the conditions of pressure 60mT, radio frequency 60MHz, power 200W, pass 100NO for 41s, so that part of the silicon nitride on the wafer is oxidized to silicon oxide; Then 0.5% HF immersion for 60s, detection found that wafer 4 loss 25.6A.

[0065] Experimental group 3: Put the above treated wafer 5 into the processing chamber, under the conditions of pressure 40mT, radio frequency 60MHz, power 200W, pass 100NO / 150CO for 50s, so that part of the silicon nitride on the wafer is oxidized to silicon oxide; Then 0.5% HF immersion for 60s, detection found that wafer 5 loss 25.2A.

[0066] Experiment group 4: the wafer 6 after the above treatment is put into a processing cavity, under the conditions of 40mT pressure, 60MHz radio frequency, and 200W power, 100NO / 200CO is inputted for 52s, so that part of the silicon nitride on the wafer is oxidized into silicon oxide; then 0.5%HF is soaked for 60s, and it is found that the wafer 6 loses 25.0A.

[0067] It can be seen that, under the current existing conditions (control group), the wafer loss is 25.3A / min, while the NO / CO mixed gas can be reduced to 25.0A / min (experiment group 4). In fact, the oxidation ability of different gases to dielectric materials comes from many aspects, and the gas pressure, power, temperature and the like can be adjusted, in addition, for the self-oxidation layer on the surface of silicon nitride, it can be found from the experiment that the inherent damage is about 20A / min. In practice, we can increase the proportion of NO gas to further improve the etching rate, so as to reduce the power to achieve the lowest oxidation ability, including the self-oxidation layer and the subsequent oxidation layer, which is obvious.

[0068] In summary, the NO / CO reaction gas provided by the present application has a selectivity ratio to BARC and PR similar to the basic condition, greatly improves the etching rate of BARC, greatly reduces the CD size of PR, reduces the oxidation ability to the SiN dielectric layer, reduces the wafer loss in subsequent wet etching, and also meets the requirement of etching uniformity.

[0069] Although the content of the present application has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present application. After reading the above content, various modifications and alternatives of the present application will be obvious to those skilled in the art. Therefore, the protection scope of the present application should be defined by the appended claims.

Claims

1. A method for forming a semiconductor device, said method being performed within a vacuum reaction chamber, characterized in that, The method includes: A substrate is provided, on which a dielectric layer is disposed, the dielectric layer including at least one opening, a bottom anti-reflective coating is disposed above the dielectric layer and within the opening, and a photoresist layer is disposed above the bottom anti-reflective coating around the opening; A reaction gas is introduced into the vacuum reaction chamber to etch the opening. The reaction gas includes a first gas and a second gas. The first gas includes NO, and the second gas includes CO and / or CO2. The volume ratio of the first gas to the second gas is 1:4 to 4:

1. The etching rate of the reaction gas on the bottom anti-reflective coating is greater than the etching rate on the photoresist layer.

2. The semiconductor device formation method according to claim 1, characterized in that, The etching rate of the reactant gas on the bottom anti-reflective coating inside the opening is greater than the etching rate on the bottom anti-reflective coating on the dielectric layer.

3. The semiconductor device formation method according to claim 1, characterized in that, The aspect ratio of the opening is greater than 4.

4. The semiconductor device formation method according to claim 1, characterized in that, The first gas is NO, the second gas is CO, and the volume ratio of the first gas to the second gas is 1:0.5 to 1:

2.

5. The semiconductor device formation method according to claim 1, characterized in that, The first gas is NO, and the second gas is CO.

6. The semiconductor device formation method according to claim 1, characterized in that, The selectivity ratio of the reactive gas to the photoresist layer and the bottom antireflective coating is greater than 1.

7. The semiconductor device formation method according to claim 1, characterized in that, The dielectric layer includes, but is not limited to, a silicon oxide layer or a silicon nitride layer.

8. The semiconductor device formation method according to claim 1, characterized in that, The etching process conditions include: a pressure of 20mT to 120mT in the vacuum reaction chamber, a radio frequency of 50MHz to 120MHz, a power of 100W to 600W, and a temperature of 15℃ to 30℃ for the lower electrode used to support the substrate in the vacuum reaction chamber.

9. The semiconductor device formation method according to claim 1, characterized in that, The width of the opening is less than 5 nm.

10. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The width of the opening is less than 15 nm.

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