Silicon carbide semiconductor device and power conversion device

Abstract

The object of the present invention is to suppress bipolar current conduction in a silicon carbide semiconductor device by relaxing the voltage applied to the terminal well region during a reflow action. The SiC-MOSFET 101 has a plurality of first well regions (30), a second well region (31), and a third well region (32) all of which are of the second conductivity type on the surface layer of a drift layer (20). The third well region (32) is arranged on the side of the second well region (31) opposite to the first well region (30). A component unit including the first well region (30) has a built-in unipolar diode. The SiC-MOSFET 101 has a source electrode (80) connected to the unipolar diode and the ohmic electrode (70) and not ohmically connected to the second well region (31) and the third well region (32).

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device and a power conversion device including silicon carbide. Background Art

[0002] It is known that when a forward current, or bipolar current, continuously flows through a pn diode made of silicon carbide (SiC), stacking defects occur in the crystal, causing a shift in forward voltage and causing reliability issues. This is believed to be due to the recombination energy of minority carriers injected through the pn diode and majority carriers, which propagate as planar defects, starting from basal plane dislocations and other defects in the silicon carbide substrate. These stacking defects obstruct the flow of current, resulting in a decrease in current and an increase in forward voltage, which reduces the reliability of the semiconductor device.

[0003] This increase in forward voltage also occurs in vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) using silicon carbide. Vertical MOSFETs have a parasitic pn diode (body diode) between the source and drain. When forward current flows through this body diode, it causes the same reliability degradation as a pn diode. Therefore, when the SiC MOSFET's body diode is used as a freewheeling diode, MOSFET characteristics may be degraded.

[0004] As one method for addressing the reliability issues associated with the forward current flowing through parasitic pn diodes, as described in Patent Document 1, there is a method that applies a stress that causes a forward current to flow through the parasitic pn diode for a long period of time, measures the change in forward voltage before and after the stress is applied, and removes (screens) components with large changes in forward voltage from the product. However, this method has the disadvantage of prolonging the current flow time, resulting in a large number of defective products when using wafers with many defects.

[0005] Another method involves embedding a unipolar diode, which conducts current only through majority carriers, as a freewheeling diode in a semiconductor device such as a unipolar transistor, such as a MOSFET. For example, Patent Documents 2 and 3 describe methods in which a Schottky barrier diode (SBD), which is a unipolar diode, is embedded in a MOSFET module unit.

[0006] In the case where a unipolar transistor having a unipolar diode built into the active region is applied to a silicon carbide semiconductor device, by designing the diffusion potential of the unipolar diode, i.e., the voltage at which the power-on action starts, to be lower than the diffusion potential of the pn junction, it is possible to prevent a bipolar current from flowing through the body diode during the backflow action, thereby suppressing the degradation of the characteristics of the unipolar transistor in the active region.

[0007] Patent Document 4 discloses a MOSFET in which an n-type epitaxial channel layer is formed on a p-type well region serving as the active region. The epitaxial channel layer operates as a unipolar diode at a gate voltage below the threshold voltage. Furthermore, the rise voltage of the unipolar diode is designed to be lower than the operating voltage of the pn diode formed by the p-type well region and the n-type drift layer. This MOSFET can also be referred to as a unipolar transistor with a built-in unipolar diode in the active region, and can be expected to provide the same benefits as a MOSFET with a built-in SBD.

[0008] However, even in unipolar transistors with a unipolar diode built into the active region, a parasitic pn diode may form in the terminal region, which is outside the active region, where it is structurally difficult to locate a unipolar diode. For example, near the gate pad or near the terminal portion of the semiconductor device, a terminal well region is formed that extends further outward than the source electrode, forming a parasitic pn diode between the terminal well region and the drift layer. Furthermore, no Schottky electrode is formed in this area, and no unipolar diode is formed. Because there is no Schottky electrode in the terminal well region, a voltage between the source and drain electrodes is applied to the pn diode formed by the terminal well region and the drift layer, causing a bipolar current to flow through the pn diode. This phenomenon is hereinafter referred to as "bipolar conduction."

[0009] When basal plane dislocations or other starting points exist in such locations, stacking defects may propagate, reducing the transistor's withstand voltage. Specifically, when the transistor is in the off state, leakage current occurs, and the heat generated by this leakage current may damage the device or circuit.

[0010] To avoid this problem, bipolar current can be prevented from flowing through the pn diode formed by the terminal well region and the drift layer. For example, the applied voltage between the source and drain can be limited to a certain value or less during semiconductor device operation. As a method for this, increasing the chip size and reducing the differential resistance of the internal SBDs per chip can reduce the source-drain voltage generated by the return current. However, this has the disadvantage of increasing chip size and cost.

[0011] One method for suppressing the forward operation of the pn diode formed by the terminal well region and the drift layer without increasing chip size is to increase the resistance of the current path formed between various portions of the terminal well region and the source electrode. Patent Document 5 discloses a structure that increases the contact resistance between the terminal well region and the source electrode as a method for increasing the resistance of the current path. With this structure, when a bipolar current flows through the pn diode formed by the terminal well region and the drift layer, the resistance component of the contact resistance generates a voltage drop, causing the potential of the terminal well region to diverge from the source potential. Consequently, the forward voltage applied to the pn diode decreases. This suppresses the flow of bipolar current.

[0012] On the other hand, a phenomenon particularly prominent in wide-bandgap semiconductor devices, such as silicon carbide, is device destruction caused by displacement current flowing in the well region during switching. When a silicon carbide semiconductor device with a MOS structure switches, a displacement current flows in the device's planar direction within the relatively large p-type well region. This displacement current and the well region's sheet resistance generate a high voltage within the well region. Furthermore, this voltage causes dielectric breakdown between the well region and the electrode formed across the insulating film, thus destroying the device. For example, if the well region's potential fluctuates by 50 V or more, and a gate electrode with a potential of approximately 0 V is formed across a 50 nm thick silicon oxide film, a high electric field of 10 MV / cm may be applied to the silicon oxide film, causing dielectric breakdown.

[0013] There are two reasons why this phenomenon occurs significantly in wide-bandgap semiconductor devices. One reason is that the impurity energy levels in the p-type well region formed in wide-bandgap semiconductors are deeper than those in silicon, resulting in a significantly higher sheet resistance in the p-type well region. Another reason is that wide-bandgap semiconductors utilize a low-resistance, high-impurity n-type drift layer, taking advantage of the higher dielectric breakdown field of wide-bandgap semiconductors than that of silicon. Consequently, the depletion layer capacitance generated in the pn junction between the n-type drift layer and the p-type well region in wide-bandgap semiconductor devices is significantly greater than in silicon semiconductor devices, resulting in a large displacement current flowing during switching.

[0014] As the switching speed increases, the displacement current increases, and the voltage generated in the well region also increases. As a method for reducing the voltage generated by the displacement current, for example, Patent Document 6 proposes forming a low-resistance p-type layer in a portion of the p-type well region.

[0015] In summary, SiC MOSFETs with a built-in unipolar diode in the active region are prone to bipolar current flow from the p-type well region, such as the peripheral region. To suppress bipolar current flow, one possible approach is to increase the resistance of the p-type well region and the source electrode. However, this approach generates a large voltage when the displacement current flows during switching. The p-type well region is required to have a high resistance during the reverse current operation to prevent current flow, but it is also required to avoid generating a voltage that would damage the insulating film above it when the displacement current flows.

[0016] As a structure that meets these requirements, for example, Patent Document 7 describes a structure in which the connection between the p-type well region, such as the peripheral region, and the source electrode forms a nonlinear resistor structure, such as a pnp slit structure. This structure can suppress bipolar current flow at voltages applied during reflow operation, and can prevent damage during switching by causing breakdown before reaching a voltage that would damage the insulating film.

[0017] In addition, a countermeasure is also considered, in which a conductive layer is formed on the p-type well region such as the peripheral region, which is not ohmically connected to the p-type well region but is connected to the source electrode, and the source electrode is connected to the p-type well region via the depletion layer capacitance of the p-type well region, so that the displacement current is energized at a low voltage and bipolar current is suppressed during the backflow action.

[0018] Prior art literature

[0019] Patent Literature

[0020] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-175412

[0021] Patent Document 2: Japanese Patent Application Laid-Open No. 2003-017701

[0022] Patent Document 3: International Publication No. 2014 / 038110

[0023] Patent Document 4: International Publication No. 2013 / 051170

[0024] Patent Document 5: International Publication No. 2014 / 162969

[0025] Patent Document 6: International Publication No. 2010 / 098294

[0026] Patent Document 7: International Publication No. 2017 / 179102 Summary of the Invention

[0027] As described above, in devices with unipolar diodes built into the active region, such as SBD-embedded MOSFETs, to suppress bipolar current flow during backflow in the terminal well region, the terminal p-type well region must be ohmically isolated from the source electrode, i.e., electrically separated. Therefore, the terminal well region must be formed independently of the active region or connected with a very high resistance.

[0028] Achieving this requirement is difficult in high-voltage components. By integrating a unipolar diode into the active region, the body diode's operation is suppressed, allowing a large unipolar current to flow during backflow. In this case, the high drift layer resistance of high-voltage components applies a high voltage to the drain. Furthermore, the built-in unipolar diode applies only a voltage sufficient to prevent the pn diode from operating in the well region of the active region, which forms the body diode.

[0029] On the other hand, in addition to the voltage applied to the body diode of the active region, the terminal well region also receives the voltage drop caused by the unipolar current flowing through the drift layer. The actual voltage applied to the terminal well region varies depending on how far away from the nearest unipolar diode the terminal well region is formed and the extent of the voltage drop generated by the drift layer. The terminal well region is typically formed to encompass the gate wiring region and the gate pad region, sufficiently away from the nearest unipolar diode. Therefore, a voltage roughly calculated by subtracting the diffusion voltage of the pn junction from the drain voltage is applied to the terminal well region. Generally, this voltage value increases with higher withstand voltage products due to increased drift layer resistance.

[0030] Therefore, due to the increase in voltage applied to the termination well region, depending on the usage situation, it becomes difficult to electrically separate the source electrode and the termination well region, as well as to electrically separate the well region of the active region connected to the source region and the termination well region. Furthermore, due to the occurrence of punch-through, the well region of the active region and the well region of the termination region are electrically connected, resulting in bipolar current flow from the termination well region.

[0031] Even when using the pnp type slit structure shown in Patent Document 7 to separate the well region connected to the source electrode and the terminal well region, there is still the problem that in high-voltage components, when a negative voltage of up to 50V is applied to the drain during a reflow operation, bipolar current may be generated from the terminal well region due to the punch-through phenomenon of the pnp slit.

[0032] The present invention has been made to solve the above-mentioned problems, and an object thereof is to suppress bipolar current conduction in a termination well region during a reflow operation in a silicon carbide semiconductor device.

[0033] The silicon carbide semiconductor device of the present invention comprises: a semiconductor substrate including silicon carbide of a first conductivity type; a drift layer of the first conductivity type formed on the semiconductor substrate; a plurality of first well regions of the second conductivity type provided in a surface layer of the drift layer; a second well region of the second conductivity type provided in the surface layer of the drift layer, with a second separation region of the first conductivity type sandwiched between the second well region and the outermost first well region; and a third well region of the second conductivity type provided in the surface layer of the drift layer, on the side of the second well region opposite to the first well region, with a third separation region of the first conductivity type sandwiched between the second well region and the second well region. Regional setting; a source region of the first conductivity type, formed on the surface layer of the first well region; an ohmic electrode, formed on the first well region, and ohmically connected to the first well region; a gate insulating film, formed on the first well region, the second well region, and the third well region; a gate electrode, formed on the gate insulating film; and a gate pad, formed on the gate insulating film on the third well region, a unipolar diode is built into the component unit including the first well region, and the silicon carbide semiconductor device has a source electrode connected to the unipolar diode and the ohmic electrode, and not ohmically connected to the second well region and the third well region.

[0034] In the silicon carbide semiconductor device of the present invention, the second and third well regions are not ohmically connected to the source electrode in the termination region, so bipolar current is less likely to flow in the second and third well regions during a reflow operation. The objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a top view of the SiC-MOSFET according to the first embodiment.

[0036] Figure 2 The SiC-MOSFET of the first embodiment is Figure 1 Cross-sectional view of line aa′.

[0037] Figure 3 This is a top view mainly showing the silicon carbide semiconductor portion of the SiC-MOSFET according to the first embodiment.

[0038] Figure 4 This is a diagram showing a resistor used in a simulation of the potential distribution in the drift layer during the reflow operation of the SiC-MOSFET.

[0039] Figure 5 This is a diagram showing T-CAD simulation results of the potential distribution in the drift layer during the reflow operation of the SiC-MOSFET.

[0040] Figure 6 It shows Figure 5 Diagram of the potential distribution on the CC′ line.

[0041] Figure 7 This is a SiC-MOSFET of a modified example of the first embodiment, along Figure 1 Cross-sectional view of line aa′.

[0042] Figure 8 This is the SiC-MOSFET of the second embodiment, along Figure 1 Cross-sectional view of line aa′.

[0043] Figure 9 This is a SiC-MOSFET of a modified example of the second embodiment, along Figure 1 Cross-sectional view of line aa′.

[0044] Figure 10 This is the SiC-MOSFET of the third embodiment, along Figure 1 Cross-sectional view of line aa′.

[0045] Figure 11 This is the SiC-MOSFET of the fourth embodiment, along Figure 1 Cross-sectional view of line aa′.

[0046] Figure 12 The SiC-MOSFET of the first modified example of the fourth embodiment is Figure 1 Cross-sectional view of line aa′.

[0047] Figure 13 The SiC-MOSFET of the second modified example of the fourth embodiment is Figure 1 Cross-sectional view of line aa′.

[0048] Figure 14 The SiC-MOSFET of the third modified example of the fourth embodiment is Figure 1 Cross-sectional view of line aa′.

[0049] Figure 15 It is a block diagram showing the structure of a power conversion system.

[0050] (Explanation of Symbols)

[0051] 15: Resistor body; 20: Drift layer; 21 - 26: Departure region; 30: First well region; 31: Second well region; 32: Third well region; 25: Contact region; 27: Channel epitaxial layer; 37: JTE region; 40: Source region; 42: Silicon carbide conductive layer; 47: Conductive layer; 50: Gate insulating film; 51: Field insulating film; 55: Interlayer insulating film; 56: Insulating film; 60: Gate electrode; 70: Ohmic electrode; 71: Schottky electrode; 75: Peripheral Schottky electrode; 76: First non-ohmic contact region; 77: Second non-ohmic contact region; 80: Source electrode; 81: Gate pad; 82: Gate wiring; 84: Drain electrode; 90: First well region contact hole; 91: Second well region contact hole; 95: Gate contact hole; 100: Power supply; 200: Power conversion device; 201: Main conversion circuit; 202: Drive circuit; 203: Control circuit; 300: Load. Detailed implementation mode

[0052] Hereinafter, the implementation mode will be described with reference to the drawings. In addition, the drawings are schematically shown, and the mutual relationship of the sizes and positions of the images respectively shown in different drawings is not necessarily correctly described and can be appropriately changed. In the following description, the same reference numerals are added to the same components for illustration, and their names and functions are also the same. Therefore, the detailed description thereof may sometimes be omitted.

[0053] In the implementation mode described in this specification, as an example of a semiconductor device, an n-channel silicon carbide MOSFET that is a silicon carbide (SiC) semiconductor device, has the first conductivity type as n-type and the second conductivity type as p-type is taken as an example for description. The description of the potential level is for the case where the first conductivity type is n-type and the second conductivity type is p-type. In the case where the first conductor is p-type and the second conductivity type is n-type, the description of the potential level is also reversed.

[0054] In this specification, in the entire semiconductor device, the region where the component units are periodically arranged is set as the active region, and the region outside the active region is set as the terminal region.

[0055] <A. Embodiment 1>

[0056] <A-1. Structure>

[0057] First, the structure of the silicon carbide semiconductor device of Embodiment 1 will be described.

[0058] Figure 1This is a schematic top view of a silicon carbide MOSFET (hereinafter referred to as "SiC-MOSFET") 101 with a built-in Schottky diode (SBD) as a silicon carbide semiconductor device according to the first embodiment. Figure 1 In the embodiment, a gate pad 81 is formed on a portion of the upper surface of the SiC-MOSFET 101, and a source electrode 80 is formed adjacent thereto. In addition, a gate wiring 82 is formed extending from the gate pad 81. In addition, in this specification, various embodiments of the SiC-MOSFET are described below, but Figure 1 It is also a top view of the SiC-MOSFET according to each of these embodiments.

[0059] Figure 2 FIG. 1 shows a cross section aa′ from the source electrode 80 to the gate wiring 82 of the SiC-MOSFET 101. Figure 3 FIG. 1 is a top view of a portion of SiC-MOSFET 101 mainly showing a silicon carbide semiconductor.

[0060] exist Figure 2 In the embodiment, a drift layer 20 composed of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 composed of n-type and low-resistance silicon carbide. Figure 1 The region of the gate wiring 82 shown corresponds approximately to the position of the surface layer, as shown in FIG. Figure 3 As shown, a third well region 32 composed of p-type silicon carbide is provided.

[0061] In the surface layer of the drift layer 20, there is provided Figure 1 The lower portion of the region of the source electrode 80 is shown, as Figure 2 As shown, a plurality of first well regions 30 made of p-type silicon carbide are provided. On the surface of each first well region 30, a source region 40 made of n-type silicon carbide is formed at a predetermined distance from the outer periphery of the first well region 30 toward the inside.

[0062] A contact region 35 composed of low-resistance p-type silicon carbide is formed on the surface layer of each first well region 30, further inward than the source region 40. A standoff region 21 is formed in each first well region 30, further inward than the contact region 35, penetrating each first well region 30 in the thickness direction. The standoff region 21 is also referred to as a first standoff region. The standoff region 21 is composed of the same n-type silicon carbide as the drift layer 20. The n-type impurity concentration of the standoff region 21 can be the same as, higher than, or lower than, the n-type impurity concentration of the drift layer 20. Furthermore, part or all of the standoff region 21 can be included in a trench structure formed by engraving on the surface of the drift layer 20.

[0063] A Schottky electrode 71 is formed on the upper surface of the separation region 21 and is Schottky-connected to the separation region 21. Here, the Schottky electrode 71 is preferably formed so as to include at least the corresponding separation region 21 when viewed from above.

[0064] An ohmic electrode 70 is formed on the upper surface of the source region 40. A source electrode 80 connected to the contact region 35 is formed on the ohmic electrode 70 and the Schottky electrode 71. The first well region 30 can easily exchange electrons and holes with the ohmic electrode 70 via the low-resistance contact region 35.

[0065] The region of the drift layer 20 between two adjacent first well regions 30 is an n-type standoff region 22. The n-type impurity concentration of the standoff region 22 can be the same as, higher than, or lower than the n-type impurity concentration of the drift layer 20. A gate insulating film 50 is formed on the upper surfaces of the first well regions 30, the standoff regions 22 between adjacent first well regions 30, and the source regions 40 within each first well region 30. A gate electrode 60 is formed on the gate insulating film 50, at least on the upper portion of the first well regions 30. The surface layer of the first well region 30 that faces the gate electrode 60 with the gate insulating film 50 interposed therebetween is referred to as the channel region.

[0066] In the surface layer of the drift layer 20, a second well region 31 is formed outside the outermost first well region 30, sandwiching a standoff region 23. In other words, the standoff region 23 is the region between the first well region 30 and the second well region 31. The standoff region 23 is composed of the same n-type silicon carbide as the drift layer 20. The n-type impurity concentration in the standoff region 23 can be the same as, higher than, or lower than, the n-type impurity concentration of the drift layer 20. The standoff region 23 and the first and second well regions 30, 31 sandwiching it on either side form a pnp contact structure in the planar direction. In this specification, this structure is referred to as a pnp slit. The standoff region 23 is also referred to as a second standoff region. A gate insulating film 50 is also formed on the second well region 31. A gate electrode 60 is formed on the gate insulating film 50 on the second well region 31, electrically connected to the gate electrode 60 formed on the first well region 30.

[0067] The second well region 31 is adjacent to the first well region 30 via the separation region 23. The second well region 31 is in non-ohmic connection with the source electrode 80. Figure 2In the embodiment, the interlayer insulating film 55, the gate electrode 60 and the gate insulating film 50 on the second well region 31 are opened to form a second well region contact hole 91, and a first non-ohmic contact region 76 is formed below the second well region contact hole 91. Furthermore, the second well region 31 is connected to the source electrode 80 via the first non-ohmic contact region 76. However, Figure 2 The structure shown is an example, and other structures may be used as long as the second well region 31 and the source electrode 80 are in non-ohmic connection.

[0068] For example, the second well region 31 can also be Schottky-connected to the source electrode 80. Alternatively, an n-type silicon carbide region can be formed on the second well region 31, and the n-type silicon carbide region and the source electrode 80 can be ohmically connected, thereby forming a diode connection between the source electrode 80 and the second well region 31 using a pn junction. Furthermore, even if contact with the source electrode 80 is not explicitly formed, the width of the standoff region 23 can be designed to be shorter than a certain value, thereby achieving a non-ohmic connection between the second well region 31 and the source electrode 80 via a nonlinear resistance generated by the punch-through of the pnp slit. Furthermore, the second well region 31 can be divided by n-type standoff regions and composed of multiple regions. In this case, not all second well regions 31 need to be adjacent to the first well region via the standoff region 23, and the gate insulating film 50 does not need to be formed on all second well regions 31.

[0069] In the surface layer of the drift layer 20, a third well region 32 is formed outside the second well region 31, sandwiching a standoff region 24. In other words, the standoff region 24 is the region between the second well region 31 and the third well region 32. The standoff region 24 is also referred to as the third standoff region. The standoff region 24 is made of the same n-type silicon carbide as the drift layer 20. The n-type impurity concentration in the standoff region 24 can be the same as, higher than, or lower than, the n-type impurity concentration of the drift layer 20. A pnp contact structure, i.e., a pnp slit, is formed in the planar direction between the standoff region 24 and the second and third well regions 31, 32 that sandwich it.

[0070] The third well region 32 is in non-ohmic connection with the source electrode 80. Figure 2 In the embodiment, the interlayer insulating film 55, the gate electrode 60 and the gate insulating film 50 on the third well region 32 are opened to form a third well region contact hole 92, and a second non-ohmic contact region 77 is formed below the third well region contact hole 92. Furthermore, the third well region 32 is connected to the source electrode 80 via the second non-ohmic contact region 77. However, Figure 2 The structure shown is an example, and other structures may be used as long as the third well region 32 and the source electrode 80 are in non-ohmic connection.

[0071] For example, the third well region 32 may be Schottky-connected to the source electrode 80. Alternatively, an n-type silicon carbide region may be formed on the third well region 32, and the n-type silicon carbide region and the source electrode 80 may be ohmically connected, thereby forming a diode connection between the source electrode 80 and the third well region 32 using a pn junction. Furthermore, even if contact with the source electrode 80 is not explicitly formed, the width of the separation region 24 may be designed to be shorter than a certain value, thereby achieving a non-ohmic connection between the third well region 32 and the source electrode 80 via a nonlinear resistance due to punch-through of the pnp slit.

[0072] An interlayer insulating film 55 is formed between the gate electrode 60 and the source electrode 80. Furthermore, the gate electrode 60 above the third well region 32 is connected to the gate wiring 82 via a gate contact hole 95 formed by opening the interlayer insulating film 55. Furthermore, a JTE region 37 is formed on the surface of the drift layer 20 on the outer peripheral side of the third well region 32, i.e., on the side opposite to the first well region 30. The JTE region 37 is composed of p-type silicon carbide, and its impurity concentration is lower than that of the second well region 31.

[0073] A field insulating film 51 having a greater thickness than the gate insulating film 50 or the gate insulating film 50 is formed on the third well region 32. The field insulating film 51 may be formed over the separation region 24 and over the second well region 31.

[0074] In the active region, the ohmic electrode 70 , the Schottky electrode 71 , and the source electrode 80 on the contact region 35 are connected to the source electrode 80 on the interlayer insulating film 55 via a first well region contact hole 90 formed through the interlayer insulating film 55 and the gate insulating film 50 .

[0075] A drain electrode 84 is formed on the back surface side of the semiconductor substrate 10 .

[0076] When the punch-through voltage during switching is limited to a certain value by using the punch-through phenomenon of the pnp slit in leaving area 23 and leaving area 24, the slit width is set to W. As in patent document 7, the punch-through voltage V provided as the solution of x=W in the following linear Poisson equation can be controlled.

[0077] [Formula 1]

[0078]

[0079] The punch-through voltage V which is a solution of x=W in the above-mentioned Poisson's equation is as follows.

[0080] [Formula 2]

[0081]

[0082] Here is the potential distribution, x is the distance in the planar direction, q is the elementary charge, N is the effective impurity concentration, and ε is the dielectric constant of the semiconductor.

[0083] Next, use Figure 3 to explain the positional relationship of the planes of the first well region 30, the second well region 31, and the third well region 32. First, the second well region 31 is formed so as to surround the first well region 30 that forms the active region of the SiC-MOSFET 101. Further, the third well region 32 is formed so as to surround the outside thereof. Therefore, the gate wiring 82 or the gate pad 81 is mainly formed on the third well region 32.

[0084] In Figure 3 , consider the case where the gate wiring 82 is formed so as to surround the active region, but also consider the case where the gate pad 81 or the gate wiring 82 is formed near the center line of the SiC-MOSFET 101. Even in this case, the third well region 32 is formed under the gate pad 81 and the gate wiring 82, and the second well region 31 is formed between the third well region 32 and the first well region 30.

[0085] <A-2. Manufacturing method>

[0086] Next, explain the manufacturing method of the SiC-MOSFET 101, which is a silicon carbide semiconductor device of the present embodiment.

[0087] First, on the semiconductor substrate 10, a drift layer 20 with a thickness of 5 to 200 μm is epitaxially grown by chemical vapor deposition (CVD method). The semiconductor substrate 10 is a (0001) plane with an off angle on the first main surface, has a 4H polytype, and includes n-type and low-resistance silicon carbide. The drift layer 20 is silicon carbide with an n-type impurity concentration of 1×10 14 to 1×10 17 cm -3 .

[0088] Next, an implantation mask is formed on a predetermined region of the surface of the drift layer 20 by a photoresist or the like, and ions of p-type impurity Al (aluminum) are implanted. At this time, the depth of the ion implantation of Al is set to about 0.3 to 3 μm that does not exceed the thickness of the drift layer 20. In addition, the doping concentration of Al is in the range of 1×10 17 to 1×10 19 cm -3 , which is higher than the impurity concentration of the drift layer 20. After that, the implantation mask is removed. The region where Al is ion-implanted through this process becomes the first well region 30, the second well region 31, and the third well region 32.

[0089] Next, an implantation mask is formed on the surface of the drift layer 20 through a photoresist or the like, and ion implantation of Al as a p-type impurity is performed. At this time, the depth of the Al ion implantation is set to be approximately 0.3 to 3 μm less than the thickness of the drift layer 20. In addition, the Al doping concentration is set to be 1×10 16 to 1×10 18 cm -3 The impurity concentration of the first well region 30 is within a range higher than that of the drift layer 20 and lower than that of the first well region 30. The implantation mask is then removed. The region where Al is ion-implanted in this step becomes the JTE region 37. Similarly, contact region 35 is formed by implanting Al ions into a predetermined region on the surface of the first well region 30 at a higher impurity concentration than that of the first well region 30.

[0090] Next, an implantation mask is formed using a photoresist or the like so as to open a predetermined portion inside the first well region 30 on the surface of the drift layer 20, and ion implantation of N (nitrogen) as an n-type impurity is performed. The depth of the N ion implantation is assumed to be shallower than the thickness of the first well region 30. In addition, the N doping concentration is assumed to be 1×10 18 to 1×10 21 cm -3 The range of , exceeds the p-type impurity concentration of the first well region 30. The region exhibiting n-type in the region into which N is implanted in this step becomes the source region 40.

[0091] Next, annealing is performed in a heat treatment apparatus in an inert gas atmosphere such as argon (Ar) gas at a temperature of 1300 to 1900° C. for 30 seconds to 1 hour. This annealing electrically activates the ion-implanted N and Al.

[0092] Next, a field insulating film 51 made of silicon oxide with a thickness of 0.3 to 2 μm is formed on the silicon carbide semiconductor layer except for the active region substantially corresponding to the region where the first well region 30 is formed, using CVD or photolithography technology.

[0093] Next, the silicon carbide surface not covered by the field insulating film 51 is thermally oxidized to form a silicon oxide film of a desired thickness as the gate insulating film 50. Next, a conductive polysilicon film is formed on the gate insulating film 50 and the field insulating film 51 using a reduced pressure CVD method and patterned to form the gate electrode 60. Next, an interlayer insulating film 55 comprising silicon oxide is formed using a reduced pressure CVD method. Next, a first well region contact hole 90 is formed through the interlayer insulating film 55 and the gate insulating film 50, reaching the contact region 35 and the source region 40 in the active region. Similarly, a second well region contact hole 91 is formed to reach the second well region 31, and a portion of a third well region contact hole 92 is formed to reach the third well region 32. At this time, by adding one photomask and processing in two stages, the first well region contact hole 90 is completely opened until the semiconductor substrate 10 is fully opened, but the second well region contact hole 91 and the third well region contact hole 92 are set to an incompletely opened state so that silicide is not formed in the subsequent process.

[0094] Of course, even when silicide is formed, this is not the only option if the acceptor concentration is designed to be such that ohmic contact with the second well region 31 and the third well region 32 is not formed. In this case, the number of masks can be reduced by one.

[0095] Next, after forming a metal film primarily composed of Ni by sputtering or other methods, a heat treatment is performed at a temperature of 600 to 1100°C. This causes the metal film primarily composed of Ni to react with the silicon carbide layer within the first well region contact hole 90, thereby forming a silicide between the silicon carbide layer and the metal film. Subsequently, the remaining metal film, other than the silicide formed by the reaction, is removed by wet etching. The remaining silicide thus forms the ohmic electrode 70. Furthermore, since the second well region contact hole 91 and the third well region contact hole 92 are not fully opened, no silicide is formed in the second well region 31 or the third well region 32.

[0096] Next, a metal film mainly composed of Ni is formed on the second main surface, which is the back surface of the semiconductor substrate 10 , and then heat-treated to form a back surface ohmic electrode (not shown).

[0097] Next, patterning using a photoresist or the like is used to remove the interlayer insulating film 55 at the position that will become the interlayer insulating film 55, the gate insulating film 50, and the gate contact hole 95 on the separation region 21. Furthermore, the interlayer insulating film 55 remaining below the second well region contact hole 91 and the third well region contact hole 92 is removed simultaneously. The removal method is wet etching that does not damage the surface of the silicon carbide layer that will become the Schottky interface.

[0098] Next, a metal film that becomes a Schottky electrode is deposited by a sputtering method or the like, and a Schottky electrode 71 is formed on the departure region 21 within the contact hole 90 of the first well region using patterning using a photoresist or the like.

[0099] At the same time, in the second well region contact hole 91 and the third well region contact hole 92, Schottky non-ohmic contacts (first non-ohmic contact region 76, second non-ohmic contact region 77) are also formed by deposition of a metal film.

[0100] Next, wiring metal such as Al is formed on the surface side of the semiconductor substrate 10 by a sputtering method or an evaporation method, and is processed into a predetermined shape using photolithography technology to form a source electrode 80, a gate pad 81, and a gate wiring 82. The source electrode 80 is in contact with the ohmic electrode 70, the Schottky electrode 71, the first non-ohmic contact region 76, and the second non-ohmic contact region 77, and the gate pad 81 is in contact with the gate electrode 60.

[0101] Finally, if a drain electrode 84 as a metal film is formed on the surface of a back ohmic electrode (not shown) formed on the back surface of the semiconductor substrate 10, Figures 1 to 3 the SiC-MOSFET 101 shown is completed.

[0102] <A-3. Operation>

[0103] Next, the operation of the SiC-MOSFET 101 will be described. Hereinafter, a SiC-MOSFET with a 4H-type silicon carbide semiconductor material will be used as an example. In this case, the diffusion potential of the pn junction is approximately 2V.

[0104] The following mainly describes the return current operation. During the return current operation, the drain voltage is lower than the source voltage. Here, the source voltage refers to the voltage of the source electrode 80, and the drain voltage refers to the voltage of the drain electrode 84. The drain voltage is between a few volts and tens of volts. In the active region, an SBD is formed by the separation region 21 and the Schottky electrode 71. This SBD becomes conductive at a lower voltage than the first well region 30. Therefore, in principle, the return current flows to the SBD and not to the first well region 30. In the terminal region, when the second well region 31 and the third well region 32 are in ohmic connection with the source electrode 80, the majority of the source-drain potential difference is applied to the pn junction formed between the second well region 31 and the third well region 32 and the drift layer 20. This forward current flows through the pn diode formed by the second well region 31 and the drift layer 20, allowing a large bipolar current to flow. However, in the SiC-MOSFET 101, the second well region 31 and the third well region 32 are not connected to the source electrode 80 ohms. Therefore, in principle, no bipolar current flows in the second well region 31 and the third well region 32 during the recirculation operation until the negative drain voltage applied during the recirculation operation reaches a certain value.

[0105] On the other hand, when the drift layer 20 is extremely thick in order to maintain the withstand voltage in a high withstand voltage product, for example, the voltage applied to the second well region 31 and the third well region 32 during the reflow operation becomes large. This is because the maximum current density (J ucmax ) is mainly determined by the rise voltage of the built-in SBD and the resistance of the separation region 21, and does not depend on the resistance of the drift layer 20.

[0106] The combined resistance per unit area of ​​the portion corresponding to the separation region 21 of the SBD constituted by the Schottky electrode 71 built into the active region is denoted as R SBD (Ωcm 2 ), set the rising voltage of SBD to V SBD , the rising voltage of the pn diode including the first well region 30 and the drift layer 20 is set to V pn In this case, the maximum current density J that can flow in the active region before the pn diode rises and the bipolar current begins to flow is ucmax It can be approximately expressed by the following formula.

[0107] [Formula 3]

[0108]

[0109] On the other hand, when the resistance per unit area of ​​the drift layer 20 is set to R drift (Ωcm 2), ignoring the resistance per unit area of ​​the semiconductor substrate 10, the voltage V applied between the drain and source at this time is expressed as follows ds .

[0110] [Formula 4]

[0111] V ds =-V SBD -J ucmax *R drift …(4)

[0112] Here, it is assumed that the current density in the active region is J ucmax Chip design is done in such a way that the chip heat density becomes a constant value when the chip is heated. diode It is expressed by the following formula.

[0113] [Formula 5]

[0114] E diode =V SBD *J ucmax +(R drift +R SBD )*J ucmax 2 …(5)

[0115] In high voltage products, the drift layer resistance R drift becomes relatively larger, and J ucmax Therefore, assuming that V SBD and R SBD Targeting E diode When the contribution

[0116] [Formula 6]

[0117] E diode =R drift *J ucmax 2 = Certainly…(6)

[0118] Therefore, when the withstand voltage is increased by k times, the thickness of the drift layer 20 is increased by k times, the impurity concentration is reduced to 1 / k, and the resistance of the drift layer 20 is reduced to k. 2 times. At this time, if J ucmax becomes 1 / k times, then E diode Therefore, in formula (4), the V applied during the reflow operation is ds Ignoring V SBD Therefore, the design constraints of the non-ohmic connection structure required for the second well region 31 and the third well region 32 to suppress bipolar current conduction, that is, in the non-ohmic connection structure until Vds If the current is prevented at -V, the voltage resistance can be increased by k times in proportion to the withstand voltage. Therefore, it is extremely difficult to achieve the characteristics of low resistance at a constant voltage for the operation during disconnection and connection described later and the bipolar current suppression during the reflow operation at the same time for the non-ohmic connection structure. Specifically, this tendency occurs when the impurity concentration of the drift layer 20 is 5×10 15 cm -3 This is particularly noticeable in the case of high-voltage products with a withstand voltage of 3 kV or more.

[0119] The SiC-MOSFET 101 is characterized in that there is a separation region 24 in the chip terminal area. When observing the SBD (hereinafter referred to as the "outermost peripheral SBD") formed from the outermost separation region 21, the separation region 24 is preferably arranged at least closer to the drift layer 20. At this time, the potential difference applied to the second well region 31 inside the separation region 24 during the reflow action is smaller than the potential difference between the source and the drain. The reason is that the voltage drop caused by the current flowing through the SBD increases according to the distance from the outermost peripheral SBD. Specifically, when viewed in cross-section in the depth direction and the peripheral direction of the device, the equipotential lines formed by the voltage drop caused by the reflow current are distributed on the arc with the outermost peripheral SBD as the starting point. Therefore, by forming the separation region 24 as innermost as possible of the arc, the potential difference applied to the second well region 31 during the reflow action can be made smaller than the potential difference between the source and the drain. The closer the separation region 24 is to the outermost peripheral SBD, the smaller the potential difference applied to the second well region 31 can be suppressed.

[0120] Next, the extent to which the potential difference applied to the second well region 31 is reduced depending on the positions of the separation region 24 and the outermost peripheral SBD will be described in detail. Figure 4 The resistor 15 simulating the drift layer 20 is shown. An electrode 1 is formed on a portion of the surface of the resistor 15, and an electrode 2 is formed on the back surface. The thickness of the resistor 15 is sufficiently small relative to the lengths of the electrodes 1 and 2. For example, when the length of the electrode 1 is set to 300 and the length of the electrode 2 is set to 600, the thickness of the resistor 15 is 30. The resistor 15 has a good approximation of the current distribution and potential distribution generated outside the outermost peripheral SBD by the flow of the return current in the drift layer 20 relative to the SiC-MOSFET 101. Figure 4 The resistor 15 is simulated using T-CAD to determine the current distribution and potential distribution.

[0121] Figure 5 The potential distribution in the resistor 15 is shown when the potential difference between the two electrodes is 20 V by grounding the electrode 1 and applying -20 V to the electrode 2. The electrodes 1 and 2 correspond to the source electrode 80 and the drain electrode 84 in the SiC-MOSFET 101. Figure 5 As shown, equipotential lines are distributed on an arc from point C of the electrode 1, which corresponds to the outermost SBD of SiC-MOSFET 101, toward point C' in the terminal direction. Furthermore, a voltage drop occurs along line CC' depending on the distance from point C.

[0122] Figure 6 The potential distribution on the CC' line is shown. Figure 6 The horizontal axis of represents the distance from point C normalized by the thickness of the resistor 15. Figure 6 It can be seen that on the surface of the resistor 15, the voltage drop from the end point C of the electrode 1 is 10% or more smaller than the potential difference between the electrodes 1 and 2 when the distance from the end point C of the electrode 1 is 1.15 times or less of the thickness of the resistor 15. Similarly, on the surface of the resistor 15, the voltage drop from the end point C of the electrode 1 is 30% or more smaller than the potential difference between the electrodes 1 and 2 when the distance from the end point C of the electrode 1 is 0.47 times or less or 0.20 times or less of the thickness of the resistor 15, respectively.

[0123] Based on these results, in SiC-MOSFET 101, if the distance between the standoff region 24 and the outermost SBD is within 1.15 times the thickness of the drift layer 20, the potential difference applied to the second well region 31 can be reduced by at least 10% relative to the potential difference between the source electrode 80 and the drain electrode 84, achieving a moderate effect. Similarly, if the distance between the standoff region 24 and the outermost SBD is within 0.47 times the thickness of the drift layer 20, the potential difference applied to the second well region 31 can be reduced by at least 30% relative to the potential difference between the source electrode 80 and the drain electrode 84, achieving an even greater effect. Furthermore, if the distance between the standoff region 24 and the outermost SBD is within 0.20 times the thickness of the drift layer 20, the potential difference applied to the second well region 31 can be reduced by at least 50% relative to the potential difference between the source electrode 80 and the drain electrode 84, achieving an even greater effect.

[0124] Next, we'll describe the on and off states as other stable states of the SiC-MOSFET 101. As with a typical FET, when a positive voltage exceeding the threshold voltage is applied to the gate electrode 60, the potential on the surface of the first well region 30, which faces the gate electrode 60, rises. This causes the conduction band on the silicon carbide semiconductor surface to approach the Fermi level. At this point, electrons are supplied from the source region 40, forming an inversion layer on the surface of the first well region 30. This inversion layer connects the source region 40 and the drift layer 20 with low resistance, thus reducing the resistance between the source electrode 80 and the drain electrode 84, resulting in an on-state.

[0125] Furthermore, when a voltage below the threshold is applied to the gate electrode 60, a high resistance is achieved between the source electrode 80 and the drain electrode 84 because no inversion layer forms on the surface of the first well region 30. Furthermore, the off-state voltage applied to the drain electrode 84 reverse-biases the pn junction comprising the first well region 30, the second well region 31, the third well region 32, and the drift layer 20, causing the depletion layer to expand primarily toward the drift layer 20, where the impurity concentration is low. Consequently, a high resistance state is achieved between the source electrode 80 and the drain electrode 84, enabling a high withstand voltage to be maintained, resulting in an off-state.

[0126] Next, the turn-off operation is described. During the turn-off operation, the potential of the drain electrode 84 increases sharply. Furthermore, a reverse bias is applied to the pn junction formed between the second well region 31 and the third well region 32 and the drift layer 20, and the depletion layer expands from the pn junction surface to both sides of the second well region 31 and the third well region 32 and the drift layer 20. At this time, due to the expansion of the depletion layer, the hole density in the undepleted regions within the second well region 31 and the third well region 32 increases. As a result, a displacement current is generated from the second well region 31 and the third well region 32 toward the source electrode 80 via the first non-ohmic contact region 76 and the second non-ohmic contact region 77. The first non-ohmic contact region 76 and the second non-ohmic contact region 77 are in non-ohmic connection with the source electrode 80, specifically, insulated or Schottky connection.

[0127] When the source electrode 80 forms a Schottky connection with the second well region 31 in the first non-ohmic contact region 76, and when the source electrode 80 forms a Schottky connection with the third well region 32 in the second non-ohmic contact region 77, a forward current flows from the second well region 31 or the third well region 32 toward the source electrode 80. Therefore, a high voltage that could damage the insulating film on the second well region 31 or the third well region 32 is not generated.

[0128] In the first non-ohmic contact region 76 or the second non-ohmic contact region 77, for example, even if the source electrode 80 is insulated from the second well region 31 or the third well region 32 by a thin insulating film, if the thickness of the insulating film is thin, the insulating film is destroyed when the source-drain voltage becomes above a certain value, so a high voltage that destroys the insulating film on the second well region 31 or the third well region 32 will not be generated.

[0129] In this case, the source electrode 80 and the second well region 31 or the third well region 32 are spatially closely adjacent to each other in the first non-ohmic contact region 76 or the second non-ohmic contact region 77. Therefore, the parasitic capacitance of the contact portion becomes very large, and a displacement current can flow from the second well region 31 or the third well region 32 to the source electrode 80 through the large parasitic capacitance with a small voltage drop.

[0130] Furthermore, when the separation regions 23 and 24 form a pnp slit that breaks down at a certain voltage, the high voltage that would cause the insulating films on the second well region 31 and the third well region 32 to break down is suppressed. For example, if the punch-through voltage V expressed by equation (2) is designed to be 50 V or less, the voltage generated in the second well region 31 can be suppressed to 50 V or less, and the voltage generated in the third well region 32 can be suppressed to 100 V or less.

[0131] Next, the turn-on characteristics will be described. During the turn-on operation, the drain voltage drops rapidly. At this time, the depletion layer formed between the drift layer 20 and the second and third well regions 31, 32 in the off state shrinks rapidly. Consequently, the depletion layer formed between the source electrode 80 and the second and third well regions 31, 32 shrinks rapidly. Consequently, displacement current flows from the source electrode 80 into the second and third well regions 31, 32.

[0132] When the source electrode 80 forms a Schottky connection between the first non-ohmic contact region 76 and the second well region 31, and forms a Schottky connection between the second non-ohmic contact region 77 and the third well region 32, the direction of the current flowing during the ON operation is opposite to the forward direction of the SBD formed between the second well region 31 or the third well region 32 and the source electrode 80. However, by designing the SBD so that it breaks down at a certain reverse voltage, the voltage generated in the second well region 31 or the third well region 32 can be suppressed to a voltage below that at which the insulating film above it breaks down.

[0133] Even in the case where the source electrode 80 and the second well region 31 or the third well region 32 are insulated, by designing the insulation breakdown to occur at a voltage below a certain value, the source electrode 80 and the second well region 31 or the third well region 32 are energized, and the voltage generated in the second well region 31 or the third well region 32 can be suppressed to a voltage below the voltage at which the insulating film above it is broken.

[0134] The source electrode 80 and the second well region 31 or the third well region 32 are spatially closely adjacent to each other in the first non-ohmic contact region 76 or the second non-ohmic contact region 77. Therefore, the parasitic capacitance at the contact portion becomes very large. By allowing a transient current to flow through this large parasitic capacitance, a displacement current can flow from the second well region 31 or the third well region 32 to the source electrode 80 with a small voltage drop. This allows the voltage generated in the second well region 31 or the third well region 32 to be sufficiently suppressed to a voltage below that at which the insulating film above it breaks down.

[0135] In addition, in the same manner as when it is disconnected, when the departure region 23 and the departure region 24 form a pnp slit that breaks down at a certain voltage, a high voltage that causes the insulating film on the second well region 31 and the third well region 32 to break is suppressed. For example, if the punch-through voltage V represented by Equation (2) is designed to be 50 V or less, the generated voltage in the second well region 31 can be suppressed to 50 V or less, and the generated voltage in the third well region 32 can be suppressed to 100 V or less.

[0136] <A-4. Modified Example>

[0137] Figure 7 is a cross-sectional view of the SiC-MOSFET 101A, which is a modified example of Embodiment 1, along Figure 1 the a-a' line. The SiC-MOSFET 101A includes a departure region 25 that penetrates the second well region 31 in the thickness direction. The departure region 25 is made of the same n-type silicon carbide as the drift layer 20. The n-type impurity concentration of the departure region 25 may be the same as, higher than, or lower than the n-type impurity concentration of the drift layer 20. The departure region 25 is also referred to as the fourth departure region.

[0138] On the upper surface of the departure region 25, an outer peripheral Schottky electrode 75 that is Schottky-connected to the departure region 25 is formed. The departure region 25 is in contact with the source electrode 80 via the outer peripheral Schottky electrode 75. Thus, in the SiC-MOSFET 101A, an SBD is formed in the outer peripheral region. With such a structure, a voltage drop during the reverse recovery operation in the outer peripheral region can be suppressed, so that bipolar conduction from the second well region 31, the third well region 32, and the first well region 30 adjacent to the second well region 31 can be further suppressed.

[0139] <B. Embodiment 2>

[0140] <B-1. Structure>

[0141] Figure 8 is a cross-sectional view of the SiC-MOSFET 102 with an SBD built-in, which is a silicon carbide semiconductor device according to Embodiment 2, along Figure 1 the a-a' line. The SiC-MOSFET 102 is different from the SiC-MOSFET 101 of Embodiment 1 in that it has a conductive layer 47 above the second well region 31 and the third well region 32. The conductive layer 47 is not ohmically connected to the second well region 31 and is ohmically connected to the source electrode 80 via the second well region contact hole 91 and the third well region contact hole 92.

[0142] The source electrode 80 is not ohmically connected to the second well region 31 and the third well region 32. However, the second well region 31 and the third well region 32 are in contact with the conductive layer 47, and the conductive layer 47 is ohmically connected to the source electrode 80. Therefore, the conductive layer 47 is connected to the second well region 31 and the third well region 32 via a high connection capacitance mainly including a depletion layer capacitance.

[0143] In the SiC-MOSFET 102, due to the high connection capacitance between the conductive layer 47 and the second well region 31 and the third well region 32, during the on and off operations, displacement current generated from the second well region 31 and the third well region 32 can be exchanged with the conductive layer 47 at a low generated voltage. By reducing the sheet resistance of the conductive layer 47, the generated voltage in the current path from the second well region 31 or the third well region 32 to the source electrode 80 can be suppressed to a low level. As a result, according to the SiC-MOSFET 102, a high bipolar conduction suppression ability during the reflux operation achieved by introducing the departure region 24 can be ensured, and damage to the insulating film on the second well region 31, the third well region 32, and the conductive layer 47 caused by displacement current during switching can be prevented, significantly improving the reliability.

[0144] In Figure 8 the conductive layer 47 is formed over the second well region 31 and the third well region 32, but it can also be formed over only any one of them. In this case, the contact between the well region on the side where the conductive layer 47 is not formed and the source electrode 80 is preferably formed in the same manner as the first non-ohmic contact region 76 or the second non-ohmic contact region 77 shown in Embodiment 1.

[0145] <B-2. Manufacturing Method>

[0146] The SiC-MOSFET 102 can be fabricated using substantially the same process as the SiC-MOSFET 101 of Embodiment 1. When the conductive layer 47 is highly doped polycrystalline silicon, only the process of forming polycrystalline silicon in the chip peripheral region and patterning it needs to be added before forming the field insulating film 51. In addition, the conductive layer can be a metal such as Al, Ti, Ni, or a semi-metal such as graphite.

[0147] <B-3. Variation Example>

[0148] Figure 9 is a cross-sectional view of the SiC-MOSFET 102A, which is a variation example of Embodiment 2, along the Figure 1 a-a' line. The SiC-MOSFET 102A has a thin insulating film 56 between the conductive layer 47 and the second well region 31 and the third well region 32, and is the same as the SiC-MOSFET 102 in other aspects.

[0149] In the SiC-MOSFET 102, the conductive layer 47 is in contact with the second well region 31 and the third well region 32. However, if there is a large capacitance component between the conductive layer 47 and the second well region 31 and the third well region 32, the effects of Embodiment 2 can be obtained. Therefore, as in the SiC-MOSFET 102A, an insulating film 56 may also be provided between the conductive layer 47 and the second well region 31 and the third well region 32.

[0150] The conductive layer 47 can be formed by the same process as the gate wiring, so the number of masks can be reduced.

[0151] <C. Embodiment 3>

[0152] <C-1. Structure>

[0153] Figure 10 A cross-sectional view along the a-a' line of the SiC-MOSFET 103 having an SBD built therein as a silicon carbide semiconductor device according to Embodiment 3. The SiC-MOSFET 103 has a structure in which the conductive layer 47 in the SiC-MOSFET 102 of Embodiment 2 is replaced with a silicon carbide conductive layer 42 of the first conductivity type. The silicon carbide conductive layer 42 is formed on the surfaces of the second well region 31 and the third well region 32. Figure 1 The impurity concentration of the silicon carbide conductive layer 42 is higher than the impurity concentration of the drift layer 20, for example, on the order of 1×10

[0154] to 1×10 18 to 1×10 20 cm -3 degree. Since the silicon carbide conductive layer 42 is a semiconductor of the first conductivity type with a high concentration, it is ohmically connected to the source electrode 80 via the second well region contact hole 91 and the third well region contact hole 92.

[0155] <C-2. Operation>

[0156] The silicon carbide conductive layer 42 exhibits the same function as the conductive layer 47. First, the silicon carbide conductive layer 42 and the second well region 31 and the third well region 32 form a pn diode. Therefore, during the reverse recovery operation, the current from the silicon carbide conductive layer 42 to the second well region 31 and the third well region 32 becomes reverse conduction of the diode, so almost no current flows. Therefore, bipolar conduction in the peripheral region during the reverse recovery operation can be significantly suppressed.

[0157] Furthermore, by virtue of the existence of the departure region 24, even when a large negative voltage is applied to the drain electrode 84, the negative voltage applied to the second well region 31 is suppressed to a small value. Therefore, as in the first and second embodiments, suppression of bipolar conduction can also be achieved for the application of a larger negative drain voltage.

[0158] In the off state, the displacement current associated with the sharp rise in the drain voltage flows as the forward current of the pn diode including the second well region 31, the third well region 32, and the silicon carbide conductive layer 42 to the source electrode 80 at a low generation voltage. Therefore, a large voltage that would break the insulating film on the second well region 31 and the third well region 32 does not occur. Thus, a silicon carbide semiconductor device with higher reliability can be achieved.

[0159] In the on state, the displacement current associated with the sharp decrease in the drain voltage flows as the reverse current of the pn diode including the second well region 31, the third well region 32, and the silicon carbide conductive layer 42. However, the pn diode is formed near the surface of the drift layer 20 and includes the second well region 31, the third well region 32, and the silicon carbide conductive layer 42 with a high impurity concentration. Therefore, the depletion layer capacitance of the pn diode during reverse bias application is very large. Therefore, the displacement current can be conducted via the depletion layer capacitance. Thus, a high voltage that would break the insulating film does not occur in the second well region 31 and the third well region 32. Therefore, a silicon carbide semiconductor device with high reliability can be achieved.

[0160] <C - 3. Manufacturing Method>

[0161] In the manufacturing process of the SiC - MOSFET 101 of the first embodiment, ions such as nitrogen or phosphorus can also be implanted after or simultaneously with the process of forming the source region 40 and the contact region 35 by ion implantation to form the silicon carbide conductive layer 42. Alternatively, the silicon carbide conductive layer 42 can also be formed on the second well region 31 and the third well region 32 by epitaxial growth using the CVD method.

[0162] In Figure 10 the silicon carbide conductive layer 42 is formed inside the second well region 31 and the third well region 32, but it can also be formed only inside any one of them. For example, the silicon carbide conductive layer 42 can be formed only inside the third well region 32, which is applied with a larger voltage only during the reflux operation. Thus, during the reflux operation, bipolar conduction can be suppressed up to a higher voltage. In addition, the impurity concentrations of the silicon carbide conductive layer 42 in the second well region 31 and the third well region 32 do not necessarily have to be equal and can also be different.

[0163] <D. Embodiment 4>

[0164] <D-1. Structure>

[0165] Figure 11 It is a cross-sectional view along the Figure 1 a-a' line of the SiC-MOSFET 104 with an SBD built in, which is a silicon carbide semiconductor device of Embodiment 4. The SiC-MOSFET 104 has a structure in which the departure region 25 that penetrates the second well region 31 in the thickness direction is provided in the SiC-MOSFET 102 of Embodiment 2. The departure region 25 is made of n-type silicon carbide same as the drift layer 20. The n-type impurity concentration of the departure region 25 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0166] On the upper surface of the departure region 25, a conductive layer 47 is formed. The conductive layer 47 that is ohm-connected to the source electrode 80 is Schottky-connected to the departure region 25. Thereby, an SBD is also formed in the second well region 31.

[0167] By forming an SBD in the second well region 31, the voltage drop in the outer peripheral region during the turn-back operation is suppressed. Therefore, even when the departure region 24 is provided far from the outermost SBD, the voltage applied to the departure region 24 can be ensured to be high. Thereby, by reducing the potential difference applied to the second well region 31, the conductive layer 47, the first well region 30, and the pnp slit including the departure region 23, the breakdown operation can be suppressed, and the bipolar conduction during the turn-back operation can be further suppressed. Regarding the on and off operations of the SiC-MOSFET 104, they are the same as those of the SiC-MOSFET 102 of Embodiment 2. In addition, the manufacturing method of the SiC-MOSFET 104 is also substantially the same as that of the SiC-MOSFET 102.

[0168] <D-2. Variation>

[0169] Figure 12 It is a cross-sectional view along the Figure 1Cross-sectional view along line aa′ of . SiC-MOSFET104A is a structure in which a separation region 26 is provided in place of the separation region 25 in the structure of SiC-MOSFET104. The separation region 26 penetrates the third well region 32 in the thickness direction. The separation region 26 is made of n-type silicon carbide, the same as the drift layer 20. The n-type impurity concentration of the separation region 26 can be the same as the n-type impurity concentration of the drift layer 20, or higher or lower than the n-type impurity concentration of the drift layer 20. An SBD is formed by the conductive layer 47 and the separation region 26. Thus, the potential drop around the separation region 24 and the second well region 31 can be reduced. Thus, even when a large negative voltage is applied to the drain during the reflow action, the applied voltage between the second well region 31 and the first well region 30 and the applied voltage between the second well region 31 and the conductive layer 47 are reduced, thereby achieving the suppression of bipolar current conduction.

[0170] Figure 13 The SiC-MOSFET 104B with built-in SBD of the silicon carbide semiconductor device according to the second modification of the fourth embodiment is Figure 1 Cross-sectional view along line aa′. SiC-MOSFET 104B has a structure similar to SiC-MOSFET 102 of Embodiment 2, in which a conductive layer 47 is formed across the separation region 24. This results in an SBD comprising the separation region 24 and the conductive layer 47. Consequently, the potential drop in the second well region 31 during the reflow operation can be reduced. When a large negative voltage is applied to the drain during the reflow operation, current flow due to punch-through between the second well region 31 and the first well region 30 can be suppressed, further reducing bipolar current flow. This improves reliability.

[0171] The above embodiments describe SiC-MOSFETs with built-in SBDs, including a separation region 21 within the active region, which is connected to the source electrode 80 via a Schottky electrode 71 formed above the separation region 21. However, a SiC-MOSFET does not necessarily need to have a built-in SBD; a built-in diode that operates in a unipolar manner when a reverse voltage is applied to the MOSFET, i.e., a unipolar diode, can be sufficient. For example, SiC-MOSFETs with built-in reverse-conducting diodes, such as those described in Patent Document 4, face the same challenges as SiC-MOSFETs with built-in SBDs in the peripheral region of the device. However, the structures of the above embodiments can be applied, and the advantages of each embodiment can be achieved.

[0172] Specifically, if Figure 14 shown. Figure 14 The third modification of the fourth embodiment is a SiC-MOSFET 104C having a reverse-conducting diode structure built in the silicon carbide semiconductor device. Figure 1Cross-sectional view taken along line a-a'. SiC-MOSFET 104C has a structure in which a channel epitaxial layer 27 of the first conductivity type is provided in the active region instead of the SBD in SiC-MOSFET 101 of Embodiment 1. The channel epitaxial layer 27 is formed on the surface of the first well region 30 where the source region 40 is not formed, and the impurity concentration of the first conductivity type is lower than that of the source region 40. The source electrode 80 is connected to the channel epitaxial layer 27. That is, SiC-MOSFET 104C has a unipolar diode with reverse conduction in the active region. With this structure, during reverse operation, a unipolar current flows through the channel portion, so that the bipolar current from the first well region 30 can be suppressed. Even if the structures of the respective embodiments are applied to a semiconductor device having such an active region, the effects of the respective embodiments can be enjoyed.

[0173] In SiC-MOSFET 104C, if the distance from the channel epitaxial layer 27 formed on the surface of the outermost first well region 30 to the separation region 24 as the third separation region is shorter than 1.15 times the film thickness of the drift layer 20, the potential difference applied to the second well region 31 can be reduced by more than 10% relative to the potential difference between the source electrode 80 and the drain electrode 84.

[0174] In addition, the SiC-MOSFETs described in the above respective embodiments have planar MOSFETs in the active region. However, the scope in which the respective embodiments have effects is not limited to planar MOSFETs. For example, the structures of the respective embodiments can also be applied to trench-type MOSFETs formed on the surface of a silicon carbide substrate with an etched gate structure, and the effects of the respective embodiments can be enjoyed.

[0175] In addition, although the peripheral structure of the SiC-MOSFETs described in the above respective embodiments is flat, for example, the trench formation process of a trench-type MOSFET can also be used to etch the peripheral structure in the depth direction.

[0176] <E. Embodiment 5>

[0177] This embodiment is an example in which the silicon carbide semiconductor device of the above Embodiments 1-4 is applied to a power conversion device. The present invention is not limited to a specific power conversion device, but hereinafter, as Embodiment 5, the case where the silicon carbide semiconductor device of Embodiments 1-4 is applied to a three-phase inverter will be described.

[0178] Figure 15 It is a block diagram showing the structure of a power conversion system to which the power conversion device of this embodiment is applied.

[0179] Figure 15The power conversion system shown includes a power supply 100, a power conversion device 200, and a load 300. Power supply 100 is a DC power supply that supplies DC power to power conversion device 200. Power supply 100 can be composed of various power sources. For example, power supply 100 can be composed of a DC system, a solar cell, or a battery, or it can be composed of a rectifier circuit or AC / DC converter connected to an AC system. Alternatively, power supply 100 can be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power level.

[0180] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300. The power conversion device 200 converts the DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. Figure 15 As shown, the main converter circuit 201 includes a main converter circuit 201, a drive circuit 202, and a control circuit 203. The main converter circuit 201 converts DC power into AC power and outputs it. The drive circuit 202 outputs a drive signal for each switching element of the main converter circuit 201. The control circuit 203 outputs a control signal to the drive circuit 202.

[0181] The driving circuit 202 controls each normally-off switching element to be turned off by making the voltage of the gate electrode and the voltage of the source electrode the same potential.

[0182] Load 300 is a three-phase electric motor driven by the AC power supplied from power conversion device 200. Load 300 is not limited to a specific application and may be a motor mounted on various electrical devices, for example, a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0183] The power conversion device 200 is described in detail below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). The switching elements are switched to convert the DC power supplied from the power supply 100 into AC power and supply it to the load 300. There are various examples of the specific circuit structure of the main conversion circuit 201, but the main conversion circuit 201 of this embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 switching elements and 6 freewheeling diodes connected in anti-parallel with each switching element. In each switching element of the main conversion circuit 201, the silicon carbide semiconductor device involved in any of the above-mentioned embodiments 1-4 is applied. With respect to the 6 switching elements, each 2 switching elements are connected in series to form an upper and lower branch, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Moreover, the output terminals of each upper and lower branch, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0184] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from the control circuit 203 described later, the drive circuit 202 outputs drive signals for turning the switching elements on and off to the control electrodes of the respective switching elements. To maintain the switching elements in the on state, the drive signals are voltage signals (on signals) that are higher than the threshold voltage of the switching elements. To maintain the switching elements in the off state, the drive signals are voltage signals (off signals) that are lower than the threshold voltage of the switching elements.

[0185] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on-time) for each switching element of the main conversion circuit 201 to be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled using PWM control, which modulates the on-time of the switching elements according to the voltage to be output. Furthermore, the control circuit 203 outputs a control instruction (control signal) to the drive circuit 202 so that, at each point in time, an on signal is output to the switching element to be in the on state, and an off signal is output to the switching element to be in the off state. In accordance with the control signal, the drive circuit 202 outputs the on signal or the off signal as a drive signal to the control electrode of each switching element.

[0186] In the power conversion device according to this embodiment, the silicon carbide semiconductor device of each of Embodiments 1 to 4 is applied as a switching element of the main conversion circuit 201 , thereby realizing a power conversion device with low loss and improved reliability of high-speed switching.

[0187] This embodiment describes an example in which the silicon carbide semiconductor devices of Embodiments 1-4 are applied to a two-level, three-phase inverter. However, the silicon carbide semiconductor devices of Embodiments 1-4 are not limited to this embodiment and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used. When supplying power to a single-phase load, the silicon carbide semiconductor devices of Embodiments 1-4 can also be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, the silicon carbide semiconductor devices of Embodiments 1-4 can also be applied to a DC / DC converter or an AC / DC converter.

[0188] In addition, the power conversion device of the silicon carbide semiconductor device applying embodiments 1-4 is not limited to the case where the above-mentioned load is an electric motor. For example, it can be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system.

[0189] Furthermore, the present invention can freely combine the various embodiments or appropriately modify or omit the various embodiments within the scope of the invention. Although the present invention has been described in detail, the above description is merely illustrative in all aspects and the present invention is not limited thereto. It should be understood that numerous unillustrated variations can be envisioned without departing from the scope of the present invention.

Claims

1. A silicon carbide semiconductor device comprising: A semiconductor substrate comprising silicon carbide of a first conductivity type; A drift layer of the first conductivity type is formed on the semiconductor substrate; A plurality of first well regions of the second conductivity type are arranged on the surface layer of the drift layer; A second well region of a second conductivity type is provided in the surface layer of the drift layer, between the first well region at the outermost periphery and a second separation region of the first conductivity type; a third well region of the second conductivity type, provided in the surface layer of the drift layer, on the side of the second well region opposite to the first well region, with the third separation region of the first conductivity type sandwiched between the second well region and the second well region; A source region of the first conductivity type is formed on the surface layer of the first well region; an ohmic electrode formed on the first well region and ohmically connected to the first well region; A gate insulating film formed on the first well region and the second well region; A field insulating film formed on the third well region; a gate electrode formed on the gate insulating film and the field insulating film; as well as a gate pad formed on the gate insulating film or the field insulating film, A unipolar diode is built into the component unit including the first well region. The silicon carbide semiconductor device includes: a source electrode connected to the unipolar diode and the ohmic electrode and not ohmically connected to the second well region and the third well region; The silicon carbide semiconductor device comprises: at least one of a first separation region of the first conductivity type penetrating each of the first well regions in the thickness direction and a fourth separation region of the first conductivity type penetrating the second well region in the thickness direction; A distance from a Schottky electrode that is Schottky-connected to the first separation region or the fourth separation region adjacent to the outermost first well region to the third separation region is shorter than 1.15 times the film thickness of the drift layer.

2. The silicon carbide semiconductor device according to claim 1, wherein: The unipolar diode is a Schottky barrier diode having the following components: the first exit area; and A Schottky electrode is formed on the first separation region and is Schottky-connected to the first separation region. The source electrode is connected to the Schottky electrode.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein: When the width of the third separation region in the direction connecting the second well region and the third well region is set to W, The effective impurity concentration of the third separation region is set to N, Let the dielectric constant of the semiconductor constituting the third separation region be ε, When the elementary charge is set to q, [Formula 1] The punch-through voltage V in the third separation region is shown to be 50V or less.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein: The impurity concentration of the drift layer is 5×10 15 cm -3 the following.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein: The second well region or the third well region is Schottky-connected to the source electrode.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein: The device further includes a conductive layer which is ohmically connected to the source electrode on the second well region or the third well region and is not ohmically connected to the second well region or the third well region.

7. The silicon carbide semiconductor device according to claim 6, wherein: The conductive layer is silicon carbide of a first conductivity type.

8. The silicon carbide semiconductor device according to claim 6, wherein: The upper surface of the fourth separation region is Schottky-connected to the source electrode via the conductive layer.

9. The silicon carbide semiconductor device according to claim 6, wherein: The conductive layer is conductive polysilicon.

10. The silicon carbide semiconductor device according to claim 9, wherein The polysilicon is formed on the second well region or the third well region via an insulating film.

11. A silicon carbide semiconductor device comprising: A semiconductor substrate comprising silicon carbide of a first conductivity type; A drift layer of the first conductivity type is formed on the semiconductor substrate; A plurality of first well regions of the second conductivity type are arranged on the surface layer of the drift layer; A second well region of a second conductivity type is provided in the surface layer of the drift layer, between the first well region at the outermost periphery and a second separation region of the first conductivity type; a third well region of the second conductivity type, provided in the surface layer of the drift layer, on the side of the second well region opposite to the first well region, with the third separation region of the first conductivity type sandwiched between the second well region and the second well region; A source region of the first conductivity type is formed on the surface layer of the first well region; an ohmic electrode formed on the first well region and ohmically connected to the first well region; A gate insulating film formed on the first well region and the second well region; A field insulating film formed on the third well region; a gate electrode formed on the gate insulating film and the field insulating film; as well as a gate pad formed on the gate insulating film or the field insulating film, A unipolar diode is built into the component unit including the first well region. The silicon carbide semiconductor device includes: a source electrode connected to the unipolar diode and the ohmic electrode and not ohmically connected to the second well region and the third well region; The unipolar diode is a reverse-conducting diode having the following components: the source region; and A first conductivity type channel epitaxial layer is formed on a surface of the first well region where the source region is not formed, and has a first conductivity type impurity concentration lower than that of the source region. The source electrode is connected to the channel epitaxial layer, A distance from the epitaxial channel layer formed on the surface of the outermost first well region to the third separation region is shorter than 1.15 times the film thickness of the drift layer.

12. A power conversion device comprising: A main conversion circuit, comprising the silicon carbide semiconductor device according to any one of claims 1 to 11, wherein the main conversion circuit converts input power and outputs the input power; a drive circuit that makes the voltage of the gate electrode of the silicon carbide semiconductor device equal to the voltage of the source electrode so that the silicon carbide semiconductor device performs a cutoff operation, and outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; as well as The control circuit outputs a control signal for controlling the drive circuit to the drive circuit.

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