Data processing modules, integrated circuits and electronic devices

Abstract

A data processing module, an integrated circuit and an electronic device, the data processing module comprising a data input port, a data output port and a routing path between the data input port and the data output port; the routing path is used to transmit a data signal of the data input port to the data output port; the routing path comprises a first signal cycle transmission channel and a second signal cycle transmission channel, the first signal cycle transmission channel is configured to make a first data signal input from the data input port output from the data output port through the first signal cycle transmission channel, the clock frequency of the first data signal is a first clock frequency, the second signal cycle transmission channel is configured to make a second data signal input from the data input port output from the data output port through the second signal cycle transmission channel, the clock frequency of the second data signal is a second clock frequency different from the first clock frequency. The data processing module can take into account the transmission of data signals with different clock frequencies.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data processing module, an integrated circuit, and an electronic device. Background Art

[0002] At present, with the continuous development and progress of chip process technology, high speed, high integration, low power consumption and low cost have become the main development direction of the integrated circuit industry, and the market performance requirements for chip products have also increased accordingly. Therefore, the design scale and complexity of chips have also increased greatly. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a data processing module, which includes a data input port, a data output port, and a routing path located between the data input port and the data output port; the routing path is used to transmit the data signal of the data input port to the data output port; the routing path includes a first signal cycle transmission channel and a second signal cycle transmission channel, the first signal cycle transmission channel is configured to enable a first data signal input from the data input port to be output from the data output port through the first signal cycle transmission channel, and the clock frequency of the first data signal is a first clock frequency, the second signal cycle transmission channel is configured to enable a second data signal input from the data input port to be output from the data output port through the second signal cycle transmission channel, and the clock frequency of the second data signal is a second clock frequency, and the first clock frequency is different from the second clock frequency.

[0004] For example, in a data processing module provided in an embodiment of the present disclosure, the clock cycle of the first data signal is a first clock cycle, and the first signal cycle transmission channel is configured to enable the first data signal input from the data input port to be output from the data output port after M first clock cycles, where M is an integer greater than or equal to 0, and the clock cycle of the second data signal is a second clock cycle, and the second signal cycle transmission channel is configured to enable the second data signal input from the data input port to be output from the data output port after N second clock cycles, where N is an integer greater than or equal to 0 and different from M.

[0005] For example, in a data processing module provided in an embodiment of the present disclosure, the second clock frequency is greater than the first clock frequency, and N is a positive integer greater than M.

[0006] For example, in a data processing module provided in an embodiment of the present disclosure, M is equal to 0, and the first signal period transmission channel is configured to enable the first data signal input from the data input port to be output from the data output port within the same first clock period.

[0007] For example, in a data processing module provided in an embodiment of the present disclosure, in response to M being a positive integer greater than or equal to 1, the first signal cycle transmission channel includes at least one first pipeline register, so that the first data signal input from the data input port is output from the data output port after M first clock cycles through the at least one first pipeline register; in response to N being a positive integer greater than or equal to 1, the second signal cycle transmission channel includes at least one second pipeline register, so that the second data signal input from the data input port is output from the data output port after N second clock cycles through the at least one second pipeline register.

[0008] For example, in a data processing module provided in an embodiment of the present disclosure, in response to the at least one first pipeline register including multiple first pipeline registers, the cycle durations of the instruction cycles of the multiple first pipeline registers are the same as or different from each other; and / or in response to the at least one second pipeline register including multiple second pipeline registers, the cycle durations of the instruction cycles of the multiple second pipeline registers are the same as or different from each other.

[0009] For example, in a data processing module provided in an embodiment of the present disclosure, the cycle length of the instruction cycle of the first pipeline register is the same as the cycle length of the first clock cycle, and the cycle length of the instruction cycle of the second pipeline register is the same as the cycle length of the second clock cycle.

[0010] For example, in a data processing module provided in an embodiment of the present disclosure, the routing path also includes a selection circuit, and the selection circuit is configured to transmit the first data signal input by the data input port to the data output port through the first signal periodic transmission channel, and to transmit the second data signal input by the data input port to the data output port through the second signal periodic transmission channel.

[0011] For example, in a data processing module provided in an embodiment of the present disclosure, the selection circuit includes a control end, a first input end, a second input end and an output end, the first input end is configured to be connected to the first signal cycle transmission channel, the second input end is configured to be connected to the second signal cycle transmission channel, the output end is connected to the data output port, and the control end is configured to output the first data signal received by the first input end from the output end, or to output the second data signal received by the second input end from the output end.

[0012] For example, in a data processing module provided in an embodiment of the present disclosure, the first end of the first signal cycle transmission channel is connected to the data input port, and the second end of the first signal cycle transmission channel is connected to the first input end of the selection circuit; the first end of the second signal cycle transmission channel is connected to the data input port, and the second end of the second signal cycle transmission channel is connected to the second input end of the selection circuit.

[0013] For example, in a data processing module provided in an embodiment of the present disclosure, the selection circuit includes a data selector or a combinational logic gate circuit.

[0014] For example, in a data processing module provided in an embodiment of the present disclosure, the routing path further includes at least one buffer connected between the data input port and the data output port.

[0015] At least one embodiment of the present disclosure further provides an integrated circuit, which includes at least one data processing module as described in any embodiment of the present disclosure.

[0016] For example, in an integrated circuit provided in an embodiment of the present disclosure, the at least one data processing module includes a plurality of data processing modules, and the plurality of data processing modules are respectively configured to perform different operations in the integrated circuit.

[0017] For example, in an integrated circuit provided in an embodiment of the present disclosure, the multiple data processing modules are respectively located at different positions in the integrated circuit.

[0018] At least one embodiment of the present disclosure further provides an electronic device, which includes the integrated circuit described in any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0020] Figure 1 A schematic diagram of a data processing module provided for some embodiments of the present disclosure;

[0021] Figure 2 A structural diagram of an implementation example of a data processing module provided in some embodiments of the present disclosure;

[0022] Figure 3 A structural diagram of another implementation example of a data processing module provided in some embodiments of the present disclosure;

[0023] Figure 4A schematic diagram of another data processing module provided for some embodiments of the present disclosure;

[0024] Figure 5 A schematic block diagram of an integrated circuit provided for some embodiments of the present disclosure; and

[0025] Figure 6 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0027] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0028] For different types of transmission signals in an integrated circuit, it is usually necessary to plan the corresponding signal transmission path and allocate routing resources in the integrated circuit according to the transmission characteristics, transmission requirements, etc. of the signal. For example, after the signal transmission path is determined, it is necessary to set the corresponding timing logic devices, combinational logic devices, etc. on the signal transmission path according to the clock domain to which the signal belongs, that is, according to the clock period or frequency of the signal, so as to meet the physical transmission distance limitations of transmission signals in different clock domains and ensure the stable transmission of the signal on the signal transmission path. For example, when the signal transmission path needs to pass through multiple modules in the integrated circuit, that is, the transmission signal is a feedthrough signal (Feedthrough Signal) that passes through multiple modules, the above-mentioned timing logic devices, combinational logic devices, etc. can be set in the corresponding modules located on the signal transmission path, and the corresponding layout design and routing resources are planned in each module according to the signal transmission path of the feedthrough signal and the timing logic devices, combinational logic devices, etc. that need to be set.

[0029] With the rapid development of the integrated circuit industry, the scale and complexity of circuit design are constantly increasing, and the difficulty of physical implementation of chips is also gradually increasing accordingly. In the physical implementation process of chips with large circuit scale or complex circuit design, for example, it may be necessary to transmit transmission signals belonging to multiple different clock domains in the integrated circuit. In order to meet the transmission requirements of signals in different clock domains, each module located on the signal transmission path needs to plan the layout design and routing resources in the module according to the corresponding through-signals, which may lead to the need to design a large number of modules with different structures in the chip. Therefore, in the design and development process of the chip, a large amount of computing resources and computing costs may be consumed, resulting in the extension of the chip design cycle and development cycle, the reduction of the physical implementation efficiency of the chip, and it is difficult to achieve the ideal physical implementation effect. It may also further increase the demand for the use of routing resources in the chip, occupy more routing resources, and increase the overall area of ​​the chip.

[0030] At least one embodiment of the present disclosure provides a data processing module, which includes a data input port, a data output port, and a routing path between the data input port and the data output port. The routing path is used to transmit a data signal of the data input port to the data output port; the routing path includes a first signal cycle transmission channel and a second signal cycle transmission channel; the first signal cycle transmission channel is configured to enable a first data signal input from the data input port to be output from the data output port through the first signal cycle transmission channel, and the clock frequency of the first data signal is a first clock frequency; the second signal cycle transmission channel is configured to enable a second data signal input from the data input port to be output from the data output port through the second signal cycle transmission channel, and the clock frequency of the second data signal is a second clock frequency, and the first clock frequency is different from the second clock frequency.

[0031] The data processing module provided in the above-mentioned embodiments of the present disclosure can be applied to integrated circuits with different circuit structures or different layout designs. By providing a first signal period transmission channel and a second signal period transmission channel for respectively transmitting data signals with different clock frequencies, the transmission of the first data signal and the second data signal with different clock frequencies can be realized based on the data processing module, which is beneficial to taking into account the transmission requirements of different data signals with different clock frequencies.

[0032] In this way, the reuse rate of the data processing module in the integrated circuit can be increased, that is, the utilization rate of the data processing modules using the same structure in the integrated circuit can be increased, so that there is no need to design a large number of data processing modules using different structures in the integrated circuit, thereby reducing the design cost and R&D cost of the integrated circuit using the data processing module, improving the physical implementation efficiency, and facilitating achieving the ideal physical implementation effect.

[0033] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements that have been described.

[0034] Figure 1 A schematic diagram of a data processing module provided in some embodiments of the present disclosure is shown. For example, the data processing module 10 can be applied to integrated circuit designs with different circuit structures or different layout designs, such as chip design.

[0035] like Figure 1 As shown, the data processing module 10 includes a data input port 101, a data output port 102, and a wiring path 103. The wiring path 103 is located between the data input port 101 and the data output port 102, and is used to transmit the data signal of the data input port 101 to the data output port 102. Furthermore, the transmission of the data signal through the data processing module 10 can be realized through the wiring path 103, that is, the transmission of the feedthrough signal through the data processing module 10 is realized.

[0036] For example, the data input port 101 and the data output port 102 can be used to transmit various types of data signals such as digital signals, analog signals, and power supply voltage signals, so that the data processing module 10 can realize data communication, information interaction and other functions with other data processing modules or external devices through the port.

[0037] The routing path 103 includes a first signal cycle transmission channel 110 and a second signal cycle transmission channel 120. The first signal cycle transmission channel 110 is configured to allow the first data signal DAT1 input from the data input port 101 to be output from the data output port 102 through the first signal cycle transmission channel 110, and the clock frequency of the first data signal DAT1 is the first clock frequency. The second signal cycle transmission channel 120 is configured to allow the second data signal DAT2 input from the data input port 101 to be output from the data output port 102 through the second signal cycle transmission channel 120, and the clock frequency of the second data signal DAT2 is a second clock frequency different from the first clock frequency. For example, the first data signal DAT1 and the second data signal DAT2 belong to different clock domains, respectively, and have first clock frequencies and second clock frequencies different from each other, respectively, that is, the clock period of the first data signal DAT1 is different from the clock period of the second data signal DAT2.

[0038] In the data processing module 10 provided in the above embodiment of the present disclosure, a first signal cycle transmission channel 110 and a second signal cycle transmission channel 120 are respectively provided, and the first signal cycle transmission channel 110 and the second signal cycle transmission channel 120 share a group of data input ports 101 and data output ports 102 in the same data processing module 10. Thus, it is possible to reduce the design requirements for routing resources in the data processing module 10 and save routing resources, and at the same time, the data processing module 10 can also take into account the transmission requirements for different data signals belonging to different clock domains. Furthermore, it is beneficial to improve the reuse rate of the data processing module 10 in, for example, an integrated circuit or chip, reduce the design cost and R&D cost of the integrated circuit or chip, and also help reduce the layout requirements for routing resources in the integrated circuit or chip to which the data processing module 10 is applied, and reduce the overall area of ​​the integrated circuit or chip.

[0039] For example, when the data processing module 10 is applied to an integrated circuit, the data processing module 10 can be repeatedly applied to the transmission paths of different data signals, or the data processing module 10 can be repeatedly used at different positions in the transmission path of the same data signal. In this way, by increasing the reuse rate of the data processing module 10 in the integrated circuit, the design requirements for data processing modules with different structures in the integrated circuit can be reduced, which helps to avoid the need to design a large number of data processing modules with different structures in the integrated circuit. Furthermore, it can not only meet the transmission requirements of various data signals in the integrated circuit, but also improve the design performance of the integrated circuit, help reduce the computing resources and computing costs required in the process of designing and developing the integrated circuit, speed up the convergence speed, thereby shortening the design cycle and development cycle of the integrated circuit, improving the physical implementation efficiency, and helping to achieve a more ideal physical implementation effect.

[0040] For example, for the first data signal DAT1 and the second data signal DAT2 with different clock frequencies, since the first data signal DAT1 and the second data signal DAT2 belong to different clock domains, the restrictions on the physical transmission distance of the first data signal DAT1 and the second data signal DAT2 during the transmission process may also be different. For example, the number of clock cycles that the first data signal DAT1 needs to go through when transmitting from the data input port 101 to the data output port 102 is different from the number of clock cycles that the second data signal DAT2 needs to go through when transmitting from the data input port 101 to the data output port 102.

[0041] For example, the clock cycle of the first data signal DAT1 is the first clock cycle, and the first signal cycle transmission channel 110 is configured to make the first data signal DAT1 input from the data input port 101 output from the data output port 102 after M first clock cycles, where M is a positive integer greater than or equal to 0; the clock cycle of the second data signal DAT2 is the second clock cycle, and the second signal cycle transmission channel 120 is configured to make the second data signal DAT2 input from the data input port 101 output from the data output port 102 after N second clock cycles, where N is a positive integer greater than or equal to 0 and different from M. In other words, the number of first clock cycles (i.e., M) experienced by the first data signal DAT1 when it is transmitted from the data input port 101 to the data output port 102 is different from the number of second clock cycles (i.e., N) experienced by the second data signal DAT2 when it is transmitted from the data input port 101 to the data output port 102.

[0042] In some embodiments of the present disclosure, different timing logic device layout methods need to be adopted in the first signal cycle transmission channel 110 and the second signal cycle transmission channel 120 according to different data signal transmission requirements, so that the first data signal DAT1 and the second data signal DAT2 can be stably transmitted from the data input port 101 to the data output port 102 through the first signal cycle transmission channel 110 and the second signal cycle transmission channel 120 respectively.

[0043] For example, sequential logic devices may include devices such as registers, triggers, latches, etc. in digital circuit design that have edge-triggered functions. For example, sequential logic devices have storage and memory functions for input signals, and when receiving the valid edge or valid level of the clock signal, the sequential logic device can be triggered to store the input signal and change the state of the output signal.

[0044] The following embodiments of the present disclosure take registers (i.e., pipeline registers) used in the pipeline operation mode as an example to exemplify the physical implementation of the routing path in the data processing module provided by the embodiments of the present disclosure. It should be noted that the implementation of the routing path of the data processing module in the embodiments of the present disclosure includes but is not limited to this.

[0045] Figure 2 This is a schematic diagram of an implementation example of a data processing module provided in some embodiments of the present disclosure. It should be noted that: Figure 2 The example shown is only used to exemplify the implementation of the routing path 103 in the data processing module 20. The embodiments of the present disclosure do not specifically limit the structure, function, etc. of the data processing module 20.

[0046] For example, in Figure 2 In the example shown, the second clock frequency of the second data signal DAT2 is greater than the first clock frequency of the first data signal DAT1. The first signal cycle transmission channel 110 is configured to enable the first data signal DAT1 input from the data input port 101 to be output from the data output port 102 after one first clock cycle, that is, the first data signal DAT1 needs to undergo one first clock cycle during the process of being transmitted from the data input port 101 to the data output port 102, that is, M=1. The second signal cycle transmission channel 120 is configured to enable the second data signal DAT2 input from the data input port 101 to be output from the data output port 102 after two second clock cycles, that is, the second data signal DAT2 needs to undergo two second clock cycles during the process of being transmitted from the data input port 101 to the data output port 102, that is, N=2.

[0047] For example, Figure 2 As shown, the first signal cycle transmission channel 110 includes a first pipeline register 201, so that the first data signal DAT1 input from the data input port 101 is output from the data output port 102 after a first clock cycle through the first pipeline register 201; the second signal cycle transmission channel 120 includes two second pipeline registers 202, so that the second data signal DAT2 input from the data input port 101 is output from the data output port 102 after two second clock cycles through the two second pipeline registers 202.

[0048] For example, in the two second pipeline registers 202 included in the second signal cycle transmission channel 120, the cycle lengths of the instruction cycles of the two second pipeline registers 202 can be the same as each other, which is beneficial to reducing the computing resources and computing costs required during design and development, and optimizing the physical implementation process of the data processing module 20.

[0049] For example, the two second pipeline registers 202 may respectively adopt the same structure, thereby improving the utilization rate of pipeline registers with the same structure in the data processing module 20 and further optimizing the physical implementation of the data processing module 20 .

[0050] Alternatively, in some other examples of the present disclosure, for example, according to different transmission requirements of the second data signal DAT2 or actual layout design requirements in the data processing module 20, the cycle durations of the instruction cycles of multiple second pipeline registers 202 may also be different from each other, or different structures may be adopted respectively to better meet different design requirements.

[0051] For example, in Figure 2 In the example shown, the cycle length of the instruction cycle of the first pipeline register 201 can be the same as the cycle length of the first clock cycle of the first data signal DAT1, and the cycle length of the instruction cycle of the second pipeline register 202 can be the same as the cycle length of the second clock cycle of the second data signal DAT2, which helps to further reduce the computing resources and computing costs required during the design and development process and improve the physical implementation efficiency.

[0052] It should be noted that in Figure 2 In the above example shown, the second clock frequency of the second data signal DAT2 is greater than the first clock frequency of the first data signal DAT1, and the number of the second pipeline registers 202 included in the second signal cycle transmission channel 120 is greater than the number of the first pipeline registers 201 included in the first signal cycle transmission channel 110. However, the embodiments of the present disclosure include but are not limited to this. In some other examples of the present disclosure, the first clock frequency of the first data signal DAT1 may be greater than the second clock frequency of the second data signal DAT2, or the number of the first pipeline registers 201 included in the first signal cycle transmission channel 110 may be greater than the number of the second pipeline registers 202 included in the second signal cycle transmission channel 120.

[0053] It should be noted that Figure 2 The number of first pipeline registers 201 and the number of second pipeline registers 202 shown in the figure are merely exemplary illustrations. The embodiments of the present disclosure do not impose any specific restrictions on the number of first pipeline registers 201 included in the first signal cycle transmission channel 110 and the number of second pipeline registers 202 included in the second signal cycle transmission channel 120.

[0054] For example, in some other examples, the number of the first pipeline registers 201 included in the first signal cycle transmission channel 110 may also be 2, 3, 4 or more, or may also be as described below. Figure 3In the example shown, the number of the second pipeline registers 202 is 0, that is, the first signal cycle transmission channel 110 may not be provided with the first pipeline register 201. For example, in some other examples, the number of the second pipeline registers 202 included in the second signal cycle transmission channel 120 may also be 0, 1, 3, 4, 5 or more, etc., and the embodiments of the present disclosure do not impose specific limitations on this.

[0055] For example, in some other examples of the present disclosure, when multiple first pipeline registers 201 are included in the first signal cycle transmission channel 110, the cycle durations of the instruction cycles of the multiple first pipeline registers 201 can be the same as each other, for example, they can all adopt the same structure, which is beneficial to reduce the computing resources and computing costs required during design and research and development; or, the cycle durations of the instruction cycles of the multiple first pipeline registers 201 can also be different from each other, or they can also adopt different structures to better meet different design requirements, and the embodiments of the present disclosure do not impose specific restrictions on this.

[0056] It should be noted that in some other examples or embodiments of the present disclosure, the first pipeline register 201 and the second pipeline register 202 may also be replaced by other types of sequential logic devices, such as triggers, latches and other devices in digital circuit design.

[0057] For example, Figure 2 As shown, the routing path 103 further includes a plurality of buffers 203 connected between the data input port 101 and the data output port 102 to reduce signal attenuation that may occur when the data signal is transmitted from the data input port 101 to the data output port 102 .

[0058] It should be noted that Figure 2 The number and position of the buffers 203 shown in the figure are merely exemplary. The specific number and position of the buffers 203 in the routing path 103 can be set according to the actual transmission requirements of the data signal, and the embodiments of the present disclosure do not impose specific restrictions on this.

[0059] For example, Figure 2 As shown, the routing path 103 further includes a selection circuit 301. The selection circuit 301 is configured to transmit the first data signal DAT1 input from the data input port 101 to the data output port 102 through the first signal cycle transmission channel 110, and transmit the second data signal DAT2 input from the data input port 101 to the data output port 102 through the second signal cycle transmission channel 120. That is, the selection circuit 301 is used to select data signals with different clock frequencies between different signal cycle transmission channels.

[0060] For example, the selection circuit 301 includes a first input terminal 310, a second input terminal 320, a control terminal 330, and an output terminal 340. The first input terminal 310 is configured to be connected to the first signal cycle transmission channel 110, the second input terminal 320 is configured to be connected to the second signal cycle transmission channel 120, and the output terminal 340 is connected to the data output port 102. The control terminal 330 is configured to output the first data signal received by the first input terminal 310 from the output terminal 340, or to output the second data signal received by the second input terminal 320 from the output terminal 340, that is, the control terminal 330 is configured to select to connect the first signal cycle transmission channel 110 to the data output port 102 or to connect the second signal cycle transmission channel 120 to the data output port 102, thereby establishing a data signal transmission path between the data input port 101 and the data output port 102, so as to realize the transmission of different data signals between the data input port 101 and the data output port 102.

[0061] For example, Figure 2 As shown, the first end of the first signal cycle transmission channel 110 is connected to the data input port 101, and the second end of the first signal cycle transmission channel 110 is connected to the first input terminal 310 of the selection circuit 301; the first end of the second signal cycle transmission channel 120 is connected to the data input port 101, and the second end of the second signal cycle transmission channel 120 is connected to the second input terminal 320 of the selection circuit 301.

[0062] In some examples or embodiments of the present disclosure, the selection circuit 301 may include a data selector. For example, a data selector may also be referred to as a multi-way selector or a multi-way switch, which refers to a logic circuit that selects and transmits data from multiple channels to one or more selected common data channels to implement a data selection function. Alternatively, in some other examples or embodiments of the present disclosure, the selection circuit 301 may also include, for example, a combinational logic gate circuit or other combinational logic device to implement a data selection function. Here, a combinational logic device refers to a device that implements logic operations such as an AND gate or an OR gate in a digital circuit design, such as a data selector, a numerical comparator, etc. The combinational logic device does not have a storage and memory function for the input signal. At any time, the state of the output signal of the combinational logic device depends on the state of the input signal at the current time. The embodiments of the present disclosure do not limit the specific implementation of the selection circuit 301.

[0063] Figure 3 A schematic diagram of another implementation example of a data processing module provided in some embodiments of the present disclosure. It should be noted that, in addition to the number of first pipeline registers 201 set in the first signal cycle transmission channel 110 and the number of second pipeline registers 202 set in the second signal cycle transmission channel 120, Figure 3The structure and function of the data processing module 30 shown are similar to those Figure 2 The data processing modules 20 shown are substantially the same or similar. For details, please refer to Figure 2 The corresponding descriptions in the examples shown are not repeated here.

[0064] For example, in Figure 3 In the example shown, the second clock frequency of the second data signal DAT2 is greater than the first clock frequency of the first data signal DAT1. The first pipeline register is not set in the first signal cycle transmission channel 110, that is, M=0, so that the first clock cycle when the first data signal DAT1 is input from the data input port 101 is the same as the first clock cycle when the first data signal DAT1 is output from the data output port 102, that is, in the same clock cycle of the first data signal DAT1, the first data signal DAT1 is transmitted from the data input port 101 to the data output port 102 through the first signal cycle transmission channel 110.

[0065] The second signal cycle transmission channel 120 is configured to make the second data signal DAT2 input from the data input port 101 output from the data output port 102 after a second clock cycle, that is, the second data signal DAT2 needs to go through a second clock cycle during the process of being transmitted from the data input port 101 to the data output port 102, that is, N=1. Figure 3 As shown, the second signal cycle transmission channel 120 includes a second pipeline register 202, so that the second data signal DAT2 input from the data input port 101 passes through the second pipeline register 202 and is output from the data output port 102 after a second clock cycle.

[0066] Figure 4 This is a schematic diagram of another data processing module provided in some embodiments of the present disclosure. It should be noted that, in addition to the number of data input ports 101, the number of data output ports 102 and the number of corresponding routing paths 103, Figure 4 The structure, function, implementation, etc. of the data processing module 40 shown in FIG. Figure 1 The data processing module 10 shown is substantially the same or similar. For example, the specific implementation example of the data processing module 40 can be referred to. Figure 2 The data processing module 20 shown or Figure 3 The data processing module 30 shown in FIG. Figures 1 to 3 The corresponding descriptions in the illustrated embodiments and examples will not be repeated here.

[0067] In some embodiments of the present disclosure, Figure 4As shown, the data processing module 40 may also include multiple groups of data input ports 101 and data output ports 102, for example, two groups of data input ports 101 and data output ports 102. Accordingly, the data processing module 40 also includes multiple routing paths 103 located between each group of data input ports 101 and data output ports 102, for example Figure 4 In the example shown, two routing paths 103 are included to transmit the data signals input from the data input port 101 in each group to the data output port 102 respectively.

[0068] In this way, through Figure 4 The multiple groups of data input ports 101 and data output ports 102 and the corresponding multiple routing paths 103 provided in the data processing module 40 can realize synchronous transmission of multiple pass-through signals through the data processing module 40 based on the multiple routing paths 103. Furthermore, the signal transmission efficiency of the integrated circuit or chip using the data processing module 40 can be improved, which is conducive to optimizing the design performance of the integrated circuit or chip.

[0069] It should be noted that in some other embodiments of the present disclosure, for example, according to the actual design requirements of the integrated circuit using the data processing module or the different transmission requirements of the data signal in the integrated circuit, the data processing module provided in the embodiment of the present disclosure may also include 3 groups, 4 groups or more groups of data input ports 101 and data output ports 102 and corresponding multiple routing paths 103, and the embodiments of the present disclosure do not impose specific restrictions on this.

[0070] It should be noted that in the embodiments of the present disclosure, the above Figures 1 to 4 The structures of the data processing modules 10, 20, 30 and 40 shown in the figure are only exemplary and not restrictive. According to actual needs, the above data processing modules 10, 20, 30 and 40 may also include other components and structures, etc., which are not limited in the embodiments of the present disclosure.

[0071] For example, the data processing modules 10, 20, 30 and 40 may be hardware, software, firmware and any feasible combination thereof, such as a dedicated or general circuit, chip or device, or a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation of the data processing modules 10, 20, 30 and 40.

[0072] It should be noted that the data processing module in the present disclosure may refer to a partial design or a partial module in a large circuit design, that is, the data processing module in the present disclosure may be a complete digital circuit itself or a partial circuit in a complete circuit, and the present disclosure does not impose any restrictions on this.

[0073] At least one embodiment of the present disclosure further provides an integrated circuit, which includes the data processing module provided by any embodiment of the present disclosure, for example, it may include Figure 1 The data processing module 10 shown, Figure 2 The data processing module 20 shown, Figure 3 The data processing module 30 shown or Figure 4 The data processing module 40 is shown.

[0074] Figure 5 A schematic block diagram of an integrated circuit provided in some embodiments of the present disclosure. Figure 5 As shown, the integrated circuit 50 includes a plurality of data processing modules 501, and the structures of the plurality of data processing modules 501 are identical to each other. Therefore, by making the data processing modules 501 be reused in the integrated circuit 50, that is, increasing the utilization rate of the data processing modules 501 with the same structure in the integrated circuit 50, it is possible to eliminate the need to design a large number of data processing modules with different structures in the integrated circuit 50, thereby reducing the design cost and R&D cost of the integrated circuit 50, improving the physical implementation efficiency, and facilitating achieving an ideal physical implementation effect.

[0075] For example, the multiple data processing modules 501 can be respectively configured to perform different operations in the integrated circuit 50, that is, the multiple data processing modules 501 can be respectively used to implement different functions in the integrated circuit 50. Furthermore, it can not only meet the transmission requirements of various data signals in the integrated circuit 50, but also improve the design performance of the integrated circuit 50, which helps to reduce the computing resources and computing costs required in the process of designing and developing the integrated circuit 50, accelerate the convergence speed, thereby shortening the design cycle and development cycle of the integrated circuit 50, improve the physical implementation efficiency, and help achieve a more ideal physical implementation effect.

[0076] For example, the multiple data processing modules 501 can be located at different positions in the integrated circuit 50 to achieve multiplexing at different positions in the integrated circuit 50. It should be noted that the embodiments of the present disclosure do not limit the specific number, distribution method, and setting position of the multiple data processing modules 501 in the integrated circuit 50.

[0077] The integrated circuit provided by the embodiments of the present disclosure may also include more components and structures, etc., which may be determined according to actual needs, and the embodiments of the present disclosure are not limited to this. It should be noted that in the above embodiments of the present disclosure, the integrated circuit may include more or fewer circuits, units or modules, and the connection relationship between each circuit, unit or module is not limited and may be determined according to actual needs. The specific configuration of each circuit is not limited, and may be composed of analog devices according to circuit principles, or may be composed of digital chips, or may be composed in other applicable ways.

[0078] The integrated circuit provided by the embodiments of the present disclosure can be applied to any electronic product or component such as mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, e-books, etc., and the embodiments of the present disclosure are not limited to this.

[0079] Regarding the technical effects of the integrated circuit provided in the above embodiments, reference may be made to the technical effects of the data processing module provided in the above embodiments of the present disclosure, which will not be repeated here.

[0080] At least one embodiment of the present disclosure further provides an electronic device, which includes the integrated circuit provided by any embodiment of the present disclosure, for example, may include Figure 5 An integrated circuit 50 is shown.

[0081] Figure 6 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure.

[0082] like Figure 6 As shown, the electronic device 60 includes an integrated circuit 601. For example, the integrated circuit 601 may be an integrated circuit provided by any of the above embodiments, such as Figure 5 An integrated circuit 50 is shown.

[0083] For example, the electronic device 60 may be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or may be any combination of electronic devices and hardware, which is not limited in the embodiments of the present disclosure.

[0084] It should be noted that in the embodiments of the present disclosure, the electronic device may include more or fewer circuits, modules or units, and the connection relationship between the various circuits, modules or units is not limited and can be determined according to actual needs. The specific configuration of each circuit is not limited and can be composed of analog devices according to circuit principles, or can be composed of digital chips, or in other applicable ways.

[0085] For the specific functions and technical effects of the electronic device provided in the above embodiments, reference may be made to the corresponding contents regarding the data processing module or the integrated circuit, and the repeated parts will not be repeated here.

[0086] There are a few points to note about this disclosure:

[0087] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0088] (2) For the sake of clarity, the thickness and size of layers or structures are exaggerated in the drawings used to describe the embodiments of the present invention. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intervening elements.

[0089] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0090] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A data processing module, comprising a data input port, a data output port and a wiring path between the data input port and the data output port, in, The routing path is used to transmit the data signal of the data input port to the data output port; The routing path includes a first signal cycle transmission channel and a second signal cycle transmission channel, The first signal cycle transmission channel is configured to enable a first data signal input from the data input port to be output from the data output port through the first signal cycle transmission channel, and a clock frequency of the first data signal is a first clock frequency. The second signal periodic transmission channel is configured to enable a second data signal input from the data input port to be output from the data output port through the second signal periodic transmission channel, the clock frequency of the second data signal is a second clock frequency, and the first clock frequency is different from the second clock frequency.

2. The data processing module according to claim 1, wherein: The clock cycle of the first data signal is a first clock cycle, and the first signal cycle transmission channel is configured to enable the first data signal input from the data input port to be output from the data output port after M first clock cycles, where M is an integer greater than or equal to 0. The clock cycle of the second data signal is a second clock cycle, and the second signal cycle transmission channel is configured to enable the second data signal input from the data input port to be output from the data output port after N second clock cycles, where N is an integer greater than or equal to 0 and different from M.

3. The data processing module according to claim 2, wherein: The second clock frequency is greater than the first clock frequency, and N is a positive integer greater than M.

4. The data processing module according to claim 3, wherein: M is equal to 0, and the first signal cycle transmission channel is configured to enable the first data signal input from the data input port to be output from the data output port within the same first clock cycle.

5. The data processing module according to claim 2, wherein: In response to M being a positive integer greater than or equal to 1, the first signal cycle transmission channel includes at least one first pipeline register, so that the first data signal input from the data input port is output from the data output port after M first clock cycles through the at least one first pipeline register; In response to N being a positive integer greater than or equal to 1, the second signal cycle transmission channel includes at least one second pipeline register, so that the second data signal input from the data input port is output from the data output port after N second clock cycles through the at least one second pipeline register.

6. The data processing module according to claim 5, wherein: In response to the at least one first pipeline register comprising a plurality of first pipeline registers, the cycle durations of instruction cycles of the plurality of first pipeline registers are the same as or different from each other; and / or In response to the at least one second pipeline register including a plurality of second pipeline registers, cycle durations of instruction cycles of the plurality of second pipeline registers are the same as or different from each other.

7. The data processing module according to claim 5, wherein: The cycle length of the instruction cycle of the first pipeline register is the same as the cycle length of the first clock cycle, and the cycle length of the instruction cycle of the second pipeline register is the same as the cycle length of the second clock cycle.

8. The data processing module according to any one of claims 1 to 7, wherein: The routing path also includes a selection circuit, The selection circuit is configured to transmit the first data signal input from the data input port to the data output port through the first signal periodic transmission channel, and to transmit the second data signal input from the data input port to the data output port through the second signal periodic transmission channel.

9. The data processing module according to claim 8, wherein: The selection circuit includes a control terminal, a first input terminal, a second input terminal and an output terminal. The first input end is configured to be connected to the first signal cycle transmission channel, the second input end is configured to be connected to the second signal cycle transmission channel, and the output end is connected to the data output port. The control end is configured to output the first data signal received by the first input end from the output end, or to output the second data signal received by the second input end from the output end.

10. The data processing module according to claim 9, wherein: A first end of the first signal cycle transmission channel is connected to the data input port, and a second end of the first signal cycle transmission channel is connected to the first input end of the selection circuit; A first end of the second signal periodic transmission channel is connected to the data input port, and a second end of the second signal periodic transmission channel is connected to the second input end of the selection circuit.

11. The data processing module according to claim 8, wherein: The selection circuit includes a data selector or a combinational logic gate circuit.

12. The data processing module according to any one of claims 1 to 7, wherein: The routing path also includes at least one buffer connected between the data input port and the data output port.

13. An integrated circuit comprising at least one data processing module as claimed in claim 1.

14. The integrated circuit of claim 13, wherein: The at least one data processing module includes a plurality of data processing modules, and the plurality of data processing modules are respectively configured to perform different operations in the integrated circuit.

15. The integrated circuit of claim 14, wherein: The multiple data processing modules are respectively located at different positions in the integrated circuit.

16. An electronic device comprising the integrated circuit according to claim 13.

Images