Circuits for high voltage and related chips and electronic devices

Abstract

The present application discloses a circuit for high voltage and related chips and electronic devices. The circuit for high voltage includes: a withstand voltage circuit, which operates between a first reference voltage and a ground voltage, and includes a P-type transistor and an N-type transistor, whose gate-source working driving voltage is less than the first reference voltage; and a control signal level shifting circuit, which is used to generate a level-shifted P-type transistor control signal according to a P-type transistor control signal, and to generate a level-shifted N-type transistor control signal according to an N-type transistor control signal, wherein the level-shifted P-type transistor control signal is coupled to the gate of the P-type transistor, and the level-shifted N-type transistor control signal is coupled to the gate of the N-type transistor. The circuit for high voltage and related chips and electronic devices provided in the present application can enable the circuit to operate normally at a higher reference voltage, eliminating the cost of redesigning and using high-voltage devices.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of electronic circuit technology, and in particular, to a circuit for high voltage and related chips and electronic devices. Background Art

[0002] In portable consumer electronics, power supply usually comes from lithium batteries / dry batteries, among which lithium batteries are gradually becoming the mainstream power supply, but their voltage output range may be higher than the voltage range of the electronic devices in the chip. The general practice is to use high-voltage devices to withstand the high voltage output range. However, the use of high-voltage devices may require a higher number of mask layers and often requires more chip area, which means higher manufacturing costs. Summary of the invention

[0003] One of the purposes of the present application is to provide a circuit for high voltage and a related chip and electronic device to solve the above-mentioned problem.

[0004] In a first aspect, an embodiment of the present application provides a circuit for high voltage, comprising: a withstand voltage circuit, operating between a first reference voltage and a ground voltage, wherein the withstand voltage circuit comprises a P-type transistor and an N-type transistor, the gate-source operating driving voltage of the P-type transistor and the N-type transistor is less than the first reference voltage, the source of the P-type transistor is coupled to the first reference voltage, and the source of the N-type transistor is coupled to the ground voltage; and a control signal level shifting circuit, used to generate a level-shifted P-type transistor control signal according to a P-type transistor control signal, and to generate a level-shifted N-type transistor control signal according to an N-type transistor control signal, wherein the level-shifted P-type transistor control signal is coupled to the gate of the P-type transistor, and the level-shifted N-type transistor control signal is coupled to the gate of the N-type transistor. The control signal level shifting circuit comprises: an intermediate level generating circuit, used for generating a third reference voltage and a fourth reference voltage according to the first reference voltage, wherein the first reference voltage is higher than the fourth reference voltage, and the fourth reference voltage is higher than the third reference voltage; a first level shifting circuit, used for converting the high voltage level and the low voltage level of the P-type transistor control signal to the first reference voltage and the third reference voltage to generate the level-shifted P-type transistor control signal; and a second level shifting circuit, used for converting the high voltage level and the low voltage level of the N-type transistor control signal to the fourth reference voltage and the ground voltage to generate the level-shifted N-type transistor control signal.

[0005] As a possible implementation, the first level shift circuit includes: a first level shifter, used to convert the high voltage level and the low voltage level of the P-type transistor control signal to the fourth reference voltage and the ground voltage to generate a preliminary level-shifted P-type transistor control signal; and a second level shifter, used to convert the high voltage level and the low voltage level of the preliminary level-shifted P-type transistor control signal from the fourth reference voltage and the ground voltage to the first reference voltage and the third reference voltage to generate the level-shifted P-type transistor control signal.

[0006] As a possible implementation, the second level shift circuit includes: a third level shifter, used to convert the high voltage level and the low voltage level of the N-type transistor control signal to the fourth reference voltage and the ground voltage to generate the level-shifted N-type transistor control signal.

[0007] As a possible implementation manner, the voltage-withstand circuit includes a power converter, which is used to convert the first reference voltage into a second reference voltage, wherein the first reference voltage is higher than the second reference voltage.

[0008] As a possible implementation manner, there is a specific voltage difference between the fourth reference voltage and the ground voltage, and the gate-source operating driving voltage of the P-type transistor and the N-type transistor is equal to the specific voltage difference.

[0009] As a possible implementation manner, there is a specific voltage difference between the fourth reference voltage and the ground voltage, and a difference between the first reference voltage and the third reference voltage is equal to the specific voltage difference.

[0010] As a possible implementation, the high voltage level of the P-type transistor control signal is equal to the high voltage level of the N-type transistor control signal, and the low voltage level of the P-type transistor control signal is equal to the low voltage level of the N-type transistor control signal.

[0011] As a possible implementation manner, the high voltage level of the N-type transistor control signal is less than the fourth reference voltage, and the low voltage level of the P-type transistor control signal is equal to the ground voltage.

[0012] As a possible implementation, the intermediate level generating circuit includes: a first voltage divider circuit, used to generate a fifth reference voltage and a sixth reference voltage based on the first reference voltage and the ground voltage; a second voltage divider circuit, used to generate the fourth reference voltage based on the fifth reference voltage, the first reference voltage and the ground voltage; and a third voltage divider circuit, used to generate the third reference voltage based on the sixth reference voltage, the first reference voltage and the ground voltage.

[0013] As a possible implementation, the first voltage divider circuit includes: a first transistor, a gate and a drain of the first transistor are coupled; a second transistor, a gate and a drain of the second transistor are coupled; the first transistor and the second transistor are connected in series between the first reference voltage and the ground voltage, and the gate voltage of the first transistor is the fifth reference voltage, and the gate voltage of the second transistor is the sixth reference voltage.

[0014] As a possible implementation, the second voltage divider circuit includes: a third transistor, the gate of the third transistor is coupled to the fifth reference voltage; the third transistor is connected in series between the first reference voltage and the ground voltage, and the source voltage of the third transistor is the fourth reference voltage.

[0015] As a possible implementation, the third voltage divider circuit includes: a fourth transistor, a gate of the fourth transistor is coupled to the sixth reference voltage; the fourth transistor is connected in series between the first reference voltage and the ground voltage, and the drain voltage of the fourth transistor is the third reference voltage.

[0016] As a possible implementation, the first level shifter includes: a fifth transistor, a gate of the fifth transistor coupled to the P-type transistor control signal, and a source of the fifth transistor coupled to the ground voltage; a sixth transistor, a gate of the sixth transistor coupled to the inverted signal of the P-type transistor control signal, and a source of the sixth transistor coupled to the ground voltage; a seventh transistor, a gate of the seventh transistor coupled to the drain of the sixth transistor and used to output the preliminary level-shifted P-type transistor control signal, a source of the seventh transistor coupled to the fourth reference voltage, and a drain of the seventh transistor coupled to the drain of the fifth transistor; and an eighth transistor, a gate of the eighth transistor coupled to the drain of the fifth transistor, a source of the eighth transistor coupled to the fourth reference voltage, and a drain of the eighth transistor coupled to the drain of the sixth transistor.

[0017] In a second aspect, an embodiment of the present application provides a chip, comprising the circuit for high voltage described in the first aspect and any possible implementation manner thereof.

[0018] In a third aspect, an embodiment of the present application provides an electronic device, comprising the chip described in the second aspect.

[0019] The circuit for high voltage and the related chip and electronic device provided in the present application can enable the circuit to operate normally at a higher reference voltage, thereby saving the cost of redesign and use of high voltage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of an embodiment of a circuit for high voltage provided in an embodiment of the present application.

[0021] Figure 2 for Figure 1 A schematic diagram of an embodiment of an intermediate level generating circuit.

[0022] Figure 3 for Figure 1 Schematic diagram of an embodiment of a first level shifter. DETAILED DESCRIPTION

[0023] The following disclosure provides a variety of implementations or illustrations that can be used to implement different features of the present disclosure. The specific examples of components and configurations described below are used to simplify the present disclosure. As can be imagined, these descriptions are only examples and are not intended to limit the present disclosure. For example, in the description below, forming a first feature on or above a second feature may include certain embodiments in which the first feature and the second feature are directly in contact with each other; and may also include certain embodiments in which additional components are formed between the above-mentioned first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse component symbols and / or labels in multiple embodiments. This repetition is based on the purpose of simplicity and clarity, and does not itself represent the relationship between the different embodiments and / or configurations discussed.

[0024] Although the numerical ranges and parameters used to define the broader scope of the present application are approximate values, the relevant numerical values ​​in the specific embodiments have been presented as accurately as possible. However, any numerical value inherently inevitably contains standard deviations due to individual testing methods. Here, "about" generally refers to the actual value within plus or minus 10%, 5%, 1% or 0.5% of a specific value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean value, depending on the consideration of a person with ordinary knowledge in the technical field to which the present application belongs. It should be understood that, except for the experimental examples, or unless otherwise explicitly stated, all ranges, quantities, values ​​and percentages used herein (for example, to describe the amount of material used, the length of time, temperature, operating conditions, quantitative ratios and the like) are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the attached patent scope are all approximate values ​​and can be changed as needed. At least these numerical parameters should be understood as the number of significant digits indicated and the values ​​obtained by applying the general rounding method. Herein, numerical ranges are expressed from one endpoint to another endpoint or between two endpoints; unless otherwise stated, the numerical ranges described herein include the endpoints.

[0025] In portable consumer electronics, power supply usually comes from lithium batteries / dry batteries, among which lithium batteries are gradually becoming the mainstream power source. Generally speaking, the voltage output range of lithium batteries is 2.5V to 4.3V. Therefore, various types of chips need to work normally within the voltage range of 2.5V to 4.3V. In order to ensure chip performance, it is common practice to use a power converter to rectify 2.5V to 4.3V and output a stable DC level for other circuits in the chip. The power converter can be, for example, a DC / DC or a low-dropout linear regulator (LDO). However, with the development of semiconductor process technology, CMOS processes below 100nm have gradually become mainstream with 0.9 / 1.8 / 3.3V devices. Therefore, 5V devices are usually required in the power converter to withstand the high voltage of 4.3V, which increases the cost.

[0026] Figure 1A schematic diagram of an embodiment of a circuit 100 for high voltage provided in an embodiment of the present application. The circuit 100 operates between a first reference voltage Vr1 and a ground voltage GND. For example, the voltage value of the first reference voltage Vr1 is 4.3V supplied by a lithium battery. The circuit 100 includes a withstand voltage circuit 108. The withstand voltage circuit 108 includes a plurality of semiconductor devices, and the operating voltages that the withstand voltage circuits 108 can withstand are all lower than the first reference voltage Vr1, for example, 3.3V. The purpose of the present application is to allow the withstand voltage circuit 108 to operate normally under the first reference voltage Vr1 without being damaged by controlling the signal level shifting circuit 101. In other words, the withstand voltage circuit 108 originally designed for a 3.3V reference voltage can be operated under a 4.3V reference voltage by combining with the control signal level shifting circuit 101, thereby eliminating the cost of redesigning and using high-voltage devices.

[0027] For ease of explanation, Figure 1 Only the P-type transistor 1082 and the N-type transistor 1084 are shown as examples, but in fact, the practice of this embodiment can be extended to all semiconductor devices in the withstand voltage circuit 108. The withstand voltage limit of the P-type transistor 1082 and the N-type transistor 1084 is lower than the first reference voltage Vr1. For example, the gate-source operating driving voltage of the P-type transistor 1082 and the N-type transistor 1084 is 3.3V, which is less than 4.3V of the first reference voltage Vr1.

[0028] In some embodiments, the withstand voltage circuit 108 may be a power converter, which is used to convert the first reference voltage Vr1 into a second reference voltage Vr2 which is lower than the first reference voltage Vr1. For example, the voltage value of the first reference voltage Vr1 is 4.3V supplied by a lithium battery, and the voltage value of the second reference voltage Vr1 is 3.3V which is commonly used in today's CMOS process. It should be noted that the withstand voltage circuit 108 is not limited to a power converter. In some embodiments, the withstand voltage circuit 108 may be other functional circuits other than a power converter.

[0029] The control signal level shift circuit 101 is used to adjust the gate control signals supplied to the P-type transistor 1082 and the N-type transistor 1084 to prevent the gate-source voltage difference of the P-type transistor 1082 and the N-type transistor 1084 from exceeding the tolerable limit. Figure 1As shown, the control signal level shifting circuit 101 generates a level-shifted P-type transistor control signal S1″ according to the P-type transistor control signal S1, and generates a level-shifted N-type transistor control signal S2′ according to the N-type transistor control signal S2, wherein the level-shifted P-type transistor control signal S1″ is coupled to the gate of the P-type transistor 1082, and the level-shifted N-type transistor control signal S2′ is coupled to the gate of the N-type transistor 1084. In this embodiment, the voltage levels of the P-type transistor control signal S1 and the N-type transistor control signal S2 operate in the same range.

[0030] The control signal level shift circuit 101 includes a first level shift circuit 104 and a second level shift circuit 106. The first level shift circuit 104 is used to perform level shift on the P-type transistor control signal S1. Specifically, the first level shift circuit 104 converts the high voltage level and the low voltage level of the P-type transistor control signal S1 into the first reference voltage Vr1 and the third reference voltage Vr3 respectively to generate a level-shifted P-type transistor control signal S1". The principle of the conversion is to transfer the high voltage level of the level-shifted P-type transistor control signal S1" to be as high as the first reference voltage Vr1, and the low voltage level of the level-shifted P-type transistor control signal S1" is shifted to the high voltage level minus the gate-source working driving voltage of the P-type transistor 1082. For example, the original voltage level of the P-type transistor control signal S1 operates at 0V to 0.9V, the first reference voltage Vr1 is 4.3V, and the gate-source working driving voltage of the P-type transistor 1082 is 3.3V. Therefore, the voltage level of the level-shifted P-type transistor control signal S1" after the control signal level shift circuit 101 is operated at 1V to 4.3V.

[0031] In the present embodiment, converting the P-type transistor control signal S1 into the level-shifted P-type transistor control signal S1" requires two conversions. Specifically, the first level shift circuit 104 includes a first level shifter 1042 and a second level shifter 1044. The first level shifter 1042 converts the P-type transistor control signal S1 into a preliminary level-shifted P-type transistor control signal S1', wherein the voltage level of the preliminary level-shifted P-type transistor control signal S1' operates between the fourth reference voltage Vr4 and the ground voltage GND. The second level shifter 1044 converts the high voltage level and the low voltage level of the preliminary level-shifted P-type transistor control signal S1' from the fourth reference voltage Vr4 and the ground voltage GND to the first reference voltage Vr1 and the third reference voltage Vr3 to generate the level-shifted P-type transistor control signal S1". For example, the P-type transistor control signal S1 of 0V to 0.9V is first converted into a preliminary level-shifted P-type transistor control signal S1' of 0V to 3.3V, and then converted into a level-shifted P-type transistor control signal S1" of 1V to 4.3V.

[0032] It should be noted that the third reference voltage Vr3 and the fourth reference voltage Vr4 are generated by the intermediate level generating circuit 102 according to the first reference voltage Vr1 , and the details thereof are described below.

[0033] The second level shift circuit 106 is used to perform level shifting on the N-type transistor control signal S2. Specifically, the second level shift circuit 106 converts the high voltage level and the low voltage level of the N-type transistor control signal S2 into the fourth reference voltage Vr4 and the ground voltage GND respectively to generate the level-shifted N-type transistor control signal S2'. The principle of the conversion is that the low voltage level of the level-shifted N-type transistor control signal S2' is shifted to be as high as the ground voltage GND, and the high voltage level of the level-shifted N-type transistor control signal S2' is shifted to the low voltage level plus the gate-source working driving voltage of the N-type transistor 1084. For example, the original voltage level of the N-type transistor control signal S2 operates at 0V to 0.9V, and the gate-source working driving voltage of the N-type transistor 1084 is 3.3V. Therefore, the voltage level of the level-shifted P-type transistor control signal S2' after the control signal level shift circuit 101 is operated at 0V to 3.3V.

[0034] In this embodiment, the conversion of the N-type transistor control signal S2 into the level-shifted N-type transistor control signal S2' only needs one conversion. Specifically, the first level shift circuit 104 includes a third level shifter 1062. The third level shifter 1062 converts the N-type transistor control signal S2 into the level-shifted N-type transistor control signal S2', wherein the voltage level of the level-shifted N-type transistor control signal S2' operates between the fourth reference voltage Vr4 and the ground voltage GND. For example, the 0V-0.9V N-type transistor control signal S2 is converted into the level-shifted N-type transistor control signal S2' of 0V-3.3V.

[0035] The intermediate level generating circuit 102 generates a third reference voltage Vr3 and a fourth reference voltage Vr4 according to the first reference voltage Vr1 . Figure 2 for Figure 1 A schematic diagram of an embodiment of an intermediate level generating circuit. Figure 2 In the embodiment, the intermediate level generating circuit 102 includes a first voltage dividing circuit 202, a second voltage dividing circuit 204 and a third voltage dividing circuit 206. The first voltage dividing circuit 202 includes a plurality of transistors and a current source 2022 connected in series between a first reference voltage Vr1 and a ground voltage GND. Figure 2 Only transistors 2024 and 2026 are shown in the figure for example. The gates and drains of the multiple transistors in the first voltage divider circuit 202 are coupled to each other. Therefore, by using the principle that the gate-source working driving voltage of each transistor remains fixed when it is turned on, the voltage divider effect can be generated by adjusting the number of multiple transistors, the channel length (L) and the width (W). Figure 2 In the embodiment, the gate voltage of the transistor 2024 is used as the fifth reference voltage Vr5; the gate voltage of the transistor 2026 is used as the sixth reference voltage Vr6.

[0036] The second voltage divider circuit 204 and the third voltage divider circuit 206 also apply similar principles. The second voltage divider circuit 204 includes a transistor 2044 and a current source 2042 connected in series between the first reference voltage Vr1 and the ground voltage GND, the gate and the drain of the transistor 2044 are coupled and coupled to the fifth reference voltage Vr5; the source voltage of the transistor 2044 is used as the fourth reference voltage Vr4. The third voltage divider circuit 206 includes a transistor 2064 and a current source 2062 connected in series between the first reference voltage Vr1 and the ground voltage GND, the gate and the drain of the transistor 2064 are coupled and coupled to the sixth reference voltage Vr6; the drain voltage of the transistor 2064 is used as the third reference voltage Vr3.

[0037] Figure 3, the structure of the first level shifter 1042 is exemplarily illustrated, wherein the gate of the transistor 302 is coupled to the P-type transistor control signal S1. The P-type transistor control signal S1 enters the gate of the transistor 304 after passing through the inverter 310. The sources of the transistors 302 and 304 are both coupled to the ground voltage GND. The gate of the transistor 306 is coupled to the drain of the transistor 304 and is used to output the P-type transistor control signal S1' after the preliminary level shift, and the drain of the transistor 306 is coupled to the drain of the transistor 302. The gate of the transistor 308 is coupled to the drain of the transistor 302, and the drain of the transistor 308 is coupled to the drain of the transistor 304. The sources of the transistors 306 and 308 are both coupled to the fourth reference voltage Vr4.

[0038] The architecture of the second level shifter 1044 and the third level shifter 1062 is similar to that of the first level shifter 1042, and the difference lies only in the input signal and the reference voltage. Specifically, the second level shifter 1044 operates between the first reference voltage Vr1 and the third reference voltage Vr3, and the input signal is the P-type transistor control signal S1' after the preliminary level shift. The third level shifter 1062 operates between the fourth reference voltage Vr4 and the ground voltage GND, and the input signal is the N-type transistor control signal S2.

[0039] The present application also proposes a chip, including circuit 100. The present application also proposes an electronic device including the chip. Specifically, the electronic device includes but is not limited to mobile communication devices, ultra-mobile personal computer devices, portable entertainment devices and other electronic devices with data interaction functions. The mobile communication device is characterized by having mobile communication functions and providing voice and data communications as the main goal. Such terminals include: smart phones (such as iPhone), multimedia phones, functional phones, and low-end phones. Ultra-mobile personal computer devices belong to the category of personal computers, have computing and processing functions, and generally also have mobile Internet access features. Such terminals include: PDA, MID and UMPC devices, such as iPad. Portable entertainment devices can display and play multimedia content. Such devices include: audio and video players (such as iPod), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.

[0040] The above description briefly presents the features of certain embodiments of the present application, so that those with ordinary knowledge in the technical field to which the present application belongs can more fully understand the various aspects of the present disclosure. Those with ordinary knowledge in the technical field to which the present application belongs should understand that they can easily use the present disclosure as a basis to design or change other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present application belongs should understand that these equal embodiments still belong to the spirit and scope of the present disclosure, and they can be variously changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A circuit for high voltage, characterized in that include: A withstand voltage circuit, operating between a first reference voltage and a ground voltage, wherein the withstand voltage circuit comprises a P-type transistor and an N-type transistor, a gate-source operating driving voltage of the P-type transistor and the N-type transistor is less than the first reference voltage, a source of the P-type transistor is coupled to the first reference voltage, and a source of the N-type transistor is coupled to the ground voltage; as well as A control signal level shifting circuit is used to generate a level-shifted P-type transistor control signal according to a P-type transistor control signal, and to generate a level-shifted N-type transistor control signal according to an N-type transistor control signal, wherein the level-shifted P-type transistor control signal is coupled to the gate of the P-type transistor, and the level-shifted N-type transistor control signal is coupled to the gate of the N-type transistor, and the control signal level shifting circuit comprises: an intermediate level generating circuit, used for generating a third reference voltage and a fourth reference voltage according to the first reference voltage, wherein the first reference voltage is higher than the fourth reference voltage, and the fourth reference voltage is higher than the third reference voltage; a first level shift circuit, configured to convert a high voltage level and a low voltage level of the P-type transistor control signal to the first reference voltage and the third reference voltage to generate the level-shifted P-type transistor control signal; and The second level shift circuit is used for converting the high voltage level and the low voltage level of the N-type transistor control signal to the fourth reference voltage and the ground voltage to generate the level-shifted N-type transistor control signal.

2. A circuit for high voltage as claimed in claim 1, characterized in that The first level shift circuit comprises: a first level shifter, configured to convert the high voltage level and the low voltage level of the P-type transistor control signal to the fourth reference voltage and the ground voltage to generate a preliminary level-shifted P-type transistor control signal; and The second level shifter is used to convert the high voltage level and the low voltage level of the P-type transistor control signal after the preliminary level shift from the fourth reference voltage and the ground voltage to the first reference voltage and the third reference voltage to generate the P-type transistor control signal after the level shift.

3. A circuit for high voltage as claimed in claim 2, characterized in that The second level shift circuit comprises: The third level shifter is used to convert the high voltage level and the low voltage level of the N-type transistor control signal to the fourth reference voltage and the ground voltage to generate the level-shifted N-type transistor control signal.

4. The circuit for high voltage according to claim 1, characterized in that The withstand voltage circuit includes a power converter for converting the first reference voltage into a second reference voltage, wherein the first reference voltage is higher than the second reference voltage.

5. The circuit for high voltage according to claim 1, characterized in that There is a specific voltage difference between the fourth reference voltage and the ground voltage, and the gate-source operating driving voltage of the P-type transistor and the N-type transistor is equal to the specific voltage difference.

6. The circuit for high voltage according to claim 1, characterized in that There is a specific voltage difference between the fourth reference voltage and the ground voltage, and a difference between the first reference voltage and the third reference voltage is equal to the specific voltage difference.

7. The circuit for high voltage according to claim 1, characterized in that The high voltage level of the P-type transistor control signal is equal to the high voltage level of the N-type transistor control signal, and the low voltage level of the P-type transistor control signal is equal to the low voltage level of the N-type transistor control signal.

8. A circuit for high voltage as claimed in claim 7, characterized in that The high voltage level of the N-type transistor control signal is less than the fourth reference voltage, and the low voltage level of the P-type transistor control signal is equal to the ground voltage.

9. The circuit for high voltage according to claim 1, characterized in that The intermediate level generating circuit comprises: A first voltage divider circuit, used for generating a fifth reference voltage and a sixth reference voltage according to the first reference voltage and the ground voltage; a second voltage divider circuit, configured to generate the fourth reference voltage according to the fifth reference voltage, the first reference voltage and the ground voltage; and The third voltage divider circuit is used for generating the third reference voltage according to the sixth reference voltage, the first reference voltage and the ground voltage.

10. The circuit for high voltage according to claim 9, characterized in that The first voltage divider circuit comprises: A first transistor, wherein a gate and a drain of the first transistor are coupled to each other; a second transistor, wherein a gate and a drain of the second transistor are coupled to each other; The first transistor and the second transistor are connected in series between the first reference voltage and the ground voltage, and a gate voltage of the first transistor is the fifth reference voltage, and a gate voltage of the second transistor is the sixth reference voltage.

11. The circuit for high voltage according to claim 9, characterized in that The second voltage divider circuit comprises: a third transistor, a gate of the third transistor being coupled to the fifth reference voltage; The third transistor is connected in series between the first reference voltage and the ground voltage, and a source voltage of the third transistor is the fourth reference voltage.

12. The circuit for high voltage according to claim 9, characterized in that The third voltage divider circuit comprises: a fourth transistor, a gate of the fourth transistor being coupled to the sixth reference voltage; The fourth transistor is connected in series between the first reference voltage and the ground voltage, and a drain voltage of the fourth transistor is the third reference voltage.

13. The circuit for high voltage according to claim 2, characterized in that The first level shifter comprises: a fifth transistor, wherein a gate of the fifth transistor is coupled to the P-type transistor control signal, and a source of the fifth transistor is coupled to the ground voltage; a sixth transistor, wherein a gate of the sixth transistor is coupled to an inverted signal of the P-type transistor control signal, and a source of the sixth transistor is coupled to the ground voltage; a seventh transistor, the gate of the seventh transistor being coupled to the drain of the sixth transistor and being used to output the preliminary level-shifted P-type transistor control signal, the A source of the seventh transistor is coupled to the fourth reference voltage, and a drain of the seventh transistor is coupled to the drain of the fifth transistor; and an eighth transistor, wherein a gate of the eighth transistor is coupled to the drain of the fifth transistor, a source of the eighth transistor is coupled to the fourth reference voltage, and a drain of the eighth transistor is coupled to the drain of the sixth transistor.

14. A chip, characterized in that: include: A circuit for high voltage as claimed in any one of claims 1 to 13.

15. An electronic device, characterized in that: include: The chip as claimed in claim 14.

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