Sensing node controller, memory device, and method of operating the memory device

Abstract

This disclosure relates to a sense node controller, a memory device, and a method of operating the memory device. The technology relates to electronic devices. A memory device for reducing noise generated during sensing operations includes: a plurality of pages, each of which includes a plurality of memory cells; peripheral circuitry configured to sense a selected page among the plurality of pages, the selected page including a selected memory cell; and a sense node controller configured to control a sense node in a page buffer connected to the selected memory cell via bit lines during a second sensing operation, based on the result of a first sensing operation performed among a plurality of sensing operations for sensing one of the plurality of logical pages among the selected page.

Description

Technical Field

[0001] One or more embodiments described herein relate to an electronic device, and more specifically, to a memory device and a method of operating the memory device. Background Technology

[0002] Storage devices store data under the control of a host device (e.g., a computer, smartphone, or tablet). Storage devices can store data in various types of memory devices. Examples include disks (e.g., hard disk drives (HDDs)), semiconductor memory (e.g., solid-state drives (SSDs)), memory cards, or other types of memory devices.

[0003] In some cases, a storage device may include a memory device for storing data and a memory controller for controlling the data storage within the memory device. Memory devices can be classified as volatile memory or non-volatile memory. Examples of non-volatile memory include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EPM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Summary of the Invention

[0004] Embodiments of this disclosure provide a memory device and a method of operating the same for reducing noise generated during sensing operations.

[0005] According to one embodiment of this disclosure, a memory device may include: a plurality of pages, each of the plurality of pages including a plurality of memory cells; peripheral circuitry configured to sense a selected page among the plurality of pages, the selected page including a selected memory cell; and a sensing node controller configured to control a sensing node in a page buffer connected to the selected memory cell via bit lines during a second sensing operation of a plurality of sensing operations performed for sensing one of the plurality of logical pages among the selected page, based on the result of a first sensing operation of the plurality of sensing operations performed for sensing one of the logical pages among the plurality of sensing operations.

[0006] According to one embodiment of the present disclosure, a method for operating a memory device (the memory device being configured to sense a selected page including a selected memory cell among a plurality of pages each including a plurality of memory cells) may include the steps of: performing a first sensing operation to sense one of a plurality of logical pages among the selected page; and, based on the result of the first sensing operation, controlling a sensing node in a page buffer connected to the selected memory cell via bit lines during a second sensing operation for sensing the logical page.

[0007] According to one embodiment of the present disclosure, a method for operating a memory device (the memory device being configured to sense a selected page, which includes a selected memory cell, among a plurality of pages, each comprising a plurality of memory cells) may include the steps of: controlling a sensing node in a page buffer connected to the selected memory cell via bit lines during the last sensing operation, based on sensing data obtained by performing one or more sensing operations performed among a plurality of sensing operations for sensing one of the plurality of logical pages prior to the last sensing operation.

[0008] According to one embodiment of the present disclosure, an apparatus may include: an output terminal coupled to a sensing node of a page buffer; and a controller configured to generate a masking value to be transmitted to the sensing node via the output terminal based on the result of a first sensing operation that is different from a second sensing operation, wherein the second sensing operation is performed after the first sensing operation and during the time when the sensing node is coupled to a selected memory cell.

[0009] According to this technology, the number of latches flipped in the page buffer can be reduced by masking the sensing node values ​​based on the sensed data before performing the final sensing operation, thereby reducing the occurrence of noise. Attached Figure Description

[0010] Figure 1 An embodiment of the storage device is shown.

[0011] Figure 2 An embodiment of the memory device is shown.

[0012] Figure 3 An implementation of a memory cell array is shown.

[0013] Figure 4 An implementation of the page buffer is shown.

[0014] Figures 5A to 5C An implementation of a method for sensing multiple logical pages contained in a single page is shown.

[0015] Figure 6 An implementation of a method for sensing the least significant bit (LSB) page is shown.

[0016] Figure 7 Example values ​​for sensing nodes are shown when sensing LSB pages.

[0017] Figure 8 An example configuration of a memory device for masking sensing nodes is shown.

[0018] Figure 9 An implementation of a method for masking and sensing data sensed during an evaluation operation is shown.

[0019] Figure 10 An implementation of a method for sensing the middle valid bit (CSB) page is shown.

[0020] Figure 11 An implementation of using masking to sense CSB pages is shown.

[0021] Figure 12 An implementation of using masking to sense CSB pages is shown.

[0022] Figure 13 An embodiment of the operational memory device is shown.

[0023] Figure 14 An embodiment of the operational memory device is shown.

[0024] Figure 15 An implementation of the memory controller is shown.

[0025] Figure 16 An implementation of the memory card is shown.

[0026] Figure 17 An implementation of a solid-state drive (SSD) system is shown.

[0027] Figure 18 An implementation of the user system is shown. Detailed Implementation

[0028] The specific structural or functional descriptions of the embodiments disclosed in this specification or application are for describing embodiments according to this disclosure only. Embodiments according to this disclosure can be implemented in various forms, and the descriptions are not limited to those described in this specification or application.

[0029] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement the technical spirit of the present disclosure.

[0030] Figure 1 This is a block diagram illustrating an embodiment of storage device 50, which may include memory device 100 and memory controller 200. Storage device 50 can store data under the control of host 300. Examples of host 300 include cellular phones, smartphones, MP3 players, laptops, desktop computers, game consoles, televisions, tablet PCs, or in-vehicle infotainment systems.

[0031] Storage device 50 may be of a type compatible with the communication standards or protocols of the host interface of host 300. Examples of storage devices 50 include SSDs, multimedia cards (in the form of MMC, eMMC, RS-MMC, and micro-MMC), secure digital cards (in the form of SD, mini-SD, and micro-SD), universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, PCI Express (PCI-E) card-type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0032] Storage devices 50 can be manufactured using various types of packages. Examples include point-of-purchase (POP), system-in-package (SIP), system-on-a-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0033] Memory device 100 can store data and operate in response to control by memory controller 200. Memory device 100 may include one or more memory cell arrays, each memory cell array including multiple memory cells for storing data. Memory cell arrays may include multiple memory blocks, each memory block including multiple memory cells. Multiple memory cells may be configured as one or more pages. In one embodiment, a page may be a unit for storing data in memory device 100 or retrieving data stored in memory device 100. A memory block may be a unit for erasing data.

[0034] The memory device 100 may be, for example, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Transfer Torque Random Access Memory (STT-RAM), etc. For ease of description, it may be assumed that the memory device 100 is NAND flash memory.

[0035] The memory device 100 can be implemented as a two-dimensional array structure or a three-dimensional array structure. Hereinafter, a three-dimensional array structure is described as an embodiment, but this disclosure is not limited to a three-dimensional array structure. Furthermore, the embodiment can be applied not only to flash memory devices (where the charge storage layer is configured by a conductive floating gate (FG)) but also to charge trapping flash memory (CTF) where the charge storage layer is configured by an insulating film.

[0036] In one embodiment, the memory device 100 may operate according to a single-level cell (SLC) method, wherein one data bit is stored in a memory cell. In another embodiment, the memory device 100 may operate according to a method that stores at least two data bits in a memory cell. For example, the memory device 100 may operate according to a multi-level cell (MLC) method that stores two data bits in a memory cell, a three-level cell (TLC) method that stores three data bits in a memory cell, or a four-level cell (QLC) method that stores four data bits in a memory cell.

[0037] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access regions selected by corresponding addresses in one or more memory cell arrays. For example, memory device 100 can perform operations corresponding to commands on the regions selected by addresses. Examples of operations performed by memory device 100 include write operations (programming operations), read operations, or erase operations based on received commands. When a programming command is received, memory device 100 can program data into the regions selected by addresses. When a read command is received, memory device 100 can read data from the regions selected by addresses. When an erase command is received, memory device 100 can erase data stored in the regions selected by addresses.

[0038] In one embodiment, the memory device 100 may include a sensing data storage unit 150, which may store data sensed from the memory cell array during a sensing operation. The sensing operation may be, for example, a read operation or a verification operation included in a programming loop and a verification operation.

[0039] For example, during a sensing operation on a selected page (including multiple pages in a memory cell array), sensing operations can be performed on multiple logical pages within the selected page. Furthermore, during a sensing operation on any one of the multiple logical pages, the sensing operation can be performed using a first (e.g., high) level sensing voltage, and then a second (e.g., low) level sensing voltage. In another embodiment, depending on, for example, the conductivity of the transistor used and / or other design requirements, the first level can be low and the second level can be high.

[0040] When a sensing operation is performed using a high-level sensing voltage and then a low-level sensing voltage, the number of latch flips in the page buffer may increase.

[0041] Therefore, according to one or more embodiments, a method is provided to mask a sensing node during a second sensing operation based on sensing data obtained during a first sensing operation. Data can then be sensed based on the result of the masking.

[0042] In one embodiment, the memory device 100 may include a sensing node controller 170, which can mask sensing nodes based on sensing data stored in the sensing data storage unit 150. For example, assuming the selected page is configured with three logical pages and the sensing operation is a read operation, two read operations can be performed during a read operation on the least significant bit (LSB) page: first, a first read operation can be performed using a high-level first read voltage, and then a second read operation can be performed using a low-level second read voltage.

[0043] In one implementation, the sensing node controller 170 may mask the sensing node during a second read operation based on the result of performing the first read operation. For example, since the first read voltage may be greater than the second read voltage, the number of latches toggled during the second read operation may increase. Therefore, the sensing node controller 170 may mask the sensing node to indicate the latches toggled during the first read operation.

[0044] When a sensing node is masked, the memory device 100 can store data in a latch based on the sensing node. For example, when the value of the sensing node is "1", the default value of the latch can be maintained. When the value of the sensing node is "0", the default value of the latch can be changed, and the changed value can be stored in the latch.

[0045] As a result, by masking the sensing node during the next read operation based on data read using a high read voltage, the number of latches that are flipped can be reduced. Since the number of flipped latches is reduced, noise in the sensing operation can be decreased.

[0046] The memory controller 200 can control the overall operation of the storage device 50. When a power supply voltage is applied to the storage device 50, the memory controller 200 can execute firmware. When the storage device 100 is a flash memory device 100, the memory controller 200 can operate the firmware (e.g., flash translation layer (FTL)) to control the communication between the host 300 and the storage device 100.

[0047] In one embodiment, the memory controller 200 may include firmware that can receive data and logical block addresses (LBAs) from the host 300 and can translate LBAs into physical block addresses (PBAs), whereby the PBAs indicate the addresses of memory cells in the memory device 100 where data will be stored. Furthermore, the memory controller 200 may store a logical-physical address mapping table configuring the mapping between LBAs and PBAs in a buffer memory.

[0048] The memory controller 200 can control the memory device 100 to perform programming, reading, erasing, or other operations according to requests from the host 300. For example, when receiving a programming request from the host 300, the memory controller 200 can convert the programming request into a programming command and provide the memory device 100 with the programming command, PBA, and data. When receiving a read request along with an LBA from the host 300, the memory controller 200 can change the read request into a read command, select the PBA corresponding to the LBA, and then provide the read command and PBA to the memory device 100. When receiving an erase request along with an LBA from the host 300, the memory controller 200 can change the erase request into an erase command, select the PBA corresponding to the LBA, and then provide the erase command and PBA to the memory device 100.

[0049] In one implementation, the memory controller 200 can generate and send programming commands, addresses, and data to the memory device 100 without a request from the host 300. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform one or more background operations, such as a programming operation for wear leveling, a programming operation for garbage collection, or another operation.

[0050] In one embodiment, the storage device 50 may further include a buffer memory. In operation, the memory controller 200 can control data exchange between the host 300 and the buffer memory. In one embodiment, the memory controller 200 may temporarily store system data for controlling the storage device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data input from the host 300 in the buffer memory, and then send the temporarily stored data to the storage device 100.

[0051] In one embodiment, the buffer memory can be used as operational memory and / or cache memory of the memory controller 200, and can store code or commands executed by the memory controller 200. In one embodiment, the buffer memory can store data processed by the memory controller 200. Examples of buffer memories include, for example, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR4 SDRAM, Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (DRAM), or Static Random Access Memory (SRAM).

[0052] In various implementations, the buffer memory can be externally connected to the storage device 50. For example, a volatile memory device externally connected to the storage device 50 can be used as the buffer memory.

[0053] In one embodiment, the memory controller 200 can control two or more memory devices. In this case, the memory controller 200 can control the memory devices according to, for example, an interleaving method to improve operational performance.

[0054] The host 300 can communicate with the storage device 50 using at least one communication protocol or standard. Examples include Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Away DIMM (LRDIMM).

[0055] Figure 2 It is shown Figure 1 A diagram illustrating an embodiment of the memory device 100. (Refer to...) Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0056] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz connected to row decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz can be connected to page buffer group 123 via bit lines BL1 to BLn. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. As one implementation, the multiple memory cells are non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block can include multiple pages.

[0057] A row line RL can include at least one source select line, multiple word lines, and at least one drain select line.

[0058] Each memory cell in the memory cell array 110 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0059] Peripheral circuitry 120 can be configured to perform programming, reading, or erasing operations on selected regions of memory cell array 110 under the control of control logic 130. Peripheral circuitry 120 can drive memory cell array 110. For example, peripheral circuitry 120 can apply various operating voltages to or release applied voltages to row lines RL and bit lines BL1 to BLn under the control of control logic 130.

[0060] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126. The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. In one embodiment, the word lines may include normal word lines and dummy word lines. In one embodiment, the row lines RL may also include pipe select lines.

[0061] Row decoder 121 is configured to decode the row address RADD received from control logic 130. Row decoder 121 selects at least one memory block from memory blocks BLK1 to BLKz based on the decoded address. Furthermore, row decoder 121 can select at least one word line of the selected memory block based on the decoded address to apply a voltage generated by voltage generator 122 to the at least one word line WL.

[0062] For example, during a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and apply a programming pass voltage with a level lower than the programming voltage to the unselected word line. During a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and apply a verification pass voltage with a level higher than the verification voltage to the unselected word line. During a reading operation, the line decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage with a level higher than the read voltage to the unselected word line.

[0063] In one embodiment, the erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the row decoder 121 can select a memory block based on the decoded address. During the erase operation, the row decoder 121 can apply a reference (e.g., ground) voltage to the word line connected to the selected memory block.

[0064] Voltage generator 122 operates in response to control of control logic 130. Voltage generator 122 can be configured to generate multiple voltages using an external power supply voltage provided to memory device 100. For example, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, and / or one or more other voltages in response to control of control logic 130.

[0065] In one implementation, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operating voltage of the memory device 100.

[0066] In one implementation, voltage generator 122 can generate multiple voltages using an external power supply voltage or an internal power supply voltage. For example, voltage generator 122 may include multiple pumping capacitors that receive an internal power supply voltage, and the multiple pumping capacitors may be selectively activated in response to control of control logic 130 to generate multiple voltages. The generated multiple voltages may be provided to memory cell array 110 by row decoder 121.

[0067] Page buffer group 123 includes first page buffers PB1 to n page buffers PBn, respectively connected to the memory cell array 110 via first bit line BL1 to n bit line BLn. The first page buffers PB1 to n page buffers PBn operate in response to control logic 130. For example, the first page buffers PB1 to n page buffers PBn may operate in response to the page buffer control signal PBSIGNALS. In one embodiment, the first page buffers PB1 to n page buffers PBn may temporarily store data received via first bit line BL1 to n bit line BLn, or the voltage or current of bit lines BL1 to BLn may be sensed during read or verification operations.

[0068] During programming operations, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the nth page buffer PBn can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first bit line BL1 to the nth bit line BLn. The memory cell of the selected page is programmed based on the transmitted data DATA. During programming verification operations, the first page buffer PB1 to the nth page buffer PBn can read page data by sensing the voltage or current from the selected memory cell via the first bit line BL1 to the nth bit line BLn.

[0069] During the read operation, the first page buffer PB1 to the nth page buffer PBn read data DATA from the memory cell of the selected page through the first bit line BL1 to the nth bit line BLn, and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0070] During the erase operation, the first page buffer PB1 to the nth page buffer PBn can be floated or an erase voltage can be applied.

[0071] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the first page buffer PB1 to the nth page buffer PBn via the data line DL, or it can exchange data with the input / output circuitry 125 via the column line CL.

[0072] Input / output circuit 125 can output from Figure 1 The memory controller 200 receives the command CMD and the address ADDR (e.g., as shown in reference). Figure 1 The data can be transmitted to control logic 130, or exchanged with column decoder 124.

[0073] The sensing circuit 126 can generate a reference current in response to the enable bit signal VRYBIT during a read operation or a verification operation, and can compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current to output a pass signal PASS or a failure signal FAIL.

[0074] Control logic 130 can output operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, and enable bit signal VRYBIT in response to commands CMD and address ADDR to control peripheral circuitry 120. For example, control logic 130 can control a read operation on a selected memory block in response to a sub-block read command and address. Control logic 130 can control an erase operation on a selected sub-block included in a selected memory block in response to a sub-block erase command and address. Control logic 130 can determine whether a verification operation passes or fails via signals PASS or FAIL.

[0075] In one embodiment, control logic 130 may include a sense data storage unit 150 and a sense node controller 170. In another embodiment, the sense data storage unit 150 and the sense node controller 170 may be included outside of control logic 130. For example, the sense data storage unit 150 and the sense node controller 170 may be located in each page buffer of page buffer group 123.

[0076] In one embodiment, when the memory device 100 performs a sensing operation on a selected page, the sensing data storage unit 150 can store sensing data, and the sensing node controller 170 can perform masking on the sensing node. For example, during a sensing operation on any of a plurality of logical pages in the selected page, the memory device 100 can perform the sensing operation using a high-level sensing voltage, and then can perform the sensing operation using a low-level sensing voltage. At this time, during the sensing operation using a low-level sensing voltage, a large number of latches in the page buffer may toggle.

[0077] Therefore, the sensing data storage unit 150 can store data sensed using a high-level sensing voltage. Subsequently, the sensing node controller 170 can mask the sensing node based on the sensing data stored in the sensing data storage unit 150. For example, the sensing node controller 170 can perform a masking operation that instructs a latch to be toggled when sensing is performed using a high-level sensing voltage.

[0078] When a sensing node is masked, the memory device 100 can store data in a latch based on the sensing node. For example, when the value of the sensing node is "1", the default value of the latch can be maintained. When the value of the sensing node is "0", the default value of the latch can be changed, and the changed value can be stored in the latch. As a result, by masking the sensing node during the next read operation based on data read using a high read voltage, the number of latches that are toggled can be reduced. Since the number of latches that are toggled is reduced, noise in the sensing operation can be reduced.

[0079] Figure 3 It is shown Figure 2 A diagram illustrating an implementation of a memory cell array. Specifically, Figure 3 It shows that can represent Figure 2 The circuit diagram of memory block BLKa of any one of the multiple memory blocks BLK1 to BLKz in the memory cell array 110.

[0080] Reference Figure 3 A first select line, a word line, and a second select line arranged in parallel to each other can be connected to a memory block BLKa. For example, the word line can be arranged in parallel to each other between the first select line and the second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL).

[0081] In one implementation, the memory block BLKa may include multiple strings connected between bit lines BL1 to BLn and source lines SL. Bit lines BL1 to BLn may be connected to each string individually, and source lines SL may be connected to each string collectively. Since the strings may be configured identically to each other, the string ST connected to the first bit line BL1 will be described as an example.

[0082] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells F1 to F16, and a drain selection transistor DST. A string ST may include one or more source selection transistors SST and one or more drain selection transistors DST, and may include memory cells F1 to F16. The number of memory cells may vary between implementations.

[0083] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST, which is included in different strings, can be connected to the source select line SSL. The gate of the drain select transistor DST can be connected to the drain select line DSL. The gates of memory cells F1 to F16 can be connected to multiple word lines WL1 to WL16. A group of memory cells (including memory cells in different strings) connected to the same word line can be referred to as a physical page PPG. Therefore, the memory block BLKa can include the number of physical pages PPGs of word lines WL1 to WL16.

[0084] A memory cell can store one bit of data and is therefore referred to as a single-level cell (SLC). In this case, a physical page (PPG) can store one logical page (LPG) of data. The number of data bits included in a logical page (LPG) can be equal to the number of memory cells in a physical page (PPG). In one implementation, a memory cell can store two or more bits of data and is therefore referred to as a multi-level cell (MLC). In this case, a physical page (PPG) can store two or more logical pages (LPGs) of data.

[0085] A memory cell that stores two or more bits of data in a single memory cell is called an MLC. As the number of bits of data stored in a single memory cell increases, MLC can refer to a memory cell that stores two bits of data. A memory cell that stores three bits of data can be called a three-level cell (TLC). A memory cell that stores four bits of data can be called a four-level cell (QLC). This embodiment can be applied to a memory device 100 that stores two or more bits of data in a single memory cell.

[0086] In one embodiment, the memory block may have a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions.

[0087] Figure 4 This is a circuit diagram showing a page buffer PB1 according to one embodiment. (Refer to...) Figure 2 and Figure 4 Page buffer PB1 can represent multiple page buffers PB1 to PBn that can be configured similarly to each other.

[0088] Page buffer PB1 can respond, for example, from Figure 2 The control logic 130 operates based on the output signals. Figure 2The signals output by the control logic 130 may include one or more of the following signals: SELBL, PB_SENSE, TRANO, BL_DIS, SA_PRECH_N, SA_CSOC, SA_STB_N, SA_DISCH, PRECHSO_N, TRANT, TRST, TSET, TRANM, MRST, MSET, TRANTOF, TRANF, TRANS, SRST, SSET, and TRANPB.

[0089] Page buffer PB1 may include bit line connector 510, bit line discharger 520, page buffer sensor 530, sensing node connector 540, sensing node precharger 550, cache latch assembly 560, main latch assembly 570, dynamic latch assembly 580, latch detector 590, current controller 610, latch circuit 620, and discharger 630.

[0090] Bit line connector 510 can be connected between the first bit line BL1 and the bit line connection node BLCM, and may include an NMOS transistor N1 that operates in response to the bit line select signal SELBL. The NMOS transistor N1 can be turned on or off in response to the bit line select signal SELBL.

[0091] Bit line discharger 520 can be connected between the ground terminal and the bit line connection node BLCM, and may include an NMOS transistor N2 that operates in response to the bit line discharge signal BL_DIS. The NMOS transistor N2 can be turned on or off in response to the bit line discharge signal BL_DIS. Bit line discharger 520 can discharge the first bit line BL1.

[0092] Page buffer sensor 530 can be connected between bit line connection node BLCM and current sensing node CSO, and may include NMOS transistor N3 that operates in response to page buffer sensing signal PB_SENSE. NMOS transistor N3 can be turned on or off in response to page buffer sensing signal PB_SENSE.

[0093] According to this embodiment, during the verification operation (including operations within the programming loop), the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted according to the programming order of the selected page among multiple pages. For example, as the programming order of the selected page is later, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted to be higher.

[0094] Furthermore, during a read operation, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted according to the position of the selected page among multiple pages. For example, as the selected page is closer to the drain select transistor, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted to be lower, and as the selected page is closer to the source select transistor, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted to be higher.

[0095] Furthermore, the activation period of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted during programming verification or read operations. For example, during programming verification, the activation period of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted according to the programming order of the selected pages. For instance, during programming verification, the activation period of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be increased as the programming order of the selected pages becomes later.

[0096] Furthermore, during a read operation, the activation period of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted based on the location of the selected page. For example, during a read operation, as the selected page becomes closer to the drain select transistor among multiple pages, the activation period of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be reduced.

[0097] Furthermore, during the bit line precharge operation in the programming verification operation, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted according to the programming order of the selected pages. Additionally, during the bit line precharge operation in the programming verification operation, the activation period of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted.

[0098] For example, during the bit line precharge operation in the programming verification operation, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted to be higher as the programming order of the selected page is later. Furthermore, the activation period of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be increased as the programming order of the selected page is later. In this case, the potential level can be adjusted together with the activation period.

[0099] Furthermore, during the bit line precharge operation in the read operation, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted according to the position of the selected page. Additionally, during the bit line precharge operation in the read operation, the activation period of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted. For example, as the selected page is closer to the drain select transistor, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted to be lower, and as the selected page is closer to the source select transistor, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted to be higher. Furthermore, as the selected page is closer to the drain select transistor among multiple pages, the activation period of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be reduced. In this case, the potential level and the activation period can be adjusted together.

[0100] Furthermore, during programming verification or read operations, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted according to the temperature of the memory cell array 110. For example, during programming verification or read operations, the potential level of the page buffer sensing signal PB_SENSE applied to the NMOS transistor N3 can be adjusted to be higher as the temperature of the memory cell array 110 decreases, and lower as the temperature of the memory cell array 110 increases.

[0101] The sensing node connector 540 can be connected between the current sensing node CSO and the sensing node SO, and may include an NMOS transistor N4 that operates in response to the node connection signal TRANSO. The NMOS transistor N4 can be turned on or off in response to the node connection signal TRANSO.

[0102] The sensing node precharger 550 can be connected between the core voltage VCORE terminal and the sensing node SO, and may include a PMOS transistor P1 that operates in response to the precharge signal PRECHSO_N. The PMOS transistor P1 can be turned on or off in response to the precharge signal PRECHSO_N. When the PMOS transistor P1 is turned on in response to the precharge signal PRECHSO_N, the core voltage VCORE is provided to the sensing node SO.

[0103] The cache latch assembly 560 may include NMOS transistors N5, N6, N9, and N10, a cache latch LATT, and a cache latch reset / set assembly RSET. The cache latch assembly 560 may temporarily store programming data.

[0104] NMOS transistor N5 can be connected between sensing node SO and NMOS transistor N6, and can be turned on or off in response to the cache data transmission signal TRANT. NMOS transistor N6 is connected between NMOS transistor N5 and the ground terminal, and can be turned on or off in response to the potential level of the second cache node QT.

[0105] The cache latch LATT may include a first inverter I1 and a second inverter I2. The first inverter I1 and the second inverter I2 may be connected in parallel between a first cache node QT_N and a second cache node QT of the cache latch LATT. The input terminal of the first inverter I1 may be connected to the second cache node QT, and the output terminal may be connected to the first cache node QT_N. The input terminal of the second inverter I2 may be connected to the first cache node QT_N, and the output terminal may be connected to the second cache node QT.

[0106] The cache latch reset / set component RSET can be connected to the first cache node QT_N and the second cache node QT of the cache latch LATT, and can reset or set the cache latch LATT. For example, the cache latch reset / set component RSET may include NMOS transistors N7 and N8. NMOS transistor N7 can connect the second cache node QT and node COM1 of the cache latch LATT to each other in response to the cache reset signal TRST. NMOS transistor N8 can connect the first cache node QT_N and node COM1 of the cache latch LATT to each other in response to the cache set signal TSET.

[0107] NMOS transistor N9 can be connected between node COM1 and the ground terminal, and can be turned on or off in response to the potential level of the sensing node SO. NMOS transistor N10 can be connected between the sensing node SO and the ground terminal, and can be turned on or off in response to the page buffer data transfer signal TRAPPB.

[0108] The master latch assembly 570 may include an NMOS transistor N13, a master latch LATM, and a master latch reset / set assembly RSEM. The master latch assembly 570 can receive programming data and determine an operation. For example, the master latch assembly 570 can determine one of a programming operation, a read operation, or an erase operation.

[0109] The NMOS transistor N13 can connect the sensing node SO and the first master node QM_N of the master latch LATM to each other in response to the master data transmission signal TRANM.

[0110] The master latch LATM may include a third inverter I3 and a fourth inverter I4. The third inverter I3 and the fourth inverter I4 may be connected in parallel between the first master node QM_N and the second master node QM of the master latch LATM. The input terminal of the third inverter I3 may be connected to the second master node QM, and the output terminal may be connected to the first master node QM_N. The input terminal of the fourth inverter I4 may be connected to the first master node QM_N, and the output terminal may be connected to the second master node QM.

[0111] The master latch reset / set component RSEM can be connected to the first master node QM_N and the second master node QM of the master latch LATM, and can reset or set the master latch LATM. For example, the master latch reset / set component RSEM may include NMOS transistors N11 and N12. NMOS transistor N11 can connect the common node COM and the second master node QM of the master latch LATM to each other in response to the master reset signal MRST. NMOS transistor N12 can connect the common node COM and the first master node QM_N of the master latch LATM to each other in response to the master set signal MSET.

[0112] The dynamic latch assembly 580 may include NMOS transistors N14, N15, and N16. The dynamic latch assembly 580 can store programming operation information. For example, the dynamic latch assembly 580 can store programming operation information for any of a multi-level cell (MLC), a three-level cell (TLC), and a four-level cell (QLC).

[0113] NMOS transistor N14 can connect the first master node QM_N and the dynamic node QF to each other in response to the dynamic data transmission signal TRANTOF. NMOS transistor N15 can be connected between NMOS transistor N16 and the ground terminal, and can be turned on or off in response to the potential of the dynamic node QF. NMOS transistor N16 can be connected between the sensing node SO and NMOS transistor N15, and can be turned on or off in response to the dynamic data transmission signal TRANF.

[0114] The latch detector 590 may include NMOS transistors N17 and N18. When performing a programming verification operation or a read operation on multiple memory cells, the latch detector 590 can detect the state of multiple memory cells. NMOS transistor N17 may be connected between the detection node LLN and the ground terminal, and may be turned on or off in response to the potential of the second sensing node QS of the latch circuit 620. NMOS transistor N18 may be connected between the sensing node SO and the detection node LLN, and may be turned on or off in response to the detection data transmission signal TRANS.

[0115] The current controller 610 may include a clamping circuit 611, a current determination circuit 612, and a discharger 613. The clamping circuit 611 may include an NMOS transistor N19 and PMOS transistors P2 and P3. PMOS transistor P2 may be connected between the core voltage VCORE terminal and the sense amplifier node SAN, and may be turned on or off in response to the potential of the second sense node QS. PMOS transistor P3 may be connected between the sense amplifier node SAN and the current sense node CSO, and may transfer the current used to precharge the first line BL1 to the current sense node CSO in response to the current precharge signal SA_PRECH_N. NMOS transistor N19 may be connected between the sense amplifier node SAN and the current sense node CSO, and may generate a sense current for sensing the first line BL1 in response to the current sense signal SA_CSOC.

[0116] According to this embodiment, during programming verification operations or read operations, the method of adjusting the current sensing signal SA_CSOC applied to NMOS transistor N19 can be performed in a manner similar to the method described above for adjusting the page buffer sensing signal PB_SENSE applied to NMOS transistor N3.

[0117] The current determination circuit 612 may include PMOS transistors P4 and P5. PMOS transistor P4 may be connected between the core voltage VCORE terminal and PMOS transistor P5, and may be turned on or off in response to the sense amplifier gating signal SA_STB_N.

[0118] According to this embodiment, during programming verification or reading operations, the activation period of the sense amplifier strobe signal SA_STB_N applied to the PMOS transistor P4 can be adjusted to increase or decrease. For example, during programming verification operations, the activation period of the sense amplifier strobe signal SA_STB_N applied to the PMOS transistor P4 can be adjusted to increase or decrease according to the programming order of the selected pages. Furthermore, during reading operations, the activation period of the sense amplifier strobe signal SA_STB_N applied to the PMOS transistor P4 can be adjusted to increase or decrease according to the position of the selected page among multiple pages.

[0119] Furthermore, the activation period of the sense amplifier gating signal SA_STB_N applied to the PMOS transistor P4 can be adjusted to increase or decrease according to the temperature of the memory cell array 110.

[0120] PMOS transistor P5 can be connected between PMOS transistor P4 and the second sensing node QS, and can be turned on or off in response to the potential level of the current sensing node CSO.

[0121] Discharger 613 can be connected between the current sensing node CSO and the detection node LLN, and may include an NMOS transistor N20 that operates in response to a discharge signal SA_DISCH from the sense amplifier. The NMOS transistor N20 can be turned on or off in response to the discharge signal SA_DISCH from the sense amplifier. Discharger 613 can discharge the current sensing node CSO.

[0122] The latch circuit 620 may include a sense latch LATS and a sense latch reset / set component RSES. The sense latch LATS may include a fifth inverter I5 and a sixth inverter I6. The fifth inverter I5 and the sixth inverter I6 may be connected in parallel between each other between a first sensing node QS_N and a second sensing node QS of the sense latch LATS. For example, the input terminal of the fifth inverter I5 may be connected to the second sensing node QS, and the output terminal may be connected to the first sensing node QS_N. The input terminal of the sixth inverter I6 may be connected to the first sensing node QS_N, and the output terminal may be connected to the second sensing node QS.

[0123] A sense latch reset / set component RSES can be connected to the first sense node QS_N and the second sense node QS of a sense latch LATS, and can reset or set the sense latch LATS. For example, the sense latch reset / set component RSES may include NMOS transistors N21 and N22. NMOS transistor N21 can connect the common node COM and the second sense node QS of the sense latch LATS to each other in response to a sense reset signal SRST. NMOS transistor N22 can connect the common node COM and the first sense node QS_N of the sense latch LATS to each other in response to a sense set signal SSET.

[0124] The discharger 630 can be connected between the common node COM and the ground terminal, and can include an NMOS transistor N23 that is turned on or off according to the potential of the sensing node SO.

[0125] Figures 5A to 5C An implementation of a method for sensing multiple logical pages included in a single page is shown, and more specifically, a method for sensing when... Figure 1 A method for reading selected pages when the memory device 100 performs a programming operation according to the TLC method. Figures 5A to 5C In the graph, the horizontal axis represents the magnitude Vth of the threshold voltage of the memory cell, and the vertical axis represents the memory cell number. Furthermore, Figures 5A to 5C Indicates when Figure 1 The threshold voltage distribution of memory cells when the memory device 100 performs a programming operation according to the TLC method.

[0126] In one implementation, when Figure 1 When the memory device 100 performs a programming operation according to the TLC method, the memory cell can have any one of an erase state E and a first programming state PV1 to a seventh programming state PV7. The voltage used to distinguish between the erase state E and the first programming state PV1 can be a first read voltage R1. The voltage used to distinguish between the first programming state PV1 and the second programming state PV2 can be a second read voltage R2. The voltage used to distinguish between the second programming state PV2 and the third programming state PV3 can be a third read voltage R3. The voltage used to distinguish between the third programming state PV3 and the fourth programming state PV4 can be a fourth read voltage R4. The voltage used to distinguish between the fourth programming state PV4 and the fifth programming state PV5 can be a fifth read voltage R5. The voltage used to distinguish between the fifth programming state PV5 and the sixth programming state PV6 can be a sixth read voltage R6. The voltage used to distinguish between the sixth programming state PV6 and the seventh programming state PV7 can be a seventh read voltage R7.

[0127] exist Figures 5A to 5C In the middle, due to the assumption Figure 1 The memory device 100 performs programming operations according to the TLC method, therefore Figure 1 Each of the plurality of pages in the memory device 100 may include three logical pages. For example, including Figure 1 Each of the plurality of pages in the memory device 100 may include a least significant bit (LSB) page, a middle significant bit (CSB) page, and a most significant bit (MSB) page. (In one embodiment, Figures 5A to 5C Can be applied to Figure 1 (The memory device 100 performs programming operations according to the SLC method, MLC method, or QLC method.)

[0128] Figure 5A This illustrates the process of reading an LSB page. An LSB page can be read via a first read operation and a second read operation (e.g., two read operations). In one implementation, Figure 1 The memory device 100 can first perform a first read operation using the fifth read voltage R5 of the first read voltage R1 and the fifth read voltage R5. For example, during a read operation on an LSB page, Figure 1 The memory device 100 can first perform a first read operation using a fifth read voltage R5, and then perform a second read operation using a first read voltage R1 that is lower than the fifth read voltage R5. This can be referred to as a reverse read operation.

[0129] when Figure 1When the memory device 100 performs the first read operation and the second read operation, the memory cell in the erase state can be read as "1", the memory cells in the first programming state PV1 to the fourth programming state PV4 can be read as "0", and the memory cells in the fifth programming state PV5 to the seventh programming state PV7 can be read as "1".

[0130] Figure 5B The process of reading a CSB page is shown. A CSB page can be read through a third to a fifth read operation (e.g., three read operations). In one implementation, Figure 1 The memory device 100 can first perform a third read operation using the sixth read voltage R6 among the second read voltage R2, the fourth read voltage R4, and the sixth read voltage R6.

[0131] For example, during a read operation on a CSB page, Figure 1 After the memory device 100 first performs a third read operation using the sixth read voltage R6, Figure 1 The memory device 100 can sequentially perform a fourth read operation using a fourth read voltage R4, which has a level lower than the sixth read voltage R6, and a fifth read operation using a second read voltage R2, which has a level lower than the fourth read voltage R4. Similar to the method of reading LSB pages, the read operation described above can be referred to as a reverse read operation.

[0132] when Figure 1 When the memory device 100 performs the third to fifth read operations, the memory cells in the erase state and the first programming state PV1 can be read as "1", and the memory cells in the second programming state PV2 and the third programming state PV3 can be read as "0". The memory cells in the fourth programming state PV4 and the fifth programming state PV5 can be read as "1", and the memory cells in the sixth programming state PV6 and the seventh programming state PV7 can be read as "0".

[0133] Figure 5C The process of reading an MSB page is shown. An MSB page can be read via a sixth and a seventh read operation (e.g., two read operations). In one implementation, Figure 1 The memory device 100 can first perform a sixth read operation using the seventh read voltage R7, which is the third read voltage R3 and the seventh read voltage R7.

[0134] For example, during a read operation on an MSB page, Figure 1The memory device 100 can first perform a sixth read operation using a seventh read voltage R7, and then perform a seventh read operation using a third read voltage R3, which is at a level lower than the seventh read voltage R7. Similar to the method of reading LSB pages, the read operation described above can be called a reverse read operation.

[0135] when Figure 1 When the memory device 100 performs the sixth and seventh read operations, the memory cells in the erase state and the first programming state PV1 and the second programming state PV2 can be read as "1". The memory cells in the third programming state PV3 to the sixth programming state PV6 can be read as "0". The memory cell in the seventh programming state PV7 can be read as "1".

[0136] However, when reading multiple logic pages via the reverse read operation described above, the number of latches toggled in the page buffer may increase when reading with a low-level read voltage. As the number of toggled latches increases, noise during the read operation may also increase.

[0137] Therefore, in this embodiment, the method is implemented to reduce the number of latches that are toggled based on the result of reading using a high-level read voltage. As a result, an increase in noise can be prevented during the read operation.

[0138] Figure 6 An implementation of a method for sensing LSB pages is illustrated. (Refer to...) Figures 4 to 6 , Figure 6 The process of sensing an LSB page is illustrated. In this figure, it is assumed that the sensing operation is a read operation. In another embodiment, the sensing operation could be a program verification operation.

[0139] In one implementation, when sensing an LSB page, the default value of the QS_N node can be set to "1", and the default value of the QM_N node can be set to "0".

[0140] In one implementation method Figure 1 The memory device 100 can perform a first read operation using a fifth read voltage R5. During the first read operation using the fifth read voltage R5, the value of the QM_N node can be maintained or changed. For example, during the first read operation, memory cells in the erase state and the first programming state PV1 to the fourth programming state PV4, where the threshold voltage is lower than the fifth read voltage R5, can be maintained at the default value of "0". Memory cells in the fifth programming state PV5 to the seventh programming state PV7, where the threshold voltage is higher than the fifth read voltage R5, can be changed from the default value of "0" to "1".

[0141] Based on the reverse read operation Figure 1 The memory device 100 can perform a first read operation using a fifth read voltage R5, and then perform a second read operation using a first read voltage R1, which is at a level lower than the fifth read voltage R5. During the second read operation using the first read voltage R1, the value of the QS_N node can be maintained or changed. For example, during the second read operation, memory cells in the erase state (with a threshold voltage lower than the first read voltage R1) can be maintained at "1" as a default value. Memory cells in the first programming state PV1 to the seventh programming state PV7 (with a threshold voltage higher than the first read voltage R1) can be changed from "1" to "0" as a default value.

[0142] After that, Figure 1 The memory device 100 can move the value of the QM_N node to the QS_N node. For example, the value of a latch that was toggled during a first read operation can be moved to the QS_N node. In one embodiment, Figure 1 The memory device 100 can again flip the values ​​of the QS_N node corresponding to the fifth programming states PV5 to the seventh programming states PV7 that were flipped during the first read operation.

[0143] As a result, data from the LSB page can be sensed to the QS_N node. However, because a large number of latches may be toggled during the second read operation performed using a first read voltage R1 that is at a level lower than the fifth read voltage R5, latches corresponding to the first programming states PV1 to the seventh programming states PV7 are toggled. Consequently, noise may occur during the read operation.

[0144] In this embodiment, noise generated during the read operation can be reduced when only the latches corresponding to the first programming states PV1 to the fourth programming states PV4 are toggled (by masking the result of the first read operation performed using the fifth read voltage R5 onto the sensing node). The above-described read method will be described with reference to the following description.

[0145] Figure 7 Example values ​​of the sense node are shown when sensing an LSB page, and more specifically, the values ​​of the sense node SO are shown when a second read operation is performed using a first read voltage R1 during the sensing of an LSB page. In this figure, it is assumed that the sensing operation is a read operation. In another embodiment, the sensing operation can be a programming verification operation.

[0146] and Figure 6 Unlike other nodes, when sensing LSB pages, the default values ​​for both the QS_N and QM_N nodes can be set to "1".

[0147] In one implementation method Figure 1The memory device 100 can perform a first read operation using a fifth read voltage R5. During the first read operation using the fifth read voltage R5, the value of the QM_N node can be maintained or changed. For example, during the first read operation, memory cells in the erase state (where the threshold voltage is lower than the fifth read voltage R5) and the first programming state PV1 to the fourth programming state PV4 can be maintained at a default value of "1". Memory cells in the fifth programming state PV5 to the seventh programming state PV7 (where the threshold voltage is higher than the fifth read voltage R5) can be changed from a default value of "1" to "0".

[0148] Based on the reverse read operation Figure 1 The memory device 100 can perform a first read operation using a fifth read voltage R5, and then perform a second read operation using a first read voltage R1, which is at a level lower than the fifth read voltage R5. During the second read operation using the first read voltage R1, the value of the QS_N node can be maintained or changed.

[0149] In one implementation, data sensed via the first bit line BL1 can be read to the sensing node SO before the value of the QS_N node is maintained or changed. The operation of reading data to the sensing node SO can be, for example, an evaluation operation. During the evaluation operation, when reading a memory cell in an erased state (with a threshold voltage below the first read voltage R1), the value of the sensing node SO can become "0". When reading memory cells in the first programming state PV1 to the seventh programming state PV7 (with a threshold voltage above the first read voltage R1), the value of the sensing node SO can become "1".

[0150] When the value of the sensing node SO is set according to the evaluation operation, the value of the QS_N node can be maintained or changed based on the value of the sensing node SO. For example, during the second read operation, when the value of the sensing node SO is "0", the value of the QS_N node can be maintained as "1" as the default value. When the value of the sensing node SO is "1", the value of the QS_N node can be changed from "1" as the default value to "0".

[0151] However, when setting the value of the QS_N node based on the value of the sensing node SO, a large number of latches are toggled because the latches corresponding to the first programming state PV1 to the seventh programming state PV7 are toggled. Therefore, noise may occur during the read operation.

[0152] Therefore, during the second read operation, a masking operation can be performed on the sensing node SO after the evaluation operation so that only the latches corresponding to the first programming state PV1 to the fourth programming state PV4 are flipped.

[0153] Figure 8 This is a diagram illustrating the configuration of the memory device used to mask the sensing nodes. More specifically, Figure 8 The diagram shows a first line BL1 connected to the sensed memory cell and a sensing node SO connected to the first line BL1. It also shows a first sensing data storage unit 151, a second sensing data storage unit 153, and a sensing node controller 170. In one embodiment, each of the first sensing data storage unit 151 and the second sensing data storage unit 153 may be... Figure 4 Any of the latches. In this document, refer to... Figure 3 The sensed memory cell is one of the memory cells connected to the first bit line BL1.

[0154] Reference Figure 7 and Figure 8 Assuming Figure 1 The memory device 100 senses LSB pages among the logical pages of the pages of the sensed memory cells. LSB pages can be read via a first read operation (performed using a fifth read voltage R5) and a second read operation (performed using a first read voltage R1, which is at a level lower than the fifth read voltage R5).

[0155] In one implementation, during the first read operation, the potential of the sensing node SO can be changed based on the magnitude of the threshold voltage of the memory cell sensed through the first bit line BL1. For example, when the threshold voltage of the sensed memory cell is less than the fifth read voltage R5, the potential of the sensing node SO can be reduced to a value close to the ground voltage level. When the threshold voltage of the sensed memory cell is greater than the fifth read voltage R5, the potential of the sensing node SO can be reduced to a value close to the precharge level. The operation of changing the potential of the sensing node SO can be an evaluation operation.

[0156] In one embodiment, the potential of the sensing node SO can be changed according to the first read operation, and the first sensing data SENSING_DATA1 based on the potential of the sensing node SO can be transmitted to the first sensing data storage unit 151. The latches in the first sensing data storage unit 151 can be flipped or not flipped according to the first sensing data SENSING_DATA1.

[0157] For example, when the value of sensing node SO is "0" (when the value of sensing node SO drops to a value close to the ground voltage level), the latch may not toggle. When the value of sensing node SO is "1" (when the value of sensing node SO drops to a value close to the precharge level), the latch may toggle.

[0158] Subsequently, a second read operation can be performed using a first read voltage R1, which is at a level lower than the fifth read voltage R5. Similar to the first read operation, during the second read operation, the potential of the sensing node SO can be changed according to the magnitude of the threshold voltage of the memory cell sensed through the first bit line BL1.

[0159] For example, when the threshold voltage of the sensed memory cell is less than the first read voltage R1, the potential of the sensed node SO can be reduced to a value close to the ground voltage level. When the threshold voltage of the sensed memory cell is greater than the first read voltage R1, the potential of the sensed node SO can be reduced to a value close to the precharge level. Changing the potential of the sensed node SO can be, for example, an evaluation operation.

[0160] In this embodiment, during the evaluation operation according to the second read operation, the sensor node controller 170 can receive first sensing data SENSING_DATA1 from the first sensing data storage unit 151, and can output a masking value MASKING_VAL based on the first sensing data SENSING_DATA1. The masking value MASKING_VAL can be transmitted to the sensor node SO through the output terminal of the sensor node controller 170 (e.g., a port or output pin of the chip including the sensor node controller 170, whether implemented in software, hardware, or a combination of both), which can be connected to a signal line that carries the masking value MASKING_VAL to the sensor node SO.

[0161] For example, the sensor node controller 170 can output "0" (in the first sensing data SENSING_DATA1 received from the first sensing data storage unit 151) to the sensor node SO as a masking value MASKING_VAL corresponding to the sensing data in the fifth programming state PV5 to the seventh programming state PV7. The sensor node SO can set its value based on the masking value MASKING_VAL output from the sensor node controller 170. When performing a masking operation, the value of the sensor node SO can be set regardless of the data sensed by the evaluation operation.

[0162] Subsequently, the second sensing data SENSING_DATA2 (sensing data from sensing node SO reflecting the masking value MASKING_VAL) can be transmitted to the second sensing data storage unit 153. The latches in the second sensing data storage unit 153 can be toggled or not toggled based on the second sensing data SENSING_DATA2. For example, when the value of sensing node SO is "0" (when the value of sensing node SO drops to a value close to the ground voltage level), the latch may not toggle. When the value of sensing node SO is "1" (when the value of sensing node SO drops to a value close to the pre-charge level), the latch may be toggled.

[0163] Through the masking operation described above, during the second read operation performed using the first read voltage R1, latches corresponding to the first programming state PV1 to the fourth programming state PV4 (among the latches corresponding to the first programming state PV1 to the seventh programming state PV7) can be flipped. As a result, the number of latches that are flipped can be reduced, thereby reducing the amount of noise generated during the read operation.

[0164] Figure 9 This is a diagram illustrating an implementation of a method for masking and sensing data sensed during an evaluation operation. Specifically, Figure 9 Showing according to Figure 8 The process involves masking the value of the sensing node SO with a masking value and performing a sensing operation based on the masked sensing data. In this figure, it is assumed that the sensing operation is a reading operation. In another embodiment, the sensing operation can be a programmatic verification operation.

[0165] Reference Figure 9 When sensing LSB pages, the default values ​​for both the QS_N node and the QM_N node can be set to "1".

[0166] In one implementation method Figure 1 The memory device 100 can perform a first read operation using a fifth read voltage R5. During the first read operation using the fifth read voltage R5, the value of the QM_N node can be maintained or changed. For example, during the first read operation, memory cells in the erase state (where the threshold voltage is lower than the fifth read voltage R5) and the first programming state PV1 to the fourth programming state PV4 can be maintained at a default value of "1". Memory cells in the fifth programming state PV5 to the seventh programming state PV7 (where the threshold voltage is higher than the fifth read voltage R5) can be changed from a default value of "1" to "0".

[0167] After that, Figure 1The memory device 100 can perform a second read operation using a first read voltage R1, which is at a level lower than the fifth read voltage R5. During the second read operation using the first read voltage R1, an evaluation operation can be performed, wherein data sensed via the first bit line BL1 is read to the sensing node SO.

[0168] During the evaluation operation, when reading memory cells in the erase state where the threshold voltage is lower than the first read voltage R1, the value of the sensing node SO can become "0". When reading memory cells in the first programming state PV1 to the seventh programming state PV7 where the threshold voltage is higher than the first read voltage R1, the value of the sensing node SO can become "1".

[0169] at this time, Figure 1 The memory device 100 can mask the value of the sensing node SO based on data sensed using the fifth read voltage R5. For example, it can be based on data from... Figure 8 The value of the sensing node SO is set by the masking value MASKING_VAL output by the sensing node controller 170. When a masking operation is performed, the value of the sensing node SO can be set regardless of the data sensed by the operation.

[0170] For example, Figure 8 The sensing node controller 170 can output "0" as a masking value MASKING_VAL corresponding to the sensing data in the fifth programming state PV5 to the seventh programming state PV7. When the masking value MASKING_VAL is output to the sensing node SO, data can be output as sensing data corresponding to the masking value MASKING_VAL reflected on the sensing node SO.

[0171] Subsequently, the value of the QS_N node can be set based on the sensing data output from the sensing node SO. For example, when the value of the sensing node SO is "0", the value of the QS_N node can remain at the default value of "1". When the value of the sensing node SO is "1", the value of the QS_N node can be changed from the default value of "1" to "0".

[0172] As a result, only latches corresponding to the first programming states PV1 to the fourth programming states PV4 (where the value of the sensing node SO is '1') can be toggled, thus reducing the number of latches toggled. For example, the number of latches toggled can be reduced during the process of storing data in the latches. Therefore, noise generated during sensing operations can be reduced.

[0173] Figure 10 An implementation of a method for sensing CSB pages is illustrated. Specifically, Figure 10This diagram illustrates the process of performing a third read operation using a sixth read voltage R6, a fourth read operation using a fourth read voltage R4, and a fifth read operation using a second read voltage R2 during the sensing of a CSB page. In this diagram, it is assumed that the sensing operation is a read operation. In another embodiment, the sensing operation can be a programming verification operation.

[0174] Reference Figure 10 When sensing CSB pages, the default values ​​for both the QS_N and QM_N nodes can be set to "1".

[0175] In one implementation method Figure 1 The memory device 100 can perform a third read operation using a sixth read voltage R6. During the third read operation using the sixth read voltage R6, the value of the QM_N node can be maintained or changed. For example, during the third read operation, memory cells in the erase state (where the threshold voltage is lower than the sixth read voltage R6) and the first programming state PV1 to the fifth programming state PV5 can be maintained at the default value of "1". Memory cells in the sixth programming state PV6 and the seventh programming state PV7 (where the threshold voltage is higher than the sixth read voltage R6) can be changed from the default value of "1" to "0".

[0176] After that, Figure 1 The memory device 100 can perform a fourth read operation using a fourth read voltage R4. During the fourth read operation using the fourth read voltage R4, the value of the QM_N node can be maintained or changed. For example, during the fourth read operation, memory cells in the erase state (where the threshold voltage is lower than the fourth read voltage R4) and the first programming state PV1 to the third programming state PV3 can be maintained at the default value of "1". Furthermore, memory cells in the fourth programming state PV4 and the fifth programming state PV5 (where the threshold voltage is higher than the fourth read voltage R4) can be changed from the default value of "1" to "0". Furthermore, memory cells in the sixth programming state PV6 and the seventh programming state PV7 can be changed from "0" to "1".

[0177] After that, Figure 1 The memory device 100 can perform a fifth read operation using the second read voltage R2. Based on the result of the fifth read operation, the value of the QS_N node can be maintained or changed.

[0178] In one implementation, data sensed via the first bit line BL1 can be read into the sensing node SO before the value of the QS_N node is maintained or changed. The operation of reading data into the sensing node SO can be, for example, an evaluation operation.

[0179] During the evaluation operation, when reading memory cells in the erase state and the first programming state (with a threshold voltage lower than the second read voltage R2), the value of the sensing node SO can become "0". When reading memory cells in the second programming state PV2 to the seventh programming state PV7 (with a threshold voltage higher than the second read voltage R2), the value of the sensing node SO can become "1".

[0180] When the value of the sensing node SO is set according to the evaluation operation, the value of the QS_N node can be maintained or changed based on the value of the sensing node SO. For example, when the value of the sensing node SO is "0" during the fifth read operation, the value of the QS_N node can be maintained as "1" as the default value. When the value of the sensing node SO is "1", the value of the QS_N node can be changed from "1" as the default value to "0".

[0181] However, when setting the value of the QS_N node based on the value of the sensing node SO, the latches corresponding to the second programming state PV2 to the seventh programming state PV7 are toggled, resulting in a large number of latches being toggled. As a result, noise may occur during read operations.

[0182] Therefore, during the fifth read operation, a masking operation can be performed on the sensing node SO after the evaluation operation. As a result, only the latches corresponding to the second programming state PV2 and the third programming state PV3, as well as the sixth programming state PV6 and the seventh programming state PV7, are toggled.

[0183] Figure 11 An implementation of using masking to sense CSB pages is shown. Specifically, Figure 11 This illustrates the process of masking the value of the sensing node SO according to a masking value during a sensing operation on a CSB page, and performing the sensing operation based on the masked sensing data. In this figure, details related to... Figure 10 Duplicate content.

[0184] In one implementation method Figure 1 The memory device 100 can perform a third read operation using a sixth read voltage R6 and a fourth read operation using a fourth read voltage R4. As a result of performing the third and fourth read operations, the value of the QM_N node of the memory cells in the erase state and the first programming state PV1 to the third programming state PV3 can remain at the default value of "1". Furthermore, the value of the QM_N node of the memory cells in the fourth programming state PV4 and the fifth programming state PV5 can be changed from the default value of "1" to "0", and the value of the QM_N node of the memory cells in the sixth programming state PV6 and the seventh programming state PV7 can be changed from "0" to "1".

[0185] After that, Figure 1The memory device 100 can perform a fifth read operation using the second read voltage R2. During the fifth read operation, an evaluation operation can be performed, in which data sensed via the first bit line BL1 is read to the sensing node SO.

[0186] During the evaluation operation, when reading memory cells in the erase state and the first programming state PV1 (with a threshold voltage lower than the second read voltage R2), the value of the sensing node SO can become "0". When reading memory cells in the second programming state PV2 to the seventh programming state PV7 (with a threshold voltage higher than the second read voltage R2), the value of the sensing node SO can become "1".

[0187] at this time, Figure 1 The memory device 100 can mask the value of the sensing node SO based on the value of the QM_N node set according to the results of performing the third and fourth read operations. In other words, it can mask the value of the sensing node SO based on the value of the QM_N node set according to the results of performing the third and fourth read operations. Figure 8 The value of the sensing node SO is set by the masking value MASKING_VAL output by the sensing node controller 170. When a masking operation is performed, the value of the sensing node SO can be set regardless of the data sensed by the operation.

[0188] For example, Figure 8 The sensing node controller 170 can output a value "0" to the sensing node SO as the masking value MASKING_VAL corresponding to the sensing data in the fourth programming state PV4 and the fifth programming state PV5, and can output a value "1" as the masking value MASKING_VAL corresponding to the sensing data in the sixth programming state PV6 and the seventh programming state PV7. When the masking value MASKING_VAL is output to the sensing node SO, the data output reflecting the masking value MASKING_VAL on the sensing node SO can be used as sensing data.

[0189] Subsequently, the value of the QS_N node can be set based on the sensing data output from the sensing node SO. For example, when the value of the sensing node SO is "0", the value of the QS_N node can remain at the default value of "1". When the value of the sensing node SO is "1", the value of the QS_N node can change from the default value of "1" to "0".

[0190] As a result, only the latches corresponding to the second programming states PV2 and PV3, and the sixth programming states PV6 and PV7, where the value of the sensing node SO is "1", can be toggled. Therefore, the number of latches toggled can be reduced; for example, the number of latches toggled during data storage can be reduced. This reduces noise generated during sensing operations.

[0191] Figure 12 An implementation of using masking to sense CSB pages is shown. Specifically, Figure 12 The display shows the operation during sensing of the CSB page based on the data obtained from... Figure 11 The different methods set masking values ​​to mask the values ​​of sensing nodes SO and perform sensing operations based on the masked sensing data. In this figure, the process of setting masking values ​​to mask the values ​​of sensing nodes SO and performing sensing operations based on the masked sensing data is omitted. Figure 11 Duplicate content.

[0192] In one implementation, Figure 1 After the memory device 100 performs a third read operation using a sixth read voltage R6 and a fourth read operation using a fourth read voltage R4, Figure 1 The memory device 100 can perform a fifth read operation using the second read voltage R2. During the fifth read operation, an evaluation operation can be performed, in which data sensed via the first bit line BL1 is read to the sensing node SO.

[0193] In one implementation method Figure 1 The memory device 100 can mask the value of the sensing node SO based on the value of the QM_N node set according to the results of performing the third and fourth read operations. In other words, it can mask the value of the sensing node SO based on the value of the QM_N node set according to the results of performing the third and fourth read operations. Figure 8 The masking value MASKING_VAL output by the sensing node controller 170 is used to set the value of the sensing node SO.

[0194] and Figure 11 different, Figure 8 The sensing node controller 170 can output a value "0" to the sensing node SO as a masking value MASKING_VAL corresponding to the sensing data in the fourth programming state PV4 and the fifth programming state PV5. That is, the masking value MASKING_VAL corresponding to the sensing data in the sixth programming state PV6 and the seventh programming state PV7 can be left unset. In one embodiment, since the sensing data corresponding to the sixth programming state PV6 and the seventh programming state PV7 is read as "1" to the sensing node SO, the masking value MASKING_VAL for this sensing data can be left unset.

[0195] Subsequently, the value of the QS_N node can be set based on the sensing data output from the sensing node SO. For example, when the value of the sensing node SO is "0", the value of the QS_N node can remain at the default value of "1". When the value of the sensing node SO is "1", the value of the QS_N node can be changed from the default value of "1" to "0".

[0196] As a result, only the latches corresponding to the second programming states PV2 and PV3, and the sixth programming states PV6 and PV7, where the value of the sensing node SO is "1", can be toggled. Therefore, the number of latches toggled can be reduced; for example, the number of latches toggled during data storage can be reduced. This reduces noise generated during sensing operations.

[0197] Figure 13 This is a diagram illustrating the operation of a memory device according to an embodiment. (Refer to...) Figure 13 In operation S1301, the memory device can perform a sensing operation using the first sensing voltage. The sensing operation can be, for example, a programming verification operation or a read operation included in a programming loop.

[0198] In one embodiment, during a sensing operation, a sensing operation can be performed on any of the logical pages in the selected page. A sensing operation on a logical page can be performed through multiple sensing operations. In operation S1301, the sensing operation performed using the first sensing voltage may be the first sensing operation performed among the multiple sensing operations. In this embodiment, it is assumed that a sensing operation on a logical page is performed through a first sensing operation and a second sensing operation.

[0199] In operation S1303, the memory device can perform an evaluation operation using a second sensing voltage. The second sensing voltage may, for example, be a voltage with a level lower than the first sensing voltage. Furthermore, the evaluation operation may correspond to the operation of sensing data sensed using the second sensing voltage to a sensing node via a bit line.

[0200] In one implementation, multiple latches may be toggled when data is stored in latches based on data from the sensed nodes. Therefore, a masking operation can be performed in operation S1305.

[0201] In operation S1305, the memory device can mask the sensing node. For example, the masking operation can be performed using the value of the sensing node corresponding to the toggled latch in the data sensed during the first sensing operation. When the masking operation is performed, the value of the sensing node can be set regardless of how the data sensed by the operation is evaluated.

[0202] In operation S1307, the memory device can sense data based on the masked sensing node. For example, when the value of the sensing node is "0", the sensed data can remain as "1" as the default value. When the value of the sensing node is "1", the sensed data can be changed from "1" as the default value to "0".

[0203] Figure 14This is a diagram illustrating the operation of a memory device according to an embodiment. (Refer to...) Figure 14 In operation S1401, the memory device can initiate a sensing operation. The sensing operation can be the operation of sensing any one of a plurality of logical pages in a selected page. A sensing operation on a logical page can be performed through multiple sensing operations. Furthermore, the sensing operation can be, for example, a programming verification operation or a read operation included in a programming loop.

[0204] In one implementation, when performing a sensing operation on a logical page, the sensing operation can be performed using three or more sensing voltages.

[0205] In operation S1403, the memory device can determine whether the currently executing sensing operation is the last sensing operation. For example, the memory device can determine whether the currently executing sensing operation is the last of a plurality of sensing operations on a logical page.

[0206] In one implementation, if the sensing operation is not the last sensing operation (No), the operation can proceed to operation S1405, and the next sensing operation can be executed. Thereafter, it can be determined whether the sensing operation executed again is the last sensing operation (S1403).

[0207] In one implementation, operation S1407 can be performed when the sensing operation is the last sensing operation (yes).

[0208] In operation S1407, the memory device can mask the sensing node based on data sensed by a sensing operation performed prior to the final sensing operation. For example, during the final sensing operation, data sensed by the sensing node via the bit line can be read. Subsequently, based on the sensed data, the potential of the sensing node can be changed. This can be referred to as evaluation. Based on the changed potential of the sensing node, the sensed data can be stored in a latch.

[0209] However, when data is stored in latches based on the data from the sensed nodes, multiple latches may be toggled. Therefore, a masking operation can be performed in operation S1407. For example, a masking operation can be performed based on the data sensed before the last sensing operation, using the values ​​of the sensed nodes corresponding to the toggled latches. When performing the masking operation, the values ​​of the sensed nodes can be set regardless of the data sensed by the evaluation operation.

[0210] In operation S1409, the memory device can sense data based on the masked sensing node. For example, when the value of the sensing node is "0", the sensed data can remain as "1" as the default value. When the value of the sensing node is "1", the sensed data can be changed from "1" as the default value to "0".

[0211] Figure 15 It is shown Figure 1 The figure illustrates an embodiment of the memory controller 1000. The memory controller 1000 is connected to a host and a memory device and is configured to access the memory device in response to a request from the host. For example, the memory controller 1000 is configured to control write operations, read operations, erase operations, and background operations of the memory device. The memory controller 1000 may also be configured to act as an interface between the memory device and the host and / or drive firmware for controlling the memory device.

[0212] Reference Figure 15 The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction circuit (ECC) 1030, a host interface 1040, a buffer controller (or buffer control circuit) 1050, a memory interface 1060, and a bus 1070.

[0213] Bus 1070 can be configured to provide one or more channels between components of memory controller 1000.

[0214] Processor 1010 can control the overall operation of memory controller 1000 and can execute logical operations. Processor 1010 can communicate with an external host through host interface 1040 and with memory devices through memory interface 1060. Furthermore, processor 1010 can communicate with memory buffer 1020 through buffer controller 1050. Processor 1010 can use memory buffer 1020 as operational memory, cache memory, or buffer memory to control the operation of the memory device.

[0215] In one implementation, processor 1010 can perform the functions of the FTL. For example, processor 1010 can translate host-provided LBAs into PBAs via the FTL. The FTL can receive LBAs and can translate LBAs into PBAs using a mapping table. The flash translation layer performs one or more address mapping methods based on the mapping unit. Examples of address mapping methods include page mapping, block mapping, and hybrid mapping.

[0216] In one implementation, processor 1010 can be configured to randomize data received from a host. For example, processor 1010 can use a randomization seed to randomize data from the host. The randomized data can be provided to a memory device as data to be stored and can be programmed into a memory cell array. Processor 1010 can perform randomization and derandomization, for example, via driver instructions (e.g., firmware or various other types of software).

[0217] The memory buffer 1020 can be used as the operating memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands executed by the processor 1010. The memory buffer 1020 can store data processed by the processor 1010. In one embodiment, the memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0218] Error correction circuit 1030 can perform error correction (e.g., error correction coding (ECC coding)) on data to be written to the memory device via memory interface 1060. Error-corrected data can be transmitted to the memory device via memory interface 1060. Error correction circuit 1030 can also perform error correction decoding (ECC decoding) on ​​data received from the memory device via memory interface 1060. For example, error correction circuit 1030 can be included as a component of memory interface 1060.

[0219] Host interface 1040 is configured to communicate with an external host under the control of processor 1010. Host interface 1040 can be configured to perform communication using one or more methods, standards, or protocols. Examples include Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Unloaded DIMM (LRDIMM).

[0220] The buffer controller 1050 is configured to control the memory buffer 1020 under the control of the processor 1010.

[0221] The memory interface 1060 is configured to communicate with the memory device under the control of the processor 1010. The memory interface 1060 can exchange commands, addresses, and data with the memory device through one or more corresponding channels.

[0222] In one embodiment, the memory controller 1000 may not include the memory buffer 1020 and the buffer controller 1050.

[0223] In one implementation, processor 1010 can use code to control the operation of memory controller 1000. Processor 1010 can load code from a non-volatile memory device (e.g., read-only memory) disposed within memory controller 1000. As another example, processor 1010 can load code from a memory device via memory interface 1060.

[0224] In one embodiment, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data within the memory controller 1000, and the control bus can be configured to transmit control information (e.g., commands, addresses, and / or other information) within the memory controller 1000. In one embodiment, the data bus and the control bus can be separate from each other and can avoid interfering with or affecting each other. The data bus can be connected to the host interface 1040, the buffer controller 1050, the error correction circuit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1020, and the memory interface 1060.

[0225] Figure 16 This is a block diagram illustrating an implementation of a memory card system to which the storage device described herein can be applied.

[0226] Reference Figure 16 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300. The memory controller 2100 is connected to the memory device 2200 and configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control read operations, write operations, erase operations, background operations, and / or other operations of the memory device 2200. The memory controller 2100 may act as an interface between the memory device 2200 and a host. The memory controller 2100 may be configured to drive instructions (e.g., firmware or other types of software) for controlling the memory device 2200. (See reference...) Figure 2 Description Figure 1 The memory device 100 is equivalent to the memory device 2200.

[0227] The memory controller 2100 may include, for example, random access memory (RAM), a processor, a host interface, a memory interface, and / or error correction circuitry.

[0228] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to specific communication standards, protocols, or methods. Examples include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. As an example, connector 2300 can be defined using at least one of the aforementioned communication standards.

[0229] As an example, the memory device 2200 can be implemented as a variety of non-volatile memory elements, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0230] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure the memory card. Examples include PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, and eMMC), SD cards (SD, miniSD, microSD, and SDHC), and universal flash storage (UFS).

[0231] In one embodiment, the memory device 2200 can perform a sensing operation on a selected page. In another embodiment, the memory device 2200 can perform a sensing operation on multiple logical pages within the selected page. In this case, the sensing operation can be a verification operation or a read operation within a programming operation and verification operation included in a programming loop.

[0232] In one embodiment, the memory device 2200 can perform a sensing operation on one of a plurality of logical pages. The sensing operation on a logical page can be performed using multiple sensing voltages, for example, a sequence from a high-level sensing voltage to a low-level sensing voltage.

[0233] However, when a sensing operation is performed using a high-level sensing voltage followed by a low-level sensing voltage, multiple latches may be toggled. In this case, the value of the sensing node can be masked to reduce the number of latches toggled.

[0234] For example, a masking operation can be performed to indicate the value of a toggled latch when sensing is performed using a high-level sensing voltage. In one embodiment, when the memory device 2200 senses using a low-level sensing voltage, the memory device 2200 can mask the value of the sensed node to indicate the value of a toggled latch. When performing the masking operation, the value of the sensed node can be set regardless of the value of the sensed node being sensed.

[0235] When a value for a sensing node is set, data can be stored in a latch based on that value. This reduces the number of latches that are flipped during the data storage process, thus reducing noise generated during sensing operations.

[0236] Figure 17 This is a block diagram illustrating an implementation of a solid-state drive (SSD) system to which the storage devices described herein can be applied.

[0237] Reference Figure 17 The SSD 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory units 3221 to 322n, an auxiliary power supply unit 3230, and a cache memory 3240.

[0238] In one implementation, the SSD controller 3210 can execute a reference... Figure 1 The memory controller 200 is described in terms of its functionality. The SSD controller 3210 can control multiple flash memory devices 3221 to 322n in response to a signal SIG received from the host 3100. As an example, the signal SIG can be a signal based on one or more interfaces between the host 3100 and the SSD 3200. Examples include at least one of Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0239] Auxiliary power supply unit 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply unit 3230 can receive power (PWR) from host 3100 and can also be charged. When the power supply from host 3100 is unstable, auxiliary power supply unit 3230 can provide power to SSD 3200. As an example, auxiliary power supply unit 3230 can be located inside SSD 3200 or externally to SSD 3200. For example, auxiliary power supply unit 3230 can be located on the motherboard and can provide auxiliary power to SSD 3200.

[0240] Buffer memory 3240 serves as a buffer for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or it may temporarily store metadata (e.g., a mapping table) of flash memories 3221 to 322n. Buffer memory 3240 may include volatile memory (e.g., DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM) or non-volatile memory (e.g., FRAM, ReRAM, STT-MRAM, and PRAM).

[0241] In one embodiment, each of the plurality of flash memories 3221 to 322n can perform a sensing operation on a selected page. For example, the plurality of flash memories 3221 to 322n can perform sensing operations on multiple logical pages among the selected pages. In this case, the sensing operation can be a programming operation in a programming loop, a verification operation in a verification operation, or a read operation.

[0242] In one embodiment, each of the plurality of flash memories 3221 to 322n can perform a sensing operation on any one of the plurality of logical pages. Multiple sensing voltages can be used to perform a sensing operation on a logical page. The multiple sensing voltages can be sequentially applied to the sensing operation from a high-level sensing voltage to a low-level sensing voltage.

[0243] However, when a sensing operation is performed using a high-level sensing voltage followed by a low-level sensing voltage, multiple latches may be toggled. In this case, the value of the sensing node can be masked to reduce the number of latches toggled.

[0244] For example, a masking operation can be performed that indicates a latch being toggled when sensing is performed using a high-level sensing voltage. For instance, when multiple flash memories 3221 to 322n are sensing using a low-level sensing voltage, the multiple flash memories 3221 to 322n can mask the value of the sensed node to the value of the latch indicating the toggled latch. When performing the masking operation, the value of the sensed node can be set regardless of the value of the sensed node being sensed.

[0245] When a value for a sensing node is set, data can be stored in a latch based on that value. In this case, the number of latches toggled during data storage can be reduced. Therefore, noise generated during sensing operations can be decreased.

[0246] Figure 18 This is a block diagram illustrating an implementation of a user system to which the storage device described herein can be applied.

[0247] Reference Figure 18 User system 4000 includes application processor 4100, memory module 4200, network module 4300, storage module 4400, and user interface 4500. Application processor 4100 can drive components, operating system (OS), user programs, and / or other features of user system 4000. Application processor 4100 may include controllers, interfaces, graphics engines, and / or other features controlling components in user system 4000. In one implementation, application processor 4100 may be configured as a system-on-a-chip (SoC).

[0248] Memory module 4200 can operate as main memory, operating memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory (e.g., DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM) or non-volatile random access memory (e.g., PRAM, ReRAM, MRAM, and FRAM). For example, application processor 4100 and memory module 4200 may be packaged based on a stacked package (POP) and configured as a single semiconductor package.

[0249] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communication (e.g., Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi). For example, network module 4300 can be included in application processor 4100.

[0250] Storage module 4400 can store, for example, data received from application processor 4100. In one embodiment, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory element, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or three-dimensional NAND flash memory. For example, storage module 4400 can be configured as a removable storage device (removable drive) such as a memory card and an external drive of user system 4000.

[0251] In one embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, which can be referenced Figure 2 and Figure 3 The described memory device operates similarly or identically. Storage module 4400 can be compared with the referenced... Figure 1 The described storage device 50 operates in a similar or identical manner.

[0252] User interface 4500 may include one or more interfaces for inputting data or instructions to application processor 4100 or for outputting data and / or instructions to external devices. Examples of user interface 4500 include user input interfaces such as keyboards, keypads, buttons, touch panels, touch screens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. User interface 4500 may include one or more user output interfaces such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) display devices, active-matrix OLED (AMOLED) display devices, LEDs, speakers, and monitors.

[0253] In one embodiment, the storage module 4400 can perform sensing operations on selected pages. In another embodiment, the storage module 4400 can perform sensing operations on multiple logical pages within the selected pages. In this case, the sensing operation can be a programming operation within a programming loop, a verification operation within a verification operation, or a read operation.

[0254] In one embodiment, the storage module 4400 can perform a sensing operation on any one of a plurality of logical pages. Multiple sensing voltages can be used to perform a sensing operation on a logical page. In one embodiment, the multiple sensing voltages can be used sequentially from a high-level sensing voltage to a low-level sensing voltage for the sensing operation.

[0255] However, when a sensing operation is performed using a high-level sensing voltage followed by a low-level sensing voltage, multiple latches may be toggled. In this case, the value of the sensing node can be masked to reduce the number of latches toggled.

[0256] For example, a masking operation can be performed that indicates a latch being toggled when sensing is performed using a high-level sensing voltage. For instance, when the storage module 4400 senses using a low-level sensing voltage, the storage module 4400 can mask the value of the sensed node to indicate the value of the toggled latch. When performing the masking operation, the value of the sensed node can be set regardless of the value of the sensed node being sensed.

[0257] According to one or more of the above embodiments, when the value of the sensing node is set, data can be stored in a latch based on the value of the sensing node. In this case, the number of latches toggled during the data storage process can be reduced. Therefore, noise generated during sensing operations can be reduced.

[0258] While this disclosure has been shown and described with reference to certain exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the exemplary embodiments described above, but should be defined not only by the appended claims but also by their equivalents.

[0259] In the above embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the operations do not necessarily have to be performed in the described order, but can be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to aid in understanding this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure. One or more embodiments may be combined to form additional embodiments.

[0260] Furthermore, exemplary embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is merely for the purpose of explaining embodiments of this disclosure. Therefore, this disclosure is not limited to the described embodiments, and many variations can be made within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure, in addition to the embodiments disclosed herein.

[0261] Cross-reference to related applications

[0262] This application claims priority to Korean Patent Application No. 10-2020-0128791, filed with the Korean Intellectual Property Office on October 6, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple pages, each of which includes multiple memory units; Peripheral circuitry that senses a selected page among the plurality of pages, the selected page including a selected memory cell; as well as A sensing node controller, based on the result of a first sensing operation among a plurality of sensing operations performed to sense one of a plurality of logical pages in the selected page, controls a sensing node connected via a bit line to a page buffer of the selected memory cell during a second sensing operation among the plurality of sensing operations. The sensing node controller generates a masking value to be transmitted to the sensing node based on the result of the first sensing operation, which is different from the second sensing operation.

2. The memory device according to claim 1, wherein, The sensing operations include programming verification operations or reading operations.

3. The memory device according to claim 1, wherein, The level of the first sensing voltage used during the first sensing operation is higher than the level of the second sensing voltage used during the second sensing operation.

4. The memory device according to claim 1, further comprising: A first sensing data storage unit stores first sensing data sensed by the sensing node during the first sensing operation; as well as The second sensing data storage unit stores the second sensing data sensed by the sensing node during the second sensing operation.

5. The memory device according to claim 4, wherein, The first sensing data storage unit outputs the first sensing data to the sensing node controller during the second sensing operation; and The sensing node controller determines whether the latch in the page buffer has been flipped based on the first sensing data.

6. The memory device according to claim 4, wherein, When the first sensed data has a value different from the default value, the sensed node controller determines that the latch in the page buffer has been flipped.

7. The memory device according to claim 4, wherein, When the second sensing data is sensed by the sensing node, the sensing node controller outputs the masking value corresponding to the latch that is flipped based on the first sensing data.

8. The memory device according to claim 7, wherein, The potential of the sensing node is set according to the masking value.

9. The memory device according to claim 8, wherein, The second sensing data storage unit stores the second sensing data sensed by the sensing node set according to the masking value.

10. The memory device according to claim 1, wherein, When the plurality of sensing operations are performed to sense any one of the plurality of logical pages included in the selected page, the sensing node controller controls the sensing node in the page buffer connected to the selected memory cell via the bit line during the last sensing operation based on sensing data obtained through one or more sensing operations performed before the last sensing operation in the plurality of sensing operations.

11. The memory device according to claim 10, wherein, The sensing node controller determines whether the latches in the page buffer have been toggled based on the sensing data.

12. The memory device according to claim 10, wherein, The sensing node controller outputs the masking value based on the sensing data, the masking value corresponding to a latch that is toggled according to the sensing operation prior to the last sensing operation.

13. The memory device according to claim 12, wherein, The sensing node is set according to the masking value; and During the final sensing operation, data sensed by the sensing node is stored according to the masking value.

14. A method of operating a memory device, the memory device sensing a selected page comprising a selected memory cell from among a plurality of pages comprising a plurality of memory cells, the method comprising the steps of: Perform a first sensing operation to sense one of a plurality of logical pages in the selected page; as well as During a second sensing operation for sensing a logical page, the sensing node in the page buffer connected to the selected memory cell via bit lines is controlled based on the result of the first sensing operation. The step of controlling the sensing node includes transmitting a masking value generated based on the result of the first sensing operation, which is different from the second sensing operation, to the sensing node.

15. The method according to claim 14, wherein, The level of the first sensing voltage used during the first sensing operation is higher than the level of the second sensing voltage used during the second sensing operation.

16. The method according to claim 14, in, The memory device further includes: A first sensing data storage unit stores first sensing data sensed by the sensing node during the first sensing operation; and The second sensing data storage unit stores the second sensing data sensed by the sensing node during the second sensing operation, and The step of controlling the sensing node includes the following steps: when the first sensing data has a value different from the default value, determining that one or more latches in the page buffer are toggled.

17. The method according to claim 16, wherein, The steps of controlling the sensing node include the following steps: when the second sensing data is sensed by the sensing node, setting the potential of the sensing node to the masking value corresponding to the latch in the page buffer that is toggled according to the first sensing data.

18. The method of claim 17, further comprising the step of: The second sensing data sensed by the sensing node is stored.

19. A sensing node controller, the sensing node controller comprising: The output terminal is connected to the sensing node of the page buffer; as well as A controller that generates a masking value to be transmitted to the sensing node via the output terminal based on the result of a first sensing operation, which is different from the second sensing operation. The second sensing operation is performed after the first sensing operation and during the time the sensing node is connected to the selected memory cell.

Images