Verification error bit quantification circuit and method for semiconductor memory

Abstract

The present application relates to a kind of verification error bit quantification circuit of semiconductor memory, including mode selection unit, select one from at least two different sizes verification standard as the verification standard signal of verification error bit quantification circuit;The highest bit quantification unit compares verification standard signal and verification error bit signal and generates first comparison result, and first enable signal is exported according to first comparison result, and first enable signal controls the opening or shutdown of the lowest bit quantification unit;The lowest bit quantification unit compares verification error bit signal and first reference signal and generates second comparison result when it is opened, and second enable signal is exported according to second comparison result, and second enable signal controls the opening or shutdown of the intermediate bit quantification unit;And intermediate bit quantification unit compares verification error bit signal and second reference signal and generates third comparison result when it is opened.The present application can select the most suitable quantification unit to open, close unnecessary quantification unit, save power consumption.

Description

[0001] This application is a divisional application of the patent filed on March 15, 2021, with application number 202110275767.5, entitled "Verification Error Bit Quantization Circuit and Method for Semiconductor Memory". Technical Field

[0002] This invention relates to the field of integrated circuit manufacturing, and more particularly to a circuit and method for verifying error bits in semiconductor memory. Background Technology

[0003] To overcome the limitations of two-dimensional memory devices, the industry has developed and mass-produced memory devices with three-dimensional (3D) structures, which increase integration density by arranging memory cells three-dimensionally on a substrate. In the manufacturing of 3D NAND memory, write verification of memory cells is required to count the number of failed or erroneous writes; this process is called Verify Failbit Count (VFC). The circuit that performs VFC is correspondingly called the VFC circuit. The operation of the VFC circuit consumes power from the 3D NAND memory; therefore, the VFC circuit needs to be optimized to save power. Summary of the Invention

[0004] The technical problem to be solved by the present invention includes providing a power-saving semiconductor memory verification error bit quantization circuit, method, and semiconductor memory including the verification error bit quantization circuit.

[0005] The technical solution adopted by the present invention to solve the above-mentioned technical problem is a verification error bit quantization circuit for a semiconductor memory. The quantization circuit includes: a mode selection unit and a plurality of quantization units, wherein the plurality of quantization units include at least a most significant bit quantization unit and a least significant bit quantization unit; wherein;

[0006] The mode selection unit is configured to select one of at least two verification criteria of different sizes as the verification criterion signal for the verification error bit quantization circuit; and to transmit the verification criterion signal to the highest bit quantization unit coupled to the mode selection unit;

[0007] The most significant bit quantization unit is configured to: receive the verification standard signal; compare the verification standard signal and the verification error bit signal to generate a first comparison result; output a first enable signal based on the first comparison result; and control the least significant bit quantization unit coupled to the most significant bit quantization unit to be turned on or remain off based on the first enable signal.

[0008] The least significant bit quantization unit is configured to: when enabled based on the first enable signal, compare the verification error bit signal and the first reference signal to generate a second comparison result;

[0009] Wherein, the first reference signal is the least significant bit standard signal that the quantization circuit can quantize, which is smaller than the verification standard signal.

[0010] In some embodiments of the present invention, the plurality of quantization units further include intermediate bit quantization units;

[0011] The least significant bit quantization unit is further configured to: output a second enable signal based on the second comparison result; and control the intermediate bit quantization unit coupled to the least significant bit quantization unit to be turned on or remain off based on the second enable signal.

[0012] The intermediate bit quantization unit is configured to: when enabled based on the second enable signal, compare the verification error bit signal and the second reference signal to generate a third comparison result;

[0013] Wherein, the second reference signal is greater than the first reference signal and less than or equal to the verification standard signal.

[0014] In some embodiments of the present invention, the quantization circuit further includes an intermediate higher-order quantization unit arranged adjacent to the intermediate-order quantization unit.

[0015] The intermediate bit quantization unit is further configured to: output a third enable signal based on the third comparison result; and control the intermediate higher bit quantization unit to be turned on or remain off based on the third enable signal.

[0016] The intermediate higher-order quantization unit is configured to: when enabled based on the third enable signal, compare the verification error bit signal and the third reference signal to generate a fourth comparison result;

[0017] The third reference signal is greater than the second reference signal and less than or equal to the verification standard signal.

[0018] In some embodiments of the present invention, when the verification error bit signal is less than the verification standard signal, the most significant bit quantization unit is configured to: control the least significant bit quantization unit to be turned on based on the first enable signal;

[0019] When the verification error bit signal is not less than the verification standard signal, the most significant bit quantization unit is configured to control the least significant bit quantization unit to remain off based on the first enable signal.

[0020] In some embodiments of the present invention, when the verification error bit signal is greater than the first reference signal, the least significant bit quantization unit is configured to: control the intermediate bit quantization unit to be turned on based on the second enable signal;

[0021] When the verification error bit signal is not greater than the first reference signal, the least significant bit quantization unit is configured to control the intermediate bit quantization unit to remain off based on the second enable signal.

[0022] In some embodiments of the present invention, when the intermediate bit quantization unit is enabled, the least significant bit quantization unit is disabled.

[0023] In some embodiments of the present invention, when the verification error bit signal is greater than the second reference signal, the intermediate bit quantization unit is configured to: control the intermediate higher bit quantization unit to be turned on based on the third enable signal;

[0024] When the verification error signal is greater than the second reference signal, the intermediate bit quantization unit is configured to control the intermediate higher bit quantization unit to remain off based on the third enable signal.

[0025] In some embodiments of the present invention, the intermediate bit quantization unit is turned off when the intermediate higher bit quantization unit is turned on.

[0026] In some embodiments of the present invention, the most significant bit quantization unit is further configured to output a fourth enable signal based on the first comparison result;

[0027] The least significant bit quantization unit further includes a first OR gate, the input of which is connected to the fourth enable signal and the second enable signal, and the output of the first OR gate is used as the second comparison result output by the least significant bit quantization unit.

[0028] In some embodiments of the present invention, the most significant bit quantization unit is further configured to output a fourth enable signal based on the first comparison result;

[0029] The intermediate bit quantization unit further includes a second OR gate, the input of which is connected to the fourth enable signal and the third enable signal, and the output of the second OR gate serves as the third comparison result output by the intermediate bit quantization unit.

[0030] In some embodiments of the present invention, the quantization unit further includes a code conversion unit configured to convert the thermometer code into binary code; wherein the input of the code conversion unit, from the high bit to the low bit, is the first comparison result, the third comparison result, and the second comparison result.

[0031] In some embodiments of the present invention, the quantization unit further includes an accumulator configured to accumulate a plurality of binary codes obtained from the code conversion unit.

[0032] To address the aforementioned technical problems, this invention also proposes a semiconductor memory, comprising: a memory array; and peripheral circuitry coupled to the memory array, wherein: the peripheral circuitry is controlled to: control the memory operation of the memory array; and wherein: the peripheral circuitry is configured with a verification error bit quantization circuit as described above.

[0033] To address the aforementioned technical problems, this invention also proposes a method for quantizing verification error bits in a semiconductor memory, applied to any of the verification error bit quantization circuits described above. The method includes:

[0034] The mode selection unit selects one of at least two verification criteria of different sizes as the most significant verification criterion signal; and transmits the verification criterion signal to the most significant quantization unit coupled to the mode selection unit.

[0035] The highest-order quantization unit receives the verification standard signal; compares the verification error bit signal and the verification standard signal to generate a first comparison result; outputs a first enable signal based on the first comparison result; and controls the lowest-order quantization unit to be turned on or remain off based on the first enable signal.

[0036] When the least significant bit quantization unit is enabled based on the first enable signal, it compares the verification error bit signal and the first reference signal to generate a second comparison result; wherein, the first reference signal is the least significant bit standard signal that the quantization circuit can quantize, which is smaller than the verification standard signal.

[0037] In some embodiments of the present invention, the method further includes:

[0038] The least significant quantization unit outputs a second enable signal based on the second comparison result; the second enable signal is used to control the intermediate quantization unit to be turned on or remain off.

[0039] When the intermediate bit quantization unit is enabled based on the second enable signal, it compares the verification error bit signal and the second reference signal to generate a third comparison result, wherein the second reference signal is greater than the first reference signal and less than or equal to the verification standard signal.

[0040] In some embodiments of the present invention, the method further includes:

[0041] The intermediate bit quantization unit also outputs a third enable signal based on the third comparison result; and controls the intermediate higher bit quantization unit to be turned on or remain off based on the third enable signal; and

[0042] When the intermediate higher-order quantization unit is enabled based on the third enable signal, it compares the verification error bit signal and the third reference signal to generate a fourth comparison result, wherein the third reference signal is greater than the second reference signal and less than or equal to the verification standard signal, and the intermediate higher-order quantization unit is adjacent to the intermediate bit quantization unit.

[0043] In some embodiments of the present invention, when the verification error bit signal is less than the verification standard signal, the most significant bit quantization unit controls the least significant bit quantization unit to turn on based on the first enable signal;

[0044] When the verification error bit signal is not less than the verification standard signal, the most significant bit quantization unit controls the least significant bit quantization unit to remain off based on the first enable signal.

[0045] In some embodiments of the present invention, when the verification error bit signal is greater than the first reference signal, the least significant bit quantization unit controls the intermediate bit quantization unit to turn on based on the second enable signal;

[0046] When the verification error bit signal is not greater than the first reference signal, the least significant bit quantization unit controls the intermediate bit quantization unit to remain off based on the second enable signal.

[0047] In some embodiments of the present invention, when the intermediate bit quantization unit is enabled, the least significant bit quantization unit is disabled.

[0048] In some embodiments of the present invention, when the verification error bit signal is greater than the second reference signal, the intermediate bit quantization unit controls the intermediate higher bit quantization unit to turn on based on the third enable signal;

[0049] When the verification error signal is greater than the second reference signal, the intermediate bit quantization unit controls the intermediate higher bit quantization unit to remain off based on the third enable signal.

[0050] In some embodiments of the present invention, the intermediate bit quantization unit is turned off when the intermediate higher bit quantization unit is turned on.

[0051] In some embodiments of the present invention, the method further includes:

[0052] The highest-order quantization unit outputs a fourth enable signal based on the first comparison result; when the verification error signal is greater than the verification standard signal, the lowest-order quantization unit, the middle-order quantization unit, and the middle higher-order quantization unit are all controlled to remain off based on the fourth enable signal.

[0053] The verification error bit quantization circuit and method of this invention can select one of at least two different verification standards as the verification standard signal. The verification standard of the verification error bit quantization circuit can be flexibly switched. Furthermore, the most significant bit quantization unit, the least significant bit quantization unit, and the middle bit quantization unit cooperate with each other. Based on the relationship between the verification error bit signal and different reference currents, the most suitable quantization unit is selected to be turned on, and unnecessary quantization units are turned off, so as to achieve the maximum saving of circuit power consumption. Attached Figure Description

[0054] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0055] Figure 1 This is a schematic diagram of a VFC circuit.

[0056] Figure 2A-2D This is an example of a quantization unit in a VFC circuit;

[0057] Figure 3 This is a block diagram of a verification error bit quantization circuit according to an embodiment of the present invention;

[0058] Figure 4A This is a schematic diagram of the mode selection unit in the verification error bit quantization circuit according to an embodiment of the present invention;

[0059] Figure 4B This is a schematic diagram of the structure of the highest-order quantization unit in the verification error bit quantization circuit of an embodiment of the present invention;

[0060] Figure 5 This is a schematic diagram of the least significant bit quantization unit in a verification error bit quantization circuit according to an embodiment of the present invention;

[0061] Figure 6 This is a schematic diagram of the intermediate bit quantization unit in a verification error bit quantization circuit according to an embodiment of the present invention;

[0062] Figure 7 This is a schematic diagram of the structure of the intermediate higher bit quantization unit in the verification error bit quantization circuit of an embodiment of the present invention;

[0063] Figure 8 This is a schematic diagram of the enable signal control circuit in the verification error bit quantization circuit of an embodiment of the present invention;

[0064] Figure 9A and 9B This is a schematic diagram of the intermediate bit quantization unit in a verification error bit quantization circuit according to an embodiment of the present invention;

[0065] Figure 10This is a schematic diagram of the code conversion unit and accumulator in the verification error bit quantization circuit of an embodiment of the present invention;

[0066] Figure 11 This is a structural block diagram of a semiconductor memory according to an embodiment of the present invention;

[0067] Figure 12 This is an exemplary flowchart of a method for verifying error bit quantization in a semiconductor memory according to an embodiment of the present invention;

[0068] Figure 13 This is a schematic diagram of the power consumption test results of a verification error bit quantization circuit and method according to an embodiment of the present invention. Detailed Implementation

[0069] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0070] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the invention is not limited to the specific embodiments disclosed below.

[0071] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0072] In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure will be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0073] For ease of description, spatial relation terms such as “below,” “below,” “lower than,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of an element or feature shown in the accompanying drawings to other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the orientation of an element described as “below,” “below,” or “below” to other elements or features will change to “above” said other elements or features. Thus, the exemplary terms “below” and “below” can encompass both upward and downward directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0074] In the context of this application, the structure described above the second feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0075] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be construed as limiting the scope of protection of this application.

[0076] As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0077] As used herein, "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0078] As used in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes thereon. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0079] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0080] Figure 1 This is a schematic diagram of a VFC circuit. (Reference) Figure 1 As shown, the memory cell array 110 is connected to the page buffer 120 via bit lines (BL), and the page buffer 120 is connected to the VFC circuit 130. The memory cell array 110 includes multiple memory cells. After programming, the page buffer 120 outputs a current signal to the VFC circuit 130. If the memory cell passes programming verification, the current signal is 0; if the memory cell fails programming verification, the page buffer of the corresponding bit line branch will output a corresponding current signal. The VFC circuit 130 counts these current signals to determine the number of memory cells that failed programming verification and outputs this number. (Reference) Figure 1 As shown, the VFC circuit 130 typically includes multiple quantization units.

[0081] Figure 2A-2D This is an example of a quantization unit in a VFC circuit. In this example, the VFC circuit includes a total of 14 quantization units, which compare the verification error bit current Iverok_q from the page buffer with different reference currents to obtain the comparison result Vercont<0:13>. Based on this comparison result, the specific number of verification error bits can be output. Figure 2A-2D Four of the 14 quantization units are shown. Figure 2AThe diagram shows a quantization cell where the reference current Ibase_0 is 1b, where 1b represents one unit of current or one standard current. When the verification error bit current Iverok_q is greater than the reference current Ibase_0, Vercont is output. <0> =1, otherwise Vercont <0> =0. Figure 2B The diagram shows a quantization cell with a reference current Ibase_1 of 2b, where 2b represents two current units or two standard currents. When the verification error bit current Iverok_q is greater than the reference current Ibase_2, Vercont is output. <1> =1, otherwise Vercont <1> =0. Figure 2C The diagram shows a quantization cell with a reference current Ibase_12 of 25 bits, where 25 bits represents 25 current units or 25 standard currents. When the verification error bit current Iverok_q is greater than the reference current Ibase_12, Vercont is output. <12> =1, otherwise Vercont <12> =0. Figure 2D The diagram shows a quantization cell with a reference current Ibase_13 of 27 bits, where 27 bits represents 27 current units or 27 standard currents. When the verification error bit current Iverok_q is greater than the reference current Ibase_13, Vercont is output. <13> =1, otherwise Vercont <13> =0.

[0082] exist Figure 2A-2D In the example shown, the verification standard of the VFC circuit is 27b, meaning that the maximum current that the VFC circuit can compare is 27 standard currents, and only one maximum current level can be set. During the operation of the VFC circuit, each quantization unit is active regardless of whether the verification error bit current Iverok_q reaches 27 standard currents. If the verification error bit current Iverok_q does not reach 27 standard currents during the entire verification process, the quantization unit with a larger reference current actually consumes unnecessary power.

[0083] Figure 2A-2D The example shown is for illustrative purposes only. The number of quantization units in a VFC circuit can be set as needed. When there are many quantization units, they can be grouped, with each group's quantization units working simultaneously, and different groups working concurrently. This can reduce the consumption of unnecessary power to some extent, but it will reduce the operating speed and extend the processing time.

[0084] Figure 3 This is a block diagram of a verification error bit quantization circuit according to an embodiment of the present invention. (Reference) Figure 3As shown, the verification error bit quantization circuit 300 of the semiconductor memory in this embodiment of the invention includes a mode selection unit 310, a most significant bit quantization unit 320, a least significant bit quantization unit 330 and a middle bit quantization unit 340 connected in sequence. The mode selection unit 310 is adapted to select one of at least two verification standards of different sizes as the verification standard signal for the verification error bit quantization circuit 300. The most significant bit quantization unit 320 is coupled to the mode selection unit 310 and is configured to compare the verification standard signal and the verification error bit signal and generate a first comparison result, and output a first enable signal based on the first comparison result. The first enable signal is used to control the least significant bit quantization unit 330 to be turned on or off. The least significant bit quantization unit 330 is configured to, when the least significant bit quantization unit 330 is controlled to be turned on, compare the verification error bit signal and the first reference signal to generate a second comparison result, and output a second enable signal based on the second comparison result. The second enable signal is used to control the intermediate bit quantization unit 340 to be turned on or off. The intermediate bit quantization unit 340 is configured to, when the intermediate bit quantization unit 340 is controlled to be turned on, compare the verification error bit signal and the second reference signal to generate a third comparison result, wherein the second reference signal is greater than the first reference signal and less than the verification standard signal.

[0085] Figure 4A This is a schematic diagram of the mode selection unit in a verification error bit quantization circuit according to an embodiment of the present invention. (Reference) Figure 4A As shown, the mode selection unit 410 is an inverter. Its input terminal 411 is connected to a verification standard Model_sel, and its output terminal 412 is connected to another verification standard Model_selb. Clearly, Model_sel and Model_selb are inverses of each other. If Model_sel is 1, then Model_selb is 0; if Model_sel is 0, then Model_selb is 1. By controlling the input signal of this inverter, one of Model_sel and Model_selb can be set to 0, and the other to 1.

[0086] Figure 4A The illustration shows an embodiment where one of two verification criteria of different sizes is selected as the verification criterion signal. For embodiments with more than two verification criteria, a corresponding mode selection unit 410 can be designed to implement the function of selecting one of more than two verification criteria.

[0087] Figure 4B This is a schematic diagram of the highest-order quantization unit in a verification error bit quantization circuit according to an embodiment of the present invention. (Reference) Figure 4BAs shown, the most significant bit quantization unit 420 includes two input terminals 421 and 422 and one output terminal 423. Input terminal 421 can be connected to the verification error bit signal Verok_q, and input terminal 422 can be connected to the verification standard signal Ver_s. The most significant bit quantization unit 420 is adapted to compare the verification error bit signal Verok_q and the verification standard signal Ver_s, and outputs a first comparison result Vercont from the output terminal 423. <13> .

[0088] This invention does not limit whether the verification error bit signal Verok_q and the verification standard signal Ver_s are current or voltage signals. It can be understood that the verification error bit signal Verok_q and the verification standard signal Ver_s can be the same type of signal, for example, both voltage signals or both current signals. In a preferred embodiment, the verification error bit signal Verok_q is a current signal from the page buffer, and the verification standard signal Ver_s is a current signal corresponding to a certain verification standard. This verification standard is the verification standard of the verification error bit quantization circuit, used to limit the maximum current of the verification error bit current that the verification error bit quantization circuit can quantize.

[0089] refer to Figure 4B As shown, input terminal 422 is connected to two verification standards, Model_sel and Model_selb. Model_sel corresponds to 27b, i.e., 27 units of standard current, and Model_selb corresponds to 10b, i.e., 10 units of standard current. That is, the verification standard corresponding to Model_sel is larger, and the verification standard corresponding to Model_selb is smaller. At the same time, according to... Figure 4A As shown in the mode selection unit, only one of the verification criteria corresponding to Model_sel and Model_selb will be selected, which will be used as the verification criterion signal Ver_s input from input terminal 422 to the highest bit quantization unit 420.

[0090] According to the above embodiments, a suitable verification standard signal Ver_s can be selected from multiple verification standards for the verification error bit quantization circuit. Compared to a VFC circuit with only one verification standard, the verification error bit quantization circuit of this embodiment can flexibly switch verification standard signals.

[0091] refer to Figure 4B As shown, the first comparison result Vercont output by the highest-order quantization unit 420 <13> This is equivalent to the quantization result of the highest bit. For ease of explanation, Figure 4B The number 13 in the text corresponds to Figure 2A-2DThe example shown, that is, the verification error bit quantization circuit, includes a total of 14 quantization units. However, this number 13 is merely an example and is not intended to limit the number of quantization units in the verification error bit quantization circuit of this invention; the specific number of quantization units can be set as needed. Figure 4B In the embodiment shown, the most significant quantization unit 420 corresponds to the quantization unit with the largest reference signal in the verification error bit quantization circuit, and its output is the first comparison result Vercont. <13> It is the 14th bit of the final output, i.e., the highest bit.

[0092] refer to Figure 4B As shown, the highest-order quantization unit 420 quantizes according to the first comparison result Vercont <13> Output the first enable signal AB <max>In this embodiment, the first enable signal AB <max>The first comparison result is Vercont. <13> The opposite signal, Figure 4B The output signal A of the highest-order quantization unit 420 is indicated in the figure. <max>Equal to the first comparison result Vercont <13> .

[0093] Figure 5 This is a schematic diagram of the least significant bit quantization unit in a verification error bit quantization circuit according to an embodiment of the present invention. (Reference) Figure 5 As shown, the least significant bit quantization unit 510 includes three input terminals 511-513 and one output terminal 514. The verification error signal Verok_q is connected to input terminal 511; the most significant bit quantization unit 420 outputs a first enable signal AB. <max>Connected to input terminal 512, the first enable signal AB <max>This is used to control the enabling or disabling of the least significant bit quantization unit 510; the first reference signal Ibase_0 is connected to the input terminal 513. When the least significant bit quantization unit 510 is enabled, it compares the verification error bit signal Verok_q with the first reference signal Ibase_0 to generate a second comparison result Vercont. <0> .exist Figure 5 In the embodiment shown, output terminal 514 outputs a second enable signal A. <0> When the fourth enable signal A <max>When = 1, the second comparison result Vercont <0> Equal to the second enable signal A <0> .

[0094] exist Figure 5 In the illustrated embodiment, the first reference signal Ibase_0 corresponds to 1b, i.e., one unit of standard current. Therefore, the least significant bit quantization unit 510 corresponds to the quantization unit with the smallest reference signal in the error-verification bit quantization circuit, and its output second comparison result Vercont... <0> It is the 0th bit of the final output result, i.e., the least significant bit.

[0095] Combination Figure 4B and Figure 5 As shown, when the verification error bit signal Verok_q is less than the verification standard signal Ver_s, the first comparison result Vercont output by the most significant bit quantization unit 420 is... <13> If it is 0, then the first enable signal AB <max>The value is 1. Based on this first enable signal AB... <max>The least significant bit quantization unit 510 is enabled, and it compares the verification error bit signal Verok_q with the first reference signal Ibase_0. In some embodiments, when the verification error bit signal Verok_q is greater than the first reference signal Ibase_0, the second comparison result Vercont... <0> If the result is 1, then the second comparison result is Vercont. <0> The value is 0. After the least significant bit quantization unit 510 completes the comparison, it outputs the second enable signal A. <0> The second enable signal A <0> Used to control the turning on or off of the intermediate bit quantization unit 610.

[0096] refer to Figure 4B and Figure 5 As shown, when the verification error bit signal Verok_q is greater than the verification standard signal Ver_s, the first comparison result Vercont output by the highest bit quantization unit 420 is... <13> If the value is 1, then the first enable signal AB <max>When the value is 0, the least significant quantization unit 510 is turned off. In this case, it indicates that the verification error bit signal Verok_q is greater than the verification standard signal Ver_s, so the error bit count is at its maximum value, and a verification failure signal (value too large) is output.

[0097] According to the above embodiments, when the verification error bit signal Verok_q is greater than the verification standard signal Ver_s, it is not necessary to enable the least significant bit quantization unit 510, thereby saving the additional power consumption of the least significant bit quantization unit 510.

[0098] Figure 6 This is a schematic diagram of the intermediate bit quantization unit in a verification error bit quantization circuit according to an embodiment of the present invention. (Reference) Figure 6 As shown, the intermediate bit quantization unit 610 includes three input terminals 611-613 and one output terminal 614. The verification error bit signal Verok_q is connected to input terminal 611; the least significant bit quantization unit 510 quantizes the bit according to the second comparison result Vercont. <0> The second enable signal A output <0> The second enable signal A is connected to input terminal 612. <0> The intermediate bit quantization unit 610 is used to control its on / off state; the second reference signal Ibase_1 is connected to the input terminal 613. When the intermediate bit quantization unit 610 is on, it compares the verification error bit signal Verok_q and the second reference signal Ibase_1 to generate a third comparison result Vercont. <1> .exist Figure 6 In the embodiment shown, output terminal 614 outputs a third enable signal A. <1> When the fourth enable signal A <max>When = 1, the third comparison result Vercont <1> Equal to the third enable signal A <1> .

[0099] exist Figure 6 In the illustrated embodiment, the second reference signal Ibase_1 corresponds to 2b, i.e., two standard currents. In some embodiments, the intermediate bit quantization unit 610 corresponds to the quantization unit in the error-verification bit quantization circuit where the reference signal is at an intermediate level, and its output is the third comparison result Vercont. <1> It is the first digit of the final output result, adjacent to the 0th and 2nd digits.

[0100] Figure 6 This is not used to limit the specific size of the second reference signal Ibase_1. As needed, the second reference signal Ibase_1 can be set to any value greater than the first reference signal Ibase_0 and less than the verification standard signal Ver_s.

[0101] Combination Figure 5-6 As shown, when the verification error bit signal Verok_q is greater than the first reference signal Ibase_0, the least significant bit quantization unit 510 outputs the second comparison result Vercont. <0> The value is 1, according to the second comparison result Vercont <0> Output the second enable signal A <0> The value is also 1, enabling the intermediate bit quantization unit 610. The intermediate bit quantization unit 610 compares the verification error bit signal Verok_q with the second reference signal Ibase_1. In some embodiments, when the verification error bit signal Verok_q is greater than the second reference signal Ibase_1, the third comparison result Vercont... <1> If the result is 1, then the third comparison result is Vercont. <1> It is 0.

[0102] In these embodiments, the second reference signal Ibase_1 is greater than the first reference signal Ibase_0, and the second reference signal Ibase_1 is less than or equal to the verification standard signal Ver_s.

[0103] Combination Figure 4B As shown, when the verification standard signal Ver_s corresponds to 10 standard currents, the magnitude of the second reference signal Ibase_1 in the intermediate bit quantization unit 610 is equal to the verification standard signal Ver_s. This verification error bit quantization circuit may consist of only one most significant bit quantization unit 420, one least significant bit quantization unit 510, and one intermediate bit quantization unit 610. In these embodiments, the least significant bit quantization unit 510, the intermediate bit quantization unit 610, and the most significant bit quantization unit 420 are structurally adjacent and connected sequentially.

[0104] In some embodiments, the verification error bit quantization circuit of the present invention may include a plurality of intermediate bit quantization units 610. For example, it may include a most significant bit quantization unit 420, a least significant bit quantization unit 510 and a plurality of intermediate bit quantization units 610 connected in sequence. The magnitude of the reference signal of these intermediate bit quantization units 610 is located between the first reference signal Ibase_0 and the verification standard signal Ver_s, and each reference signal is different, gradually increasing from the least significant bit to the most significant bit.

[0105] In some embodiments, the verification error bit quantization circuit of the present invention may further include an intermediate higher bit quantization unit. Figure 7 This is a schematic diagram of the structure of the intermediate higher-order quantization unit in a verification error bit quantization circuit according to an embodiment of the present invention. (Reference) Figure 7 As shown, the intermediate higher-order quantization unit 710 includes three input terminals 711-713 and one output terminal 714. The verification error bit signal Verok_q is connected to input terminal 711. In embodiments including the intermediate higher-order quantization unit 710, the intermediate bit quantization unit 610 also outputs a third enable signal A based on the comparison result. <1> The third enable signal A is connected to input terminal 712. <1> This is used to control the on / off state of the intermediate higher-order quantization unit 710; the third reference signal Ibase_2 is connected to the input terminal 713. When the intermediate higher-order quantization unit 710 is on, it compares the verification error bit signal Verok_q and the third reference signal Ibase_2 to generate a fourth comparison result Vercont. <2> .exist Figure 7 In the embodiment shown, output terminal 714 outputs an enable signal A. <2> When the fourth enable signal A <max>When = 1, the fourth comparison result Vercont <2> Equal to enable signal A <2> .

[0106] Among them, the third reference signal Ibase_2 is greater than the second reference signal Ibase_1, and the third reference signal Ibase_2 is less than or equal to the verification standard signal Ver_s. Structurally, the intermediate higher bit quantization unit 710 is adjacent to the intermediate bit quantization unit 610.

[0107] exist Figure 7 In the illustrated embodiment, the third reference signal Ibase_2 corresponds to 12b, i.e., 12 standard currents. In some embodiments, the intermediate higher-order quantization unit 710 corresponds to the quantization unit in the error-verification bit quantization circuit where the reference signal is at an intermediate level, and its output is the fourth comparison result Vercont. <2> It is the second digit in the final output, adjacent to the first and third digits.

[0108] for Figure 7 In the illustrated embodiment, since the third reference signal Ibase_2 is greater than 10 bits, if the intermediate higher-order quantization unit 710 is enabled, then in Figure 4B The highest-order quantization unit 420 shown must select a larger verification standard signal Ver_s, that is, the verification standard signal Ver_s corresponds to 27b.

[0109] Combination Figure 6 and Figure 7 When the verification error bit signal Verok_q is greater than the second reference signal Ibase_1, the intermediate bit quantization unit 610 outputs the third comparison result Vercont. <1> The third enable signal A is 1. <1> Also set to 1, the intermediate higher-order quantization unit 710 is enabled. If the verification error bit signal Verok_q is less than the second reference signal Ibase_1, then the third comparison result Vercont output by the intermediate bit quantization unit 610 is... <1> The value is 0, and the third enable signal A is... <1> It is also 0, and the intermediate higher-order quantization unit 710 is turned off.

[0110] According to the above embodiment, the intermediate bit quantization unit 610 is turned on only when the verification error bit signal Verok_q is greater than the first reference signal Ibase_0, and the intermediate higher bit quantization unit 710 is turned on only when the verification error bit signal Verok_q is greater than the second reference signal Ibase_1. In other words, the intermediate bit quantization unit 610 and the intermediate higher bit quantization unit 710 are only turned on when necessary and turned off when unnecessary, thereby saving power consumption.

[0111] According to the above embodiments, the least significant quantization unit 510 represents the least significant quantization unit among the plurality of quantization units, the middle quantization unit 610 represents the lower quantization unit among the plurality of quantization units, the middle higher quantization unit 710 represents the higher quantization unit among the plurality of quantization units, and the most significant quantization unit 420 represents the most significant quantization unit among the plurality of quantization units.

[0112] In some embodiments, when the intermediate bit quantization unit 610 is enabled, the least bit quantization unit 510 is disabled, thereby further saving power consumption.

[0113] In some embodiments, when the intermediate higher-order quantization unit 710 is turned on, the intermediate-order quantization unit 610 is turned off, thereby further saving power consumption.

[0114] refer to Figure 4B As shown, in some embodiments, the most significant bit quantization unit 420 of the present invention further quantizes based on the first comparison result Vercont. <13> Output the fourth enable signal A <max>. refer to Figure 5 As shown, the least significant bit quantization unit 510 in this embodiment further includes a first OR gate 515, the input of which is connected to the fourth enable signal A. <max>Second enable signal A <0> The output of the first OR gate 515 is the result of the second comparison, Vercont. <0> . refer to Figure 6 As shown, the intermediate bit quantization unit 610 in this embodiment further includes a second OR gate 615, the input of which is connected to a fourth enable signal A. <max>and the third enable signal A <1> The output of the second OR gate 615 is the result of the third comparison, Vercont. <1> .

[0115] Combination Figure 3 As shown, the most significant quantization unit 320 is connected to the least significant quantization unit 330, as well as the intermediate quantization unit 340 and the intermediate higher quantization unit 350, to output the fourth enable signal A. <max>This applies to each quantization unit. It can be understood that, in embodiments with multiple quantization units, the most significant quantization unit 320 outputs the fourth enable signal A. <max>To each quantization unit.

[0116] According to the above embodiments, regardless of the verification standard signal Ver_s, when the verification error bit signal Verok_q is greater than the verification standard signal Ver_s, the fourth enable signal A... <max>=1, then regardless of the comparison result between the least significant quantization unit 510 and the intermediate quantization unit 610, the final output second comparison result Vercont will be 1. <0> Comparison results with the third Vercont <1> Both are 1. At this time, due to the first enable signal AB <max>=0, the least significant quantization unit 510 is turned off, and correspondingly the intermediate quantization unit 610 and the intermediate higher quantization unit 710 are also turned off.

[0117] In some embodiments, reference Figure 7 As shown, the intermediate higher-order quantization unit 710 also includes a third OR gate 715, the input of which is connected to a fourth enable signal A. <max>and the next bit enable signal A output by the intermediate higher-order quantization unit 710 <2> The output of the third OR gate 715 is the result of the fourth comparison, Vercont. <2> The next enable signal here is A. <2> It can be used as an enable signal for a higher-order quantization unit adjacent to the intermediate higher-order quantization unit 710. When A <max>When = 0, Vercont <2> =A <2> If there is no higher-order quantization unit adjacent to the intermediate higher-order quantization unit 710, then A <2> It is not used as an enable signal.

[0118] Figure 8 This is a schematic diagram of the enable signal control circuit in a quantization circuit for verifying error bits according to an embodiment of the present invention. This enable signal control circuit is part of the quantization circuit and can be a part of the most significant bit quantization unit 420, the least significant bit quantization unit 510, the intermediate bit quantization unit 610, and the intermediate higher bit quantization unit 710. (See reference) Figure 8 As shown, the first enable signal AB <max>For example, the enable signal control circuit includes at least three transistors T1, T2, and T3, and the first enable signal AB <max>The error verification signal Verok_q is connected to the base of transistor T1, and the error bit signal is connected to the base and drain of transistor T2. When the first enable signal AB... <max>When the value is 0, transistor T1 is turned off, thereby turning off the enable signal control circuit, for example, turning off the least significant bit quantization unit; when the first enable signal AB... <max>When the value is 1, transistor T1 is turned on, thereby enabling the circuit controlled by the enable signal, for example, turning on the least significant bit quantization unit. When different verification standard signals Ver_s are selected, the first enable signal AB... <max>The magnitudes of the corresponding verification error bit signal Verok_q are different, which allows control over the activation and deactivation of the quantization circuit under different verification standards.

[0119] Understandable. Figure 8 The diagram shown is merely an example. Based on the ideas of this invention, techniques in this field can be used to control the quantization unit to be turned on or off according to an enable signal, and the circuit structure is not limited to the one described above.

[0120] Figure 9A This is a schematic diagram of the intermediate bit quantization unit in a verification error bit quantization circuit according to an embodiment of the present invention. Figure 9B This is a schematic diagram of the structure of the intermediate higher-order quantization unit in a verification error bit quantization circuit according to an embodiment of the present invention. The verification error bit quantization circuit of this embodiment includes multiple intermediate bit quantization units and intermediate higher-order quantization units, corresponding to quantization units where the reference signal is at an intermediate level. The intermediate bit quantization units and intermediate higher-order quantization units are adjacent to each other. Figure 9A In the quantization, the i-th quantization unit represents the intermediate bit quantization unit. Figure 9B In this embodiment, the (i+1)th quantization unit represents the intermediate higher-order quantization unit. Assuming the quantization units are connected sequentially according to the reference signal from low to high, the reference signal of the ith quantization unit is less than the reference signal of the (i+1)th quantization unit.

[0121] refer to Figure 9A As shown, the i-th quantization unit mainly includes a comparator 910. The input terminal 911 of the comparator 910 is connected to the enable signal A output by the (i-1)-th quantization unit. <i-1>The input terminal 912 is connected to the reference signal Vbias. The output terminal 913 outputs the comparison result Vercont. In this case, the (i-1)th quantization unit can be an intermediate bit quantization unit, whose corresponding reference signal is less than the reference signal of the ith quantization unit. In this case, the ith quantization unit is an intermediate higher bit quantization unit.

[0122] For the i-th quantization unit, the enable signal A output by the (i-1)-th quantization unit is... <i-1>This serves as the enable signal for the i-th quantization unit. When the verification error bit signal Verok_q is greater than the reference signal of the (i-1)-th quantization unit, the enable signal A... <i-1>=1, enabling the i-th quantization unit. The i-th quantization unit compares the verification error bit signal Verok_q with the reference signal Vbias. If the verification error bit signal Verok_q is greater than the reference signal Vbias Then the comparison result of the i-th quantization unit, Vercont =1, and enable signal A =1. Enable signal A It is also connected to the base of transistor T4 via NAND gate 914, together with the system voltage VDD, to enable signal A. When = 1, the NAND gate 914 outputs 0, turning off transistor T4 and thus turning off the i-th quantization unit.

[0123] refer to Figure 9B As shown, the (i+1)th quantization unit mainly includes a comparator 920. The input terminal 922 of the comparator 920 is connected to the enable signal A output by the i-th quantization unit. The input terminal 921 is connected to the reference signal Vbias.<i+1> The output terminal 913 outputs the comparison result Vercont.<i+1> When the i-th quantization unit is the middle bit quantization unit, the (i+1)-th quantization unit is the middle higher bit quantization unit.

[0124] When enable signal A When the value is 1, transistor T1 is turned on, thereby enabling the (i+1)th quantization unit. The reference signal Vbias of the (i+1)th quantization unit...<i+1> The reference signal Vbias greater than the i-th quantization unit The (i+1)th quantization unit then compares and verifies the error bit signal Verok_q with the reference signal Vbias.<i+1> If the verification error bit signal Verok_q is less than the reference signal Vbias<i+1> Then comparator 920 outputs enable signal A.<i+1> =0; otherwise, output enable signal A.<i+1> =1. Enable signal A<i+1> It is also connected to the base of transistor T4 via NAND gate 924, together with the system voltage VDD. When the enable signal A...<i+1> When = 1, the NAND gate 924 outputs 0, transistor T4 is turned off, thus turning off the (i+1)th quantization unit.

[0125] according to Figure 9A and 9B The quantization unit shown can be activated by only one of multiple quantization units based on the relationship between the verification error bit signal Verok_q and the reference signal, thereby maximizing power saving and improving efficiency.

[0126] In some embodiments, the verification error bit quantization circuit of the present invention may further include a code conversion unit, which is adapted to convert the thermometer code into binary code. The inputs of the code conversion unit, from the high bit to the low bit, are the first comparison result, the third comparison result, and the second comparison result, respectively.

[0127] In some embodiments, the verification error bit quantization circuit of the present invention may further include an accumulator adapted to accumulate multiple binary codes obtained from the code conversion unit.

[0128] refer to Figure 3 As shown, in the verification error bit quantization circuit 300, each quantization unit outputs the comparison result to the code conversion unit 360. The code conversion unit 360 transmits the converted binary code to the accumulator 370, which accumulates multiple binary codes and outputs the final result.

[0129] Figure 10 This is a schematic diagram of the code conversion unit and accumulator in the error-checking bit quantization circuit of an embodiment of the present invention. (Reference) Figure 10 As shown, the input of the code conversion unit 1010 is connected to multiple comparison results of the quantization unit described above. According to the embodiment described above, the comparison results of the 14 quantization units can be represented by Vercont<0:13>, where Vercont... <13> It is the first comparison result output by the highest-order quantization unit 420, representing the highest-order bit; Vercont <0> Vercont<1:12> is the second comparison result output by the least significant bit quantization unit 510, representing the least significant bit; Vercont<1:12> is the third comparison result output by multiple intermediate bit quantization units 610, which can be further divided into lower bits and higher bits. The lower bits are the third comparison result output by the intermediate bit quantization unit 610, and the higher bits are the fourth comparison result output by the intermediate higher bit quantization unit 710.

[0130] The first comparison result, the third comparison result, and the second comparison result can be represented sequentially as the high-order bits of the thermometer code. For an embodiment including a fourth comparison result, the first comparison result, the third comparison result, the fourth comparison result, and the second comparison result can be represented sequentially as the high-order bits of the thermometer code.

[0131] exist Figure 10 In the embodiment shown, the output of the code conversion unit 1010 is a 6-bit binary code data data<5:0>. Figure 10 It is not used to limit the specific number of bits in the binary code.

[0132] The binary code data data<5:0> is input to the accumulator 1020. In some embodiments, a semiconductor memory can be subjected to multiple verification error bit quantizations, each time using the verification error bit quantization circuit of the present invention to obtain an error bit count. The accumulator 1020 can sum the multiple error bit counts as the final count result of the semiconductor memory. Because multiple verification error bit quantizations are used, the current required for each quantization is small, thereby further reducing the power consumption of the circuit.

[0133] Figure 11 This is a structural block diagram of a semiconductor memory according to an embodiment of the present invention. (Reference) Figure 11 As shown, the semiconductor memory 1100 includes a memory array 1110 and peripheral circuitry 1120. The peripheral circuitry 1120 is coupled to the memory array 1110 and is used to control the memory operations of the memory array 1110. The peripheral circuitry 1120 is configured with the aforementioned error-checking bit quantization circuit. Therefore, the foregoing description and accompanying drawings regarding the error-checking bit quantization circuit can be used to illustrate the semiconductor memory of the present invention.

[0134] Figure 12 This is an exemplary flowchart of a verification error bit quantization method for a semiconductor memory according to an embodiment of the present invention. This verification error bit quantization method can be executed by the verification error bit quantization circuit described above; therefore, the accompanying drawings and related descriptions can be used to illustrate the verification error bit quantization method of this embodiment, and repeated content will not be elaborated upon. Reference Figure 12 As shown, the verification error bit quantization method of this embodiment includes the following steps:

[0135] Step S1210: Select one of at least two verification criteria of different sizes as the verification criterion signal.

[0136] This step can be performed by Figure 4A The mode selection unit 410 shown is used to perform this.

[0137] Step S1220: Compare the verification error bit signal and the verification standard signal and generate a first comparison result. Output a first enable signal based on the first comparison result. The first enable signal is used to control the opening or closing of the least significant bit quantization unit.

[0138] This step can be performed by Figure 4B The highest-order quantization unit 420 shown is used to perform this step. The lowest-order quantization unit in this step can be... Figure 5 The least significant quantization unit shown is 510.

[0139] Step S1230: When the least significant bit quantization unit is controlled to be on, the least significant bit quantization unit compares the verification error bit signal and the first reference signal to generate a second comparison result, and outputs a second enable signal according to the second comparison result. The second enable signal is used to control the opening or closing of the intermediate bit quantization unit.

[0140] The intermediate bit quantization unit in this step can be... Figure 6 The intermediate bit quantization unit 610 is shown.

[0141] Step S1240: When the intermediate bit quantization unit is controlled to be turned on, the intermediate bit quantization unit compares the verification error bit signal and the second reference signal to generate a third comparison result, wherein the second reference signal is greater than the first reference signal and the second reference signal is less than or equal to the verification standard signal.

[0142] In some embodiments, the method may further include:

[0143] Step S1250: When the intermediate bit quantization unit is controlled to be turned on, the intermediate bit quantization unit also outputs a third enable signal according to the third comparison result. The third enable signal is used to control the turning on or off of the intermediate higher bit quantization unit.

[0144] The intermediate higher-order quantization unit in this step can be... Figure 7 The intermediate bit quantization unit 710 is shown.

[0145] Step S1260: When the intermediate higher bit quantization unit is controlled to be turned on, the intermediate higher bit quantization unit compares the verification error bit signal and the third reference signal to generate a fourth comparison result, wherein the third reference signal is greater than the second reference signal and the third reference signal is less than or equal to the verification standard signal, and the intermediate higher bit quantization unit is adjacent to the intermediate bit quantization unit.

[0146] In some embodiments, when the verification error bit signal is less than the verification standard signal, the first enable signal enables the least significant bit quantization unit.

[0147] In some embodiments, when the verification error bit signal is greater than the first reference signal, the second enable signal enables the intermediate bit quantization unit.

[0148] In some embodiments, when the intermediate bit quantization unit is controlled to be on, the least bit quantization unit is turned off.

[0149] In some embodiments, when the verification error bit signal is greater than the second reference signal, the third enable signal enables the intermediate higher bit quantization unit.

[0150] In some embodiments, the intermediate bit quantization unit is turned off when the intermediate higher bit quantization unit is controlled to be on.

[0151] In some embodiments, the method further includes outputting a fourth enable signal based on the first comparison result. When the verification error bit signal is greater than the verification standard signal, the fourth enable signal turns off the least significant bit quantization unit, the middle bit quantization unit, and the middle higher bit quantization unit.

[0152] The verification error bit quantization method according to the embodiments of the present invention can flexibly switch the verification standard signal. Based on the actual magnitude of the verification error bit signal, only the necessary quantization units are turned on and unnecessary quantization units are turned off, which can minimize the power consumption of the verification error bit quantization function.

[0153] Figure 13 This is a schematic diagram of the power consumption test results of a verification error bit quantization circuit and method according to an embodiment of the present invention. It includes three curves located in three coordinate systems. In each coordinate system, the horizontal axis represents the count value of the failure bits, and the vertical axis represents the average current; the lower the average current, the lower the power consumption corresponding to the test result. Curve 1310 represents the power consumption test result with the current VFC circuit, with the vertical axis unit being mA; curve 1320 represents the power consumption test result using the verification error bit quantization circuit and method of the present invention, with a verification standard of 25 bits, with the vertical axis unit being mA; curve 1330 represents the power consumption test result using the verification error bit quantization circuit and method of the present invention, with a verification standard of 10 bits, with the vertical axis unit being μA. (Reference) Figure 13 As shown, curve 1330 clearly indicates the lowest power consumption. Table 1 below is based on... Figure 13 The results were obtained by comparing the peak current (peak I) and average current (average I) obtained from curves 1310, 1320, and 1330.

[0154] Table 1:

[0155]

[0156] Where 6 (peak I) represents the peak current when the error bit count is 6, 11 (peak I) represents the peak current when the error bit count is 11, 16 (peak I) represents the peak current when the error bit count is 16, and 16-6 (average I) represents the average current between the error bit counts of 6 and 16.

[0157] According to the results in Table 1, for a die comprising 4 planes, each plane containing 8 units, when the verification standard is 25b, the peak current per unit can be reduced by 0.364mA. When the misalignment count is 11, the total peak current reduction is 11.648mA. When the verification standard is 10b, the peak current per unit can be reduced by 1.2mA. When the misalignment count is 16, the total peak current reduction is 38.4mA.

[0158] Compared to the current VFC circuit, when the verification standard is 25b, the average current can be reduced by I_sp = 10.5uA; when the verification standard is 10b, the average current can be reduced by I_sp = 47.7uA.

[0159] Although the present invention has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are merely illustrative of the invention, and various equivalent changes or substitutions can be made without departing from the spirit of the invention. Therefore, any changes or modifications to the above embodiments within the essential spirit of the invention will fall within the scope of the claims of this application. < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max> < / max>

Claims

1. A semiconductor memory error-verification bit quantization circuit, characterized in that, The quantization circuit comprises at least one inverter and a plurality of quantization units, the plurality of quantization units comprising a highest bit quantization unit, a lowest bit quantization unit and at least one middle bit quantization unit, wherein The at least one inverter selects one verification standard signal from at least two verification standard signals of different sizes according to an input signal of itself, and transmits the verification standard signal to the highest bit quantization unit; The highest bit quantization unit receives the verification standard signal and a verification error bit signal, compares the verification standard signal and the verification error bit signal to generate a first comparison result, and outputs a first enable signal according to the first comparison result; The lowest bit quantization unit is connected with the highest bit quantization unit, receives the first enable signal, and receives the verification error bit signal and a first reference signal; when being turned on based on the first enable signal, the lowest bit quantization unit compares the verification error bit signal and the first reference signal to generate a second comparison result, and outputs a second enable signal according to the second comparison result; The at least one middle bit quantization unit is connected with the lowest bit quantization unit, receives the second enable signal, and receives the verification error bit signal and a second reference signal; when being turned on based on the second enable signal, the at least one middle bit quantization unit compares the verification error bit signal and the second reference signal to generate a third comparison result; The first reference signal is the lowest bit standard signal that can be quantized by the quantization circuit, and is smaller than the verification standard signal; the second reference signal is larger than the first reference signal and smaller than the verification standard signal.

2. The verify error bit quantization circuit of claim 1, wherein, The at least one middle bit quantization unit comprises a middle bit quantization unit and a middle higher bit quantization unit arranged adjacent to the middle bit quantization unit; The middle higher bit quantization unit is connected with the middle bit quantization unit, receives a third enable signal output by the middle bit quantization unit according to the third comparison result, and receives the verification error bit signal and a third reference signal; when being turned on based on the third enable signal, the middle higher bit quantization unit compares the verification error bit signal and the third reference signal to generate a fourth comparison result; The third reference signal is larger than the second reference signal and smaller than or equal to the verification standard signal.

3. The verify error bit quantization circuit of claim 1, wherein, The highest bit quantization unit comprises a first comparator and a first inverter; wherein The first comparator receives the verification standard signal and the verification error bit signal through two input ends respectively, compares the verification standard signal and the verification error bit signal to generate a first comparison result, and outputs the first comparison result at an output end of the first comparator; The first inverter is connected with the output end, receives the first comparison result, and outputs the first enable signal according to the first comparison result; the first enable signal is an inverse signal of the first comparison result.

4. The verify error bit quantization circuit of claim 3, wherein, The lowest bit quantization unit comprises a second comparator and a first enable signal control circuit, wherein The first enable signal control circuit is connected with the output end of the first inverter, receives the first enable signal, and controls the turning on or turning off of the lowest bit quantization unit based on the first enable signal; The second comparator receives the verification error bit signal and a first reference signal when the first enable signal control circuit controls the lowest bit quantization unit to be turned on based on the first enable signal; and compares the verification error bit signal and the first reference signal to generate a second comparison result.

5. The verify error bit quantization circuit of claim 4, wherein, The lowest bit quantization unit further comprises a second inverter connected to an output terminal of the second comparator to receive the second comparison result; and outputs the second enable signal according to the second comparison result; the second enable signal is an inverse signal of the second comparison result.

6. The verify error bit quantization circuit of claim 4, wherein, The first enable signal control circuit comprises at least a transistor T1, a transistor T2 and a transistor T3; a drain of the transistor T1 is connected to a source of the transistor T2; a drain of the transistor T2 is connected to a drain of the transistor T3; a gate of the transistor T1 is connected to an output terminal of the first inverter; a gate of the transistor T2 is connected to the verification error bit signal; and a gate of the transistor T3 is connected to the first reference signal. The transistor T1 is turned on or turned off based on the first enable signal to control the lowest bit quantization unit to be turned on or turned off; the transistor T2 is turned on based on the verification error bit signal being in an on state; and the transistor T3 is turned on based on the first reference signal being in an on state; the verification error bit signal and the first reference signal are transmitted to the second comparator through the transistor T2 and the transistor T3 respectively when the transistor T1 is turned on.

7. The verify error bit quantization circuit of claim 6, wherein, The first enable signal control circuit further comprises a transistor T4 and a first NAND gate; wherein The drain of the transistor T4 is connected to the source of the transistor T3; a gate of the transistor T4 is connected to an output terminal of the first NAND gate; and the transistor T4 is turned on or turned off based on the output of the first NAND gate; the transistor T4 is turned off to turn off the intermediate bit quantization unit when the first NAND gate outputs 0.

8. The verify error bit quantization circuit of claim 7, wherein, The first NAND gate has two input terminals connected to a system voltage VDD and a second enable signal respectively.

9. The verify error bit quantization circuit of claim 8, wherein, Each of the at least one intermediate bit quantization unit has the same structure as the lowest bit quantization unit.

10. The verify error bit quantization circuit of claim 9, wherein, The at least one intermediate bit quantization unit is connected in sequence from low to high according to reference signals; a reference signal of an i-th intermediate bit quantization unit is smaller than that of an i+1-th intermediate bit quantization unit; and the i-th intermediate bit quantization unit is controlled by the i-1-th intermediate bit quantization unit; wherein the i-1-th intermediate bit quantization unit is a non-lowest bit quantization unit or the lowest bit quantization unit.

11. The verify error bit quantization circuit of claim 1, wherein, The highest bit quantization unit further outputs a fourth enable signal according to the first comparison result. The lowest bit quantization unit further comprises a first OR gate having input terminals connected to the fourth enable signal and the second enable signal; and an output of the first OR gate is used as the second comparison result output by the lowest bit quantization unit.

12. The verify error bit quantization circuit of claim 2, wherein, The highest bit quantization unit further outputs a fourth enable signal according to the first comparison result. The intermediate bit quantization unit further comprises a second OR gate, an input of the second OR gate is connected with the fourth enable signal and the third enable signal, and an output of the second OR gate is taken as the third comparison result output by the intermediate bit quantization unit.

13. The verify error bit quantization circuit of claim 1, wherein, The quantization circuit further comprises a code conversion unit configured to convert the thermometer code into binary codes, wherein inputs of the code conversion unit from high bit to low bit are the first comparison result, the third comparison result and the second comparison result in sequence.

14. The verify error bit quantization circuit of claim 13, wherein, The quantization circuit further comprises an accumulator configured to accumulate the binary codes obtained from the code conversion unit.

15. A verification error bit quantization method of a semiconductor memory, selecting one of at least two verification criteria of different sizes as a highest bit verification criterion signal; comparing the verification error bit signal and the verification criterion signal to generate a first comparison result; outputting a first enable signal according to the first comparison result; judging whether the verification error bit signal needs to be compared with a first reference signal based on the first enable signal; when it is judged based on the first enable signal that the verification error bit signal needs to be compared with the first reference signal, comparing the verification error bit signal with the first reference signal to generate a second comparison result; outputting a second enable signal according to the second comparison result; judging whether the verification error bit signal needs to be compared with a second reference signal based on the second enable signal; when it is judged based on the second enable signal that the verification error bit signal needs to be compared with the second reference signal, comparing the verification error bit signal with the second reference signal to generate a third comparison result; wherein the first reference signal is the lowest bit criterion signal that can be quantized by the method, and is smaller than the verification criterion signal; and the second reference signal is larger than the first reference signal and smaller than the verification criterion signal.

16. The method of claim 15, wherein, The method further comprises: outputting a third enable signal according to the third comparison result; judging whether the verification error bit signal needs to be compared with a third reference signal based on the third enable signal; when it is judged based on the third enable signal that the verification error bit signal needs to be compared with the third reference signal, comparing the verification error bit signal with the third reference signal to generate a fourth comparison result; wherein the third reference signal is larger than the second reference signal and smaller than or equal to the verification criterion signal.

17. The method of claim 15, wherein, The judging whether the verification error bit signal needs to be compared with the first reference signal based on the first enable signal comprises: when the verification error bit signal is smaller than the verification criterion signal, judging based on the first enable signal that the verification error bit signal needs to be compared with the first reference signal; and controlling a lowest bit quantization unit to be turned on; when the verification error bit signal is not smaller than the verification criterion signal, judging based on the first enable signal that the verification error bit signal does not need to be compared with the first reference signal.

18. The method of claim 15, wherein, The judging whether the verification error bit signal and the second reference signal need to be compared based on the second enable signal comprises: when the verification error bit signal is greater than the first reference signal, judging based on the second enable signal that the verification error bit signal and the second reference signal need to be compared; when the verification error bit signal is not greater than the first reference signal, judging based on the second enable signal that the verification error bit signal and the second reference signal do not need to be compared.

19. The method of claim 15, wherein, The method further comprises: when the verification error bit signal and the second reference signal are compared and a third comparison result is generated, turning off a lowest bit quantization unit corresponding to the first comparison result.

20. The method of claim 16, wherein, The judging whether the verification error bit signal and the third reference signal need to be compared based on the third enable signal comprises: when the verification error bit signal is greater than the second reference signal, judging based on the third enable signal that the verification error bit signal and the third reference signal need to be compared; when the verification error bit signal is not greater than the second reference signal, judging based on the third enable signal that the verification error bit signal and the third reference signal do not need to be compared.

21. The method of claim 16, wherein, The method further comprises: when the verification error bit signal and the third reference signal are compared and a fourth comparison result is generated, turning off a middle bit quantization unit corresponding to the third comparison result.

22. The method of claim 16, wherein, The method further comprises: outputting a fourth enable signal according to the first comparison result; when the verification error bit signal is greater than the verification standard signal, judging at least one of the following based on the fourth enable signal: whether the verification error bit signal and the first reference signal need to be compared; whether the verification error bit signal and the second reference signal need to be compared; whether the verification error bit signal and the third reference signal need to be compared.

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