A method for analyzing the void evolution mechanism of IGBT solder layer for locomotives based on multi-physics fields

Abstract

The present invention discloses a method for analyzing the evolution mechanism of voids in the solder layer of IGBT for locomotives based on multi-physics fields. First, according to the CT scanning of the solder layer of the locomotive IGBT module, the statistical results show that the number of voids in the solder layer of the IGBT module with different service mileages obeys the Poisson distribution, and the Poisson distribution variance λ value has a mapping relationship with the service mileage of the device; based on the void distribution law, a multi-physics simulation model of the locomotive IGBT and a mathematical description of the strains of the upper and lower surfaces of the solder layer are established, and the evolution inducement and law of random voids are studied; finally, the relationship between the void size and the evolution rate is verified based on the energy-based fatigue life model. The present invention is based on the CT scanning results of the solder layer with different service mileages, and the distribution law of voids in the solder layer is statistically obtained; the multi-physics simulation model of the locomotive IGBT and the mathematical description of the strain of the solder layer creep are established by using the statistical law, and the evolution mechanism and law of the voids are studied, providing support for guiding the device optimization design and active operation and maintenance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for analyzing the void evolution mechanism of an IGBT solder layer for a locomotive based on multi-physics field modeling. Background Art

[0002] With high railway investment and growing operating mileage, the number of locomotives in China has increased year by year. In 2018, the number of locomotives in China was 21,000, of which electric locomotives accounted for as high as 61.3%. As a key component of the locomotive, the traction converter realizes direct and alternating energy conversion through high-power insulated gate bipolar transistors (IGBTs) to achieve the starting, braking and speed control of the AC traction motor. Its reliability is directly related to the safe operation of the electric locomotive. However, due to the start and stop of the locomotive, load changes and mismatch of packaging material properties, the failure mechanism of high-power IGBTs is unclear, and it is difficult to accurately characterize the life of IGBT devices. At the same time, according to a survey by the Zhuzhou Electric Locomotive Research Institute, the failure of IGBT devices in HXD1, HXD1C and HXD1D electric locomotives accounted for 82%, 71% and 90% of the converter failures respectively. The reason is that the physical process of device performance degradation and defect generation, evolution and failure is not clearly understood. Therefore, it is urgent to conduct research on the failure evolution mechanism of IGBTs for locomotives to provide support for guiding device optimization design and active operation and maintenance.

[0003] In the existing research on the void evolution mechanism of IGBT solder layer for locomotives, there are several technical difficulties:

[0004] 1) How to calculate and count the distribution law of random voids in the solder layer under different service mileages; 2) How to use the distribution law of random voids to establish an accurate multi-physics model; 3) How to use the multi-physics model to simulate the void evolution mechanism; 4) How to obtain the strain mathematical description of solder layer creep based on the simulation results of the multi-physics model. However, existing research cannot effectively solve these problems. Summary of the invention

[0005] In view of the above problems, the purpose of the present invention is to provide a multi-physics field locomotive IGBT solder layer void evolution mechanism analysis method, using the statistical law to establish a locomotive IGBT multi-physics field simulation model and solder layer creep strain mathematical description, the study of the void evolution mechanism and law, to provide support for guiding device optimization design and active operation and maintenance, with low cost, simple calculation, simple application, strong portability and other advantages. The technical solution is as follows:

[0006] A method for analyzing the void evolution mechanism of IGBT solder layer for locomotives based on multi-physics fields comprises the following steps:

[0007] Step 1: Use CT scanning test to obtain the solder layer scanning results;

[0008] Step 2: Import the OpenCV library in Python to perform binarization on the scan results and calculate the sizes of different holes;

[0009] Step 3: Divide the voids into different sizes and draw a distribution diagram of the void quantity, showing the Poisson distribution law;

[0010] Step 4: A multi-physics model is established in COMSOL in combination with the locomotive IGBT device, and a random void that conforms to statistical results is generated in the solder layer using the built-in JAVA compiler;

[0011] Step 5: Build a multi-physics field model, perform simulations under multiple groups of different random void distributions, and analyze the strain and deformation laws under voids of different sizes;

[0012] Step 6: Based on the difference in thermal expansion coefficient between the chip and the solder layer, a mathematical description relationship for the strain on the upper and lower surfaces of the solder layer is established.

[0013] Furthermore, the step 6 specifically includes:

[0014] During the operation of the IGBT module, the module power loss P is transferred to the base plate through each layer of material to complete the heat transfer process, and the module junction temperature T J Calculated by thermal resistance, power loss and case temperature:

[0015] T J =P×Z JC +T C

[0016] Z JC =Z die +Z D-S +Z DBC +Z B-S +Z base

[0017] Among them, Z JC , Z die , Z D-S , Z DBC , Z B-S , Z base Respectively represent the thermal resistance of the junction, IGBT chip, chip solder layer, DBC, bottom plate solder layer, and substrate; T C Indicates shell temperature;

[0018] Chip temperature fluctuation ΔT d The temperature fluctuation ΔT of the chip solder layer ds It is expressed as:

[0019]

[0020] Where, ΔT d is the chip temperature fluctuation, ΔT ds Temperature fluctuation of chip solder layer, T d_max and T d_min Respectively represent the highest and lowest temperatures of the chip; T ds_max and T ds_min Respectively represent the highest and lowest temperatures of the chip solder layer; η 1 Indicates the ratio of chip temperature fluctuation to chip solder layer temperature fluctuation;

[0021] IGBT chip bottom surface strain ε d Thermal strain ε on the upper surface of the chip solder layer ds_u They are as follows:

[0022]

[0023] Among them, L d and ΔL d are the length of the IGBT chip and its change after the temperature rises; α d and α ds are the expansion coefficient of the chip and the expansion coefficient of the chip solder layer respectively; h d and h ds are the height of the chip and the chip solder layer respectively; E d and E ds are Young’s modulus of chip and chip solder layer, respectively;

[0024] The thermal strain on the lower surface of the chip solder layer is obtained using the same method as follows:

[0025]

[0026] Where, ΔT uc is the temperature fluctuation of the upper copper layer; η 2 is the ratio of the temperature fluctuation of the upper copper layer to the temperature fluctuation of the chip solder layer; α c is the expansion coefficient of the upper copper layer; h uc is the height of the upper copper layer; E uc is the Young’s modulus of the upper copper layer;

[0027] The energy-based fatigue life model is as follows, combined with the strain in the multi-physics model, to calculate the void life:

[0028] ΔW c =W f (2×N f ) -m

[0029]

[0030] Where, ΔW c is the increment of inelastic strain energy density in a single cycle; E is the Young's modulus of the chip solder layer; ε is the strain of the chip solder layer; W f is the accumulation of plastic work density in each cycle; m is a constant; N f is the void lifetime, void lifetime W f 5.5×10 6 (J / m 3 ), the constant m is 0.69, and the Young's modulus E of the chip solder layer is 5.4×10 10 (Pa).

[0031] The beneficial effects of the present invention are as follows: based on experiments, simulations and theories, the present invention firstly discusses the distribution and expansion of voids in the chip solder layer before and after the operation of a multi-chip IGBT for locomotives; secondly, a multi-physical field finite element model of a multi-chip IGBT for locomotives is established, and the strain distribution around the voids under different forms is analyzed; finally, a mathematical model is established according to the IGBT structure, which explains the reasons for the strain distribution of the chip solder layer, and has the advantages of low cost, simple calculation, simple application, strong portability, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is the CT scan result of the solder layer of the IGBT module.

[0033] Figure 2 Figure 3 shows the void size distribution in the solder layer of a new IGBT module.

[0034] Figure 3 Figure 3 shows the void size distribution in the solder layer of IGBT modules in service.

[0035] Figure 4 is the inelastic strain of voids of different sizes under power cycling.

[0036] Figure 5 Multiphysics model of a solder layer containing random voids.

[0037] Figure 6 The deformation of solder layer voids of different sizes; (a) deformation of small voids; (b) deformation of large voids.

[0038] Figure 7 Schematic diagram of the void deformation in the solder layer.

[0039] Figure 8 This is a simulation diagram of the void deformation in the solder layer.

[0040] Fig. 9Strain and life distribution of different void sizes on the solder layer surface; (a) strain distribution on the upper surface of the chip solder layer; (b) strain distribution on the lower surface of the chip solder layer; (c) maximum strain and minimum life of different void sizes.

[0041] Fig.10 The figure is a basic flow chart of the method for analyzing the void evolution mechanism of the solder layer of IGBT for locomotives based on multi-physics fields of the present invention. DETAILED DESCRIPTION

[0042] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The present invention utilizes the radiation of the CD-50BG CT tester, which loses a portion of its energy after penetrating any material. The attenuation of its radiation depends on the properties of the material and the size of the object being detected. This characteristic is used to detect defects inside the solder layer. The present invention is aimed at the multi-chip CM600HG-130HIGBT module (6500V / 600A) for locomotives. For a brand-new module, there are a large number of small-sized voids distributed inside the solder layer, which contains a very small number of large-sized voids. And after observing its distribution position, it is found that the voids are mainly distributed at the edge of the solder layer, which fully explains why the corners first begin to crack after the IGBT has been in power cycling for a period of time; for the in-service module, it can be found that the size of the module voids has increased significantly and new voids have been generated. The corners of the solder layer have evolved into cracks, and the number and size of the voids have increased significantly. When the module continues to operate, cracks and voids in the solder layer gradually expand, and the effective heat dissipation area from the chip to the heat sink in the module is reduced, resulting in an increase in the thermal resistance from the chip to the environment and an increase in the junction temperature, which causes the module to overheat and fail.

[0043] The present invention uses the Opencv toolkit imported into Python and uses its built-in functions to implement image processing, track and count the changes in the area and number of solder layer voids. According to the toolkit measurement, the total void area of ​​the new IGBT module is 12.0231mm 2 The void rate is about 0.2545%, and the total void area of ​​the IGBT module in service is 50.2392mm after the power cycle. 2, the void rate is about 1.0635%. From the statistical results, it can be obtained that the number of 0-100μm voids in the new module presents a Poisson distribution, and the number of voids in 10-20μm reaches the maximum value. As the void size increases, the corresponding number of voids decreases. The void size distribution of the new module is 0-100μm, accounting for more than 80%, and after power cycling, the number of voids in 0-50μm drops sharply, and the voids in 50-150μm increase significantly, accounting for more than 40% of the total number of voids, which shows that small voids gradually evolve into large voids. Large-sized voids will gradually expand and eventually merge with surrounding voids to form cracks, and the number is extremely small. Therefore, large voids are more likely to be distributed at the edge, making it easy for the voids to merge with surrounding voids to form cracks after expansion, thereby affecting the life of the solder layer.

[0044] From a thermodynamic point of view, the greater the curvature and the smaller the void, the higher the stress concentration in the surrounding area. However, as the void size increases, the curvature decreases, resulting in reduced stress, which may cause the void expansion rate to decrease with the increase in radius. Therefore, the expansion rate of large voids is lower than that of small voids, and small voids have a faster growth rate. In order to compare the number distribution law of different void sizes between the new module and the in-service module, mathematical and statistical analysis was performed. The number of voids of different sizes in each module follows the Poisson distribution, and its probability density function is expressed as follows:

[0045]

[0046] Among them, λ represents the average occurrence rate of random events per unit area. The number of voids under different sizes is fitted, and the fitting effect is better when λ=2 for the new module and λ=4 for the serviced module. This means that the void size distribution of the new module is mostly between 10-20μm, and the void size is relatively small, while the void size distribution of the serviced module is mostly between 30-40μm and obeys the Poisson distribution of λ=4.

[0047] Then, two IGBT modules that had been in service under the same working conditions were disassembled for verification. After the same mathematical and statistical analysis, it was found that for the void distribution of the new modules, the percentage of voids in the new modules was evenly distributed near the λ=2 Poisson distribution curve, indicating that the two modules after service obeyed the Poisson distribution of λ=2. Similarly, the distribution of the modules after service approximately obeyed the Poisson distribution of λ=4. This distribution law provides a basis for the simulation of void distribution in the subsequent finite element method. At the same time, after statistically analyzing the distribution of voids of different sizes, the parameter λ can be used to judge the fatigue degree of the solder layer.

[0048] Based on the underlying JAVA script file of COMSOL, this paper develops a void simulation model that can define the void position, void number and void size. According to the conclusion of void distribution in Section 2, the void number distribution of the new module is set to obey the Poisson distribution of λ=2; the void number of the module after service is also set to obey the Poisson distribution, and the aging degree of the module is characterized by setting the variance λ. According to the strain simulation results of the solder layer of the IGBT chip, the strain is the largest at the corners of the chip solder layer and the position where the chip solder layer and the boundary of the IGBT chip are connected, which means that the position where the corners and the boundary of the IGBT chip are connected are aged first. When the chip solder layer containing initial voids is in the power cycle process, cracks will be generated at the position below the corners of the solder layer and the boundary of the IGBT chip. When there is an initial void, the stress will gather at the tip of the void, and a high level of inelastic strain will gather in this local area, which will cause the void to gradually accelerate along the chip interface to the center of the solder layer. If there are voids around, they will merge with the surrounding voids to form cracks, causing solder layer fatigue.

[0049] From an overall observation, the strain direction of the upper surface of the chip solder layer is distributed radially with the center as the origin, and the upper surfaces of all voids are expanding outward, causing the overall voids to shift toward larger sizes. By comparing voids of different sizes, it can be found that about half of the side length of small voids is subjected to a higher level of strain, while the area of ​​large voids subjected to larger strain is less than a quarter of the side length of the void, that is, the proportion of small voids with larger strain is much greater than that of large voids, and the strain value of the edge of small voids is greater than that of large voids. From an overall observation, the strain direction of the lower surface is exactly opposite to that of the upper surface, that is, the strain direction of all voids on the lower surface gathers toward the center, and the strain at the corner of the lower surface solder layer and the boundary of the IGBT chip is the smallest, forming two extremes with the strain size of the upper surface.

[0050] For the upper surface of a single cavity in the chip solder layer, the shear strain of the side length facing the outside of the cavity is greater than the shear strain of the inside of the cavity, while the shear strain of the inside of the cavity on the lower surface is greater than the shear strain of the outside of the cavity. Due to the height difference of the chip solder layer, a pair of torques will be formed on the upper and lower surfaces to pull the cavity, causing the cavity to grow at a faster rate, causing uneven deformation of the upper and lower surfaces of the cavity, that is, the upper surface of the cavity stretches outward, and the lower surface of the cavity is compressed inward, gradually forming a Z-shaped cavity. In addition, according to the thermodynamic stress concentration effect and the numerical value of the simulation results, it can be concluded that small cavities are subjected to relatively large strains, and large cavities are subjected to relatively small strains, that is, small cavities have larger deformations than large cavities, so small cavities have faster growth rates than large cavities.

[0051] The analysis process of the present invention is as follows:

[0052] Step 1: Use CT scanning test to obtain the solder layer scanning results, such as Figure 1 shown.

[0053] Step 2: Use the OpenCV library imported into Python to binarize the scan results and count the sizes of different holes.

[0054] Step 3: Divide the voids into different sizes and draw a distribution diagram of the void quantity, showing the Poisson distribution law, such as Figure 2 The figure shows the void distribution of the solder layer of a new module, which obeys the Poisson distribution with λ=2. Figure 3 The figure shows the void distribution of the solder layer of the service module, which obeys the Poisson distribution with λ=4.

[0055] Step 4: Combine the locomotive IGBT device to establish a multi-physics model in COMSOL, and use the built-in JAVA compiler to generate random voids in the solder layer that meet statistical results, such as Figure 5 Shown is a multiphysics model of a solder layer containing random voids.

[0056] Step 5: Use the multi-physics field model to perform simulations under different random void distributions and analyze the strain and deformation laws under voids of different sizes, such as Figure 6-8 As shown, small voids have a faster growth rate than large voids, and the strain of small voids is higher than that of large voids.

[0057] Step 6: Based on the difference in thermal expansion coefficients between the chip and the solder layer, a mathematical description relationship for the strain on the upper and lower surfaces of the solder layer is established.

[0058] During the operation of the IGBT module, the module power loss P is transferred to the base plate through each layer to complete the heat transfer process. j It can be calculated by thermal resistance, power loss and case temperature, where Z die , Z D-S , Z DBC , Z B-S , Z base They represent the thermal resistances of the IGBT chip, chip solder layer, DBC, base plate solder layer, and substrate respectively.

[0059]

[0060] During the power cycle, due to the influence of thermal resistance, the temperature of the IGBT chip is significantly higher than that of other layers, and the temperature fluctuation of the chip is ΔT d The temperature fluctuation of the chip solder layer ΔT ds As follows:

[0061]

[0062] During the power cycle, the temperature of the IGBT module fluctuates, causing the IGBT chip and the chip solder layer attached to it to deform and expand and contract. However, due to the small thermal expansion coefficient (CTE value) of the IGBT chip, the IGBT chip is

[0063] The CTE values ​​between the sheet solder layers are quite different, and the strain of the chip solder layer is much greater than the strain of the IGBT chip.

[0064] IGBT chip d Thermal strain of chip solder layer ε ds_u They are expressed as follows, where L d and ΔL d They are respectively expressed as the IGBT chip length and the change after the temperature rises.

[0065]

[0066] According to Newton's third law, the IGBT chip force F d Force F on chip solder layer ds The magnitude is equal but the direction is opposite, as shown below, where h d 、E d 、h ds and E ds They are respectively represented as the height and Young's modulus of the IGBT chip and chip solder layer.

[0067] F d =h d ×E d ×ε d =F ds =h ds ×E ds ×ε ds_u (5)

[0068] Therefore, the thermal strain on the upper surface of the chip solder layer can be rewritten as follows:

[0069]

[0070] Similarly, the thermal strain on the lower surface of the chip solder layer can be obtained by the same method as follows, where h uc and E uc They are respectively represented by the height of the upper copper layer and Young's modulus.

[0071]

[0072] Due to the difference in CTE values, the chip solder layer cannot perfectly match the IGBT chip and the upper copper layer at the same time. According to equations (9) and (11), the thermal strains on the upper and lower surfaces of the chip solder layer will never be equal during the power cycle, and the strain on the upper surface expands outward while the strain on the lower surface expands toward the center of the solder layer. Due to the height difference between the upper and lower surfaces, a pair of torques will be generated around the void to pull the void, causing the void to continue to expand. The void strains on the upper and lower surfaces of the void present a body-center symmetric relationship. Shear strain is the main factor in the aging of the chip solder layer, which will eventually affect the life of the IGBT module.

[0073] The shear strain caused by the void is locally destructive to the solder layer. Morrow theory believes that energy is required to produce inelastic deformation of the material, and the stress-strain hysteresis loop in each cycle reflects the energy consumed by the material in a loading cycle. Part of this energy is converted into heat energy, and the other part causes damage to the material, causing the solder layer to fail. The energy-based fatigue life model is as follows. The life of the first fatigued part around the void can be calculated based on the local shear strain around the void, and then the life of different void sizes can be calculated.

[0074] ΔW c =W f (2×N f ) -m (9)

[0075]

[0076] According to the above two formulas, the life span can be expressed as:

[0077]

[0078] Where, ΔW c is the increment of inelastic strain energy density in a single cycle; E is the Young's modulus of the chip solder layer; ε is the strain of the chip solder layer; W f is the accumulation of plastic work density in each cycle; m is a constant; N f is the void lifetime, W f 5.5×10 6 (J / m 3 ), m is 0.69, E is 5.4×10 10 (Pa).

[0079] By using the multi-physics simulation model and combining the above formula, the maximum average strain of the upper and lower surfaces around the voids of different sizes and the void life under the corresponding strain can be calculated. The void life is inversely proportional to the square of its strain value, which means that small voids have a shorter life, and as the power cycle progresses, more small voids expand into large voids. On the contrary, large voids will age after a relatively long power cycle, and small voids have a faster expansion rate.

Claims

1. A method for analyzing the void evolution mechanism of IGBT solder layer for locomotives based on multi-physics fields, characterized in that: The steps include: Step 1: Use CT scanning test to obtain the solder layer scanning results; Step 2: Import the OpenCV library in Python to perform binarization on the scan results and calculate the sizes of different holes; Step 3: Divide the voids into different sizes and draw a distribution diagram of the void quantity, showing the Poisson distribution law; Step 4: A multi-physics model is established in COMSOL in combination with the locomotive IGBT device, and a random void that conforms to statistical results is generated in the solder layer using the built-in JAVA compiler; Step 5: Build a multi-physics field model, perform simulations under multiple groups of different random void distributions, and analyze the strain and deformation laws under voids of different sizes; Step 6: According to the difference in thermal expansion coefficient between the chip and the solder layer, a mathematical description relationship of the strain on the upper and lower surfaces of the solder layer is established; The step 6 specifically includes: During the operation of the IGBT module, the module power loss P is transferred to the base plate through each layer of material to complete the heat transfer process, and the module junction temperature T J Calculated by thermal resistance, power loss and case temperature: T J =P×Z JC +T C WITH JC =Z die +Z D-S +Z DBC +Z B-S +Z base Among them, Z JC , Z die , Z D-S , Z DBC , Z B-S , Z base Respectively represent the thermal resistance of the junction, IGBT chip, chip solder layer, DBC, bottom plate solder layer, and substrate; T C Indicates shell temperature; Chip temperature fluctuation ΔT d The temperature fluctuation ΔT of the chip solder layer ds It is expressed as: Where, ΔT d is the chip temperature fluctuation, ΔT ds Temperature fluctuation of chip solder layer, T d_max and T d_min Respectively represent the highest and lowest temperatures of the chip; T ds_max and T ds_min They represent the highest and lowest temperatures of the chip solder layer respectively; η1 represents the ratio of the chip temperature fluctuation to the chip solder layer temperature fluctuation; IGBT chip bottom surface strain ε d Thermal strain ε on the upper surface of the chip solder layer ds_u They are as follows: Among them, L d and ΔL d are the length of the IGBT chip and its change after the temperature rises; α d and α ds are the expansion coefficient of the chip and the expansion coefficient of the chip solder layer respectively; h d and h ds are the height of the chip and the chip solder layer respectively; E d and E ds are Young’s modulus of chip and chip solder layer, respectively; The thermal strain on the lower surface of the chip solder layer is obtained using the same method as follows: Where, ΔT uc is the temperature fluctuation of the upper copper layer; η2 is the ratio of the temperature fluctuation of the upper copper layer to the temperature fluctuation of the chip solder layer; α c is the expansion coefficient of the upper copper layer; h uc is the height of the upper copper layer; E uc is the Young’s modulus of the upper copper layer; The energy-based fatigue life model is as follows, combined with the strain in the multi-physics model, to calculate the void life: ΔW c =In f (2×N f ) -m Where, ΔW c is the increment of inelastic strain energy density in a single cycle; E is the Young's modulus of the chip solder layer; ε is the strain of the chip solder layer; W f is the accumulation of plastic work density in each cycle; m is a constant; N f is the void lifetime, void lifetime W f 5.5×10 6 (J / m 3 ), the constant m is 0.69, and the Young's modulus E of the chip solder layer is 5.4×10 10 (Pa).

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