A fast decoupling method and device for three-dimensional integrated circuit

Abstract

The present invention discloses a fast decoupling method for a three-dimensional integrated circuit, comprising: modeling the three-dimensional integrated circuit to obtain an equivalent circuit model; constructing a time domain equation group based on WLP‑FDTD according to the equivalent circuit model; applying noise current excitation to the equivalent circuit model, and calculating SSN using the time domain equation group, and updating SSN according to the circuit state; when the peak-to-peak value of SSN is greater than the expected value, selecting different decoupling capacitors, and scanning and calculating the SSN under each decoupling capacitor value using the time domain equation group; selecting the decoupling capacitor value corresponding to the minimum peak-to-peak value of SSN as the optimal decoupling capacitor to decouple the three-dimensional integrated circuit. The method can realize fast time domain noise analysis of a three-dimensional integrated circuit with a complex structure, and determine the optimal decoupling capacitor value of the circuit accordingly, and the method has high accuracy, avoiding the waste of chip area caused by over-design of the three-dimensional integrated circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a fast decoupling method and device for a three-dimensional integrated circuit. Background Art

[0002] Three-dimensional integration technology refers to a manufacturing packaging structure that uses through silicon via technology (TSV) to bond and stack circuit modules or chips with different functions in the vertical direction. In recent years, the urgent demand for high-performance, high-bandwidth, and high-power density systems has promoted the rapid development of three-dimensional integration technology. However, in three-dimensional integrated circuits, the realization of high performance is inseparable from a large number of simultaneously switched input / output ports in active circuits. The simultaneous switching of clocks produces large voltage ripple fluctuations, namely synchronous switching noise (SSN). In order to maintain a stable power supply in the chip, the solution of installing decoupling capacitors is widely used.

[0003] At present, there is little work on the optimization of decoupling capacitors in three-dimensional integrated circuits, and the existing methods basically use numerical calculation methods and software simulation methods. For example, Stefano Piersanti, Francesco de Paulis, et al. proposed a capacitor optimization method based on the impedance of the power distribution network (PDN) of a three-dimensional integrated circuit in "Decoupling Capacitors Placement for a Multichip PDN by a Nature-Inspired Algorithm" (DOI: 10.1109 / TEMC.2017.2770089). This method uses a genetic algorithm to find a capacitor decoupling solution that reduces the impedance of the three-dimensional integrated circuit. However, this method is a frequency domain calculation method, which ignores the transient changes and resonant impedance of the switching current, and has inaccurate estimates of time domain noise, which can easily cause over-design of three-dimensional integrated circuits and waste chip area. For example, Huanyu He, James Jian, Qiang Lu, and others proposed a software simulation method in "Modeling and Analysis of PDN Impedance and Switching Noise in TSV-Based 3-D Integration" (DOI: 10.1109 / TED.2015.2396914), which uses ANASYS Q3D software to extract the parasitic parameters of each part of the circuit in turn, and then uses SPICE software to simulate the circuit to obtain the transient response of the circuit. However, this method requires modeling and simulation calculations in ANASYS Q3D and SPICE simulation software, which makes the method inefficient and time-consuming. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a method and device for rapid decoupling of a three-dimensional integrated circuit. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In one aspect, an embodiment of the present invention provides a fast decoupling method for a three-dimensional integrated circuit, comprising:

[0006] Model the three-dimensional integrated circuit to obtain an equivalent circuit model;

[0007] Constructing a time domain equation group based on WLP-FDTD according to the equivalent circuit model;

[0008] Applying noise current excitation to the equivalent circuit model, calculating SSN using the time domain equation group, and updating SSN according to the circuit state;

[0009] When the peak-to-peak value of SSN is greater than the expected value, different decoupling capacitors are selected, and the SSN under each decoupling capacitor value is scanned and calculated using the time domain equation group;

[0010] The decoupling capacitor value corresponding to the minimum peak-to-peak value of SSN is selected as the optimal decoupling capacitor to decouple the three-dimensional integrated circuit.

[0011] In one embodiment of the present invention, a three-dimensional integrated circuit is modeled to obtain an equivalent circuit model, including:

[0012] Construct equivalent circuit diagrams of PDN units in interposer layers and chips in 3D integrated circuits;

[0013] Based on the self-inductance, resistance, mutual inductance, mutual capacitance of TSV and the self-inductance and resistance of solder balls, the equivalent circuit diagram of TSV array and solder ball array in three-dimensional integrated circuit is constructed;

[0014] The complete equivalent circuit model of the three-dimensional integrated circuit is obtained by using the equivalent circuit diagram of the insertion layer and the PDN unit in the chip and the equivalent circuit diagram of the TSV array and the solder ball array.

[0015] In one embodiment of the present invention, a time domain equation group based on WLP-FDTD is constructed according to the equivalent circuit model, including:

[0016] For each PDN node in the equivalent circuit model, construct an expression for the total current flowing through the node;

[0017] Define the boundary conditions of the PDN;

[0018] Construct voltage and current expressions for TSV arrays;

[0019] A matrix equation is constructed based on the above total current expression, the boundary conditions of the PDN, and the voltage and current expressions of the TSV array.

[0020] In one embodiment of the present invention, for each PDN node of the equivalent circuit model, an expression for the total current flowing through the node is constructed, including:

[0021] If the node (i, j) is not connected to the TSV array, the total current flowing through the node (i, j) is obtained according to the relationship between the current and voltage along the X and Y directions at the node (i, j), and its expression is:

[0022]

[0023] The relationship between the current and voltage along the X and Y directions at the node (i, j) is expressed as:

[0024]

[0025]

[0026] in, They represent the current and voltage along the X and Y directions at the node (i, j) of the insertion layer and the PDN in the chip in the equivalent circuit model, β represents the order, and R x | i,j , R y | i,j , L x | i,j , L y | i,j , C i,j , G| i,j Represent the resistance, inductance, capacitance and conductance of each PDN unit at the node (i, j), I noise | i,j represents the noise current flowing into the node (i, j) generated by the load and other modules, C decap | i,j represents the decoupling capacitance at the node (i, j), and s represents the time scale factor.

[0027] In one embodiment of the present invention, for each PDN node of the equivalent circuit model, constructing an expression for the total current flowing through the node also includes:

[0028] If the node (i, j) is connected to the TSV array, the total current flowing through the node (i, j) is expressed as:

[0029]

[0030] in, p1, p2, p3…∈P, q1, q2, q3…∈Q, P is the set of power TSV abscissas, Q is the set of power TSV ordinates, B is the set of ground TSV abscissas, D is the set of ground TSV ordinates, where b1, b2, b3…∈B and d1, d2, d3…∈D, and They represent the current flowing into and out of the node (i, j) through the TSV, and C TSV | (i,j),(p,q) and G TSV | (i,j),(p,q) represent the substrate capacitance and substrate conductance between TSVs, respectively.

[0031] In one embodiment of the present invention, the boundary condition of the PDN is expressed as:

[0032]

[0033] In one embodiment of the present invention, the voltage and current formula of the TSV array is:

[0034]

[0035]

[0036]

[0037] Among them, L TSV,s | i,j represents the self-inductance of the TSV with coordinate (i, j), L TSV,m | (p,q),(i,j) represents the mutual inductance between TSVs with coordinates (i, j) and (p, q), V bot | i,j and V top | i,j Represent the top voltage and bottom voltage of the adjacent PDN respectively.

[0038] In one embodiment of the present invention, the matrix equation is expressed as:

[0039]

[0040] Among them, the matrix is a sparse matrix of coefficients, {X β} is the unknown quantity to be determined, is the noise current, is the sum of the right side of the equation from order 0 to order β-1.

[0041] In one embodiment of the present invention, updating the SSN according to the circuit state includes: monitoring the circuit state,

[0042] When the circuit structure or the noise source changes, the time domain equation group is used again to calculate the SSN; otherwise, the circuit state is continuously monitored.

[0043] On the other hand, an embodiment of the present invention further provides a fast decoupling device for a three-dimensional integrated circuit, comprising:

[0044] A model building module is used to model the three-dimensional integrated circuit and obtain an equivalent circuit model;

[0045] An equation building module, used for building a time domain equation group based on WLP-FDTD according to the equivalent circuit model;

[0046] An excitation module, used for applying noise current excitation to the equivalent circuit model, calculating SSN using the time domain equation group, and updating SSN according to the circuit state;

[0047] A scanning calculation module, used for selecting different decoupling capacitors when the peak-to-peak value of SSN is greater than the expected value, and performing scanning calculation on the SSN under each decoupling capacitor value by using the time domain equation group;

[0048] The decoupling module is used to select the decoupling capacitor value corresponding to the minimum peak-to-peak value of SSN as the optimal decoupling capacitor to decouple the three-dimensional integrated circuit.

[0049] Beneficial effects of the present invention:

[0050] The present invention models the three-dimensional integrated circuit and establishes a time domain equation group based on WLP-FDTD. The time domain SSN is calculated in real time by using the equation group. When the peak-to-peak value of SSN is greater than the expected value, different decoupling capacitors are selected. Finally, the optimal decoupling capacitor is selected from different decoupling capacitor values. Coupling Capacitors are used to quickly decouple three-dimensional integrated circuits. This method can quickly perform time-domain noise analysis on three-dimensional integrated circuits with complex structures, and determine the optimal decoupling capacitor value of the circuit accordingly. This method has high accuracy and avoids chip area waste caused by over-design of three-dimensional integrated circuits.

[0051] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a flow chart of a rapid decoupling method for a three-dimensional integrated circuit provided by an embodiment of the present invention;

[0053] Figure 2 is a structural diagram of a three-dimensional integrated circuit provided by an embodiment of the present invention;

[0054] Figure 3 The PDN structure and equivalent circuit used by the insertion layer and chip provided in the embodiment of the present invention;

[0055] Figure 4 is an equivalent circuit diagram of a TSV array and a solder ball array provided by an embodiment of the present invention;

[0056] Figure 5 is a complete three-dimensional integrated circuit total equivalent circuit diagram provided by an embodiment of the present invention;

[0057] Figure 6 is another flow chart of a fast decoupling method for a three-dimensional integrated circuit provided by an embodiment of the present invention;

[0058] Figure 7 is an example diagram of a three-dimensional HBM structure based on an interposer provided in an embodiment of the present invention;

[0059] Figure 8is the port position and switch current region provided by the embodiment of the present invention;

[0060] Fig. 9 is a schematic diagram of synchronous switching noise current modeling provided by an embodiment of the present invention;

[0061] Fig.10 is the optimal capacitance value corresponding to the SSN generated by the noise current of different periods provided in the embodiment of the present invention;

[0062] Fig.11 It is a schematic structural diagram of a fast decoupling device for a three-dimensional integrated circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0063] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0064] Embodiment 1

[0065] See also Figure 1 , Figure 1 1 is a flow chart of a rapid decoupling method for a three-dimensional integrated circuit provided by an embodiment of the present invention, which includes:

[0066] Step 1: Model the three-dimensional integrated circuit to obtain an equivalent circuit model.

[0067] Generally speaking, a complete PDN of a three-dimensional integrated circuit consists of a PDN in an insertion layer, a PDN in a chip, a through silicon via (TSV) array, a solder ball array, and a decoupling capacitor. The three-dimensional structure diagram is shown in FIG. Figure 2 This embodiment is mainly based on Figure 2 The three-dimensional integrated circuit structure shown in the figure constructs a general equivalent circuit model of the three-dimensional integrated circuit containing multiple parasitic parameters, specifically including:

[0068] 1a) Construct the equivalent circuit diagram of the PDN unit in the insertion layer and chip in the three-dimensional integrated circuit.

[0069] See also Figure 3 , Figure 3 The PDN structure and equivalent circuit used by the insertion layer and chip provided in the embodiment of the present invention are shown in FIG. Figure 3 Figures (a) and (b) are the most widely used gate-type PDN and mesh-type PDN respectively. Figure (c) is the equivalent circuit model of Figures (a) and (b), which mainly includes resistance Rx, Ry in the X and Y directions, inductance Lx, Ly in the X and Y directions, conductance C and capacitance G. Each dotted box represents the minimum PDN unit.

[0070] Specifically, for Figure 3The gate-type PDN structure shown in Figure (a) can be directly equivalent to the equivalent circuit model in Figure (c) using the method in the literature "Modeling of an on-chip power / ground meshed plane using frequency dependent parameters" (DOI: 10.5515 / JKIEES.2011.11.3.192); for the mesh-type PDN structure shown in Figure (b), the method in the literature "Fast and Accurate Power Distribution Network Modeling of a Silicon Interposer for 2.5-D / 3-D ICs With MultiarrayTSVs" (DOI: 10.1109 / TCPMT.2013.2276050) can be directly equivalent to the equivalent circuit model in Figure (c), which represents the smallest unit of PDN used for insertion layer or chip, referred to as PDN unit.

[0071] 1b) Based on the self-inductance, resistance, mutual inductance, mutual capacitance of TSV and the self-inductance and resistance of solder balls, the equivalent circuit diagram of TSV array and solder ball array in three-dimensional integrated circuit is constructed.

[0072] Specifically, see Figure 4 , Figure 4 This is an equivalent circuit diagram of a TSV array and a solder ball array provided in an embodiment of the present invention.

[0073] First, we build a model based on the methods in the literature “Modeling and Optimization of Multiground TSVs forSignals Shield in 3-D ICs” (DOI: 10.1109 / TEMC.2016.2608981) and “High-FrequencyScalable Electrical Model and Analysis of a Through Silicon Via(TSV)” (DOI: 10.1109 / TCPMT.2010.2101890). Figure 4 Equivalent circuit model of TSV array and solder ball array shown in Figure (a). Figure 4 The equivalent circuit model of Figure (a) includes: the sidewall capacitance C related to the substrate i 、Silicon substrate capacitance C Si,ij and conductivity G Si,ij 、TSV self-inductance L TSV_self，i , mutual inductance L TSV_mutu，ij and resistor RTSV，i .

[0074] It is worth noting that in order to obtain a more accurate model, this embodiment also takes into account the self-inductance L of the solder ball. Bump_self，i and resistor R Bump，i In addition, a ground TSV is arbitrarily set as a reference, marked as #0.

[0075] Furthermore, in order to be compatible with the subsequent WLP-FDTD method, this embodiment uses the following formulas (1)-(6) to convert Figure 4 The equivalent circuit model of Figure (a) is converted to Figure 4 The form shown in Figure (b) is compatible with the WLP-FDTD method. Specifically, the conversion formula is as follows:

[0076] R′ TSV,i =R TSV,i +R Bump,i (1)

[0077] For the convenience of description, Figure 3 In Figure (b) and subsequent equations, R' is omitted. TSV,i The superscript of .

[0078] L TSV_s,i =L TSV_self,i +L Bump_self,i (2)

[0079] L TSV_m,ij =L TSV_mutu,ij (3)

[0080] G TSV,ij =real(Y) (4)

[0081] C TSV,ij =imag(Y) / ω (5)

[0082] in,

[0083]

[0084] 1c) Obtaining a complete equivalent circuit model of the three-dimensional integrated circuit using the equivalent circuit diagram of the insertion layer and the PDN unit in the chip and the equivalent circuit diagram of the TSV array and the solder ball array.

[0085] Specifically, according to Figure 3 Figure (c) and Figure 4 The equivalent circuit model of the complete three-dimensional integrated circuit is constructed by using the partial equivalent circuit diagram shown in Figure (b). Figure 5 shown.

[0086] Step 2: Construct a time domain equation group based on WLP-FDTD according to the equivalent circuit model.

[0087] In this embodiment, mainly based on the voltage-current relationship in the equivalent circuit, refer to Figure 5 At each node in the FDTD, the time factor-related FDTD update equations are constructed and substituted into the Laguerre polynomials to obtain the noise-time WLP-FDTD (Finite-Difference Time-Domain method based on Weighted Laguerre polynomials) equations for the transient response of the three-dimensional integrated circuit. The details are as follows:

[0088] 2a) For each PDN node in the equivalent circuit model, construct an expression for the total current flowing through the node.

[0089] It should be noted that each layer of insertion layer PDN or chip PDN in the equivalent circuit model includes several PDN units corresponding to several nodes, and the PDN nodes in the insertion layer and the chip are interconnected through TSV. Therefore, for any node (i, j) of the equivalent circuit model PDN, it may not be connected to TSV or may be connected to TSV.

[0090] If the node (i, j) is not connected to the TSV array, the total current flowing through the node (i, j) is obtained according to the relationship between the current and the voltage along the X and Y directions at the node (i, j).

[0091] Specifically, at the node (i, j) of each layer of insertion layer PDN or chip PDN, the relationship between the current and voltage along the X and Y directions can be expressed as:

[0092]

[0093]

[0094] In this embodiment, Figure 3 Figure (c) in Figure 1 represents the smallest unit of PDN used in the insertion layer or chip, referred to as PDN unit. Figure 5 In formulas (7)-(8), i is the sequence number of the PDN unit in the X direction, and j is the sequence number of the PDN unit in the Y direction.

[0095] Then, the total current flowing through the node (i, j) is expressed as:

[0096]

[0097] in, They represent the current and voltage along the X and Y directions at the node (i, j) of the insertion layer and the PDN in the chip in the equivalent circuit model, β represents the order, and R x | i,j , R y | i,j , L x | i,j , L y | i,j 、C| i,j , G| i,j Represent the resistance, inductance, capacitance and conductance of each PDN unit at the node (i, j), I noise | i,j represents the noise current flowing into the node (i, j) generated by the load and other modules, C decap | i,j represents the decoupling capacitance at the node (i, j), and s represents the time scale factor.

[0098] If the node (i, j) is connected to the TSV array, the total current at the node (i, j) connected to the TSV is expressed as:

[0099]

[0100] in, p1, p2, p3…∈P, q1, q2, q3…∈Q, P is the set of power TSV abscissas, Q is the set of power TSV ordinates, B is the set of ground TSV abscissas, D is the set of ground TSV ordinates, where b1, b2, b3…∈B and d1, d2, d3…∈D, and They represent the current flowing into and out of the node (i, j) through the TSV, and C TSV | (i,j),(p,q) and G TSV | (i,j),(p,q) denote the substrate capacitance and substrate conductance between TSVs respectively; the coordinates (i, j) and (p, q) are as follows Figure 4 As shown in (b), L TSV,s | i,j represents the self-inductance of TSV at point (i, j), L TSV,m | (p,q),(i,j) represents the mutual inductance of TSV at point (i, j) and point (p, q), V bot | i,j and V top | i,j Represents the voltage on the adjacent bottom and top PDNs.

[0101] 2b) Define the boundary conditions of the PDN.

[0102] Specifically, since the edges of the PDN in the interposer and the PDN in the chip are open, the boundary conditions are:

[0103]

[0104] 2c) Construct the voltage and current formula of the TSV array, which is expressed as:

[0105]

[0106]

[0107]

[0108] Among them, L TSV,s | i,j represents the self-inductance of the TSV with coordinate (i, j), L TSV,m | (p,q),(i,j) represents the mutual inductance between TSVs with coordinates (i, j) and (p, q), V bot | i,j and V top | i,j Represents the top voltage and bottom voltage of the adjacent PDN.

[0109] 2d) Construct a matrix equation based on the above total current expression, the boundary conditions of the PDN, and the voltage and current expressions of the TSV array.

[0110] Specifically, by solving equations (7)-(14) simultaneously, we have:

[0111]

[0112] Among them, the matrix is a sparse matrix of coefficients, which has nothing to do with the order β. β} is the unknown quantity to be determined, is the noise current. It is the sum of the right side of the equation from 0th order to β-1st order. The upper term of β is usually replaced by a finite value Q. Assuming that the noise cutoff frequency in the three-dimensional integrated circuit is f c , the noise period is T f , the minimum value of Q is:

[0113] Q min =2f c T f +1 (16)

[0114] This embodiment adopts the WLP-FDTD method without the time step limit, and can perform efficient calculations for complex structures such as three-dimensional integrated circuits.

[0115] Step 3: Apply noise current excitation to the equivalent circuit model, calculate SSN using the time domain equation group, and update SSN according to the circuit state.

[0116] First, the input noise current excitation is modeled according to the switching clock cycle and the number of clocks in the three-dimensional integrated circuit. Then, the noise current is input into the time domain equation group obtained in step 2 for initialization optimization to obtain the initial SSN without adding decoupling capacitors.

[0117] Specifically, this embodiment uses Matlab software to solve the matrix equation (15) composed of equations (7)-(14). In Matlab, the matrix is a sparse matrix composed of coefficients, which is independent of the order β and only requires one inversion operation. The noise current value on the right side of formula (15) is a known quantity during calculation, and the term The order of is lower than the left side, β = 0, and there is only one known quantity on the right side of (15), which is solved recursively as the order increases.

[0118] Then, the circuit status is monitored so as to selectively update the SSN according to the circuit status.

[0119] The monitoring here means that if the circuit structure or noise source changes, the equation in step 2 is used again to calculate SSN. Otherwise, the circuit status is continuously monitored.

[0120] Step 4: When the peak-to-peak value of SSN is greater than the expected value, different decoupling capacitors are selected, and the SSN under each decoupling capacitor value is scanned and calculated using the time domain equation group.

[0121] Specifically, when the initial peak-to-peak value of SSN is greater than the expected value of noise, or the subsequent circuit conditions or noise current excitation change, and the peak-to-peak value of SSN is found to be greater than the expected value of noise through the monitoring step, a decoupling capacitor value with a certain range and numerical interval is selected, and the time domain equation group in step 2 is used to scan and calculate SSN to obtain the peak-to-peak value of SSN under different decoupling capacitor values. If the peak-to-peak value of SSN is less than the expected value of noise, continue monitoring. See Figure 6 , Figure 6 This is another flow chart of the rapid decoupling method for a three-dimensional integrated circuit provided by an embodiment of the present invention.

[0122] It should be noted that the above-mentioned expected noise value is an upper limit of the tolerable SSN value that is artificially determined based on actual circuit conditions or relevant experience.

[0123] Furthermore, for the selection of decoupling capacitors, there are currently types of decoupling capacitors such as Metal-Insulator-Metal (MIM) capacitors, Metal-Oxide-Semiconductor (MOS) capacitors, and Deep Trench (DT) capacitors. Due to the ultra-low loss factor of MIM capacitors, especially the extremely small equivalent series inductance and equivalent series resistance, MIM capacitors are widely used in three-dimensional integrated circuits. In this embodiment, MIM capacitors can be Figure 5 It is directly equivalent to a single capacitor without other parasitic parameters.

[0124] Step 5: Select the decoupling capacitor value corresponding to the minimum peak-to-peak value of SSN as the optimal decoupling capacitor to decouple the three-dimensional integrated circuit.

[0125] This embodiment models the three-dimensional integrated circuit and establishes a time-domain equation group based on WLP-FDTD. The time-domain SSN is calculated in real time using the equation group, and different decoupling capacitors are selected when the peak-to-peak value of the SSN is greater than the expected value. Finally, the optimal decoupling capacitor is selected from different decoupling capacitor values, thereby completing the rapid decoupling of the three-dimensional integrated circuit. This method can realize rapid time-domain noise analysis of a three-dimensional integrated circuit with a complex structure, and determine the optimal decoupling capacitor value of the circuit accordingly. The method has high accuracy and avoids the waste of chip area caused by over-design of the three-dimensional integrated circuit.

[0126] Embodiment 2

[0127] On the basis of the above-mentioned embodiment 1, this embodiment adopts a currently popular three-dimensional PDN to verify the method proposed in embodiment 1. In order to adapt to the development trend of information technology such as big data management, cloud computing and three-dimensional games, high-bandwidth memory (HBM) based on silicon interposers has been widely studied. Due to frequent data transmission and exchange, noise problems will inevitably arise, so it is necessary to perform time domain noise analysis and decoupling capacitor optimization on the structure. Based on this, this embodiment takes the three-dimensional HBM structure based on the interposer as an example for verification and explanation.

[0128] Specifically, an example structure of a three-dimensional HBM structure based on an interposer is as follows: Figure 7As shown. The left figure is the overall structure diagram and partial enlarged diagram of the PDN and TSV on the chip and the interposer, and the right figure is a top view of the overall structure. The interposer layer PDN has 100×100 units, while each on-chip PDN has 20×20 units. In order to simplify the modeling process, the metal thickness of each PDN layer is set to 0.7μm. At the same time, the design parameters of the PDN unit, TSV, substrate, intermetallic dielectric (IMD) and TSV external insulation layer (IL) in the interposer and chip are consistent. The specific parameters are shown in Table 1.

[0129] Table 1

[0130]

[0131] Among them, the design parameters of the PDN unit, TSV, substrate, IMD and IL in the interposer and chip are consistent.

[0132] In an embodiment, an I / O buffer generating a switching current is placed between an HBM and a GPU / CPU module, such as Figure 8 The shaded area contains 125 PDN cells, each of which is connected in series with a switching current source to represent the transistor switching process of the I / O buffer. Each switching current is modeled as having t c / 4 rise time, t c / 4 fall time and t c / 2 triangle wave with stationary time, t c is the time period of the clock cycle, which is 2ns in this embodiment. Peak current occurs when the transistor switches, and the maximum switching current is set to 18mA. Based on this, the Fig. 9 The synchronous switching noise current model is shown.

[0133] According to the method provided in the first embodiment, the circuit in the embodiment is optimized. Substitute the noise current and the structural parameters of each part, and perform steps 1-3 in sequence, wherein the noise expectation value is set to 500mV. The initial noise of the circuit does not meet the noise expectation value, so the subsequent steps 4-5 are continued. The results are shown in Fig.10 When the noise current cycle is 4ns, the optimal capacitance value is 700fF; when the noise current cycle is 2ns, the optimal capacitance value is 400fF; when the noise current cycle is 1ns, the optimal capacitance value is 550fF.

[0134] It can be seen that the fast decoupling method for a three-dimensional integrated circuit provided by the present invention can realize fast time-domain noise analysis of a three-dimensional integrated circuit with a complex structure, and thereby determine the optimal decoupling capacitance value of the circuit.

[0135] Embodiment 3

[0136] Based on the above embodiment 1, this embodiment also provides a fast decoupling device for a three-dimensional integrated circuit. Fig.11 , Fig.11 1 is a schematic diagram of a structure of a fast decoupling device for a three-dimensional integrated circuit provided by an embodiment of the present invention, which includes:

[0137] Model building module 1, used for modeling the three-dimensional integrated circuit to obtain an equivalent circuit model;

[0138] An equation construction module 2, used for constructing a time domain equation group based on WLP-FDTD according to the equivalent circuit model;

[0139] An excitation module 3 is used to apply noise current excitation to the equivalent circuit model, calculate SSN using the time domain equation group, and update SSN according to the circuit state;

[0140] A scanning calculation module 4 is used for selecting different decoupling capacitors when the peak-to-peak value of SSN is greater than the expected value, and performing scanning calculation on the SSN under each decoupling capacitor value by using the time domain equation group;

[0141] The decoupling module 5 is used to select a decoupling capacitor value corresponding to the minimum peak-to-peak value of the SSN as an optimal decoupling capacitor to decouple the three-dimensional integrated circuit.

[0142] The fast decoupling device for a three-dimensional integrated circuit provided in this embodiment can implement the fast decoupling method for a three-dimensional integrated circuit described in the first embodiment above, and the detailed process will not be repeated here.

[0143] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A fast decoupling method for a three-dimensional integrated circuit, characterized in that: include: Model the three-dimensional integrated circuit to obtain an equivalent circuit model; According to the equivalent circuit model, a time domain equation group based on WLP-FDTD is constructed; including: For each PDN node in the equivalent circuit model, an expression for the total current flowing through the node is constructed; if the node (i, j) is not connected to the TSV array, the total current flowing through the node (i, j) is obtained based on the relationship between the current and voltage along the X and Y directions at the node (i, j), and its expression is: The relationship between the current and voltage along the X and Y directions at the node (i, j) is expressed as: in, They represent the current and voltage along the X and Y directions at the node (i, j) of the insertion layer and the PDN in the chip in the equivalent circuit model, β represents the order, and R x | i,j , R y | i,j , L x | i,j , L y | i,j 、C| i,j , G| i,j Represent the resistance, inductance, capacitance and conductance of each PDN unit at the node (i, j), I noise | i,j represents the noise current flowing into the node (i, j) generated by the load and other modules, C decap | i,j represents the decoupling capacitance at the node (i, j), and s represents the time scale factor; If the node (i, j) is connected to the TSV array, the total current flowing through the node (i, j) is expressed as: in, p1, p2, p3… ∈ P, q1, q2, q3… ∈ Q, P is the set of power TSV horizontal coordinates, Q is the set of power TSV vertical coordinates, B is the set of ground TSV horizontal coordinates, and D is the set of ground TSV vertical coordinates, where b1, b2, b3… ∈ B and d1, d2, d3… ∈ D, They represent the current flowing into and out of the node (i, j) through the TSV, and C TSV(i,j),(p,q) and G TSV(i,j),(p,q) They represent the substrate capacitance and substrate conductance between TSVs, respectively; Define the boundary conditions of the PDN; Construct voltage and current expressions for TSV arrays; Construct a matrix equation based on the above total current expression, the boundary conditions of the PDN, and the voltage and current expression of the TSV array; Applying noise current excitation to the equivalent circuit model, calculating SSN using the time domain equation group, and updating SSN according to the circuit state; When the peak-to-peak value of SSN is greater than the expected value, different decoupling capacitors are selected, and the SSN under each decoupling capacitor value is scanned and calculated using the time domain equation group; The decoupling capacitor value corresponding to the minimum peak-to-peak value of SSN is selected as the optimal decoupling capacitor to decouple the three-dimensional integrated circuit.

2. The fast decoupling method of a three-dimensional integrated circuit according to claim 1, characterized in that: Model the three-dimensional integrated circuit and obtain an equivalent circuit model, including: Construct equivalent circuit diagrams of PDN units in interposer layers and chips in 3D integrated circuits; Based on the self-inductance, resistance, mutual inductance, mutual capacitance of TSV and the self-inductance and resistance of solder balls, the equivalent circuit diagram of TSV array and solder ball array in three-dimensional integrated circuit is constructed; The complete equivalent circuit model of the three-dimensional integrated circuit is obtained by using the equivalent circuit diagram of the insertion layer and the PDN unit in the chip and the equivalent circuit diagram of the TSV array and the solder ball array.

3. The fast decoupling method of a three-dimensional integrated circuit according to claim 1, characterized in that: The boundary conditions of the PDN are expressed as:

4. The fast decoupling method of a three-dimensional integrated circuit according to claim 3, characterized in that: The voltage and current expressions of the TSV array are: Among them, L TSV,s | i,j represents the self-inductance of the TSV with coordinate (i, j), L TSV,m | (p,q),(i,j) represents the mutual inductance between TSVs with coordinates (i, j) and (p, q), V bot | i,j and V top | i,j Represent the top voltage and bottom voltage of the adjacent PDN respectively.

5. The rapid decoupling method of a three-dimensional integrated circuit according to claim 4, characterized in that: The matrix equation is expressed as: Among them, the matrix is a sparse matrix of coefficients, {X β } is the unknown quantity to be determined, is the noise current, is the sum of the right side of the equation from order 0 to order β-1.

6. The fast decoupling method of a three-dimensional integrated circuit according to claim 1, characterized in that: Updating the SSN based on the circuit status includes: monitoring the circuit status, When the circuit structure or the noise source changes, the time domain equation group is used again to calculate the SSN; otherwise, the circuit state is continuously monitored.

7. A fast decoupling device for a three-dimensional integrated circuit, characterized in that: include: A model building module (1) is used to model the three-dimensional integrated circuit to obtain an equivalent circuit model; An equation construction module (2), used for constructing a time domain equation group based on WLP-FDTD according to the equivalent circuit model; An excitation module (3) is used to apply noise current excitation to the equivalent circuit model, calculate SSN using the time domain equation group, and update SSN according to the circuit state; A scanning calculation module (4) is used to select different decoupling capacitors when the peak-to-peak value of the SSN is greater than the expected value, and to perform scanning calculations on the SSN under each decoupling capacitor value using the time domain equation group; A decoupling module (5) is used to select a decoupling capacitor value corresponding to the minimum peak-to-peak value of the SSN as an optimal decoupling capacitor to decouple the three-dimensional integrated circuit; The equation construction module (2) specifically implements the construction of a time domain equation group based on WLP-FDTD according to the equivalent circuit model in the following steps: For each PDN node in the equivalent circuit model, an expression for the total current flowing through the node is constructed; if the node (i, j) is not connected to the TSV array, the total current flowing through the node (i, j) is obtained based on the relationship between the current and voltage along the X and Y directions at the node (i, j), and its expression is: The relationship between the current and voltage along the X and Y directions at the node (i, j) is expressed as: in, They represent the current and voltage along the X and Y directions at the node (i, j) of the insertion layer and the PDN in the chip in the equivalent circuit model, β represents the order, and R x | i,j , R y | i,j , L x | i,j , L y | i,j 、C| i,j , G| i,j Represent the resistance, inductance, capacitance and conductance of each PDN unit at the node (i, j), I noise | i,j represents the noise current flowing into the node (i, j) generated by the load and other modules, C decap | i,j represents the decoupling capacitance at the node (i, j), and s represents the time scale factor; If the node (i, j) is connected to the TSV array, the total current flowing through the node (i, j) is expressed as: in, p1, p2, p3… ∈ P, q1, q2, q3… ∈ Q, P is the set of power TSV horizontal coordinates, Q is the set of power TSV vertical coordinates, B is the set of ground TSV horizontal coordinates, and D is the set of ground TSV vertical coordinates, where b1, b2, b3… ∈ B and d1, d2, d3… ∈ D, and They represent the current flowing into and out of the node (i, j) through the TSV, and C TSV(i,j),(p,q) and G TSV(i,j),(p,q) They represent the substrate capacitance and substrate conductance between TSVs, respectively; Define the boundary conditions of the PDN; Construct voltage and current expressions for TSV arrays; A matrix equation is constructed based on the above total current expression, the boundary conditions of the PDN, and the voltage and current expressions of the TSV array.

Images