Failed bit repair method, device, equipment and storage medium

Abstract

The present disclosure provides a method, device, equipment and storage medium for repairing a failed bit, and relates to the field of semiconductor technology. The method includes: obtaining the repair specifications of the spare circuit of the chip where the failed bit is located; standardizing the repair specifications of the spare circuit to obtain a standardized repair specification; obtaining the position of the failed bit on the chip; processing the position of the failed bit on the chip according to the standardized repair specification to obtain the standardized position of the failed bit; using a spare circuit allocation algorithm to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specification to obtain the standardized repair position of the spare circuit; restoring the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specification to repair the failed bit. This method achieves the goal of improving the versatility of the repair algorithm.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a failed bit repair method, device, equipment and readable storage medium. Background Art

[0002] With the rapid development of computer technology, integrated circuit chips play an increasingly important role in people's production and life. However, chip failures are inevitable during the development, production and use of chips. Usually, backup circuits can be used to repair the failed bits in the chip.

[0003] Repair Algorithm (RA) is a method that can effectively assign spare circuits to repair the circuits where the above-mentioned failed bits are located. RA can obtain the positions assigned for spare circuits, and replace them with positions that have a high probability of covering all failed bits on the chip. However, the higher the probability that an RA assigns positions to cover all failed bits on a specific chip, the more difficult it is for this RA to be applied to chips with different product specifications, and redeveloping RA for chips with different product specifications takes a long time and is costly. Therefore, improving the versatility of RA has become an urgent problem to be solved.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0005] The purpose of the present disclosure is to provide a failed bit repair method, device, equipment and readable storage medium to improve the versatility of the repair algorithm.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for repairing a failed bit is provided, comprising: obtaining a repair specification of a spare circuit of a chip where a failed bit is located; standardizing the repair specification of the spare circuit to obtain a standardized repair specification; obtaining a position of the failed bit on the chip; processing the position of the failed bit on the chip according to the standardized repair specification to obtain a standardized position of the failed bit; using a spare circuit allocation algorithm to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specification to obtain a standardized repair position of the spare circuit; and restoring the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specification to repair the failed bit.

[0008] According to an embodiment of the present disclosure, the repair specification of the backup circuit includes the line width of the backup circuit and the preset repair range of the backup circuit; the standardized repair specification includes the standardized line width and the standardized repair range; the standardizing the repair specification of the backup circuit to obtain the standardized repair specification includes: standardizing the line width of the backup circuit according to bits to obtain the standardized line width; dividing the chip into multiple unified areas according to the preset repair range to obtain the range of each unified area; standardizing the preset repair range according to the range of each unified area to obtain the standardized repair range of the backup circuit.

[0009] According to an embodiment of the present disclosure, the processing of the position of the failed bit on the chip according to the standardized repair specification to obtain the standardized position of the failed bit includes: processing the position of the failed bit on the chip according to the standardized line width to obtain the standardized position of the failed bit as the position of the failed bit in the corresponding unified area; the use of the spare circuit allocation algorithm to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specification includes: in each unified area, using the spare circuit allocation algorithm to allocate the spare circuit according to the position of the failed bit in the corresponding unified area and the standardized repair range, and obtaining the standardized repair position as the repair position of the spare circuit in the corresponding unified area.

[0010] According to an embodiment of the present disclosure, restoring the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specification to repair the failed bit includes: restoring the repair position of the spare circuit in the corresponding unified area to the repair position of the spare circuit on the chip according to the standardized line width to repair the failed bit.

[0011] According to an embodiment of the present disclosure, the chip is divided into multiple unified areas according to the preset repair range, and obtaining the range of each unified area includes: obtaining the length of the range of each unified area as the length of the corresponding preset repair range in the extension direction of the spare circuit, or obtaining the width of the range of each unified area as the length of the corresponding preset repair range in the extension direction of the spare circuit.

[0012] According to an embodiment of the present disclosure, the backup circuit includes a global backup circuit and a sub-domain backup circuit; the extension direction of the global backup circuit is orthogonal to the extension direction of the sub-domain backup circuit; the preset repair range includes a global repair range and a sub-domain repair range, and the global repair range includes a plurality of sub-domain repair ranges; the global backup circuit is used to repair failed bits within the global repair range on the chip, and the sub-domain backup circuit is used to repair failed bits within the sub-domain repair range on the chip; the length of the range of each unified area is the same as the length of the corresponding global repair range in the extension direction of the global backup circuit, and the width of the range of each unified area is the same as the length of the corresponding sub-domain repair range in the extension direction of the sub-domain backup circuit.

[0013] According to an embodiment of the present disclosure, the standardized repair range includes a standardized global repair range and a standardized subdomain repair range; the preset repair range is standardized according to the range of each unified area to obtain the standardized repair range of the spare circuit, including: obtaining the standardized global repair range as the range of the corresponding unified area; when the subdomain spare circuit is used for co-location repair, the subdomain repair range corresponding to the subdomain spare circuit is standardized to obtain the standardized subdomain repair range, and the length of the standardized subdomain repair range in the extension direction of the global spare circuit is one data grid.

[0014] According to an embodiment of the present disclosure, the position of the failed bit on the chip is processed according to the standardized repair specification to obtain the standardized position of the failed bit, which includes: scaling the position of the failed bit on the chip according to the line width of the backup circuit and the standardized line width to obtain the standardized position of the failed bit.

[0015] According to an embodiment of the present disclosure, restoring the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specification to repair the failed bit includes: restoring the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the line width of the spare circuit and the standardized line width to repair the failed bit.

[0016] According to another aspect of the present disclosure, a failed bit repairing device is provided, including: a parameter acquisition module, used to obtain the repair specifications of the spare circuit of the chip where the failed bit is located; obtain the position of the failed bit on the chip; a specification conversion module, used to standardize the repair specifications of the spare circuit to obtain a standardized repair specification; process the position of the failed bit on the chip according to the standardized repair specification to obtain the standardized position of the failed bit; a circuit allocation module, used to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specification using a spare circuit allocation algorithm to obtain the standardized repair position of the spare circuit; a position restoration module, used to restore the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specification to repair the failed bit.

[0017] According to one embodiment of the present disclosure, the repair specification of the backup circuit includes the line width of the backup circuit and the preset repair range of the backup circuit; the standardized repair specification includes the standardized line width and the standardized repair range; the specification conversion module is also used to: standardize the line width of the backup circuit according to bits to obtain the standardized line width; divide the chip into multiple unified areas according to the preset repair range to obtain the range of each unified area; standardize the preset repair range according to the range of each unified area to obtain the standardized repair range of the backup circuit.

[0018] According to an embodiment of the present disclosure, the specification conversion module is further used to: process the position of the failed bit on the chip according to the standardized line width, and obtain the standardized position of the failed bit as the position of the failed bit in the corresponding unified area; the circuit allocation module is further used to: in each unified area, use the spare circuit allocation algorithm to allocate the spare circuit according to the position of the failed bit in the corresponding unified area and the standardized repair range, and obtain the standardized repair position as the repair position of the spare circuit in the corresponding unified area.

[0019] According to an embodiment of the present disclosure, the position restoration module is further used to restore the repair position of the spare circuit in the corresponding unified area to the repair position of the spare circuit on the chip according to the standardized line width to repair the failed bit.

[0020] According to one embodiment of the present disclosure, the specification conversion module is also used to: obtain the length of the range of each unified area as the length of the corresponding preset repair range in the extension direction of the spare circuit, or obtain the width of the range of each unified area as the length of the corresponding preset repair range in the extension direction of the spare circuit.

[0021] According to an embodiment of the present disclosure, the backup circuit includes a global backup circuit and a sub-domain backup circuit; the extension direction of the global backup circuit is orthogonal to the extension direction of the sub-domain backup circuit; the preset repair range includes a global repair range and a sub-domain repair range, and the global repair range includes a plurality of sub-domain repair ranges; the global backup circuit is used to repair failed bits within the global repair range on the chip, and the sub-domain backup circuit is used to repair failed bits within the sub-domain repair range on the chip; the length of the range of each unified area is the same as the length of the corresponding global repair range in the extension direction of the global backup circuit, and the width of the range of each unified area is the same as the length of the corresponding sub-domain repair range in the extension direction of the sub-domain backup circuit.

[0022] According to an embodiment of the present disclosure, the standardized repair range includes a standardized global repair range and a standardized subdomain repair range; the specification conversion module is also used to: obtain the standardized global repair range as a range of a corresponding unified area; when the subdomain spare circuit is used for co-location repair, standardize the subdomain repair range corresponding to the subdomain spare circuit to obtain the standardized subdomain repair range, and the length of the standardized subdomain repair range in the extension direction of the global spare circuit is one data grid.

[0023] According to an embodiment of the present disclosure, the specification conversion module is further used to: scale the position of the failed bit on the chip according to the line width of the backup circuit and the standardized line width to obtain the standardized position of the failed bit.

[0024] According to an embodiment of the present disclosure, the position restoration module is further used to restore the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the line width of the spare circuit and the standardized line width to repair the failed bit.

[0025] According to another aspect of the present disclosure, a device is provided, comprising: a memory, a processor, and executable instructions stored in the memory and executable in the processor, wherein the processor implements any of the above methods when executing the executable instructions.

[0026] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored, and when the executable instructions are executed by a processor, any of the above methods is implemented.

[0027] The failed bit repair method provided by the embodiment of the present disclosure obtains the repair specifications of the spare circuit of the chip where the failed bit is located and the position of the failed bit on the chip, standardizes the repair specifications of the spare circuit to obtain the standardized repair specifications, processes the position of the failed bit on the chip according to the standardized repair specifications to obtain the standardized position of the failed bit, and then uses the spare circuit allocation algorithm to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specifications to obtain the standardized repair position of the spare circuit, and then restores the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specifications to repair the failed bit, thereby improving the versatility of the repair algorithm.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0030] Figure 1 A schematic diagram showing a system structure in an embodiment of the present disclosure.

[0031] Figure 2 A flow chart of a failed bit repair method in an embodiment of the present disclosure is shown.

[0032] Figure 3 is based on Figure 2 A data flow diagram of a backup circuit analysis system is shown.

[0033] Figure 4A is based on Figure 3 A block diagram of a product unit is shown.

[0034] Figure 4B The diagram is a schematic diagram showing data segmentation using a backup circuit analysis system according to an exemplary embodiment.

[0035] Figure 5A The figure is a flow chart showing a method for converting specifications of a standby circuit according to an exemplary embodiment.

[0036] Figure 5B The figure is a schematic diagram of area division according to an exemplary embodiment.

[0037] Fig. 6A The flowchart of another method for converting specifications of a standby circuit is shown according to an exemplary embodiment.

[0038] Figure 6B The figure is a schematic diagram of standardized sub-domain division according to an exemplary embodiment.

[0039] Figure 6C is a schematic diagram of co-location repair according to an exemplary embodiment.

[0040] Figure 7 The figure is a schematic diagram of unified specification data according to an exemplary embodiment.

[0041] Figure 8 The figure is a flow chart showing another failed bit repairing method according to an exemplary embodiment.

[0042] Fig. 9 is based on Figure 8 A data flow diagram of another backup circuit analysis system is shown.

[0043] Fig.10 is based on Figure 8 and Fig. 9 A data flow diagram of another backup circuit analysis system is shown.

[0044] Fig.11 A schematic structural diagram of an electronic device in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0045] Example embodiments will now be described in more detail with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to more fully convey the concepts of the example embodiments to those skilled in the art. The accompanying drawings are only schematic illustrations of the disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0046] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, devices, steps, etc. may be adopted. In other cases, well-known structures, methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0047] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. The symbol " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0048] In this disclosure, unless otherwise clearly specified and limited, terms such as "connection" should be understood in a broad sense, for example, it can be an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0049] As described above, a spare circuit is provided on a chip containing failed bits, and the chip includes spare circuits extending in a predetermined direction, and these spare circuits are used to repair the chip by replacing failed bits within a preset repair range. The number of spare circuits is limited, so it is necessary to design RA to assign the spare circuits. RA can obtain positions assigned to various spare circuits, and replace positions at these positions with a high probability of covering all failed bits on the chip. However, the higher the probability that an RA assigns a position to cover all failed bits, the more difficult it is for this RA to become a general algorithm. A general algorithm refers to one that can be easily applied to most (or even all) product specifications. However, RA development is time-consuming and costly. Therefore, improving the versatility of RA has become an urgent problem to be solved.

[0050] Therefore, the present disclosure provides a method for repairing a failed bit, which obtains the repair specifications of the spare circuit of the chip where the failed bit is located and the position of the failed bit on the chip, standardizes the repair specifications of the spare circuit to obtain the standardized repair specifications, processes the position of the failed bit on the chip according to the standardized repair specifications to obtain the standardized position of the failed bit, and then uses a spare circuit allocation algorithm to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specifications to obtain the standardized repair position of the spare circuit, and then restores the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specifications to repair the failed bit, thereby improving the versatility of the repair algorithm.

[0051] Figure 1 An exemplary system architecture 10 is shown to which the failed bit repair method or spare circuit analysis system of the present disclosure may be applied.

[0052] like Figure 1As shown, the system architecture 10 may include a terminal device 102, a network 104, a server 106, and a database 108. The terminal device 102 may be any electronic device having a display screen and supporting input and output, including but not limited to a smart phone, a tablet computer, a laptop computer, a desktop computer, a chip repair device, etc. The network 104 is used to provide a medium for a communication link between the terminal device 102 and the server 106. The network 104 may include various connection types, such as wired, wireless communication links or optical fiber cables, etc. The server 106 may be a server or a server cluster that provides various services, etc. The database 108 may be a large database software placed on a server, or a small database software installed on a computer, for storing data.

[0053] The terminal device 102 may be used to interact with the server 106 and the database 108 through the network 104 to receive or send data, etc. For example, the terminal device 102 may be a chip repair device, which uploads chip failure bit position data and spare circuit repair specifications to the server 106 through the network 104, and obtains the allocated spare circuit repair position from the server 106 through the network 104. The server 106 may also receive data from the database 108 or send data to the database 108 through the network 104. For example, the server 106 may be a background processing server, which is used to obtain chip failure bit position data and spare circuit repair specifications from the database 108 through the network 104, and perform spare circuit allocation, and then feed the allocated spare circuit repair position back to the chip repair device 102 through the network 104.

[0054] It should be understood that Figure 1 The number of terminal devices, networks, servers and databases in the embodiment is only for illustration. Any number of terminal devices, networks, servers and databases may be provided as required.

[0055] Figure 2 FIG. 1 is a flow chart showing a method for repairing a failed bit according to an exemplary embodiment. Figure 2 The method shown can be applied to the server side of the above system, for example, and can also be applied to the terminal device of the above system.

[0056] refer to Figure 2 , the method 20 provided in the embodiment of the present disclosure may include the following steps.

[0057] In step S202, the repair specifications of the spare circuit of the chip where the failed bit is located are obtained. The repair specifications of the spare circuit may include the line width of the spare circuit and the preset repair range of the spare circuit, and may also include the number of spare circuits, etc. Different chip products may have different spare circuit repair specifications.

[0058] In step S204, the repair specifications of the spare circuit are standardized to obtain standardized repair specifications. The standardized repair specifications may include standardized line width and standardized repair range. The line width of the spare circuit may be standardized according to the number of bits, and the repair range may be re-divided according to parameters such as the length and number of the spare circuit to obtain a standardized repair range. For specific implementation methods, please refer to FIG. 5A to FIG. 5B By standardizing the repair specifications of spare circuits, the spare circuit repair specifications of various products are converted into unified standard specifications, which can be used in subsequent spare circuit allocation algorithms.

[0059] In step S206, the position of the failed bit on the chip is obtained. The position data of all failed bits in a chip can be obtained. Different chip products have different ways of arranging the positions. On the chip, it is usually counted in multiples of 2. For example, a chip product consists of 2 2 Each BG is divided into 2 2 The location of a bit in a bank can be represented by 2-bit data such as X15-0, D0-2, Y0-3, etc. In other words, the location of a bit in a chip can be represented by 32 binary values.

[0060] In step S208, the position of the failed bit on the chip is processed according to the standardized repair specification to obtain the standardized position of the failed bit. The position of the failed bit on the chip is scaled according to the line width of the spare circuit and the standardized line width to obtain the standardized position of the failed bit.

[0061] In some embodiments, for example, the scaling parameter may be obtained as normalized line width / original line width of a spare circuit.

[0062] In step S210, a spare circuit allocation algorithm is used to allocate spare circuits according to the standardized positions of the failed bits and the standardized repair specifications to obtain the standardized repair positions of the spare circuits. According to the standardized line width of the spare circuits, the standardized repair range and the number of spare circuits, any algorithm that can effectively allocate spare circuits to completely cover all failed bit positions on the chip can be used to allocate spare circuits to obtain the standardized repair positions of the spare circuits for the standardized repair range.

[0063] In step S212, the standardized repair position of the spare circuit is restored to the repair position of the spare circuit on the chip according to the standardized repair specification to repair the failed bit. The standardized repair position of the spare circuit can be restored to the repair position of the spare circuit on the chip according to the line width of the spare circuit and the standardized line width to repair the failed bit. For example, the repair position of the spare circuit on the chip can be reversely restored according to the above-mentioned scaling parameters, and the data is provided to the chip repair equipment for repair.

[0064] According to the failed bit repair method provided by the embodiment of the present disclosure, the repair specifications of the spare circuit of the chip where the failed bit is located and the position of the failed bit on the chip are obtained, the repair specifications of the spare circuit are standardized to obtain the standardized repair specifications, the position of the failed bit on the chip is processed according to the standardized repair specifications to obtain the standardized position of the failed bit, and then a spare circuit allocation algorithm is used to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specifications to obtain the standardized repair position of the spare circuit, and then the standardized repair position of the spare circuit is restored to the repair position of the spare circuit on the chip according to the standardized repair specifications to repair the failed bit, thereby improving the versatility of the repair algorithm.

[0065] Figure 3 is based on Figure 2 A data flow diagram of a backup circuit analysis system is shown in FIG. Figure 3 As shown, the source data input into the spare circuit analysis system includes the location data 302 of the failed bit on the original chip and the product specification parameter 304. The product specification parameter 304 may be the repair specification of the spare circuit. Figure 3 The solid arrows in the middle represent the processing flow, and the dashed arrows represent the input / output. The backup circuit analysis system may include a product unit 306 and a common unit 308, which are described in detail as follows.

[0066] The product unit 306 can standardize specifications for various product specifications, configure a unified specification data conversion method and specification definition, so that any product specification data (such as new product specifications) can be converted into unified specification data through a standardized method of product specification parameters. The product unit 306 can be used to implement Figure 2 Steps S202 to S208 in .

[0067] The common unit 308 can embed any spare circuit allocation algorithm, so that various spare circuit allocation algorithms can take over the process of unified specification data, and control the unified specification data to perform algorithmic operations to obtain the final spare circuit allocation repair position data 310. The repair position data 310 can be the position data of the repair failed bits of all spare circuit allocations in a chip. The product unit 306 can be used to implement Figure 2Steps S210 to S212 in .

[0068] Figure 4A is based on Figure 3 A data interaction diagram showing data segmentation using an alternate circuit analysis system. Figure 4A The solid arrows in the middle represent the processing flow, and the dashed arrows represent input / output. Figure 4A As shown, the product unit 306 may include a data segmentation module 3062 and a specification conversion module 3064, which are described in detail as follows.

[0069] The data segmentation module 3062 can be used to segment the data of a chip into several independently processable range data that will not affect each other when the backup circuit is allocated. The data segmentation module 3062 can segment the data in the chip according to the product specification parameter 304. Figure 4B FIG. 1 is a schematic diagram of data segmentation according to an exemplary embodiment. Figure 4B As shown, data in a chip is divided into several banks 30722 of data. Each bank of data is divided into several global regions 30724 based on the maximum range (this range is called global region) that can be allocated by the global redundancy (GR) in the product specification, and stored as global region data 3072. The global region data 3072 can be sent to the specification conversion module 3064.

[0070] The specification conversion module 3064 can be used to convert the global data 3072 into the unified specification data 3074 and transmit it to the common unit 308 without affecting the known invalid bit position information. In addition, the data provides the scaling parameters of all bit positions before and after standardization, so that the original position can be calculated for each standardized position. The specific processing flow of the specification conversion module 3064 can be referred to FIG. 5A to FIG. 6C .

[0071] The shared unit 308 provides an algorithm for allocating spare circuits, specifying which spare circuit is to be used to repair each failed bit. There is no need to provide different algorithms for a particular product. Instead, a unified specification data 3074 is provided to implement an orderly processing flow for a large number of segmented data, thereby obtaining the final spare circuit allocation repair position data 310.

[0072] Figure 5A FIG. 1 is a flow chart of a method for converting the specifications of a standby circuit according to an exemplary embodiment. Figure 5A The method shown can be Figure 2 The specific processing process from step S204 to step S208 in FIG. Figure 5AThe method shown can be applied to the server side of the above system, for example, and can also be applied to the terminal device of the above system.

[0073] In step S502, the line width of the spare circuit is standardized according to bits to obtain a standardized line width. To solve the problem that the line widths of various spare circuits in various products are different, the line width of the spare circuit can be standardized according to bits, for example, standardized to 1, 2, or 3 bits.

[0074] In step S504, the chip is divided into a plurality of uniform regions according to the preset repair range, and the range of each uniform region is obtained. The length of the range of each uniform region can be obtained as the length of the corresponding preset repair range in the extension direction of the spare circuit, or the width of the range of each uniform region can be obtained as the length of the corresponding preset repair range in the extension direction of the spare circuit.

[0075] In some embodiments, for example, the spare circuit may include a global spare circuit (GR) and a sub-domain spare circuit (Local Redundancy, LR), the extension direction of the global spare circuit is orthogonal to the extension direction of the sub-domain spare circuit, the preset repair range may include a global repair range and a sub-domain repair range, the global repair range includes multiple sub-domain repair ranges, wherein the global spare circuit is used to repair the failed bits within the global repair range on the chip, and the sub-domain spare circuit is used to repair the failed bits within the sub-domain repair range on the chip. The length of the range of each unified area can be obtained as the length of the corresponding global repair range in the extension direction of the global spare circuit, and the width of the range of each unified area is the same as the length of the corresponding sub-domain repair range in the extension direction of the sub-domain spare circuit.

[0076] Figure 5B FIG. 1 is a schematic diagram of area division according to an exemplary embodiment. Figure 5B As shown, it can be Figure 4B After the chip is divided into multiple global domains, each global domain can be divided into several regions 5002. The GR and LR allocation process of any region will not affect other regions. For example, the GR or LR allocated to a region A cannot cross or overlap with the GR or LR allocation position of other regions except A. The range of a region 5002 can be defined as follows: the GR extension direction range is the length range 50024 of a GR that can be allocated for patching, and the LR extension direction range is the length range 50022 of a LR that can be allocated for patching, where the GR allocation patch example 50026 is Figure 5B In the middle GR direction dashed line, LR dispatch patch example 50028 is Figure 5B Solid line in the middle LR direction.

[0077] In step S506, the preset repair range is standardized according to the range of each unified area to obtain the standardized repair range of the spare circuit. The chip or a whole domain is divided into the range of each unified area, and the repair range of the spare circuit is corresponded to the range of each unified area. For example, the standardized repair range corresponding to each GR or LR can be obtained.

[0078] In step S508, the position of the failed bit on the chip is processed according to the standardized line width, and the standardized position of the failed bit is obtained as the position of the failed bit in the corresponding unified area. The position of each bit on the chip can be standardized to its position in the unified area, and a bit value matrix can be used to indicate whether the bit at the position on the chip or the area is failed. When performing spare circuit allocation calculations, the line width can be standardized by OR operation. For example, if the line width is 3 bits, the values ​​of the first bit, the second bit, and the third bit are ORed, that is, the standardized bit value = the first bit value or the second bit value or the third bit value.

[0079] In some embodiments, for example, GR is used to replace the word line where the failed bit is located, that is, GR = RWL (Redundant Word Line, spare word line), and LR is used to replace the bit line where the failed bit is located, that is, LR = RBL (Redundant Bit Line, spare bit line). For example, the line width of RWL is 2 (bits), the line width of RBL is also 2, and the original sub-domain is

[0080]

[0081] Then the GR line width can be standardized as

[0082]

[0083] In other embodiments, the chip partition can be further refined. For example, a chip can be divided into multiple banks. The GR and LR lengths will not exceed the range of 1 bank, and the GR length is greater than the LR length. Each bank is divided into multiple global domains, each global domain is divided into multiple regions (segments), and each segment can be divided into multiple subdomains and multiple sections. 1 subdomain or section = multiple data areas (or data grids, DQ), 1DQ = multiple bits. In a chip, the size of its bank and global domain will be consistent, while the segment, subdomain, and DQ may have different sizes.

[0084] According to the method for converting the specification of the spare circuit provided in the embodiment of the present disclosure, the spare circuit repair specifications of various products are converted into a unified standard specification, so as to obtain standardized repair data of products with different spare circuit repair specifications. Different products will have different processing processes, so that the final output standardized repair data can meet the input specification requirements of the common unit, and any circuit allocation algorithm can allocate the spare circuits of the standardized repair specifications in the common unit, thereby improving the versatility of the repair algorithm.

[0085] Fig. 6A FIG. 1 is a flow chart showing another method for converting the specifications of a standby circuit according to an exemplary embodiment. Fig. 6A The method shown can be Fig. 6A The specific processing process of step S506 in FIG. Fig. 6A The method shown can be applied to the server side of the above system, for example, and can also be applied to the terminal device of the above system.

[0086] The standardized patch scope includes the standardized global patch scope and the standardized subdomain patch scope.

[0087] In step S602, a standardized global patching range is obtained as a range of a corresponding unified area.

[0088] In step S604, when the subdomain spare circuit is used for co-location repair, the subdomain repair range corresponding to the subdomain spare circuit is standardized to obtain a standardized subdomain repair range, and the length of the standardized subdomain repair range in the extension direction of the global spare circuit is one data grid (DQ).

[0089] In some embodiments, for example, the LR line width may be normalized to

[0090]

[0091] This is the standardized subdomain. The vertical axis uses DQ as the basic unit for OR operation or addition operation. For example, if the vertical DQ in each original subdomain is regarded as a matrix, then

[0092]

[0093] where d ijk represents the value of the kth bit in the DQ at the i-th row and j-th column in the original sub-field; Represents the value of the kth bit in the jth column DQ in the normalized subfield. As mentioned above, the value of the bit is 0 or 1.

[0094] Figure 6B FIG. 1 is a schematic diagram showing the division of standardized subdomains according to an exemplary embodiment. Figure 6BAs shown, if LR has the feature of patching the same position in continuous DQ in the GR direction, the original subdomain 6002 is standardized to obtain the standardized subdomain 6004, that is, the range of the original subdomain 6002 in the GR direction is standardized to the minimum acceptable range, usually 1DQ, so that the uniform specification data does not need to consider the same-position patching problem when used.

[0095] Figure 6C FIG. 1 is a schematic diagram of co-location repair according to an exemplary embodiment. Figure 6C As shown in the figure, without unified specification data, the left figure shows a failed bit in the original sub-domain, and the right figure shows the LR repair circuit assigned in the LR direction. One LR is just a spare circuit, not multiple spare circuits. It looks like multiple (or rows) because of the circuit design behind them. They are all the same. When repairing, just specify a certain LR position and replace the line position that originally had a failed bit, so as to achieve the purpose of repairing the failed bit.

[0096] Figure 7 FIG. 1 is a schematic diagram of unified specification data according to an exemplary embodiment. Figure 7 As shown, a chip may include multiple full domains 6008, a full domain 6008 may be divided into multiple regions 6006, and a region 6006 may be divided into multiple standardized sub-domains 6004 in the GR direction.

[0097] Figure 8 FIG. 1 is a flow chart showing another method for repairing a failed bit according to an exemplary embodiment. Figure 8 The method shown can be Figure 5A The failed bit repair process is performed after step S508. Figure 8 The method shown can be applied to the server side of the above system, for example, and can also be applied to the terminal device of the above system.

[0098] In step S802, in each unified area, a spare circuit allocation algorithm is used to allocate spare circuits according to the position of the failed bit in the corresponding unified area and the standardized repair range, and the standardized repair position is the repair position of the spare circuit in the corresponding unified area. Any spare circuit allocation algorithm that effectively allocates spare circuits to completely cover the failed bit position can be used to output the position and result of spare circuit allocation, which is whether the failed bit in the whole domain can be successfully and completely covered and repaired by the limited spare circuit. If successful, it is a valid whole domain, otherwise it is a failed whole domain.

[0099] In step S804, the repair position of the spare circuit in the corresponding unified area is restored to the repair position of the spare circuit on the chip according to the standardized line width to repair the failed bit. When the line width is standardized according to the bit, the standardized line width is obtained, for example, standardized to 1, or 2, or 3 bits, and the corresponding GR direction is reduced to 1 / original GR line width, or 2 / original GR line width, or 2 / original GR line width, and the LR direction is reduced to 1 / original LR line width, or 2 / original LR line width, or 2 / original LR line width. When the repair position data is finally output, the reduced position needs to be enlarged back for restoration.

[0100] Fig. 9 is based on Figure 8 A data flow diagram of another backup circuit analysis system is shown. Fig. 9 The solid connecting arrows represent the processing flow, and the dashed connecting arrows represent input / output.

[0101] refer to Fig. 9 , where Figure 3 and Figure 4A Modules with the same meaning have the same numbers and will not be repeated here. Fig. 9 As shown, the shared unit 308 may include an input control module 3082, which can be used to input a large number of uniform specification data 3074 that have been data segmented, so that the GR and LR allocation process of any area will not affect other areas, and each area can enter the allocation algorithm module 3084 in sequence for spare circuit allocation processing. When each area enters the allocation algorithm module 3084, additional auxiliary parameters can be given, such as the available number of GRs in the current global domain and LRs in the area, etc. The allocation algorithm module 3084 provides any algorithm that can effectively allocate spare circuits to completely cover the failed bit positions, and outputs the position and result of the spare circuit allocation, namely the allocation data 3088. The result is whether the failed bits in the global domain can be successfully and completely covered and repaired by the limited spare circuits. If successful, it is a valid global domain, otherwise it is a failed global domain. The bank to which the failed global domain belongs will also be designated as a failed bank. The position restoration module 3086 restores the spare circuit allocation repair positions (which are standardized positions) in the allocation data 3088 to the original positions by using the scaling parameters provided in the unified specification data 3074 , and outputs all allocation repair original positions to the repair position data 310 .

[0102] Fig.10 is based on Figure 8 and Fig. 9 A data flow diagram of another backup circuit analysis system is shown. Fig.10 The solid connecting arrows represent the processing flow, and the dashed connecting arrows represent input / output.

[0103] refer to Fig.10, where Figure 3 , Figure 4A and Fig. 9 Modules with the same meaning have the same numbers and will not be repeated here. Fig. 9 As shown, in the shared unit 308, after receiving the unified specification data 3074, the input control module 3082 first reads the entire domain in the chip in sequence (S3002), and then reads the regions in the entire domain in sequence (S30010) and then enters the dispatch algorithm module 3084. When the dispatch algorithm module 3084 performs spare circuit dispatch, it determines whether the dispatch result is that the failed bits in the region can be successfully and completely covered and repaired by the limited spare circuit (S3008). If so, it further determines whether there is an unprocessed region in the corresponding entire domain (S3004). If there is an unprocessed region, it returns to step S30010 for reading. If there is no unprocessed region, it determines whether there is an unprocessed entire domain (S3006). If there is an unprocessed entire domain, it returns to step S3002 for reading. If there is no unprocessed entire domain, it enters the position restoration module 3086 to restore the spare circuit dispatch repair position in the dispatch data 3088 to the original position, and outputs all dispatch repair original positions to the repair position data 310.

[0104] Fig.11 The following is a schematic diagram showing the structure of an electronic device in an embodiment of the present disclosure. It should be noted that: Fig.11 The device shown is only an example of a computer system, which should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0105] like Fig.11 As shown, the device 1100 includes a central processing unit (CPU) 1101, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1102 or a program loaded from a storage part 1108 into a random access memory (RAM) 1103. In the RAM 1103, various programs and data required for the operation of the device 1100 are also stored. The CPU 1101, the ROM 1102, and the RAM 1103 are connected to each other via a bus 1104. An input / output (I / O) interface 1105 is also connected to the bus 1104.

[0106] The following components are connected to the I / O interface 1105: an input section 1106 including a keyboard, a mouse, etc.; an output section 1107 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1108 including a hard disk, etc.; and a communication section 1109 including a network interface card such as a LAN card, a modem, etc. The communication section 1109 performs communication processing via a network such as the Internet. A drive 1110 is also connected to the I / O interface 1105 as needed. A removable medium 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1110 as needed, so that a computer program read therefrom is installed into the storage section 1108 as needed.

[0107] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 1109, and / or installed from a removable medium 1111. When the computer program is executed by a central processing unit (CPU) 1101, the above-mentioned functions defined in the system of the present disclosure are executed.

[0108] It should be noted that the computer-readable medium shown in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0109] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0110] The modules involved in the embodiments described in the present disclosure may be implemented by software or hardware. The modules described may also be set in a processor, for example, it may be described as: a processor includes a parameter acquisition module, a specification conversion module, a circuit allocation module and a position restoration module. The names of these modules do not constitute a limitation on the modules themselves in some cases, for example, the parameter acquisition module may also be described as a "module for acquiring chip parameters from a connected terminal".

[0111] As another aspect, the present disclosure also provides a computer-readable medium, which may be included in the device described in the above embodiment; or it may exist independently and not be assembled into the device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by a device, the device includes: obtaining the repair specifications of the spare circuit of the chip where the failed bit is located; standardizing the repair specifications of the spare circuit to obtain the standardized repair specifications; obtaining the position of the failed bit on the chip; processing the position of the failed bit on the chip according to the standardized repair specifications to obtain the standardized position of the failed bit; using the spare circuit allocation algorithm to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specifications to obtain the standardized repair position of the spare circuit; restoring the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specifications to repair the failed bit.

[0112] The exemplary embodiments of the present disclosure are specifically shown and described above. It should be understood that the present disclosure is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present disclosure is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. A method for repairing a failed bit, characterized in that: include: Obtaining repair specifications for a spare circuit of a chip where the failed bit is located; Standardizing the repair specifications of the standby circuit to obtain standardized repair specifications; Obtaining the position of the failed bit on the chip; Processing the position of the failed bit on the chip according to the standardized repair specification to obtain the standardized position of the failed bit; Using a spare circuit allocation algorithm to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specification, to obtain a standardized repair position of the spare circuit; Restoring the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specification to repair the failed bit; The repair specification of the standby circuit includes the line width of the standby circuit and the preset repair range of the standby circuit; The standardized repair specifications include standardized line width and standardized repair range; The step of standardizing the repair specifications of the standby circuit to obtain the standardized repair specifications includes: Standardizing the line width of the backup circuit according to bits to obtain a standardized line width; Dividing the chip into a plurality of unified areas according to the preset repair range to obtain the range of each unified area; The preset repair range is standardized according to the range of each unified area to obtain a standardized repair range of the standby circuit.

2. The method according to claim 1, characterized in that The step of processing the position of the failed bit on the chip according to the standardized repair specification to obtain the standardized position of the failed bit includes: Processing the position of the fail bit on the chip according to the standardized line width, obtaining the standardized position of the fail bit as the position of the fail bit in the corresponding unified area; The method of using a spare circuit allocation algorithm to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specification includes: In each unified area, the spare circuit allocation algorithm is used to allocate the spare circuit according to the position of the failed bit in the corresponding unified area and the standardized repair range, and the standardized repair position is obtained as the repair position of the spare circuit in the corresponding unified area.

3. The method according to claim 2, characterized in that The step of restoring the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specification to repair the failed bit comprises: The repair position of the spare circuit in the corresponding unified area is restored to the repair position of the spare circuit on the chip according to the standardized line width to repair the failed bit.

4. The method according to any one of claims 2 to 3, characterized in that: The step of dividing the chip into a plurality of unified areas according to the preset repair range and obtaining the range of each unified area comprises: The length of each unified area is obtained as the length of the corresponding preset repair range in the extension direction of the spare circuit, or The width of each uniform area is obtained as the length of the corresponding preset repair range in the extension direction of the standby circuit.

5. The method according to claim 4, characterized in that The backup circuit includes a global backup circuit and a sub-domain backup circuit; The extension direction of the global backup circuit is orthogonal to the extension direction of the sub-domain backup circuit; The preset repair range includes a global repair range and a sub-domain repair range, and the global repair range includes a plurality of sub-domain repair ranges; The global spare circuit is used to repair failed bits within the global repair range on the chip, and the sub-domain spare circuit is used to repair failed bits within the sub-domain repair range on the chip; The length of the range of each unified area is the same as the length of the corresponding global repair range in the extension direction of the global spare circuit, and the width of the range of each unified area is the same as the length of the corresponding sub-domain repair range in the extension direction of the sub-domain spare circuit.

6. The method according to claim 5, characterized in that The standardized repair scope includes a standardized global repair scope and a standardized subdomain repair scope; The step of standardizing the preset repair range according to the range of each unified area to obtain the standardized repair range of the standby circuit includes: Obtaining the standardized global patching range as the range of the corresponding unified area; When the subdomain spare circuit is used for co-location repair, the subdomain repair range corresponding to the subdomain spare circuit is standardized to obtain the standardized subdomain repair range, and the length of the standardized subdomain repair range in the extension direction of the global spare circuit is one data grid.

7. The method according to claim 1, characterized in that The step of processing the position of the failed bit on the chip according to the standardized repair specification to obtain the standardized position of the failed bit includes: The position of the failed bit on the chip is scaled according to the line width of the spare circuit and the standardized line width to obtain the standardized position of the failed bit.

8. The method according to claim 7, characterized in that The step of restoring the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specification to repair the failed bit comprises: The standardized repair position of the spare circuit is restored to the repair position of the spare circuit on the chip according to the line width of the spare circuit and the standardized line width to repair the failed bit.

9. A failed bit repair device, comprising: A parameter acquisition module, used to acquire the repair specification of the spare circuit of the chip where the failed bit is located; and acquire the position of the failed bit on the chip; A specification conversion module, used for standardizing the repair specification of the standby circuit to obtain a standardized repair specification; processing the position of the failure bit on the chip according to the standardized repair specification to obtain a standardized position of the failure bit; A circuit allocation module, configured to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specification by using a spare circuit allocation algorithm to obtain a standardized repair position of the spare circuit; A position restoration module, used for restoring the standardized repair position of the standby circuit to the repair position of the standby circuit on the chip according to the standardized repair specification to repair the failed bit; The repair specification of the standby circuit includes the line width of the standby circuit and the preset repair range of the standby circuit; The standardized repair specifications include standardized line width and standardized repair range; The step of standardizing the repair specifications of the standby circuit to obtain the standardized repair specifications includes: Standardizing the line width of the backup circuit according to bits to obtain a standardized line width; Dividing the chip into a plurality of unified areas according to the preset repair range to obtain the range of each unified area; The preset repair range is standardized according to the range of each unified area to obtain a standardized repair range of the standby circuit.

10. A device comprising: A memory, a processor, and executable instructions stored in the memory and executable in the processor, wherein the processor implements the method according to any one of claims 1 to 8 when executing the executable instructions.

11. A computer-readable storage medium having computer-executable instructions stored thereon, characterized in that: When the executable instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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