Super junction structure for improving EMI and manufacturing method thereof

Abstract

This invention discloses a superjunction structure and manufacturing method for improving EMI. The method involves alternately growing epitaxial layers N- and N-2 on an N+ substrate; etching deep trenches on the N- epitaxial surface, followed by P-type epitaxy, and performing CMP (Continuous Metal-Plasma Processing) to form an alternating N-pillar and P-pillar superjunction structure; implanting a body region using a PWELL photolithography plate and annealing to form a PWELL region; depositing a field oxide layer and etching it back to form the gate structure of the device; implanting As and annealing to form the N-source of the device; depositing an ILD (Integrated Layer Diameter) and etching it back; performing via injection; and finally depositing metal and etching it back to form the final structure of the device. This invention improves the C-V characteristics of the device through optimization of the epitaxial structure, thereby improving EMI performance, reducing the characteristic on-resistance, lowering conduction losses, and increasing device efficiency.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor discrete device technology, and relates to a superjunction structure and manufacturing method for improving EMI. It can effectively improve the capacitance characteristics of superjunction MOSFETs, optimize EMI performance, and reduce the characteristic on-resistance of the device. Background Technology

[0002] The high on-resistance of conventional VDMOS devices increases the static power consumption of the switching circuit; its RDS(on) is related to BV. 2.5 Proportional, while the RDS(on) of a superjunction MOSFET is proportional to BV. 1.3 Proportional to RDS(on), therefore, under the same voltage withstand conditions, RDS(on) is much lower than that of ordinary MOSFETs. At the same Ron condition, the chip area is smaller, the switching losses are lower, and the overall efficiency is higher. These superjunction devices are widely used in power supplies or adapters for consumer electronics products such as computers, mobile phones, lighting, and LCD or plasma TVs and game consoles.

[0003] Currently, there are two main process paths for superjunction MOSFET devices: superjunction processes involving multiple epitaxial growth and implantation, and superjunction processes involving trench etching and filling. The multiple epitaxial growth and implantation process involves more photomasks and more photolithography steps; advanced multiple epitaxial growth processes typically require over twenty photolithography steps. Furthermore, the quality of each epitaxial growth step and interlayer alignment are challenging, resulting in high thermal budgets, long production cycles, and high costs. However, these are standard semiconductor processes with relatively low implementation difficulty. The trench etching and filling superjunction process uses fewer photomask layers, has simpler process steps, shorter production cycles, and lower production costs. However, etching trenches with extremely high aspect ratios and filling requires high process control, making implementation more difficult. Both process paths are developing towards continuously shrinking the device cell size, which leads to continuously increasing power density and faster switching speeds. As power switching transistors, power MOSFETs operate in a rapid on-off cycle, with their voltage and current changing drastically. They are the main sources of interference from electric and magnetic field coupling, and one of the main sources of EMI in circuits such as switching power supplies. Due to differences in structure and process, the optimization of EMI performance of deep trench etching and filling processes is particularly important. Summary of the Invention

[0004] The purpose of this invention is to provide a superjunction MOSFET structure and manufacturing method. It adopts a trench etching and filling process path and optimizes the design of the epitaxial layer structure to combine the advantages of multiple epitaxial processes. The process steps are simple, effectively improving EMI performance and reducing the characteristic on-resistance of the device.

[0005] The specific implementation method is as follows:

[0006] A method for manufacturing a superjunction MOSFET structure, characterized in that:

[0007] The method includes the following steps:

[0008] Step 1: Grow an epitaxial layer N- on an N+ substrate, and then grow another epitaxial layer N-2;

[0009] Step 2: Continue growing epitaxial layer N- on top of epitaxial layer N-2, then grow another epitaxial layer N-2, and continue growing epitaxial layer N- until the target epitaxial thickness is reached;

[0010] Step 3: On the N-epitaxial surface, deep trenches are etched using a Trench photolithography plate, and then a certain concentration of P-type epitaxial material is grown to fill the trenches. CMP process is then performed to remove the P-type and N-type epitaxial material outside the trenches, forming a superjunction structure with alternating N-pillar and P-pillar phases.

[0011] Step 4: Inject the bulk region through PW photolithography and anneal to form the PWELL region, deposit the field oxide layer and etch back, and deposit and etch back through gate oxide Gox and polysilicon to form the gate structure of the device.

[0012] Step 5: Implant As and anneal to form the N-source of the device;

[0013] Step 6: Deposit ILD and etch back, perform hole injection, and finally deposit metal and etch back to form the final structure of the device.

[0014] The resistivity of epitaxial layer N- is higher than that of epitaxial layer N-2.

[0015] The resistivity of the epitaxial layer N- is twice that of the epitaxial layer N-2.

[0016] The thickness of the epitaxial layer N-2 is 2 μm.

[0017] The N-thickness of the epitaxial layer decreases sequentially in the three growth stages.

[0018] In step 1, the N-thickness of the epitaxial layer is 60% of the target epitaxial thickness.

[0019] In step 2, during the first growth of the epitaxial layer N-, the thickness reaches 90% of the target epitaxial thickness.

[0020] A superjunction MOSFET structure obtained by the manufacturing method described above.

[0021] The present invention has the following advantages:

[0022] This invention improves the CV characteristics of a device by optimizing its epitaxial structure without altering the existing superjunction process or redesigning the photolithography mask. This improves EMI performance, reduces the device's characteristic on-resistance, lowers conduction losses, and increases device efficiency. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of step 1.

[0024] Figure 2 This is a schematic diagram of step 2.

[0025] Figure 3 This is a schematic diagram for step 3.

[0026] Figure 4 This is a schematic diagram for step 4.

[0027] Figure 5 This is a schematic diagram for step 5.

[0028] Figure 6 This is a schematic diagram for step 6.

[0029] Figure 7 The diagram shows the improved Cgd capacitor characteristics of this invention. Detailed Implementation

[0030] The present invention will now be described in detail with reference to specific embodiments.

[0031] This invention relates to a method for manufacturing a superjunction MOSFET structure, the method comprising the following steps:

[0032] Step 1: See Figure 1 An epitaxial layer N- with slightly higher resistivity is grown on an N+ substrate. The thickness of the layer is 60% of the target epitaxial thickness, and the resistivity is R. At the same time, a 2µm epitaxial layer N-2 is grown, with a resistivity 0.5 times that of the epitaxial layer, i.e., a resistivity of 0.5R.

[0033] Step 2: See Figure 2 On top of epitaxial layer N-2, another epitaxial layer N- is grown with a resistivity of R and a thickness of 90% of the target epitaxial thickness. Then, another 2µm epitaxial layer N-2 is grown with a resistivity of 0.5 times that of the epitaxial layer (i.e., 0.5R). Epitaxial layer N- is grown until the target epitaxial thickness is reached.

[0034] Step 3: See Figure 3 On the N-epitaxial surface, deep trenches are etched using a Trench photolithography plate, and a certain concentration of P-type epitaxial material is grown to fill the trenches. Then, a CMP process is performed to remove both the P-type and N-type epitaxial material outside the trenches, forming a superjunction structure with alternating N-pillar and P-pillar phases.

[0035] Step 4: See Figure 4 The PWELL region is formed by injecting the body region through a PW photolithography plate and annealing. The field oxide layer is deposited and etched back. The gate structure of the device is formed by depositing gate oxide Gox and polysilicon through etching back.

[0036] Step 5: See Figure 5 As is injected and annealed to form the N-source of the device.

[0037] Step 6: See Figure 6 The process involves depositing an ILD and etching it back, hole injection, and finally depositing metal and etching it back to form the final structure of the device.

[0038] See Figure 7 Through the design and verification of this invention, it was found that compared with conventional superjunction structures, the optimized doping distribution of the internal epitaxial layer improves the CV characteristics of the device. The capacitance change in the low-voltage VDS section is relatively smooth, and the capacitance value in the high-voltage VDS section is also significantly improved, which can improve the EMI problem of the device during fast switching. At the same time, due to the reduction of the effective drift region concentration, the characteristic on-resistance is reduced by about 6%, which reduces the conduction loss of the device.

[0039] The content of this invention is not limited to the embodiments listed. Any equivalent modifications made by those skilled in the art to the technical solutions of this invention by reading this specification are covered by the claims of this invention.

Claims

1. A method for manufacturing a superjunction MOSFET structure, characterized in that: The method includes the following steps: Step 1: Grow an epitaxial layer N- on an N+ substrate, and then grow another epitaxial layer N-2; Step 2: Continue growing epitaxial layer N- on top of epitaxial layer N-2, then grow another epitaxial layer N-2, and continue growing epitaxial layer N- until the target epitaxial thickness is reached; wherein, epitaxial layers N- and N-2 are stacked alternately three times, and the thickness of epitaxial layer N- decreases in each of the three growths. Step 3: On the N-epitaxial surface, deep trenches are etched using a Trench photolithography plate, and then a certain concentration of P-type epitaxial material is grown to fill the trenches. CMP process is then performed to remove the P-type and N-type epitaxial material outside the trenches, forming a superjunction structure with alternating N-pillar and P-pillar phases. Step 4: Inject the bulk region through PW photolithography and anneal to form the PWELL region, deposit the field oxide layer and etch back, and deposit and etch back through gate oxide Gox and polysilicon to form the gate structure of the device. Step 5: Implant As and anneal to form the N-source of the device; Step 6: Deposit ILD and etch back, perform via injection, and finally deposit metal and etch back to form the final structure of the device; The resistivity of the epitaxial layer N- is twice that of the epitaxial layer N-2; The thickness of the epitaxial layer N-2 is 2 μm; In step 1, the N-thickness of the epitaxial layer is 60% of the target epitaxial thickness; In step 2, during the first growth of the epitaxial layer N-, the thickness reaches 90% of the target epitaxial thickness.

2. A superjunction MOSFET structure obtained by the manufacturing method as described in claim 1.

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