Memory element and method for manufacturing the same

Abstract

A memory device is provided, comprising a semiconductor substrate having a first active region and a second active region, the second active region being adjacent to the first active region. The memory device also has a first word line extending through the first active region and the second active region. The memory device also has a first source / drain region located in the first active region and a second source / drain region located in the second active region, wherein the first source / drain region and the second source / drain region are disposed on opposite sides of the first word line. In addition, the memory device has a first capacitor and a second capacitor; the first capacitor is disposed on the first source / drain region in the first active region and is electrically connected to the first source / drain region in the first active region; and the second capacitor is disposed on the second source / drain region in the second active region and is electrically connected to the second source / drain region in the second active region. The first capacitor and the second capacitor have different sizes.

Description

Technical Field

[0001] This application claims priority to and the benefit of U.S. regular application No. 17 / 099,206, filed on November 16, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a memory device and a method for manufacturing the same, and more particularly to a memory device having different types of capacitors and a method for manufacturing the same. Background Art

[0003] Due to its simple structure, dynamic random access memory (DRAMs) can provide more memory cells per unit chip area than other types of memory, such as static random access memory (SRAMs). DRAM is constructed from multiple DRAM cells, where each DRAM cell includes a capacitor for storing information and a transistor coupled to the capacitor to regulate when the capacitor is charged or discharged. During a read operation, the DRAM turns on the transistor by enabling a word line (WL). The enabled transistor allows voltage to pass through the capacitor to be read by a sense amplifier via a bit line (BL). During a write operation, and when the WL is in the enabled state, the data to be written is provided on the BL.

[0004] To meet the demand for greater memory storage capacity, the size of DRAM memory cells has continued to shrink, significantly increasing the storage density of DRAMs. However, the manufacturing and integration of these memory devices involves many complex steps and operations. The integration of these memory devices is becoming increasingly complex. The increased complexity of manufacturing and integrating these memory devices can lead to defects. Therefore, there is a need to continuously improve the structure and manufacturing process of these memory devices to address these defects and enhance their performance.

[0005] The above description of “prior art” is merely to provide background technology, and does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0006] One embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate having a first active region and a second active region, the second active region being adjacent to the first active region. The memory element also has a first word line extending through the first active region and the second active region. The memory element further has a first source / drain region located in the first active region and a second source / drain region located in the second active region, the first source / drain region and the second source / drain region being disposed on opposite sides of the first word line. In addition, the memory element has a first capacitor disposed on the first source / drain region in the first active region and electrically connected to the first source / drain region in the first active region; and a second capacitor disposed on the second source / drain region in the second active region and electrically connected to the second source / drain region in the second active region.

[0007] In some embodiments, the first capacitor and the second capacitor have different widths along a longitudinal axis of the first active region. In some embodiments, a first dielectric layer in the first capacitor and a second dielectric layer in the second capacitor comprise different materials. In some embodiments, the memory device further comprises a third capacitor disposed on a third source / drain region in the first active region and electrically connected to the third source / drain region in the first active region; and a fourth capacitor disposed on a fourth source / drain region in the second active region and electrically connected to the fourth source / drain region in the second active region, wherein the third capacitor and the fourth capacitor have different sizes.

[0008] In some embodiments, the memory device further includes a first bit line disposed on a fifth source / drain region in the first active region and electrically connected to the fifth source / drain region in the first active region; and a second bit line disposed on a sixth source / drain region in the second active region and electrically connected to the sixth source / drain region in the second active region. In some embodiments, the first source / drain region in the first active region and the second source / drain region in the second active region are disposed between the first bit line and the second bit line. In some embodiments, the memory device further includes a conductive contact disposed between the first capacitor and the first source / drain region, wherein an air gap is defined between the first bit line and the conductive contact.

[0009] Another embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate having a first active region and a second active region, the second active region being adjacent to the first active region. The memory element also has a first word line extending through the first active region and the second active region. The memory element further has a first source / drain region located in the first active region and a second source / drain region located in the second active region, the first source / drain region and the second source / drain region being disposed on opposite sides of the first word line. In addition, the memory element has a first capacitor disposed on the first source / drain region in the first active region and electrically connected to the first source / drain region in the first active region; and a second capacitor disposed on the second source / drain region in the second active region and electrically connected to the second source / drain region in the second active region. The first capacitor and the second capacitor comprise different materials.

[0010] In some embodiments, the first capacitor includes a first dielectric layer sandwiched between a first conductive layer and a second conductive layer; the second capacitor includes a second dielectric layer sandwiched between a third conductive layer and a fourth conductive layer; wherein the first dielectric layer and the second dielectric layer comprise different materials. In some embodiments, an area occupied by the first capacitor is smaller than an area occupied by the second capacitor. In some embodiments, the memory element further includes a third capacitor disposed on a third source / drain region in the first active region and electrically connected to the third source / drain region in the first active region; and a fourth capacitor disposed on a fourth source / drain region in the second active region and electrically connected to the fourth source / drain region in the second active region, wherein the third capacitor and the fourth capacitor comprise different dielectric materials. In some embodiments, an area occupied by the third capacitor is smaller than an area occupied by the fourth capacitor.

[0011] In some embodiments, the memory device further includes a second word line extending through the first active region but not through the second active region; and a third word line extending through the second active region but not through the first active region, wherein the first word line is disposed between the second word line and the third word line. Furthermore, the memory device has a first bit line disposed on a fifth source / drain region in the first active region between the first word line and the second word line and electrically connected to the fifth source / drain region in the first active region between the first word line and the second word line; and a second bit line disposed on a sixth source / drain region in the second active region between the first word line and the third word line and electrically connected to the sixth source / drain region in the second active region between the first word line and the third word line. In some embodiments, the memory device further includes a dielectric layer disposed on the semiconductor substrate, wherein the first bit line and the second bit line are disposed in the dielectric layer, and the first bit line and the second bit line are separated from the dielectric layer by a plurality of air gaps.

[0012] Another embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate having a first active region and a second active region, the second active region being adjacent to the first active region. The memory element also has a first word line extending through the first active region and the second active region; and a second word line extending through the first active region but not through the second active region. The memory element also has a first source / drain region disposed in the first active region; a second source / drain region disposed in the second active region; and a third source / drain region disposed in the first active region. The first source / drain region and the second source / drain region are disposed on opposite sides of the first word line, and the second source / drain region and the third source / drain region are disposed on opposite sides of the second word line. Furthermore, the memory device includes a first capacitor disposed on the first source / drain region in the first active region and electrically connected to the first source / drain region in the first active region; a second capacitor disposed on the second source / drain region in the second active region and electrically connected to the second source / drain region in the second active region; and a third capacitor disposed on the third source / drain region in the first active region and electrically connected to the third source / drain region in the first active region. A size of the first capacitor is substantially the same as a size of the third capacitor, and a size of the first capacitor is different from a size of the second capacitor.

[0013] In some embodiments, a lower surface of the second capacitor is larger than a lower surface of the first capacitor. In some embodiments, the first capacitor includes a first dielectric layer sandwiched between a first conductive layer and a second conductive layer; the second capacitor includes a second dielectric layer sandwiched between a third conductive layer and a fourth conductive layer; wherein the first dielectric layer and the second dielectric layer comprise different materials. In some embodiments, the third capacitor includes a third dielectric layer sandwiched between a fifth conductive layer and a sixth conductive layer, wherein the third dielectric layer comprises the same material as the first dielectric layer of the first capacitor.

[0014] In some embodiments, the memory device further includes a third word line extending through the second active region but not through the first active region; and a fourth source / drain region disposed in the second active region, wherein the first source / drain region and the fourth source / drain region are disposed on opposite sides of the third word line. Furthermore, the memory device has a fourth capacitor disposed on the fourth source / drain region in the second active region and electrically connected to the fourth source / drain region in the second active region, wherein a size of the fourth capacitor is substantially the same as a size of the second capacitor. In some embodiments, the memory device further includes a fifth source / drain region disposed in the first active region and between the first word line and the second word line; and a sixth source / drain region disposed in the second active region and between the first word line and the third word line. Furthermore, the memory device has a first bit line electrically connected to the fifth source / drain region; and a second bit line electrically connected to the sixth source / drain region.

[0015] The present disclosure provides some embodiments of a memory device and methods for fabricating the same. In some embodiments, the memory device comprises a first capacitor and a second capacitor disposed on and electrically connected to source / drain regions in different active regions. Because the first and second capacitors have different sizes and / or different dielectric materials, multiple levels of storage capacity can be achieved, thereby improving overall device performance.

[0016] The above has provided a fairly broad overview of the technical features and advantages of the present disclosure, allowing for a better understanding of the detailed description of the present disclosure below. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure pertains that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure pertains that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] A more complete understanding of the disclosure of this application may be obtained by referring to the embodiments and claims in conjunction with the drawings, in which like reference numerals refer to like elements.

[0018] Figure 1 A top view schematically illustrates a memory device according to some embodiments of the present disclosure.

[0019] Figure 2 Some embodiments of the present disclosure are illustrated along Figure 1 Schematic cross-sectional view of the memory element as viewed along the section line AA'.

[0020] Figure 3 Some embodiments of the present disclosure are illustrated along Figure 1 Schematic cross-sectional view of the memory element as viewed along the section line BB'.

[0021] Figure 4 A top view schematically illustrates an improved memory device according to some embodiments of the present disclosure.

[0022] Figure 5 Some embodiments of the present disclosure are illustrated along Figure 4 FIG. 5 is a schematic cross-sectional view of the improved memory element taken along the section line AA′. FIG.

[0023] Figure 6 Some embodiments of the present disclosure are illustrated along Figure 4 FIG. 5 is a schematic cross-sectional view of the improved memory element taken along the section line BB′.

[0024] Figure 7 A schematic flow chart illustrating a method for fabricating a memory device according to some embodiments of the present disclosure is provided.

[0025] Figure 8 A top view schematically illustrates an intermediate stage in some embodiments of the present disclosure, wherein the intermediate stage is forming a plurality of active regions on a semiconductor substrate during fabrication of the memory device.

[0026] Figure 9 Some embodiments of the present disclosure are illustrated in an intermediate stage of preparing the memory element. Figure 8 A schematic cross-sectional view taken along the section line AA'.

[0027] Figure 10 A schematic top view illustrating an intermediate stage in some embodiments of the present disclosure, wherein the intermediate stage is forming a plurality of trenches through the active region during fabrication of the memory device.

[0028] Figure 11 Some embodiments of the present disclosure are illustrated in an intermediate stage of preparing the memory element. Figure 10 A schematic cross-sectional view taken along the section line AA'.

[0029] Figure 12 A top view schematically illustrates an intermediate stage in some embodiments of the present disclosure, wherein the intermediate stage is forming a plurality of word lines in the trench during fabrication of the memory device.

[0030] Figure 13 Some embodiments of the present disclosure are illustrated in an intermediate stage of preparing the memory element. Figure 12 A schematic cross-sectional view taken along the section line AA'.

[0031] Figure 14 A top view schematically illustrates an intermediate stage in some embodiments of the present disclosure, wherein the intermediate stage is forming a dielectric cap layer on the word line during fabrication of the memory device.

[0032] Figure 15 Some embodiments of the present disclosure are illustrated in an intermediate stage of preparing the memory element. Figure 14 A schematic cross-sectional view taken along the section line AA'.

[0033] Figure 16 A top view schematically illustrates an intermediate stage in some embodiments of the present disclosure, wherein the intermediate stage is forming a plurality of bit lines on the dielectric cap layer during fabrication of the memory device.

[0034] Figure 17 Some embodiments of the present disclosure are illustrated in an intermediate stage of preparing the memory element. Figure 16 A schematic cross-sectional view taken along the section line AA'.

[0035] Figure 18 A top view schematically illustrates an intermediate stage in some embodiments of the present disclosure, wherein the intermediate stage is forming a plurality of air gaps on sidewalls of the bit line during fabrication of the memory device.

[0036] Figure 19 Some embodiments of the present disclosure are illustrated in an intermediate stage of preparing the memory element. Figure 18 A schematic cross-sectional view taken along the section line AA'.

[0037] Figure 20 A top view schematically illustrates an intermediate stage in some embodiments of the present disclosure, wherein the intermediate stage is forming a dielectric layer to cover the bit line and the air gap during fabrication of the memory device.

[0038] Figure 21 Some embodiments of the present disclosure are illustrated in an intermediate stage of preparing the memory element. Figure 20 A schematic cross-sectional view taken along the section line AA'.

[0039] Figure 22 A schematic top view illustrating an intermediate stage in some embodiments of the present disclosure, wherein the intermediate stage is forming a plurality of conductive contacts in the dielectric layer during fabrication of the memory device.

[0040] Figure 23 Some embodiments of the present disclosure are illustrated in an intermediate stage of preparing the memory element. Figure 22 A schematic cross-sectional view taken along the section line AA'.

[0041] Figure 24 Some embodiments of the present disclosure are illustrated in an intermediate stage of preparing the memory element. Figure 22 A schematic cross-sectional view taken along the section line BB'.

[0042] The description of the accompanying drawings is as follows:

[0043] 10: Preparation method

[0044] 100: Memory element

[0045] 101: Semiconductor substrate

[0046] 103: Insulation structure

[0047] 105: Active Zone

[0048] 107: Doping area

[0049] 110: Groove

[0050] 113a: Source / drain region

[0051] 113b: Source / drain region

[0052] 115: Gate dielectric layer

[0053] 117: Gate electrode

[0054] 119: Character line

[0055] 121: Dielectric cover layer

[0056] 123: Opening

[0057] 125: Lower bit line layer

[0058] 127: Upper bit line layer

[0059] 129: Bit line

[0060] 131: Dielectric interstitial

[0061] 133: Dielectric layer

[0062] 135: Air Gap

[0063] 137: Dielectric layer

[0064] 139: Opening

[0065] 141: Conductive contact point

[0066] 143: Dielectric layer

[0067] 145a: Opening

[0068] 145b: Opening

[0069] 151a: Conductive layer

[0070] 151b: Conductive layer

[0071] 153a: Dielectric layer

[0072] 153b: Dielectric layer

[0073] 155a: Conductive layer

[0074] 155b: Conductive layer

[0075] 157a: Capacitor

[0076] 157b: Capacitor

[0077] 200: Memory element

[0078] 251a: Conductive layer

[0079] 251b: Conductive layer

[0080] 253a: Dielectric layer

[0081] 253b: Dielectric layer

[0082] 255a: Conductive layer

[0083] 255b: conductive layer

[0084] 257a: Capacitor

[0085] 257b: Capacitor

[0086] BS1: Lower surface

[0087] S11: Steps

[0088] S13: Steps

[0089] S15: Steps

[0090] S17: Steps

[0091] S19: Steps

[0092] S21: Steps

[0093] S23: Steps

[0094] W1: width

[0095] W2: width

[0096] W3: Width

[0097] W4: Width DETAILED DESCRIPTION

[0098] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0099] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0100] Figure 1 A top view schematically illustrates a memory device 100 according to some embodiments of the present disclosure. Figure 2 Some embodiments of the present disclosure are illustrated along Figure 1 FIG. 1 is a schematic cross-sectional view of the memory element 100 taken along the section line AA′. Figure 3Some embodiments of the present disclosure are illustrated along Figure 1 FIG. 1 is a schematic cross-sectional view of the memory element 100 taken along the section line BB′.

[0101] like Figures 1 to 3 As shown, the memory device 100 comprises a semiconductor substrate 101, an insulating structure 103, a plurality of word lines 119 (e.g., gate structures), and a plurality of source / drain regions 113a and 113b. The insulating structure 103 is disposed in the semiconductor substrate 101 to define a plurality of active regions 105. The plurality of word lines 119 extend through the active regions 105. The plurality of source / drain regions 113a and 113b are located in the active regions 105 and separated by the word lines 119. In some embodiments, each active region 105 has two source / drain regions 113b and one source / drain region 113a disposed between the two source / drain regions 113b. Furthermore, each word line 119 has a gate dielectric layer 115 and a gate electrode 117, and the gate electrode 117 is surrounded by the gate dielectric layer 115.

[0102] The memory device 100 also includes a dielectric cap layer 121, a dielectric layer 133, and a plurality of bit lines 129. The dielectric cap layer 121 covers the word lines 119. The dielectric layer 133 is disposed on the dielectric cap layer 121. The plurality of bit lines 129 pass through the dielectric layer 133 and the dielectric cap layer 121 to electrically connect to the source / drain regions 113a. In some embodiments, each bit line 129 includes a lower bit line layer 125 and an upper bit line layer disposed on the lower bit line layer 125. In some embodiments, the bit lines 129 are separated from the dielectric layer 133 by a plurality of air gaps 135.

[0103] The memory device 100 further comprises a dielectric layer 137, a plurality of conductive contacts 141, and a dielectric layer 143. The dielectric layer 137 is disposed on the dielectric layer 133. The plurality of conductive contacts 141 pass through the dielectric cap layer 121 and the dielectric layers 133 and 137 to be electrically connected to the source / drain regions 113b. The dielectric layer 143 is disposed on the dielectric layer 137. Figures 1 to 3 As shown, according to some embodiments, the memory device 100 has a first set of capacitors 157 a and a second set of capacitors 157 b disposed in the dielectric layer 143 to be electrically connected to the source / drain regions 113 b via the conductive contacts 141 .

[0104] In some embodiments, the capacitors 157a are substantially the same size, and the capacitors 157b are substantially the same size. In the context of this disclosure, the word "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%. In some embodiments, the first set of capacitors 157a and the second set of capacitors 157b have different sizes. In some embodiments, the first set of capacitors 157a has a smaller footprint than the second set of capacitors 157b. Figure 2 As shown, according to some embodiments, along the longitudinal axis of the active region 105, each capacitor 157a has a width W1; and Figure 3 As shown, each capacitor 157b has a width W2 along the longitudinal axis of the active region 105. In some embodiments, width W2 is greater than width W1. In addition, each bottom surface of the capacitor 157b is greater than each bottom surface BS1 of the capacitor 157a.

[0105] In some embodiments, as Figure 2 As shown, according to some embodiments, each capacitor 157a includes a conductive layer 151a, a dielectric layer 153a, and a conductive layer 155a. The dielectric layer 153a is disposed on the conductive layer 151a, and the conductive layer 155a is disposed on the dielectric layer 153a. In some embodiments, the conductive layer 155a is surrounded by the dielectric layer 153a, and the dielectric layer 153a is surrounded by the conductive layer 151a. In some embodiments, the dielectric layer 153a is sandwiched between the conductive layers 151a and 155a.

[0106] In addition, if Figure 3 As shown, according to some embodiments, each capacitor 157b includes a conductive layer 151b, a dielectric layer 153b, and a conductive layer 155b. The dielectric layer 153b is disposed on the conductive layer 151b, and the conductive layer 155b is disposed on the dielectric layer 153b. In some embodiments, the conductive layer 155b is surrounded by the dielectric layer 153b, and the dielectric layer 153b is surrounded by the conductive layer 151b. In some embodiments, the dielectric layer 153b is sandwiched between the conductive layers 151b and 155b.

[0107] In some embodiments, the dielectric layer 153a of the first set of capacitors 157a comprises a first material, and the dielectric layer 153b of the second set of capacitors 157b comprises a second material, where the first material is different from the second material. For example, the dielectric layer 153a of the first set of capacitors 157a comprises silicon dioxide, while the dielectric layer 153b of the second set of capacitors 157b comprises hafnium dioxide (HfO2). In some embodiments, the memory device 100 is a dynamic random access memory (DRAM). Because the dimensions of the first set of capacitors 157a differ from those of the second set of capacitors 157b, multiple levels of memory capacity are achieved. Consequently, overall device performance can be improved.

[0108] Figure 4 A top view schematically illustrates an improved memory device 200 according to some embodiments of the present disclosure. Figure 5 Some embodiments of the present disclosure are illustrated along Figure 4 Schematic cross-sectional view of the improved memory element 2020 as viewed along the section line AA′. Figure 6 Some embodiments of the present disclosure are illustrated along Figure 4 sectional view of the improved memory element 200 as viewed from the section line BB'. Figures 1 to 6 Similar components that appear will be designated with the same component numbers.

[0109] like Figures 4 to 6 As shown, according to some embodiments, similar to the memory device 100, the improved memory device 200 has a first set of capacitors 257a and a second set of capacitors 257b, which are disposed in the dielectric layer 143 and electrically connected to the source / drain region 113b via the conductive contact 141. However, the size of the capacitor 257a is substantially the same as the size of the capacitor 257b. Figure 5 As shown, along the longitudinal axis of the active region 105, each capacitor 257a has a width W3; and Figure 6 As shown, according to some embodiments, each capacitor 257b has a width W4 along the longitudinal axis of the active region 105. In some embodiments, the width W3 is substantially the same as the width W4.

[0110] In some embodiments, as Figure 5As shown, according to some embodiments, each capacitor 257a includes a conductive layer 251a, a dielectric layer 253a, and a conductive layer 255a. The dielectric layer 253a is disposed on the conductive layer 251a, and the conductive layer 255a is disposed on the dielectric layer 253a. In some embodiments, the conductive layer 255a is surrounded by the dielectric layer 253a, and the dielectric layer 253a is surrounded by the conductive layer 251a. In some embodiments, the dielectric layer 253a is sandwiched between the dielectric layers 251a and 255a.

[0111] Furthermore, in some embodiments, as Figure 6 As shown, according to some embodiments, each capacitor 257b includes a conductive layer 251b, a dielectric layer 253b, and a conductive layer 255b. The dielectric layer 253b is disposed on the conductive layer 251b; the conductive layer 255b is disposed on the dielectric layer 253b. In some embodiments, the conductive layer 255b is surrounded by the dielectric layer 253b, and the dielectric layer 253b is surrounded by the conductive layer 251b. In some embodiments, the dielectric layer 253b is sandwiched between the dielectric layers 251b and 255b.

[0112] In some embodiments, the dielectric layer 253a of the first set of capacitors 257a comprises a first material, and the dielectric layer 253b of the second set of capacitors 257b comprises a second material, where the first material is different from the second material. For example, the dielectric layer 253a of the first set of capacitors 257a comprises silicon dioxide, while the dielectric layer 253b of the second set of capacitors 257b comprises hafnium dioxide (HfO2). In some embodiments, the memory device 100 is a dynamic random access memory (DRAM). Because the dimensions of the first set of capacitors 257a differ from those of the second set of capacitors 257b, multiple levels of memory capacity are achieved. Consequently, overall device performance can be improved.

[0113] Figure 7 A flow chart illustrating a method 10 for fabricating a memory device (including memory devices 100 and 200 ) according to some embodiments of the present disclosure is provided. The method 10 includes steps S11 , S13 , S15 , S17 , S19 , S21 , and S23 . Figure 7 Steps S11 to S23 are described in detail with reference to the following figures.

[0114] Figure 8 、 Figure 10 、 Figure 12 、 Figure 14 、 Figure 16 、 Figure 18 、 Figure 20 as well as Figure 22is a top view schematically illustrating various intermediate stages in the fabrication of the memory element 100 according to some embodiments of the present disclosure; and Figure 9 、 Figure 11 、 Figure 13 、 Figure 15 、 Figure 17 、 Figure 19 、 Figure 21 、 Figure 23 as well as Figure 24 1 is a cross-sectional view illustrating various intermediate stages in the preparation of the memory element 100 according to some embodiments of the present disclosure. It should be understood that Figure 9 、 Figure 11 、 Figure 13 、 Figure 15 、 Figure 17 、 Figure 19 、 Figure 21 as well as Figure 23 are respectively exemplified along Figure 8 、 Figure 10 、 Figure 12 、 Figure 14 、 Figure 16 、 Figure 18 、 Figure 20 as well as Figure 22 A schematic cross-sectional view along the section line AA', and Figure 24 Example edge Figure 22 Schematic cross-sectional view of the section line BB'.

[0115] like Figure 8 and Figure 9 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or in addition, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of the elemental semiconductor materials may include, but are not limited to, single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of the compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of the alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0116] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 includes an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator (SIO) substrate, which may include a substrate, a buried oxide layer, and a semiconductor layer, wherein the buried oxide layer is disposed on the substrate, and the semiconductor layer is disposed on the buried oxide layer. The SIO substrate is, for example, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SIO substrate may be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0117] Please still refer to Figure 8 and Figure 9 According to some embodiments, an insulating structure 103 is formed in the semiconductor substrate 101 to define the active region 105, and the insulating structure 103 is a shallow trench isolation (STI) structure. The individual steps are shown in FIG. Figure 7 Step S11 of the preparation method 10 is shown. Furthermore, the insulating structure 103 may comprise silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials; and the formation of the insulating structure 103 may include forming a patterned mask (not shown) on the semiconductor substrate 101; etching the semiconductor substrate 101 using the patterned mask as a mask to form a plurality of openings (not shown); depositing a dielectric material in the openings and on the semiconductor substrate 101; and polishing the dielectric material until the semiconductor substrate 101 is exposed.

[0118] Furthermore, a plurality of doped regions 107 are formed in the active region 105 defined by the insulating structure 103. In some embodiments, the fabrication techniques for the doped regions 107 include one or more ion implantation processes, and a plurality of P-type dopants or a plurality of N-type dopants may be implanted into the active region 105 to form the doped regions 107. The P-type dopant is, for example, boron (B), gallium (Ga), or indium (In), and the N-type dopant is, for example, phosphorus (P) or arsenic (As), depending on the conductivity type of the memory device 100. Furthermore, in subsequent fabrication processes, the doped regions 107 will become the source / drain regions of the semiconductor device 100.

[0119] like Figure 10 and Figure 11 As shown, according to some embodiments, after the doped region 107 is formed, the semiconductor substrate 101 is etched to form a plurality of trenches 110. In some embodiments, the trenches 110 are parallel to each other. In some embodiments, the trenches 110 extend through the doped region 107 located in the active region 105 to form source / drain regions 113a and 113b. The individual steps are shown in FIG. Figure 7 Step S13 in the preparation method 10 shown.

[0120] In some embodiments, the source / drain regions 113b are located at opposite ends of the active region 105, while the source / drain regions 113a are located at intermediate portions of the active region 105. Forming the trench 110 may include forming a patterned mask (not shown) on the semiconductor substrate 101 and etching the semiconductor substrate 101 using the patterned mask as a mask. After the trench 110 is formed, the patterned mask may be removed.

[0121] Then, if Figure 12 and Figure 13 As shown, according to some embodiments, a plurality of word lines 119 (eg, gate structures) may be formed in the trench 110. The respective steps are shown in FIG. Figure 7 In step S15 of the manufacturing method 10 , in some embodiments, the word line 119 includes a plurality of gate dielectric layers 115 and a plurality of gate electrodes 117 .

[0122] In some embodiments, the gate dielectric layer 115 comprises silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (high-k), or a combination thereof; and the gate electrode 117 comprises a conductive material such as aluminum, copper, tungsten, titanium, tantalum, or may be a multilayer structure comprising any combination of the foregoing materials. In some embodiments, multiple barrier layers (not shown) are formed between the gate dielectric layer 115 and the gate electrode 117.

[0123] The formation of the gate dielectric layer 115 may include conformally depositing a gate dielectric material (not shown) on each inner surface of the trench 110 and on the upper surface of the semiconductor substrate 101, and planarizing the gate dielectric material to expose the upper surface of the semiconductor substrate 101. After the gate dielectric layer 115 is formed, the formation of the gate electrode 117 may include depositing a gate electrode material (not shown) on the gate dielectric layer 115, and recessing the gate electrode material to form the gate electrode 117.

[0124] The gate dielectric material deposition process may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other applicable processes. The gate dielectric material planarization process may be a chemical mechanical polishing (CMP) process. The gate electrode material deposition process may include one or more deposition processes, such as a CVD process, a PVD process, an ALD process, a plasma enhanced chemical vapor deposition (MOCVD) process, a plating process, a sputtering process, or other applicable deposition processes. The gate electrode material may be recessed by an etch-back process so that the upper surfaces of the gate electrodes 117 are lower than the upper surface of the semiconductor substrate 101. The etch-back process may include a wet etching process, a dry etching process, or a combination thereof.

[0125] Next, if Figure 14 and Figure 15 As shown, according to some embodiments, a dielectric capping layer 121 is formed to cover the word lines 119, and the dielectric capping layer 121 is partially removed to form a plurality of openings 123, which expose the source / drain regions 113a. In some embodiments, portions of the dielectric capping layer 121 are surrounded by the gate dielectric layer 115. In some embodiments, the dielectric capping layer 121 comprises silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials.

[0126] In some embodiments, the manufacturing technology of the dielectric cap layer 121 includes a CVD process, a PVD process, a spin coating process, other applicable processes or a combination thereof. In some embodiments, the opening 123 passing through the dielectric cap layer 121 is a bit line opening. The formation of the opening 123 may include forming a patterned mask (not shown) on the dielectric cap layer 121; and etching the dielectric cap layer 121 using the patterned mask as a mask. The etching process may be a wet etching process, a dry etching process or a combination thereof. In some embodiments, the etching process is used to remove some portions of the source / drain region 113a exposed by the patterned mask. After the opening 123 is formed, the patterned mask may be removed.

[0127] like Figure 16 and Figure 17 As shown, according to some embodiments, after partially removing the dielectric cap layer 121, the bit line 129 is formed on the dielectric cap layer 121, and the opening 123 is filled with the bit line 129. The respective steps are shown in FIG. Figure 7 This is step S17 of the manufacturing method 10. In some embodiments, the bit line 129 is electrically connected to the source / drain region 113a.

[0128] In some embodiments, the bit line 129 includes multiple lower bit line layers 125 and multiple upper bit line layers 127, and the opening 123 is filled with the lower bit line layers 125. Forming the bit line 129 may include forming a lower bit line material (not shown) on the dielectric cap layer 121 and filling the opening 123; forming an upper bit line material (not shown) on the lower bit line material; forming a patterned mask (not shown) on the upper bit line material; and etching the upper and lower bit line materials using the patterned mask as a mask. In some embodiments, the remaining portion of the lower bit line material (e.g., the lower bit line layer 125) and the remaining portion of the upper bit line material (e.g., the upper bit line layer 127) have aligned sidewalls. After the bit line is formed, the patterned mask may be removed.

[0129] Then, if Figure 16 and Figure 17 As shown, according to some embodiments, a plurality of dielectric spacers 131 are formed on the sidewalls of the bit line 129. In some embodiments, the dielectric spacers 131 comprise a doped spin-on glass (SOG) material, such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In some embodiments, the dielectric spacers 131 are fabricated using a spin-on coating process followed by a planarization process, such as a CMP process. The planarization process may be performed to expose the upper surfaces of the bit line 129.

[0130] Then, if Figure 18 and Figure 19 As shown, according to some embodiments, a dielectric layer 133 is formed to surround the dielectric spacers 131, and the dielectric spacers 131 are removed to form a plurality of air gaps 135 between the bit line 129 and the dielectric layer 133. In other words, the air gaps 134 are formed on each sidewall of the bit line 129, and the bit line 129 is separated from the dielectric layer 133 by the air gaps 135. The respective steps are shown in FIG. Figure 7 Step S19 in the preparation method 10 shown.

[0131] In some embodiments, dielectric layer 133 includes a low-k dielectric material. In some embodiments, the low-k dielectric material has a dielectric constant (k value) less than approximately 4. Examples of the low-k dielectric material include, but are not limited to, silicon oxide, silicon nitride, silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), or polyimide.

[0132] In some embodiments, the fabrication technique for dielectric layer 133 includes a deposition process followed by a planarization process. The deposition process may include a CVD process, a PVD process, a spin coating process, or other applicable processes. The planarization process may include a polishing process, a CMP process, an etching process, other applicable processes, or a combination thereof. After the planarization process, the upper surface of dielectric layer 133 is coplanar with the upper surfaces of the bit lines 129 and the upper surfaces of the dielectric spacers 131.

[0133] In some embodiments, after the dielectric layer 133 is formed, the dielectric spacers 131 are removed by a vapor phase hydrofluoric acid (VHF) etching process. During the etching process, VHF is used as an etchant and has a high selectivity for the dielectric spacers 131 relative to the dielectric layer 133. Therefore, the dielectric spacers 131 are removed by the etching process while the dielectric layer 133 is substantially left, thereby forming the air gap 135.

[0134] Next, if Figure 20 and Figure 21 As shown, according to some embodiments, a dielectric layer 137 is formed on the dielectric layer 133 to seal the air gap 135, and the dielectric cap layer 131 and the dielectric layers 133 and 137 are partially removed to form a plurality of openings 139. The openings 1398 expose the source / drain regions 113b. Some materials and processes used to form the dielectric layer 137 are similar to or the same as those used to form the dielectric layer 133, and their detailed descriptions are not repeated herein.

[0135] In some embodiments, the dielectric layer 137 is formed by a spin-on coating process, and the air gap 135 having a high aspect ratio is sealed by the dielectric layer 137, with the air gap 135 remaining therein, rather than being completely filled by the dielectric layer 137. In some embodiments, the dielectric layer 137 extends into an upper portion of the air gap 135, such that a top surface of the air gap 135 is lower than a top surface of the bit line 129.

[0136] In some embodiments, the openings 139 formed through the dielectric cap layer 121 and the dielectric layers 133 and 137 are capacitor contact openings. Forming the openings 139 may include forming a patterned mask (not shown) on the dielectric layer 137 and etching the dielectric layer 137 using the patterned mask as a mask. The etching process may be a wet etching process, a dry etching process, or a combination thereof. After the openings 139 are formed, the patterned mask may be removed.

[0137] like Figures 22 to 24 As shown, according to some embodiments, after the opening 139 is formed, the conductive contact 141 is formed in the opening 139, and a dielectric layer 143 is formed on the dielectric layer 137 to cover the conductive contact 141. In some embodiments, the conductive contact is a capacitor contact that electrically connects the source / drain region 113b located between the bit lines 129 to a plurality of capacitors formed subsequently. The individual steps are shown in FIG. Figure 7 Step S21 in the preparation method 10 shown.

[0138] In some embodiments, the conductive contact 141 comprises a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, or silver. The fabrication technique for the conductive contact 141 may include a deposition process followed by a planarization process. The deposition process may include a CVD process, a PVD process, a sputtering process, a plating process, or other applicable processes. The planarization process may be a CMP process. Some of the materials and processes used to form the dielectric layer 143 are similar to those used to form the dielectric layer 133, and their detailed descriptions are not repeated herein.

[0139] Please still refer to Figures 22 to 24According to some embodiments, a first set of openings 145a and a second set of openings 145b are formed to pass through the dielectric layer 143 to expose the conductive contacts 141. In some embodiments, the sizes of the openings 145a are substantially the same, and the sizes of the openings 145b are substantially the same. In some embodiments, the first set of openings 145a and the second set of openings 145b have different sizes. In some embodiments, as Figure 23 As shown, along the longitudinal axis of the active region 105, each opening 145a has a width W1; Figure 24 As shown, each opening 145b has a width W2 along the longitudinal axis of the active region 105. In some embodiments, the width W2 is greater than the width W1.

[0140] The formation of the openings 145a and 145b may include forming a patterned mask (not shown) on the dielectric layer 143; and etching the dielectric layer 143 using the patterned mask as a mask to expose the conductive contacts 141. The etching process may be a wet etching process, a dry etching process, or a combination thereof. After the openings 145a and 145b are formed, the patterned mask may be removed.

[0141] Next, please refer back to Figures 1 to 3 According to some embodiments, a first set of capacitors 157a is formed in a first set of openings 145a in the dielectric layer 143, and a second set of capacitors 157b is formed in a second set of openings 145b in the dielectric layer 143. The individual steps are shown in FIG. Figure 7 This is step S23 of the manufacturing method 10. It should be understood that, according to some embodiments, the size of the capacitor 157a is different from the size of the capacitor 157b.

[0142] As described above, the first set of capacitors 157a includes conductive layers 151a and 155a, and a plurality of dielectric layers 153a disposed between the conductive layers 151a and 155a. The second set of capacitors 157b includes conductive layers 151b and 155b, and a plurality of dielectric layers 153b disposed between the conductive layers 151b and 155b. In some embodiments, the conductive layers 151a and 151b comprise titanium nitride; the dielectric layers 153a and 153b comprise a dielectric material such as silicon dioxide, hafnium dioxide, aluminum oxide, zirconium dioxide, or a combination thereof; and the conductive layers 155a and 155b comprise titanium nitride, low-stress silicon germanium (SiGe), or a combination thereof.

[0143] In some embodiments, the dielectric layer 153a of the first set of capacitors 157a comprises a material that is different from the material of the dielectric layer 153b of the second set of capacitors 157b. For example, the dielectric layer 153a comprises silicon dioxide, and the dielectric layer 153b comprises hafnium dioxide. After the formation of the capacitors 157a and 157b, the semiconductor device 100 is obtained.

[0144] The present disclosure provides some embodiments of memory devices 100 and 200. In some embodiments, each memory device 100, 200 has a first set of capacitors and a second set of capacitors, which are disposed on source / drain regions in different active regions and electrically connected to source / drain regions in different active regions; and the first set of capacitors and the second set of capacitors have different characteristics. For example, in memory device 100, the first set of capacitors 157a and the second set of capacitors 157b have different sizes. Furthermore, in memory device 200, the dielectric layer 1253a of the first set of capacitors 257a and the dielectric layer 253b of the second set of capacitors 257b comprise different materials. Thus, multiple levels of storage capacity can be obtained. This can improve overall device performance.

[0145] One embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate having a first active region and a second active region, the second active region being adjacent to the first active region. The memory element also has a first word line extending through the first active region and the second active region. The memory element further has a first source / drain region located in the first active region and a second source / drain region located in the second active region, the first source / drain region and the second source / drain region being disposed on opposite sides of the first word line. In addition, the memory element has a first capacitor disposed on the first source / drain region in the first active region and electrically connected to the first source / drain region in the first active region; and a second capacitor disposed on the second source / drain region in the second active region and electrically connected to the second source / drain region in the second active region.

[0146] Another embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate having a first active region and a second active region, the second active region being adjacent to the first active region. The memory element also has a first word line extending through the first active region and the second active region. The memory element further has a first source / drain region located in the first active region and a second source / drain region located in the second active region, the first source / drain region and the second source / drain region being disposed on opposite sides of the first word line. In addition, the memory element has a first capacitor disposed on the first source / drain region in the first active region and electrically connected to the first source / drain region in the first active region; and a second capacitor disposed on the second source / drain region in the second active region and electrically connected to the second source / drain region in the second active region. The first capacitor and the second capacitor comprise different materials.

[0147] Another embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate having a first active region and a second active region, the second active region being adjacent to the first active region. The memory element also has a first word line extending through the first active region and the second active region; and a second word line extending through the first active region but not through the second active region. The memory element also has a first source / drain region disposed in the first active region; a second source / drain region disposed in the second active region; and a third source / drain region disposed in the first active region. The first source / drain region and the second source / drain region are disposed on opposite sides of the first word line, and the second source / drain region and the third source / drain region are disposed on opposite sides of the second word line. Furthermore, the memory device includes a first capacitor disposed on the first source / drain region in the first active region and electrically connected to the first source / drain region in the first active region; a second capacitor disposed on the second source / drain region in the second active region and electrically connected to the second source / drain region in the second active region; and a third capacitor disposed on the third source / drain region in the first active region and electrically connected to the third source / drain region in the first active region. A size of the first capacitor is substantially the same as a size of the third capacitor, and a size of the first capacitor is different from a size of the second capacitor.

[0148] The disclosed embodiments have several advantages. By combining different types of capacitors (e.g., multiple capacitors with different sizes and / or different dielectric materials) in a memory device, multiple levels of storage capacity can be achieved. This can improve overall device performance.

[0149] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0150] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A memory element comprising: A semiconductor substrate having a first active region and a second active region, wherein the second active region is adjacent to the first active region; wherein the first active region includes a first source / drain region and the second active region includes a second source / drain region; a first word line extending through both the first active region and the second active region; wherein the first source / drain region in the first active region and the second source / drain region in the second active region are disposed on opposite sides of the first word line, wherein the first source / drain region and the second source / drain region are separated by the first word line; a first capacitor disposed on the first source / drain region in the first active region and electrically connected to the first source / drain region in the first active region; as well as a second capacitor disposed on the second source / drain region in the second active region and electrically connected to the second source / drain region in the second active region, wherein the first capacitor in the first active region and the second capacitor in the second active region have different sizes, and both the first capacitor and the second capacitor extend through the first word line. 2 . The memory device of claim 1 , wherein the first capacitor and the second capacitor have different widths along a longitudinal axis of the first active region. 3 . The memory device of claim 1 , wherein a first dielectric layer in the first capacitor and a second dielectric layer in the second capacitor comprise different materials.

4. The memory element of claim 1 , further comprising: a third capacitor disposed on a third source / drain region in the first active region and electrically connected to the third source / drain region in the first active region; as well as A fourth capacitor is disposed on a fourth source / drain region in the second active region and is electrically connected to the fourth source / drain region in the second active region, wherein the third capacitor and the fourth capacitor have different sizes.

5. The memory element of claim 1 , further comprising: a first bit line disposed on a fifth source / drain region in the first active region and electrically connected to the fifth source / drain region in the first active region; as well as A second bit line is disposed on a sixth source / drain region in the second active region and is electrically connected to the sixth source / drain region in the second active region. 6 . The memory device as claimed in claim 5 , wherein the first source / drain region in the first active region and the second source / drain region in the second active region are disposed between the first bit line and the second bit line.

7. The memory device as claimed in claim 5, further comprising a conductive contact disposed between the first capacitor and the first source / drain region, wherein an air gap is formed between the first bit line and the conductive contact.

8. A memory element comprising: A semiconductor substrate having a first active region and a second active region, wherein the second active region is adjacent to the first active region; a first word line extending through both the first active region and the second active region; wherein the first source / drain region in the first active region and the second source / drain region in the second active region are disposed on opposite sides of the first word line, wherein the first source / drain region and the second source / drain region are separated by the first word line; a first capacitor disposed on the first source / drain region in the first active region and electrically connected to the first source / drain region in the first active region; as well as a second capacitor disposed on the second source / drain region in the second active region and electrically connected to the second source / drain region in the second active region, wherein the first capacitor and the second capacitor comprise different materials, and both the first capacitor and the second capacitor extend through the first word line.

9. The memory element of claim 8, wherein the first capacitor comprises a first dielectric layer sandwiched between a first conductive layer and a second conductive layer; the second capacitor comprises a second dielectric layer sandwiched between a third conductive layer and a fourth conductive layer; wherein, The first dielectric layer and the second dielectric layer include different materials. 10 . The memory device as claimed in claim 8 , wherein an occupied area of ​​the first capacitor is smaller than an occupied area of ​​the second capacitor.

11. The memory element of claim 8, further comprising: a third capacitor disposed on a third source / drain region in the first active region and electrically connected to the third source / drain region in the first active region; as well as A fourth capacitor is disposed on a fourth source / drain region in the second active region and electrically connected to the fourth source / drain region in the second active region, wherein the third capacitor and the fourth capacitor comprise different dielectric materials. 12 . The memory device as claimed in claim 11 , wherein an occupied area of ​​the third capacitor is smaller than an occupied area of ​​the fourth capacitor.

13. The memory element of claim 8, further comprising: a second word line extending through the first active area but not through the second active area; a third word line extending through the second active region but not through the first active region, wherein the first word line is disposed between the second word line and the third word line; a first bit line disposed on a fifth source / drain region in the first active region between the first word line and the second word line and electrically connected to the fifth source / drain region in the first active region between the first word line and the second word line; as well as A second bit line is disposed on a sixth source / drain region in the second active region between the first word line and the third word line and is electrically connected to the sixth source / drain region in the second active region between the first word line and the third word line.

14. The memory device of claim 13, further comprising a dielectric layer disposed on the semiconductor substrate, wherein the first bit line and the second bit line are disposed in the dielectric layer, and the first bit line and the second bit line are separated from the dielectric layer by a plurality of air gaps.

15. A memory element comprising: A semiconductor substrate having a first active region and a second active region, wherein the second active region is adjacent to the first active region; wherein the first active region includes a first source / drain region and the second active region includes a second source / drain region; a first word line extending through both the first active region and the second active region; wherein the first source / drain region in the first active region and the second source / drain region in the second active region are disposed on opposite sides of the first word line, wherein the first source / drain region and the second source / drain region are separated by the first word line; a second word line extending through the first active region but not through the second active region; wherein the second source / drain region and the third source / drain region are disposed on opposite sides of the second word line; a first capacitor disposed on the first source / drain region in the first active region and electrically connected to the first source / drain region in the first active region; a second capacitor disposed on the second source / drain region in the second active region and electrically connected to the second source / drain region in the second active region; as well as a third capacitor disposed on the third source / drain region in the first active region and electrically connected to the third source / drain region in the first active region; wherein a size of the first capacitor is substantially the same as a size of the third capacitor, and the first capacitor in the first active region and the second capacitor in the second active region have different sizes, and both the first capacitor and the second capacitor extend through the first word line. 16 . The memory device of claim 15 , wherein a lower surface of the second capacitor is larger than a lower surface of the first capacitor.

17. The memory element of claim 15 , wherein the first capacitor comprises a first dielectric layer sandwiched between a first conductive layer and a second conductive layer; the second capacitor comprises a second dielectric layer sandwiched between a third conductive layer and a fourth conductive layer; wherein, The first dielectric layer and the second dielectric layer include different materials.

18. The memory device of claim 17, wherein the third capacitor comprises a third dielectric layer sandwiched between a fifth conductive layer and a sixth conductive layer, wherein the third dielectric layer comprises a same material as the first dielectric layer of the first capacitor.

19. The memory element of claim 15, further comprising: a third word line extending through the second active area but not through the first active area; a fourth source / drain region disposed in the second active region, wherein the first source / drain region and the fourth source / drain region are disposed on opposite sides of the third word line; and A fourth capacitor is disposed on the fourth source / drain region in the second active region and electrically connected to the fourth source / drain region in the second active region, wherein a size of the fourth capacitor is substantially the same as that of the second capacitor.

20. The memory element of claim 19, further comprising: a fifth source / drain region disposed in the first active region and between the first word line and the second word line; a sixth source / drain region disposed in the second active region and between the first word line and the third word line; a first bit line electrically connected to the fifth source / drain region; as well as A second bit line is electrically connected to the sixth source / drain region.

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