A three-dimensional self-regulating chaotic oscillator with memristor feedback

Abstract

The present invention discloses a memristor feedback type three-dimensional self-regulating chaotic oscillator, which relates to a design of a three-dimensional memristor chaotic oscillator with adjustable amplitude and bias, and outputs a chaotic signal through a memristor feedback circuit combined with other feedback inputs. The parameter change of the memristor feedback circuit changes the amplitude of the signal, and the bias of the signal is regulated by the voltage of the corresponding branch. The chaotic circuit designed by the present invention can fully realize the amplitude bias control of the chaotic signal, and therefore can be widely used in the fields of confidential communication, signal detection, radar and communication.

Description

Technical Field

[0001] The invention relates to the technical field of electronics, communication and information engineering, and in particular to a memristor feedback type three-dimensional self-regulating chaotic oscillator. Background Art

[0002] Memristors are easy to realize chaos due to their unique nonlinearity, so memristor chaotic systems can also be widely used in fields such as image encryption and secure communications. The special nonlinearity of memristors can give their corresponding systems a special structure, so it is possible to design and control simple chaotic circuits that can achieve amplitude and bias control by a single component parameter to facilitate engineering applications.

[0003] Regarding memristor chaotic circuits, related patents have given different chaotic implementation schemes. For example, the patent application with application number 201810461123.3 proposed a memristor chaotic circuit based on Cai's circuit. The patent application changes the chaotic dynamic characteristics of various chaotic signals by changing certain specific resistors in the circuit. The patent does not have any amplitude control of chaotic signals; the patent application with application number 201910561036.X proposed a four-dimensional hyperchaotic circuit based on memristors. The patent adjusts the weight value of the memristor to make the chaotic circuit generate chaotic signals or periodic signals with different attractors. The patent does not have any bias control of chaotic signals. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a memristor feedback three-dimensional self-regulating chaotic oscillator. The chaotic circuit designed by the present invention can fully realize the amplitude bias control of the chaotic signal, and therefore can be widely used in confidential communication, signal detection, radar and communication and other fields.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] A memristor feedback three-dimensional self-regulating chaotic oscillator according to the present invention comprises a memristor circuit, an integral operation circuit, a first inverting proportional operation circuit, a second inverting proportional operation circuit, first to third resistors, an adjustable DC power supply, a capacitor and an integral operation unit; wherein,

[0007] The memristor circuit, the integral operation circuit, and the first inverting proportional operation circuit are connected in sequence;

[0008] One end of the first resistor is connected to one end of the second resistor, one end of the third resistor, one end of the capacitor, and the inverting input end of the integral operation unit respectively, the other end of the capacitor is connected to the output end of the integral operation unit and the input end of the second inverting proportional operation circuit respectively, the other end of the third resistor is connected to the adjustable DC power supply, and the non-inverting input end of the integral operation unit is grounded.

[0009] As a further optimization scheme of a memristor feedback three-dimensional self-regulating chaotic oscillator described in the present invention, the memristor circuit includes a first multiplier, a second multiplier, a fourth resistor, a fifth resistor, a sixth resistor, an absolute value circuit, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a first integral operation unit, a first power supply, an inverting proportional operation unit, and a third inverting proportional operation circuit; wherein,

[0010] The output end of the first multiplier is connected to one end of the fourth resistor, the other end of the fourth resistor is respectively connected to one end of the first capacitor, one end of the fifth resistor, and the inverting input end of the first integral operation unit, the non-inverting input end of the first integral operation unit is grounded, the other end of the first capacitor is respectively connected to the output end of the first integral operation unit and one end of the sixth resistor, the other end of the sixth resistor is connected to the input end of the absolute value circuit, the output end of the absolute value circuit is connected to one end of the eighth resistor, the other end of the eighth resistor is respectively connected to one end of the seventh resistor, one end of the ninth resistor, and the inverting input end of the inverting proportional operation unit, the other end of the seventh resistor is connected to the first power supply, the non-inverting input end of the inverting proportional operation unit is grounded, the other end of the ninth resistor is respectively connected to the output end of the inverting proportional operation unit and the input end of the second multiplier, and the output end of the second multiplier is connected to the third inverting proportional operation circuit.

[0011] As a further optimization scheme of the memristor feedback three-dimensional self-regulating chaotic oscillator described in the present invention, the chaotic waveform amplitude output by the memristor feedback three-dimensional self-regulating chaotic oscillator is controlled by the size of the fourth resistor, and the signal bias is controlled by an adjustable DC power supply.

[0012] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0013] The present invention uses a summing integral operation circuit, an inverting proportional operation circuit, a multiplier and a diode to output a chaotic signal with adjustable amplitude and bias parameters. The amplitude of the chaotic signal is output through a resistance adjustment circuit of a branch to achieve amplitude regulation, and the bias of the chaotic signal is achieved by adjusting the power supply voltage of a branch, which increases the flexibility of the memristor chaotic circuit, reduces the difficulty of circuit implementation and debugging, and provides convenience for the application of chaotic signals in electronic and information engineering. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a phase trajectory diagram of a three-dimensional self-regulating chaotic oscillator with memristor feedback; wherein, (a) is an x-y plane diagram, (b) is a y-z plane diagram, (c) is an x-z ​​plane diagram, and (d) is an x-y-z plane diagram;

[0015] Figure 2This is a schematic diagram of a memristor feedback three-dimensional self-regulating chaotic oscillator circuit; wherein (a) is a system circuit diagram, and (b) is a memristor circuit diagram.

[0016] Figure 3 It is the phase track and waveform diagram of amplitude control of three-dimensional self-regulating chaotic oscillator with memristor feedback; wherein, (a) is the x-z plane diagram, and (b) is the waveform diagram of x signal;

[0017] Figure 4 It is the phase trajectory and waveform diagram of the bias control of the three-dimensional self-regulating chaotic oscillator with memristor feedback; wherein, (a) is the x-z plane diagram, and (b) is the waveform diagram of the x signal;

[0018] Figure 5 is a phase trajectory diagram of the experimental simulation of a three-dimensional self-regulating chaotic oscillator with memristor feedback; wherein, (a) is an x-z ​​plane diagram, and (b) is a y-z plane diagram;

[0019] Figure 6 It is the phase trajectory diagram and waveform diagram of the amplitude control experiment simulation of the memristor feedback three-dimensional self-regulating chaotic oscillator; among them, (a) is the x-z plane diagram and x signal waveform diagram when R9=10kΩ, (b) is the x-z plane diagram and x signal waveform diagram when R9=3.3kΩ, and (c) is the x-z plane diagram and x signal waveform diagram when R9=1kΩ.

[0020] Figure 7 It is the phase trajectory diagram and waveform diagram of the experimental simulation of bias control of a memristor feedback three-dimensional self-regulating chaotic oscillator; among them, (a) is the x-z plane diagram and x signal waveform diagram when V1=-4V, (b) is the x-z plane diagram and x signal waveform diagram when V1=0V, and (c) is the x-z plane diagram and x signal waveform diagram when V1=4V. DETAILED DESCRIPTION

[0021] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings:

[0022] As a new type of nonlinear element, memristor is widely used in chaotic systems. In recent years, with the development of memristors, some classical systems can be successfully transformed into valuable memristor chaotic systems, which can expand the application scope of memristors and make full use of the characteristics of memristors to realize new functions. The construction and design of memristor chaotic circuits have important theoretical, physical significance and engineering application value. The present invention includes a memristor feedback circuit, an integral operation circuit, a reverse proportional circuit, and uses a diode to realize absolute value calculation. The bias control of the memristor chaotic signal is realized by using the adjustable DC power supply voltage of a branch. The device parameters of the memristor can change the amplitude of the memristor chaotic signal, thereby increasing the flexible control of the chaotic circuit and realizing the self-regulation of the chaotic signal based on the system parameters.

[0023] A memristor feedback type three-dimensional self-regulating chaotic oscillator, comprising a memristor circuit, an integral operation circuit, a first inverting proportional operation circuit, a second inverting proportional operation circuit, first to third resistors R1-R3, an adjustable DC power supply V1, a capacitor C2 and an integral operation unit U3; wherein,

[0024] The memristor circuit, the integral operation circuit, and the first inverting proportional operation circuit are connected in sequence;

[0025] One end of the first resistor is connected to one end of the second resistor, one end of the third resistor, one end of the capacitor, and the inverting input end of the integral operation unit U3 respectively, the other end of the capacitor is connected to the output end of the integral operation unit and the input end of the second inverting proportional operation circuit respectively, the other end of the third resistor is connected to the adjustable DC power supply, and the non-inverting input end of the integral operation unit is grounded.

[0026] The memristor circuit includes a first multiplier A1, a second multiplier A2, a fourth resistor R9, a fifth resistor R 10 , the sixth resistor R 11 , absolute value circuit, seventh resistor R 16 , the eighth resistor R 17 、The ninth resistor R 18 , a first capacitor C3, a first integral operation unit U5, a first power supply V2, an inverting proportional operation unit U8, and a third inverting proportional operation circuit; wherein,

[0027] The output end of the first multiplier is connected to one end of the fourth resistor, the other end of the fourth resistor is respectively connected to one end of the first capacitor, one end of the fifth resistor, and the inverting input end of the first integral operation unit, the non-inverting input end of the first integral operation unit is grounded, the other end of the first capacitor is respectively connected to the output end of the first integral operation unit and one end of the sixth resistor, the other end of the sixth resistor is connected to the input end of the absolute value circuit, the output end of the absolute value circuit is connected to one end of the eighth resistor, the other end of the eighth resistor is respectively connected to one end of the seventh resistor, one end of the ninth resistor, and the inverting input end of the inverting proportional operation unit, the other end of the seventh resistor is connected to the first power supply, the non-inverting input end of the inverting proportional operation unit is grounded, the other end of the ninth resistor is respectively connected to the output end of the inverting proportional operation unit and the input end of the second multiplier, and the output end of the second multiplier is connected to the third inverting proportional operation circuit.

[0028] The amplitude of the chaotic waveform output by the memristor feedback three-dimensional self-regulating chaotic oscillator is controlled by the size of the fourth resistor, and the bias of the signal is controlled by an adjustable direct current power supply.

[0029] The memristor feedback type three-dimensional self-regulating chaotic oscillator is constructed by an integral operation circuit, an inverting proportional operation circuit and a memristor circuit. The internal parameters of the memristor circuit can control the signal amplitude change, and the unipolar bias of the signal is adjusted by the power supply voltage of the second branch.

[0030] The chaotic oscillator includes three branches, in which the first branch inputs the signal y through the memristor and the resistor R1 to connect the integral operation unit U1, outputs the signal x, and then passes through the inverting proportional operation unit U2 to output the signal -x; the second branch inputs the signal z, -x, V1 respectively connects the input end resistors R4, R5, R6 of the integral operation unit U3 to output the signal z, and then passes through the inverting proportional operation unit U4 to output the signal -z; the third branch is the memristor module unit, the input signal is z, -z, y, and finally outputs -W(y)z through the memristor circuit.

[0031] The first branch input signal y is connected to the input end of the integral operation unit U1 through the resistor R1; the input signal y is connected to the memristor W(y) and outputs the -W(y)z term; the integral operation module U1 outputs a signal x, which is connected to the input end R2 of the inverting proportional operation unit U2 and finally outputs a signal -x; the inverting input end of the integral operation unit U1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the output end x of the integral operation unit U1; the inverting input end of the inverting operation unit U2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the output end -x of the inverting proportional operation unit U2.

[0032] The second branch includes three input terminals, namely, input signals -x, z and power supply V1, which are respectively connected to R4, R5 and R6 to be connected to the summing and integrating operation unit U3; the output signal of the summing and integrating operation unit is z, and the output signal z is connected to R7 to be connected to the inverting proportional operation unit U4, and the final output signal is -z; the inverting input terminal of the integrating operation unit U3 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the output terminal z of the integrating operation unit U3; the inverting input terminal of the inverting operation unit U4 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the output terminal -z of the inverting proportional operation unit U4.

[0033] The third branch inputs signals y, z and -z through multiplier A1, integral operation unit U5 outputs signal y, passes through inverting proportional unit U6, diodes D1, D2, inverting proportional operation unit U7 outputs signal |y|, connects inverting proportional operation unit U8 and input voltage V2, outputs W(y) and input signal z, passes through multiplier A2 and inverting proportional operation unit U9, and finally outputs -W(y)z. The memristor circuit includes multipliers A1 and A2, resistors R9, and resistor R 10 , resistor R 11 , resistor R 12 , resistor R 13, resistor R 14 , resistor R 15 , resistor R 16 , resistor R 17 , resistor R 18 , resistor R 19 , resistor R 20 , diodes D1 and D2, capacitor C3, power supply V2, integral operation unit U5, inverting proportional operation units U6, U7, U8 and U9.

[0034] The amplitude of the chaotic waveform output by the oscillation circuit can be controlled by a certain resistance parameter in the memristor analog equivalent unit circuit, that is, the size of the R9 resistor is used to control the signal amplitude, and the signal bias is controlled by the power supply voltage V1 of the second branch.

[0035] (1) Modeling of a three-dimensional self-regulating chaotic oscillator system with memristor feedback

[0036] The dimensionless mathematical model of the memristor feedback three-dimensional self-regulating chaotic oscillator is as follows:

[0037]

[0038] The corresponding memristor equation is:

[0039]

[0040] In formula (1), x, y, z are system state variables, and parameters a, b, c, d are constants. When parameters a = 4, b = 0.4, c = 4, d = 1, IC = (1, 1, 1), the chaotic attractor output by the system is as follows: Figure 1 As shown, Figure 1 is the phase trajectory diagram of the memristor feedback three-dimensional self-regulating chaotic oscillator; among them, Figure 1 (a) is the x-y plane graph. Figure 1 (b) is the y-z plane diagram. Figure 1 (c) in the figure is the x-z plane graph. Figure 1 (d) is the x-y-z plane diagram; the corresponding experimental oscilloscope simulation shows Figure 5 As shown, Figure 5 It is the phase trajectory diagram of the experimental simulation of the three-dimensional self-regulating chaotic oscillator with memristor feedback; among them, Figure 5 (a) is the x-z plane graph. Figure 5 (b) is the y-z plane diagram. Equation (1) can be implemented by a memristor feedback circuit, an inverting proportional circuit, and an integral operation circuit. The circuit diagram is shown in Figure 2 As shown, Figure 2 This is the schematic diagram of the memristor feedback type three-dimensional self-regulating chaotic oscillator circuit; Figure 2 (a) is the system circuit diagram. Figure 2(b) in the figure is the memristor circuit diagram. The circuit equation corresponding to formula (1) is:

[0041]

[0042] The circuit equation is consistent with the system dynamics equation. Here, the coefficients of each feedback term in the system are realized by the joint setting of resistance and capacitance, which can be realized by the variable resistor R9, and the adjustable DC power supply V1 to realize signal bias control. The chaotic phase trajectory generated by the circuit is displayed on the oscilloscope. The circuit simulation graph is as follows Figure 6 and Figure 7 shown. Figure 6 It is the phase trajectory diagram and waveform diagram of the amplitude control experiment simulation of the memristor feedback three-dimensional self-regulating chaotic oscillator; among them, Figure 6 (a) is the x-z plane diagram and x signal waveform diagram when R9 = 10kΩ. Figure 6 (b) is the x-z plane diagram and x signal waveform diagram when R9 = 3.3kΩ. Figure 6 (c) in the figure is the x-z plane diagram and x signal waveform diagram when R9=1kΩ. Figure 7 It is the phase trajectory diagram and waveform diagram of the bias control experiment simulation of the memristor feedback three-dimensional self-regulating chaotic oscillator; among them, Figure 7 (a) is the x-z plane diagram and x signal waveform diagram when V1 = -4V. Figure 7 (b) is the x-z plane diagram and x signal waveform diagram when V1 = 0V. Figure 7 (c) in the figure is the x-z plane diagram and the x signal waveform diagram when V1=4V.

[0043] The first branch input signal y is connected to the input end of the integral operation unit U1 through the resistor R1; the input signal y is connected to the memristor W(y) and outputs the -W(y)z item; the integral operation module U1 outputs a signal x, which is connected to the input end R2 of the inverting proportional operation unit U2; the inverting input end of the integral operation unit U1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the output end x of the integral operation unit U1; the inverting input end of the inverting operation unit U2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the output end -x of the inverting proportional operation unit U2, and finally the output signal -x is output.

[0044] The second branch includes three input terminals, namely input signals -x, z and power supply V1, which are respectively connected to R4, R5 and R6 to be connected to the summing and integrating operation unit U3; the output signal of the summing and integrating operation unit is z, and the output signal z is connected to R7 to be connected to the inverting proportional operation unit U4; the inverting input terminal of the integrating operation unit U3 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the output terminal z of the integrating operation unit U3; the inverting input terminal of the inverting operation unit U4 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the output terminal -z of the inverting proportional operation unit U4, and the final output signal is -z.

[0045] The third branch includes multipliers A1 and A2, resistor R9, resistor R 10 , resistor R 11 , resistor R 12 , resistor R 13 , resistor R 14 , resistor R 15 , resistor R 16 , resistor R 17 , resistor R 18 , resistor R 19 , resistor R 20 , diodes D1 and D2, capacitor C3, power supply V2, integral operation unit U5, inverting proportional operation units U6, U7, U8 and U9. Input signals y, z and -z pass through multiplier A1, integral operation unit U5 outputs signal y, passes through inverting proportional unit U6, diodes D1, D2, inverting proportional operation unit U7 outputs signal |y|, connects inverting proportional operation unit U8 and input voltage V2, outputs W(y) and input signal z, passes through multiplier A2 and inverting proportional operation unit U9, and finally outputs -W(y)z.

[0046] (2) Amplitude Control of a Three-Dimensional Self-Regulating Chaotic Oscillator with Memristor Feedback

[0047] In the memristor chaotic system (1), the second dimension adds parameter e, which can adjust the amplitude of the output signal. The system equation is:

[0048]

[0049] When the parameters a=4,b=0.4,c=4,d=1,IC=(1,1,1), the output chaotic attractor phase trajectory and waveform are as follows: Figure 3 As shown, Figure 3 It is the phase track and waveform diagram of amplitude control of three-dimensional self-regulating chaotic oscillator with memristor feedback; among them, Figure 3 (a) is the x-z plane graph. Figure 3(b) is the waveform of the x signal. In the circuit experiment, when the value of R9 in the memristor circuit is changed, the corresponding circuit experiment oscilloscope displays Figure 6 shown.

[0050] (3) Bias control of a three-dimensional self-regulating chaotic oscillator with memristor feedback

[0051] In the memristor chaotic system (1), adding parameter f in the third dimension can adjust the bias of the output signal. The system equation is:

[0052]

[0053] When the parameters a=4,b=0.4,c=4,d=1,IC=(1,1,1), the output chaotic attractor phase trajectory and waveform are shown in Figure 2. Figure 4 As shown, Figure 4 It is the phase track and waveform diagram of the bias control of the three-dimensional self-regulating chaotic oscillator with memristor feedback; among them, Figure 4 (a) is the x-z plane graph. Figure 4 (b) is the waveform of the x signal. In the circuit experiment, when the power supply voltage V1 in the second branch is changed, the corresponding circuit experiment oscilloscope displays Figure 7 shown.

[0054] The above description is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A memristor feedback three-dimensional self-regulating chaotic oscillator, characterized in that: It includes a memristor circuit, an integral operation circuit, a first inverting proportional operation circuit, a second inverting proportional operation circuit, first to third resistors, an adjustable DC power supply, a capacitor and an integral operation unit; wherein, The memristor circuit, the integral operation circuit, and the first inverting proportional operation circuit are connected in sequence; One end of the first resistor is connected to one end of the second resistor, one end of the third resistor, one end of the capacitor, and the inverting input end of the integral operation unit, respectively; the other end of the capacitor is connected to the output end of the integral operation unit and the input end of the second inverting proportional operation circuit, respectively; the other end of the third resistor is connected to the adjustable DC power supply; and the non-inverting input end of the integral operation unit is grounded; The memristor circuit includes a first multiplier, a second multiplier, a fourth resistor, a fifth resistor, a sixth resistor, an absolute value circuit, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a first integral operation unit, a first power supply, an inverting proportional operation unit, and a third inverting proportional operation circuit; wherein, The output end of the first multiplier is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to one end of the first capacitor, one end of the fifth resistor, and the inverting input end of the first integral operation unit, the non-inverting input end of the first integral operation unit is grounded, the other end of the first capacitor is connected to the output end of the first integral operation unit and one end of the sixth resistor, the other end of the sixth resistor is connected to the input end of the absolute value circuit, the output end of the absolute value circuit is connected to one end of the eighth resistor, the other end of the eighth resistor is connected to one end of the seventh resistor, one end of the ninth resistor, and the inverting input end of the inverting proportional operation unit, the other end of the seventh resistor is connected to the first power supply, the non-inverting input end of the inverting proportional operation unit is grounded, the other end of the ninth resistor is connected to the output end of the inverting proportional operation unit and the input end of the second multiplier, and the output end of the second multiplier is connected to the third inverting proportional operation circuit; The amplitude of the chaotic waveform output by the memristor feedback three-dimensional self-regulating chaotic oscillator is controlled by the size of the fourth resistor, and the bias of the signal is controlled by an adjustable direct current power supply.

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