Chip testing method and chip testing system

Abstract

The present application discloses a chip testing method and a chip testing system, the chip testing method comprising: using a manipulator in a chip testing system to test at least one chip to be tested; wherein the manipulator comprises a first test station and a second test station; in response to the arrival of the chip to be tested at the second test station, retrieving a first result obtained by the first test station for testing the chip to be tested, and obtaining a second result obtained by the second test station for testing the chip to be tested; and performing a correlation operation on the first result and the second result to obtain a test result of the chip to be tested. Through this design method, cross-station value acquisition can be directly performed between test stations to achieve real-time comparison of parameter performance of the same chip, and the calculation results can be directly displayed in the data, which not only avoids manual data analysis in the later stage, but also directly screens out potential risk products with unstable electrical performance parameters, thereby reducing product quality risks.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor testing technology, and specifically relates to a chip testing method and a chip testing system. Background Art

[0002] At present, the general testing method is multi-station series testing, and each test station is tested independently of each other. The common testing method of "electrical performance parameter test → avalanche test → thermal resistance test → gate resistance test → electrical performance parameter test" is taken as an example. The electrical performance parameter test is an important parameter of the chip product, such as VTH (threshold voltage), BVDSS (source-drain breakdown voltage), IDSS (drain current), VDSON (drain-source voltage), VF (forward conduction voltage) and other parameters.

[0003] The product performance is determined by checking the test values ​​of relevant parameters. Since the test stations are independent of each other, the stored electrical performance parameter test data is also independent. If you want to confirm whether the electrical performance parameters have changed after the test of the three intermediate stations to verify the stability of the chip product, you need to manually analyze the data. This method has a large amount of data and is not easy to operate. Therefore, the current multi-station serial test solution has the following defects: (1) manual data analysis is required, and the data volume is large and difficult to operate; (2) there is a potential risk to product performance; (3) there may be rework, resulting in waste of production capacity.

[0004] Therefore, a new chip testing method is urgently needed to solve the above problems. Summary of the Invention

[0005] The main technical problem solved by this application is to provide a chip testing method and a chip testing system, which can directly obtain values ​​across different test sites to achieve real-time comparison of parameter performance of the same chip.

[0006] In order to solve the above technical problems, a technical solution adopted in this application is: providing a chip testing method, including: using a manipulator in a chip testing system to test at least one chip to be tested; wherein, the manipulator includes a first test station and a second test station; in response to the chip to be tested arriving at the second test station, retrieving the first result obtained by the first test station for testing the chip to be tested, and obtaining the second result obtained by the second test station for testing the chip to be tested; performing correlation operations on the first result and the second result to obtain the test result of the chip to be tested.

[0007] In which, the manipulator also includes an empty test station and at least one intermediate test station located between the first test station and the second test station, and the empty test station is located before the first test station; the step of using the manipulator in the chip testing system to test at least one chip to be tested includes: transferring the at least one chip to be tested to the first test station through the empty test station for testing to obtain the first result; wherein, the empty test station does not have a testing function; transferring the at least one chip to be tested from the first test station to the at least one intermediate test station and the second test station in sequence for testing to obtain at least one intermediate result and the second result.

[0008] Among them, before the step of sequentially transmitting the at least one chip to be tested to the at least one intermediate test station and the second test station for testing to obtain at least one intermediate result and the second result, the step includes: sequentially communicating in series with the first test station, the at least one intermediate test station, and the second test station, so that the results obtained after the chip to be tested passes through the first test station, the at least one intermediate test station, and the second test station in sequence can be retrieved across stations; wherein, the intermediate test station is located between the first test station and the second test station.

[0009] Among them, the intermediate test station includes a first intermediate test station, a second intermediate test station and a third intermediate test station; the step of transferring the at least one chip to be tested from the first test station to the at least one intermediate test station and the second test station in sequence for testing to obtain at least one intermediate result and the second result includes: transferring the chip to be tested from the first test station to the first intermediate test station, the second intermediate test station and the third intermediate test station in sequence for testing to obtain a first intermediate result, a second intermediate result and a third intermediate result; transferring the chip to be tested to the second test station for testing to obtain the second result.

[0010] In which, the manipulator also includes a marking station, which is used to mark the chip to be tested, and the marking station is located between the at least one intermediate testing station and the second testing station; before the step of transferring the chip to be tested to the second testing station for testing to obtain the second result, it also includes: transferring the chip to be tested from the third intermediate testing station to the marking station to mark the chip to be tested.

[0011] Among them, the step of retrieving the first result obtained by testing the chip to be tested using the first test station in response to the chip to be tested arriving at the second test station, and obtaining the second result obtained by testing the chip to be tested using the second test station, includes: obtaining the first moment when the chip to be tested is located at the first test station and starts testing; in response to the time interval between the first moment and the current moment being a first preset value, determining that the chip to be tested arrives at the second test station, retrieving the first result obtained by testing the chip to be tested by the first test station; and testing the chip to be tested using the second test station to obtain the second result.

[0012] Among them, the step of performing an associative operation on the first result and the second result to obtain the test result of the chip to be tested includes: obtaining the difference between the second result and the first result; in response to the difference being less than or equal to a second preset value, determining that the test result of the chip to be tested is qualified; and / or, in response to the difference being greater than the second preset value, determining that the test result of the chip to be tested is unqualified.

[0013] Wherein, after the step of determining that the test result of the chip to be tested is unqualified, the method further includes: outputting the test result and performing defective processing on the chip to be tested.

[0014] In order to solve the above technical problems, a technical solution adopted in this application is: to provide a chip testing system, including: a processor, a manipulator coupled to the processor, and a testing machine coupled to the processor and the manipulator respectively; wherein, the manipulator includes a first testing station and a second testing station, and the testing machine is used to control the timing of the manipulator to test the chip to be tested; wherein, the processor, the manipulator and the testing machine cooperate with each other to implement the chip testing method mentioned in any of the above embodiments.

[0015] The manipulator further includes an empty test station and at least one intermediate test station located between the first test station and the second test station; wherein the first test station, the at least one intermediate test station and the second test station communicate in series in sequence.

[0016] The beneficial effects of the present application are as follows: the chip testing method provided by the present application includes: using a manipulator in a chip testing system to test at least one chip to be tested; wherein the manipulator includes a first test station and a second test station; in response to the arrival of the chip to be tested at the second test station, retrieving a first result obtained by the first test station for testing the chip to be tested, and obtaining a second result obtained by the second test station for testing the chip to be tested; performing a correlation operation on the first result and the second result to obtain a test result of the chip to be tested. Through this design method, cross-station value acquisition can be directly performed between test stations to achieve real-time comparison of parameter performance of the same chip, and the calculation results can be directly displayed in the data. This not only avoids manual data analysis in the later stage, but also directly screens out potential risk products with unstable electrical performance parameters, thereby reducing product quality risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0018] Figure 1 It is a structural diagram of an embodiment of a chip testing system;

[0019] Figure 2 yes Figure 1 A schematic structural diagram of an embodiment of the robot;

[0020] Figure 3 This is a flow chart of an embodiment of the chip testing method of the present application;

[0021] Figure 4 yes Figure 3 Schematic diagram of the process of step S1 in the embodiment;

[0022] Figure 5 yes Figure 4 A flow chart of an embodiment of step S11;

[0023] Figure 6 yes Figure 3 A schematic flow chart of an embodiment of step S2;

[0024] Figure 7 yes Figure 3 Flow chart of an implementation method of step S3 in FIG. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] See also Figure 1 , Figure 1 It is a schematic structural diagram of an embodiment of a chip testing system. Figure 2 yes Figure 1 Specifically, in this embodiment, the chip testing system provided by this application includes: a processor 10, a manipulator 12 (ST DPAK Automotive Instruction) coupled to the processor 10, and a tester 14 coupled to the processor 10 and the manipulator 12 respectively. Specifically, as Figure 1 and Figure 2 As shown, the manipulator 12 includes a first test station T2 and a second test station T6, and the tester 14 is used to control the timing of the manipulator 12 to test the chip to be tested. In this embodiment, the processor 10, the manipulator 12 and the tester 14 cooperate with each other to implement the chip testing method provided in this application.

[0027] Specifically, the processor 10 may also be referred to as a CPU (Central Processing Unit). The processor 10 may be an integrated circuit chip having signal processing capabilities. The processor 10 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. In addition, the processor 10 may be implemented by multiple integrated circuit chips.

[0028] Specifically, in this embodiment, please continue to refer to Figure 1 and Figure 2The robot 12 also includes an empty test station T1 and at least one intermediate test station M located between the first test station T2 and the second test station T6. Specifically, the first test station T2, the at least one intermediate test station M, and the second test station T6 are serially connected. This allows for direct cross-station data acquisition between test stations, enabling real-time comparison of the performance parameters of the same chip. The calculated results are directly displayed in the data, eliminating the need for manual data analysis later and directly screening out potentially risky products with unstable electrical performance parameters, thereby reducing product quality risks.

[0029] Specifically, in the manipulator 12, the empty test station T1 does not have a test function, that is, it is left empty and not tested. In this embodiment, the first test station T2 can be an FT station (FET3402 Site1), which is used to test the electrical performance parameters of the chip, such as VTH (threshold voltage), BVDSS (source-drain breakdown voltage), IDSS (drain current), VDSON (drain-source voltage), VF (forward conduction voltage), etc., which are not limited in this application; the second test station T6 is a QA station, and the parameters tested by it are consistent with the parameters tested by the first test station T2, which facilitates the comparison of the test results of the second test station T6 with the test results of the first test station T2; the intermediate test station M is used to perform avalanche testing, thermal resistance testing, gate resistance testing, etc. on the chip, which are not limited in this application.

[0030] The chip testing method provided by this application is described in detail below.

[0031] Please also refer to Figure 2 and Figure 3 , Figure 3 This is a flow chart of an embodiment of the chip testing method of the present application. The chip testing method includes:

[0032] S1: Using a manipulator in a chip testing system to test at least one chip to be tested.

[0033] Specifically, if Figure 2 As shown, the manipulator includes a first test station T2 and a second test station T6. Specifically, in this embodiment, the manipulator also includes an empty test station T1 and at least one intermediate test station M located between the first test station T2 and the second test station T6, and the empty test station T1 is located before the first test station T2. ​​In this embodiment, the chip to be tested can be a MOSFET (full oxygen half field effect transistor) and the like, which is not limited in this application. In addition, in this embodiment, please refer to Figure 2 and Figure 4 , Figure 4 yes Figure 3 Schematic diagram of a flow chart of an embodiment of step S1 in FIG. Step S1 specifically includes:

[0034] S10: Transferring at least one chip to be tested to a first testing station through an empty testing station for testing to obtain a first result.

[0035] Specifically, the empty test station T1 has no testing capabilities and is vacant. The test stations with testing capabilities are moved one station back. In this embodiment, the chip to be tested is first transferred to the empty test station T1, then transferred to the first test station T2 via the empty test station T1, where it is tested and a first result is obtained. Of course, in other embodiments, the chip to be tested can be transferred directly to the first test station T2 for testing and a first result is obtained without passing through the empty test station T1, and this application is not limited thereto.

[0036] S11: transferring at least one chip to be tested from a first testing station to at least one intermediate testing station and a second testing station in sequence for testing to obtain at least one intermediate result and a second result.

[0037] Specifically, in this embodiment, before step S11, the process includes sequentially connecting the first test station T2, the at least one intermediate test station M, and the second test station T6 in series communication, so that the test results of the chip to be tested can be retrieved across the test stations. Specifically, the intermediate test station M is located between the first test station T2 and the second test station T6.

[0038] In addition, in this embodiment, Figure 2 As shown, the intermediate test station M specifically includes a first intermediate test station T3, a second intermediate test station T4 and a third intermediate test station T5. Specifically, in this embodiment, please refer to Figure 2 and Figure 5 , Figure 5 yes Figure 4 Schematic diagram of a flow chart of an embodiment of step S11. Step S11 includes:

[0039] S110: Transferring the chip to be tested from the first test station to the first intermediate test station, the second intermediate test station, and the third intermediate test station in sequence for testing to obtain a first intermediate result, a second intermediate result, and a third intermediate result.

[0040] Specifically, the chip to be tested is transferred from the first test station T2 to the first intermediate test station T3, the second intermediate test station T4, and the third intermediate test station T5 for testing, to obtain a first intermediate result, a second intermediate result, and a third intermediate result, respectively. Specifically, in this embodiment, the first intermediate test station T3 can be an LV (UIS) station (ITC55100C, etc.), which is used to perform an avalanche test on the chip to be tested; the second intermediate test station T4 can be a DV station (TESEC4324-KT, etc.), which is used to perform a thermal resistance test on the chip to be tested; and the third intermediate test station T5 can be an RG station (Agilent E4980AL, etc.), which is used to perform a gate electrode test on the chip to be tested. In this embodiment, the first intermediate test station T3, the second intermediate test station T4, and the third intermediate test station T5 can also be a DV station, a LV (UIS) station, and a RG station, respectively. The software interface of the chip test system provided by this application adds a corresponding special mode. When this test mode is selected during testing, the empty test station T1 is vacated, and the test sequence after the empty test station T1 is FT-LV (UIS)-DV-RG-QA. Of course, the first intermediate test station T3, the second intermediate test station T4, and the third intermediate test station T5 can also be an RG station, a LV (UIS) station, a DV station, etc., respectively. The order of the tests in the first intermediate test station T3, the second intermediate test station T4, and the third intermediate test station T5 can be changed, and this application does not limit this.

[0041] S111: Transfer the chip to be tested to a second testing station for testing to obtain a second result.

[0042] Specifically, if Figure 2 As shown, the manipulator also includes a marking station L, which is used to mark the chip to be tested, and the marking station L is located between at least one intermediate test station M and the second test station T6. Specifically, in this embodiment, before step S111, it also includes: transferring the chip to be tested from the third intermediate test station T5 to the marking station L to mark the chip to be tested. Specifically, the marking station L is laser-marking, which is used to laser mark the chip to be tested. According to the system software timing requirements of the tester, the test sequence of the product is FT-LV (UIS)-DV-RG-laser marking-QA. The second test station T6 is a regular SOT. Regardless of whether the test result of the previous test station is pass or fail, the second test station T6 must be tested to ensure that the data FT / QA data can correspond one to one.

[0043] With this design, the first test station of the manipulator is set as an empty test station, and the next few test stations are used for uninterrupted testing. This can avoid the loss of the signal of the chip to be tested due to the test station being vacant in the middle, so as to ensure that the same chip is tested from beginning to end, thereby ensuring that the second result obtained by the second test station T6 and the first result obtained by the first test station T2 belong to the same chip, so as to verify whether there are test differences between different test heads of the test equipment.

[0044] S2: In response to the chip to be tested arriving at the second test station, a first result of testing the chip to be tested obtained by the first test station is retrieved, and a second result of testing the chip to be tested obtained by the second test station is obtained.

[0045] Specifically, the tester's system software controls the timing, adds a calculation item at the second test station T6, and calculates the time interval between the chip starting testing at the first test station T2, passing through other parameter test stations, and reaching the second test station T6. This is used to determine whether the chip under test has arrived at the second test station. Specifically, if the chip under test has not arrived at the second test station T6, the determination of whether the chip under test has arrived at the second test station T6 continues until the chip under test arrives at the second test station T6.

[0046] Specifically, first, the interval between the chip starting from the first test station T2 and passing through other test stations and the marking station L and arriving at the second test station T6 is set in the test machine, which is the preset value. Figure 2 and Figure 6 , Figure 6 yes Figure 3 Schematic diagram of a flow chart of an embodiment of step S2 in FIG. Step S2 includes:

[0047] S20: Obtain the first moment when the chip to be tested is located at the first testing station and begins testing.

[0048] Specifically, the first moment when the chip to be tested is located at the first testing station T2 and begins testing is obtained.

[0049] S21: Determine whether the time interval between the first moment and the current moment is a first preset value.

[0050] Specifically, during the test process of the chip to be tested, the time interval between the first moment and the current moment in the above step S20 is obtained by calculation, and it is determined whether the time interval reaches a first preset value.

[0051] S22: If yes, it is determined that the chip to be tested has arrived at the second test station, and a first result obtained by the first test station on the chip to be tested is retrieved.

[0052] Specifically, if the time interval is within the first preset value, the chip under test is determined to have arrived at the second test station T6. When a product arrives for testing at the second test station T6, the test values ​​of the associated parameters for the same product at the first test station T2 are retrieved and associated calculations are performed. This cycle is repeated to complete the testing and calculations for all products. Because the second test station T6 and the first test station T2 communicate in series, the second test station T6 can directly retrieve the first result from the first test station T2 across the test stations.

[0053] S23: Using a second testing station to test the chip to be tested to obtain a second result.

[0054] Specifically, the chip to be tested is tested using the second test station T6 to obtain a second result. Of course, in other embodiments, step S22 and step S23 can be performed simultaneously, or step S23 can be performed first and then step S22. This application does not limit the order in which steps S22 and S23 are performed.

[0055] S24: Otherwise, it is determined that the chip to be tested has not arrived at the second testing station, and the process returns to step S20.

[0056] Specifically, if the time interval between the first moment and the current moment is not the first preset value, the process returns to the step of obtaining the first moment when the chip under test is located at the first test station T2 and begins testing, and determines whether the time interval between the first moment and the current moment is the first preset value, until the chip under test arrives at the second test station T6. Of course, in an actual test round, the first moment when the chip under test is located at the first test station T2 and begins testing is fixed, and only this first moment needs to be obtained each time. In other embodiments, the first moment can be obtained and saved to a processor, and then the time interval between the first moment and the current moment can be directly determined to determine whether it is the first preset value. This eliminates the need to obtain the time interval each time, saving testing time and cost. This is not limited to this in the present application.

[0057] S3: Performing a correlation operation on the first result and the second result to obtain a test result of the chip to be tested.

[0058] Specifically, in this embodiment, please refer to Figure 2 and Figure 7 , Figure 7 yes Figure 3 Schematic diagram of a flow chart of an embodiment of step S3 in FIG. Step S3 includes:

[0059] S30: Obtaining a difference between the second result and the first result.

[0060] S31: Determine whether the difference is less than or equal to a second preset value.

[0061] S32: If yes, the test result of the chip to be tested is determined to be qualified.

[0062] Specifically, if the difference is less than or equal to the second preset value, it means that the electrical performance parameters of the chip have not changed after being tested at the intermediate test station, indicating that the product is stable and there is no problem, and the test result of the chip to be tested is determined to be qualified.

[0063] S33: Otherwise, the test result of the chip to be tested is determined to be unqualified.

[0064] Specifically, if the difference is greater than the second preset value, it means that the electrical performance parameters of the chip have changed after being tested at the intermediate test station, indicating that the product has potential risks, and the test result of the chip is determined to be unqualified.

[0065] Through this design method, cross-site value acquisition can be directly carried out between test sites, and the parameter performance of the same chip can be compared in real time. The calculation results can be directly displayed in the data. This not only avoids manual data analysis in the later stage, but also directly screens out potential risk products with unstable electrical performance parameters, thereby reducing product quality risks.

[0066] Specifically, in this embodiment, after step S33, it includes: outputting the unqualified test results of the chip to be tested, performing defective treatment on the chip to be tested, treating the chip to be tested as a defective product, and directly arranging it into a defective material pipe or performing other defective treatments, etc. This application does not limit this.

[0067] In this way, if the test result of the previous test station is fail, no matter whether the test result of the second test station T6 is pass or fail, it will be processed as the test result of the previous test station is fail; only when all the previous test stations pass and the test result of the second test station T6 is fail, QA failure processing will be performed.

[0068] In summary, different from the prior art, the chip testing method provided by the present application includes: using a manipulator in a chip testing system to test at least one chip to be tested; wherein the manipulator includes a first test station and a second test station; in response to the arrival of the chip to be tested at the second test station, retrieving the first result obtained by the first test station for testing the chip to be tested, and obtaining the second result obtained by the second test station for testing the chip to be tested; performing a correlation operation on the first result and the second result to obtain the test result of the chip to be tested. Through this design method, it is possible to directly cross-station value acquisition between test sites, realize real-time comparison of parameter performance of the same chip, and directly display the calculation results in the data, which not only avoids manual data analysis in the later stage, but also directly screens out potential risk products with unstable electrical performance parameters, thereby reducing product quality risks.

[0069] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip testing method, characterized in that: include: Testing at least one chip to be tested using a manipulator in a chip testing system; wherein the manipulator includes a first testing station, a second testing station, and at least one intermediate testing station located between the first testing station and the second testing station; In response to the chip to be tested arriving at the second test station, a first result obtained by the first test station from testing the chip to be tested, an intermediate result obtained by the intermediate test station from testing the chip to be tested, and a second result obtained by the second test station from testing the chip to be tested are retrieved; wherein the first result, the intermediate result, and the second result are obtained by continuously testing the chip from the first test station, the at least one intermediate test station, to the second test station; Performing a correlation operation on the first result and the second result of the chip to be tested to obtain a test result of the chip to be tested.

2. The chip testing method according to claim 1, characterized in that: The manipulator further includes an empty test station, which is located before the first test station. The step of using the manipulator in the chip testing system to test at least one chip to be tested includes: The at least one chip to be tested is transferred to the first testing station through the empty testing station for testing to obtain the first result; wherein the empty testing station does not have a testing function.

3. The chip testing method according to claim 2, characterized in that: Before the step of testing at least one chip to be tested by using a manipulator in the chip testing system, the method includes: The first test station, the at least one intermediate test station, and the second test station are sequentially connected in series, so that the test results of the chip to be tested can be retrieved across the stations after being tested in the first test station, the at least one intermediate test station, and the second test station.

4. The chip testing method according to claim 2, characterized in that: The intermediate test stations include a first intermediate test station, a second intermediate test station, and a third intermediate test station; the step of using a manipulator in the chip test system to test at least one chip to be tested includes: transferring the chip to be tested from the first test station to the first intermediate test station, the second intermediate test station, and the third intermediate test station in sequence for testing to obtain a first intermediate result, a second intermediate result, and a third intermediate result; The chip to be tested is transferred to the second testing station for testing to obtain the second result.

5. The chip testing method according to claim 4, characterized in that: The robot further includes a marking station, which is used to mark the chip to be tested, and the marking station is located between the at least one intermediate testing station and the second testing station. Before the step of retrieving, in response to the chip to be tested arriving at the second testing station, a first result of the first testing station testing the chip to be tested, an intermediate result of the intermediate testing station testing the chip to be tested, and a second result of the second testing station testing the chip to be tested, the robot further includes: The chip to be tested is transferred from the third intermediate testing station to the marking station to mark the chip to be tested.

6. The chip testing method according to claim 1, characterized in that: The step of retrieving, in response to the chip to be tested arriving at the second test station, a first result obtained by the first test station from testing the chip to be tested, an intermediate result obtained by the intermediate test station from testing the chip to be tested, and a second result obtained by the second test station from testing the chip to be tested, comprising: Obtaining a first moment when the chip to be tested is located at the first testing station and begins testing; In response to a time interval between the first moment and the current moment being a first preset value, determining that the chip to be tested has arrived at the second testing station, and retrieving a first result obtained by the first testing station of the chip to be tested; The chip to be tested is tested using the second testing station to obtain the second result.

7. The chip testing method according to claim 6, characterized in that: The step of performing a correlation operation on the first result and the second result to obtain a test result of the chip to be tested includes: obtaining a difference between the second result and the first result; In response to the difference being less than or equal to a second preset value, determining that the test result of the chip to be tested is qualified; and / or, In response to the difference being greater than the second preset value, the test result of the chip to be tested is determined to be unqualified.

8. The chip testing method according to claim 7, characterized in that: After the step of determining that the test result of the chip to be tested is unqualified, the method includes: Output the test result and perform defect processing on the chip to be tested.

9. A chip testing system, characterized in that: include: A processor, a manipulator coupled to the processor, and a testing machine coupled to the processor and the manipulator respectively; wherein the manipulator includes a first testing station and a second testing station, and the testing machine is used to control the timing of the manipulator testing the chip to be tested; wherein the processor, the manipulator and the testing machine cooperate with each other to implement the chip testing method described in any one of claims 1 to 8.

10. The chip testing system according to claim 9, characterized in that: The manipulator further includes an empty test station and at least one intermediate test station located between the first test station and the second test station; wherein the first test station, the at least one intermediate test station and the second test station communicate in series in sequence.

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