Single event effect test method and device for serdes module of FPGA device

Abstract

This application relates to the field of integrated circuit technology, and in particular to a method and apparatus for single-event effect testing of SerDes modules of FPGA devices. The method includes: generating a first SBS code of a target pattern using a first FPGA device as the main controller; controlling the first FPGA device to receive radiation during the transmission of the first SBS code while a second FPGA device (the device under test) transmits the first SBS code, and detecting the second SBS code of the target pattern after radiation; and statistically analyzing the number and type of errors in the SBS code based on the second SBS code to generate a single-event effect test result. This solves the problems of low stability, low accuracy, poor real-time performance, and poor applicability in testing SerDes modules of FPGA devices in related technologies.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method and apparatus for testing single-event effects on the SerDes (Serializer / De-serializer) module of an FPGA (Field Programmable Gate Array) device. Background Technology

[0002] SRAM (Static Random Access Memory) FPGAs, with their advantages of reconfigurability and high integration, have strongly supported the development of my country's aerospace technology. Most SRAM FPGAs integrate SerDes to meet the demands of high data transmission rates for large-scale data transfers. However, SRAM FPGAs are highly sensitive to single-event effects (SEE). In harsh radiation environments, the internal SerDes are prone to SEU (Single Event Upset) and SEFI (Single Event Functional Interruption), leading to data errors and incalculable losses. Domestic research on SEE in SerDes modules mainly focuses on the design and testing of radiation-resistant ASIC SerDes chips. Research on SEE in the internal SerDes modules of large-scale computing chips such as billion-gate FPGAs is limited, and systematic testing methods are lacking.

[0003] However, the data transmission function of the complex internal circuitry of SerDes is susceptible to single-event effects, particularly in CMOS process circuits at 28nm and below. Their high operating frequency and data transmission rate exacerbate problems such as a high proportion of single-event failures, difficulties in testing and characterization, decreased fault location accuracy, and reduced effectiveness of general protection measures, impacting the on-orbit data security of large-scale computing chips and leading to an increased spacecraft failure rate. FPGAs are monolithic systems containing various resource types. Direct irradiation experiments inevitably expose adjacent SerDes modules to particle beams, causing not only experimental data errors but also affecting the stability of the entire system, making testing difficult. Using metal shielding to reduce the impact of radiation on non-test modules is insufficient for precise location and differentiation, thus requiring improvement to reduce the probability of unnecessary single-event failures. More importantly, this method is only applicable to devices with large process dimensions and low internal resource density. With the advancement of integrated circuit technology, advanced FPGAs, such as the 28nm Kintex-7, have smaller feature sizes and higher operating frequencies for their SerDes modules, with a maximum GTX transmission rate of 12.5Gb / s. This places higher demands on data interference resistance, so SEE in this case should be further studied.

[0004] A single-event effect (SEE) testing scheme for SerDes within a 65nm process FPGA was designed in the relevant technology. This scheme places the FPGA under test under a radiation source, irradiating half of the SerDes modules, while the other half of the SerDes and other resources are shielded with a metal sheet to reduce the impact of SEE. The final collected data is analyzed, and SEE is categorized into BE (Bit Error) and LOL (Loss-of-Link Events) based on recovery time, calculating the sensitivity of SerDes to various errors. This scheme has several problems: determining the location of SerDes resources based on layout information is difficult to achieve precise positioning and is only applicable to FPGAs with larger process dimensions; furthermore, in current advanced process FPGAs, the internal resource arrangement is highly dense, making it difficult to precisely control the range of physical shielding, which reduces the accuracy of experimental data; the differentiation of SEE types is not detailed enough, and the differentiation criteria are relatively singular, limiting further in-depth analysis. Other testing methods for FPGA SerDes modules are rare, and none of them shield the non-test parts, resulting in experimental accuracy far lower than the above scheme. Summary of the Invention

[0005] This application provides a method, apparatus, electronic device, and storage medium for single-event effect testing of SerDes modules of FPGA devices, in order to solve the problems of low stability, low accuracy, poor real-time performance, and poor applicability of testing SerDes modules of FPGA devices in related technologies.

[0006] The first aspect of this application provides a single-event effect testing method for a SerDes module of an FPGA device, comprising the following steps: generating a first SBS (Specific Binary Sequence) code of a target pattern using a first FPGA device as the master controller; during the transmission of the first SBS code by a second FPGA device as the device under test, controlling the first FPGA device to allow the first SBS code to be irradiated, and detecting the second SBS code of the target pattern after irradiation; referring to the second SBS code, counting the number of errors and error types of the SBS, and generating a single-event effect test result.

[0007] Furthermore, the step of statistically analyzing the number and types of errors in SBS and generating single-event effect test results includes: calculating a single-event effect cross-section for at least one error type; fitting a cross-sectional curve based on the single-event effect cross-section for the at least one error type; calculating the single-event flip rate based on the fitted cross-sectional curve and estimating the space flip rate.

[0008] Furthermore, the formula for calculating the single-particle flip rate is as follows:

[0009]

[0010]

[0011]

[0012] Where λ is the LET value, σ SEU σ rec_SEFI σ Unrec_SEFI It is the Weibull section, and D(λ) is the deposition of Q with λ within the sensitive volume. crit The differential of the path length, F(λ) is the integral flux of heavy ions and LET>λ.

[0013] Furthermore, before counting the number of errors and error types of the SBS, the method further includes: obtaining the total amount of flux in the second FPGA device at preset intervals; determining whether the total amount of flux is greater than a preset threshold; if it is less than the preset threshold, then continuing to irradiate the second FPGA device with a preset particle beam.

[0014] Furthermore, before generating the first SBS code of the target code pattern using the first FPGA device as the main control device, the method further includes: detecting whether the SerDes module of the second FPGA device is in near-end loopback mode; and after detecting that it is in the near-end loopback mode, setting a logic window on the SerDes module to shield other parts.

[0015] A second aspect of this application provides a single-event effect testing apparatus for a SerDes module of an FPGA device, comprising: a generation module for generating a first SBS code of a target pattern using a first FPGA device as the main control device; a control module for controlling the first FPGA device to receive radiation during the transmission of the first SBS code by a second FPGA device as the device under test, and detecting the second SBS code of the target pattern after radiation; and a statistics module for calculating the number of bit errors and error types of the SBS code with reference to the second SBS code, and generating a single-event effect test result.

[0016] Furthermore, the statistical module is further used to calculate the single-event effect cross section for at least one error type; fit a cross-sectional curve to the single-event effect cross section for the at least one error type; calculate the single-event flip rate based on the fitted cross-sectional curve of the single-event effect cross section, and estimate the space flip rate; the formula for calculating the single-event flip rate is:

[0017]

[0018]

[0019]

[0020] Where λ is the LET value, σ SEU σ rec_SEFI σ Unrec_SEFI It is the Weibull section, and D(λ) is the deposition of Q with λ within the sensitive volume. crit The differential of the path length, F(λ) is the integral flux of heavy ions and LET>λ.

[0021] Furthermore, it also includes: a judgment module, used to obtain the total amount of the second FPGA device at preset intervals before counting the number of errors and error types of the SBS; to determine whether the total amount of the SBS is greater than a preset threshold; if it is less than the preset threshold, to continue irradiating the second FPGA device with a preset particle beam; and a setting module, used to detect whether the SerDes module of the second FPGA device is in near-end loopback mode before generating the first SBS code of the target code pattern using the first FPGA device as the master control device; and after detecting that it is in the near-end loopback mode, to set a logic window on the SerDes module to shield other parts.

[0022] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the single-event effect testing method for an FPGA device SerDes module as described in the above embodiments.

[0023] A fourth aspect of this application provides a computer-readable storage medium storing computer instructions for causing the computer to perform a single-event effect testing method for an FPGA device SerDes module as described in the above embodiments.

[0024] Therefore, this application has at least the following beneficial effects:

[0025] This high-speed SerDes module is suitable for advanced FPGA devices at process nodes of 28nm and below, aligning with the needs of aerospace and aviation research on the radiation effect mechanism of high-end electronic components. By locating the physical position of the SerDes through code stream analysis and employing logic shielding technology to block radiation, it significantly reduces interference from the ion beam to non-test modules, minimizing errors in single-event experimental data from the SerDes module and improving data validity. Detailed classification of SEE and SerDes sensitivity analysis, combined with the number of error bits and error duration, provide a reliable testing approach for single-event effect research on FPGAs in aerospace and other radiation environments. This promotes the research of high-reliability FPGA SerDes modules, facilitating breakthroughs in data transmission capabilities to overcome bottlenecks in AI applications, and thus has broad applicability. This addresses the problems of low stability, low accuracy, poor real-time performance, and limited applicability in related technologies for testing SerDes modules of FPGA devices.

[0026] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0027] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 This is a flowchart of a single-event effect testing method for an FPGA device SerDes module provided according to an embodiment of this application;

[0029] Figure 2 This is a block diagram of the logic window and FPGA resource distribution according to embodiments of this application;

[0030] Figure 3 This is a flowchart of a single-event effect testing method for an FPGA device SerDes module according to an embodiment of this application;

[0031] Figure 4 A block diagram illustrating the test path provided according to an embodiment of this application.

[0032] Figure 5 This is an example diagram of a single-event effect device for an FPGA device SerDes module provided according to an embodiment of this application;

[0033] Figure 6 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. Detailed Implementation

[0034] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0035] In related technologies, it is difficult to accurately locate the position of the SerDes under test on the FPGA. This inevitably leads to other resources being affected by radiation, causing single-event effects and reducing the accuracy of test data. This application employs a bitstream analysis method. By modifying the test link and comparing the differences in underlying bitstream information corresponding to different paths, the method maps these differences to the hardware circuit, thereby determining the location information of the SerDes resource on the FPGA. A state machine is used to set state traps, maintaining resources other than the SerDes under test in their initial state. Logical masking technology is used to shield the bitstream, control the irradiation range, eliminate the possibility of unnecessary SEE (Self-Effect Interference), and improve the accuracy of the test experiment. Furthermore, considering factors such as the scale of data errors, error duration, and recoverability, different manifestations of SEE are meticulously classified.

[0036] SerDes are widely used for high-speed data transmission. Their structure can be divided into three parts: TX (Transmitter), RX (Receiver), and PLL (Phase Locked Loop). TX and RX transmit and receive data, respectively, while the PLL provides the clock for the SerDes circuit. The SerDes module in an FPGA is also called a GTX (Gigabit Transceiver). Taking Xilinx's 7-series devices as an example, it contains four GTX quads, each with four channels. Each channel integrates TX, RX, and a CPLL (Charge Pump Phase Locked Loop). The CPLL provides a separate operating clock for each channel. In radiated environments, all three parts of a SerDes are susceptible to interference, leading to SEU and SEFI.

[0037] SEU refers to a charged particle hitting a sensitive node in a memory cell, causing a bit flip. An error in a single logic bit of sequential logic can cause data errors, but it will not cause the data transmission link to be lost, and the flipped bit will often be restored after the next write, set, or reset operation.

[0038] SEFI (Search Engine Fissure Ingress) can cause numerous errors in SerDes data transmission, even leading to a loss of transmission link and temporary circuit malfunction. Based on its duration, SEFI can be further categorized into recoverable and unrecoverable SEFI. Recoverable SEFI is generally caused by configuration bit flips related to function or global signals, resulting in a large number of data errors in a short period, but it can recover on its own after a while. Unrecoverable SEFI lasts for a long time, causing a large accumulation of errors that eventually affect the circuit's functionality. The time threshold for distinguishing between the two types of SEFI needs to be set based on the specific circuit's operating frequency. The higher the frequency, the faster the error accumulates until the circuit loses its correct function, at which point it changes from recoverable SEFI to unrecoverable SEFI. To recover the circuit from this state, some intervention is required, such as reset, restart, or loop input.

[0039] This classification method of different types of single-event effects is widely applicable to SEE research of various aerospace electronic equipment, and provides a theoretical reference for radiation protection technology in radiation scenarios such as high-altitude areas and space environments.

[0040] The following description, with reference to the accompanying drawings, describes a method, apparatus, electronic device, and storage medium for single-event effect testing of an FPGA device SerDes module.

[0041] Specifically, Figure 1 This is a flowchart illustrating a single-event effect testing method for a SerDes module of an FPGA device, provided in an embodiment of this application.

[0042] like Figure 1 As shown, the single-event effect testing method for the SerDes module of the FPGA device includes the following steps:

[0043] In step S101, the first SBS code of the target code pattern is generated using the first FPGA device, which serves as the main control device.

[0044] It should be noted that, in specific testing, the SEE system of this application embodiment should include two 28nm bulk silicon FPGAs and electronic devices, such as a host computer. Taking the host computer as an example, the method of this application embodiment can be applied to a host computer for single-event effect testing of the SerDes module of the FPGA device.

[0045] It is understood that, in the embodiments of this application, the system kernel can be called on the main control FPGA to generate the SBS generation module. The function of the SBS generation module is to generate SBS codes of a specified code type for receiving radiation during transmission.

[0046] In this embodiment, the test sequence used can also be generated by calling the PRBS (Pseudo-Random Binary Sequence) generator inside the SerDes module. Those skilled in the art can choose according to actual test requirements, and there is no specific limitation.

[0047] In this embodiment, before generating the first SBS code of the target code pattern using the first FPGA device as the main control device, the method further includes: detecting whether the second FPGA device SerDes module is in near-end loopback mode; after detecting that it is in near-end loopback mode, setting a logic window on the SerDes module to shield other parts.

[0048] Specifically, in this embodiment of the application, before testing, the DUT's GTX is controlled to run in near-end loopback mode, different Quads are called, the bitstream files generated after each call are compared, the differences are analyzed, the bitstream coordinates are mapped to the specific location of the SerDes resource in the circuit, and the size of a single Quad is calculated to be 1.8mm × 2.5mm.

[0049] A state trap is set on the DUT to automatically correct the minimal logic resources used to the initial state when a SEE occurs, thus achieving logic shielding. No processing is applied to Quad3 of the DUT, forming a logic window to ensure that Quad3 is fully exposed to radiation. Quad3 and Quad0 of the DUT are selected for data transmission, with a 5mm spacing between them on the board, the furthest possible distance. This ensures that Quad3 is exposed to the radiation source while Quad0 is shielded, reducing experimental errors. Some I / O (Input / Output) ports and some internal FPGA logic resources are configured far from Quad3, and the I / O ports are refreshed. A small number of CLBs (Configurable Logic Blocks) are distributed to the left of Quad3, and Quad2 is below it. These resources may be exposed to radiation due to their proximity to Quad3, but this has no impact on the experimental data because Quad2 is not used for data transmission, and the DUT is only used for data transmission, occupying very few logic resources and being far from Quad3. The logic window and FPGA resource distribution are as follows. Figure 2 As shown.

[0050] In step S102, during the transmission of the first SBS code by the second FPGA device, which is the device under test, the first FPGA device is controlled to receive radiation of the first SBS code, and the second SBS code of the target code pattern after radiation is detected.

[0051] Understandably, the DUT only transmits SBS codes. This method separates the generation and processing of the code stream from the radiation environment, minimizing the impact of SEE on the control system.

[0052] It should be noted that, in the embodiments of this application, physical shielding (such as metal sheet shielding) can also be used to shield the FPGA under test while exposing the SerDes module, which can also achieve the purpose of controlling the irradiation area.

[0053] In step S103, referring to the second SBS code, the number of SBS errors and error types are counted to generate single-event effect test results.

[0054] It is understood that, in the embodiments of this application, the system kernel can be called on the main control FPGA to generate the SBS detection and statistics module. The function of the SBS detection and statistics module is to detect the SBS code of the specified code type and count the number of errors.

[0055] Specifically, such as Figure 3 As shown, during the test, SerDes was set to run in remote loopback mode, establishing two test paths: TX and RX. The test path diagram is shown below. Figure 4As shown, a high-energy particle beam is used to irradiate Quad3 of the DUT, controlling the core of the main control FPGA to generate an SBS bitstream, as detailed below:

[0056] For the TX test path, the Quad3 of the main FPGA generates SBS parallel data and saves a correct copy of this data. The TX sends the parallel data to the 8b / 10b encoder through the interface FIFO (First In First Out) to avoid excessively long "0"s or "1"s and ensure DC balance. Then, it is converted from parallel to serial through a serializer. After conversion, the equalizer at the transmitting end adjusts the data, and then the driver sends the high-speed serial data to the Quad0 of the DUT. After receiving this data, the RX of the DUT Quad0 removes some deterministic jitter through the DFE (Decision Feedback Equalization), and then recovers the sampling clock through the CDR (Clock Data Recovery). In the deserializer, the starting position of the serial-to-parallel conversion is determined by detecting the feature codeword, and the deserialized data is converted into an aligned parallel signal. The 8b / 10b decoder completes the decoding, and finally, the parallel data is transmitted to the TX of the DUT Quad3. After receiving the data, the Quad3 TX serializes it and transmits it to the RX of the main FPGA Quad0. The RX of the main control FPGA Quad0 receives data and sends it to the error detection module to detect bit errors, count error types, and count error numbers. The host computer reads back and retains the statistical results every data packet transmission threshold time ε.

[0057] For the RX test path, Quad0 of the master FPGA generates SBS parallel data and saves a correct copy of this data. Quad0's TX encodes the SBS in 8b / 10b format and then serializes the parallel data. The high-speed serial data, after being adjusted by the equalizer, is sent from the driver to the RX of DUT Quad3. Upon receiving the data, the RX of DUT Quad3 parallelizes and decodes it using DFE and CDR, and then sends it to the TX of DUT Quad0. The TX of DUT Quad0 serializes the data and sends it to the RX of master FPGA Quad3. Error data detection is then performed in the Quad3 of the master FPGA. The host computer reads back the error statistics every data packet transmission threshold time ε.

[0058] In this embodiment, before counting the number of errors and error types of SBS, the method further includes: obtaining the total amount of flux of the second FPGA device at preset intervals; determining whether the total amount of flux is greater than a preset threshold; if it is less than the preset threshold, then continuing to irradiate the second FPGA device with a preset particle beam.

[0059] The preset threshold can be set according to actual testing needs; for example, it can be set to 10. 6 One particle·cm -2 etc., without making specific limitations.

[0060] Specifically, such as Figure 3 As shown, the FPGA configuration bits are refreshed after each data packet transmission threshold time ε to mitigate accumulated configuration bit errors. The bit stream refresh uses a blind refresh technique, refreshing all configuration bits of the SerDes module, which significantly alleviates the single-event effect of SerDes. During irradiation experiments, the bit stream is stored in the BPI Flash. The FPGA refresh module reads the bit stream data from the BPI Flash and refreshes the DUT bit stream data through the SelectMap interface. The reason for using a refresh cycle of one data packet transmission threshold time ε is that an excessively long refresh cycle will cause a large number of accumulated errors in the DUT's configuration bits, affecting the experimental results; an excessively short refresh cycle will result in insufficient data processing time. Therefore, setting the refresh cycle to one data packet transmission threshold time ε is the optimal solution in engineering. When the total injection amount reaches 10... 6 One particle·cm -2 When the time comes, stop irradiation.

[0061] In this embodiment, the number of errors and error types of SBS are counted to generate single-event effect test results, including: calculating the single-event effect cross section of at least one error type; fitting a cross section curve based on the single-event effect cross section of at least one error type; calculating the single-event flip rate based on the fitted cross section curve of the single-event effect cross section, and estimating the space flip rate.

[0062] Specifically, such as Figure 3 As shown, based on the data collected by the PC host computer, SEE (Search Escapes) are classified: Let n bits represent a word, N words form a group, and t be the threshold. n, N, and t can be determined as needed. If any bit in a word is flipped, it is recorded as a misspelling. The number of misspellings in each group is denoted as m, where m ≤ N. When m < t, it is counted as one SEE; when m ≥ t, it is counted as one SEE. If the duration of an SEE exceeds a data packet transmission threshold time ε, it is recorded as an unrecoverable SEE; otherwise, it is recorded as a recoverable SEE.

[0063] Calculate the single-event effect flip-off cross section P for these three types, which represents the area where a single-event effect (SEE) will occur under bombardment by high-energy particles with a certain LET (Linear Energy Transfer) density. Let the total number of particles bombarding a unit area of ​​the device be Q, and the number of times SerDes produces an SEE under particle bombardment be N. This analysis examines the single-event sensitivity of different structural units within SerDes.

[0064] The relationship between the flip cross section and the heavy ion LET value was analyzed, and the flip thresholds and saturation cross sections of SEU, recoverable SEFI, and non-recoverable SEFI were calculated. The saturation cross section refers to the maximum value of the SEE cross section P, which is the saturation cross section P of SEU. sat_SEU Recoverable SEFI saturated cross section P sat_rec_SEFI and the irrecoverable SEFI saturated cross section P sat_Unrec_SEFI By fitting the curves using the Weibull function, the P-LET curves for the corresponding SEU, recoverable SEF, and non-recoverable SEF are obtained. The formulas for calculating the Weibull cross-sections of the three types of SEE are as follows:

[0065]

[0066]

[0067]

[0068] Among them, LET th_SEU LET th_rec_SEFI LET th_Unrec_SEFI These represent the lowest LET values ​​for the observed SEU, recoverable SEFI, and non-recoverable SEFI, respectively; W is the width parameter; and v is the dimensionless exponent. The characteristics and influence of the three typical SEE types on SerDes are analyzed based on the cross-sectional curves.

[0069] Calculate the single-event flip rate φ for heavy-ion-induced SEU, recoverable SEFI, and unrecoverable SEFI. SEU φ rec_SEFI φ Unrec_SEFI The formulas are as follows:

[0070]

[0071]

[0072]

[0073] Where λ is the LET value, σ SEU σ rec_SEFI σ Unrec_SEFI This is the previously calculated Weibull cross section, where D(λ) is the value that can be deposited with λ within the sensitive volume. critThe differential of the path length, F(λ), is the integral flux of heavy ions and LET > λ. Based on the fault frequency and Weibull function fitting results, the space flip rate is predicted using software such as Crème. The different sensitivities of the transmitter, receiver, and clock circuit of the SerDes module to different types of SEE are analyzed to determine the most suitable radiation hardening method.

[0074] The single-event effect (SEE) testing method for SerDes modules in FPGA devices proposed in this application is applicable to high-speed SerDes modules in advanced FPGA devices with process nodes of 28nm and below, which aligns with the needs of aerospace for studying the radiation effect mechanism of high-end electronic components. By locating the physical position of the SerDes through code stream parsing and employing logic shielding technology to block radiation, the interference of the ion beam on non-test modules is significantly reduced, minimizing the error in SerDes module SEE experimental data and improving data validity. Detailed classification of SEE and SerDes sensitivity analysis are performed by combining the number of error bits and error duration, providing a reliable testing approach for SEE research on FPGAs in aerospace and other radiation environments. This promotes the research of high-reliability FPGA SerDes modules and helps overcome the bottleneck of data transmission capabilities in AI applications, thus demonstrating broad applicability.

[0075] Next, referring to the accompanying drawings, a single-event effect testing apparatus for an FPGA device SerDes module is described according to an embodiment of this application.

[0076] Figure 5 This is a block diagram of a single-event effect testing device for an FPGA device SerDes module according to an embodiment of this application.

[0077] like Figure 5 As shown, the single-event effect testing device 10 for the SerDes module of the FPGA device includes: a generation module 100, a control module 200, and a statistics module 300.

[0078] The generation module 100 is used to generate the first SBS code of the target code pattern using the first FPGA device as the main control device; the control module 200 is used to control the first FPGA device to receive radiation during the transmission of the first SBS code by the second FPGA device as the device under test, and to detect the second SBS code of the target code pattern after radiation; the statistics module 300 is used to count the number of bit errors and error types of SBS with reference to the second SBS code, and generate single-event effect test results.

[0079] Furthermore, the statistics module 300 is further used to calculate the single-event effect cross section for at least one error type; fit a cross-sectional curve to the single-event effect cross section for at least one error type; calculate the single-event flip rate based on the fitted cross-sectional curve of the single-event effect cross section, and estimate the space flip rate; the formula for calculating the single-event flip rate is:

[0080]

[0081]

[0082]

[0083] Where λ is the LET value, σ SEU σ rec_SEFI σ Unrec_SEFI It is the Weibull section, and D(λ) is the deposition of Q with λ within the sensitive volume. crit The differential of the path length, F(λ) is the integral flux of heavy ions and LET>λ.

[0084] Furthermore, the apparatus 10 in this embodiment further includes a judgment module and a setting module. The judgment module is configured to, before counting the number of errors and error types of the SBS, acquire the total amount of the second FPGA device at preset intervals; determine whether the total amount of the error is greater than a preset threshold; if it is less than the preset threshold, continue irradiating the second FPGA device with a preset particle beam; the setting module is configured to, before generating the first SBS code of the target code pattern using the first FPGA device as the master controller, detect whether the SerDes module of the second FPGA device is in near-end loopback mode; after detecting that it is in near-end loopback mode, set a logic window on the SerDes module to shield other parts.

[0085] It should be noted that the foregoing explanation of the single-event effect testing method embodiment for the SerDes module of the FPGA device also applies to the single-event effect testing device for the SerDes module of the FPGA device in this embodiment, and will not be repeated here.

[0086] The single-event effect (SEE) testing device for SerDes modules of FPGA devices proposed in this application is applicable to high-speed SerDes modules in advanced FPGA devices with process nodes of 28nm and below, which meets the needs of aerospace for studying the radiation effect mechanism of high-end electronic components. By parsing the bitstream to locate the physical position of the SerDes module and employing logic shielding technology to block radiation, the interference of the ion beam on non-test modules is significantly reduced, minimizing the error of the SerDes module's SEE experimental data and improving the validity of the data. Detailed classification of SEE and SerDes sensitivity analysis are performed by combining the number of error bits and error duration, providing a reliable testing approach for SEE research on FPGAs in aerospace and other radiation environments. This promotes the research of high-reliability FPGA SerDes modules and helps overcome the bottleneck of data transmission capabilities in AI applications, thus having wide applicability.

[0087] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include:

[0088] The memory 601, the processor 602, and the computer program stored on the memory 601 and capable of running on the processor 602.

[0089] When the processor 602 executes the program, it implements the single-event effect testing method for the SerDes module of the FPGA device provided in the above embodiments.

[0090] Furthermore, electronic devices also include:

[0091] Communication interface 603 is used for communication between memory 601 and processor 602.

[0092] The memory 601 is used to store computer programs that can run on the processor 602.

[0093] The memory 601 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0094] If the memory 601, processor 602, and communication interface 603 are implemented independently, then the communication interface 603, memory 601, and processor 602 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0095] Optionally, in a specific implementation, if the memory 601, processor 602, and communication interface 603 are integrated on a single chip, then the memory 601, processor 602, and communication interface 603 can communicate with each other through an internal interface.

[0096] The processor 602 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0097] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described single-event effect testing method for the SerDes module of an FPGA device.

[0098] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0099] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0100] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0101] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0102] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0103] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments.

[0104] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0105] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for single event effect testing of a SerDes module of an FPGA device, the method comprising: providing a test pattern to the SerDes module; and applying a single event upset (SEU) to the SerDes module. The method comprises the following steps: generating a first SBS code of a target code type by a first FPGA device as a master device; before generating the first SBS code of the target code type by the first FPGA device as the master device, further comprising: detecting whether a SerDes module of a second FPGA device is in a near-end loopback mode; and after detecting that the SerDes module is in the near-end loopback mode, setting a logical window for shielding other parts on the SerDes module; in the process of transmitting the first SBS code by the second FPGA device as a device to be tested, controlling the first FPGA device to make the first SBS code accept radiation, and detecting a second SBS code of the target code type after the radiation; and referencing the second SBS code, counting the number of error codes and error types of SBS, and generating a single-particle effect test result.

2. The method of claim 1, wherein, The counting of the number of error codes and error types of SBS and the generation of the single-particle effect test result comprise: calculating a single-particle effect cross section of at least one error type; fitting a cross section curve graph from the single-particle effect cross section of the at least one error type; calculating a single-particle flip rate and estimating a space flip rate according to the cross section curve graph fitted from the single-particle effect cross section.

3. The method of claim 2, wherein, The calculation formula of the single-particle flip rate is: where λ is the LET value, σ SEU , σ rec_SEFI , σ Unrec_SEFI is the Weibull section, D(λ) is the differential path length within the sensitive volume that deposits Q crit at λ, and F(λ) is the integrated flux of heavy ions with LET > λ.

4. The method of claim 1, wherein, before counting the number of error codes and error types of SBS, further comprising: acquiring a total fluence of the second FPGA device every preset time length; judging whether the total fluence is greater than a preset threshold; if the total fluence is less than the preset threshold, continuing to irradiate the second FPGA device with a preset particle beam.

5. A single-event effect testing device for a SerDes module of an FPGA device, characterized in that, comprise: a generating module configured to generate a first SBS code of a target code type by a first FPGA device as a master device; a setting module configured to, before generating the first SBS code of the target code type by the first FPGA device as the master device, detect whether a SerDes module of a second FPGA device is in a near-end loopback mode; and after detecting that the SerDes module is in the near-end loopback mode, set a logical window for shielding other parts on the SerDes module; a control module configured to, in the process of transmitting the first SBS code by the second FPGA device as a device to be tested, control the first FPGA device to make the first SBS code accept radiation, and detect a second SBS code of the target code type after the radiation; and a statistical module configured to, reference the second SBS code, count the number of error codes and error types of SBS, and generate a single-particle effect test result. The statistical module is further configured to calculate a single-particle effect cross section of at least one error type; fit a cross section curve graph from the single-particle effect cross section of the at least one error type; calculate a single-particle flip rate and estimate a space flip rate according to the cross section curve graph fitted from the single-particle effect cross section; and the calculation formula of the single-particle flip rate is:

6. The apparatus of claim 5, wherein, further comprise: where λ is the LET value, σ SEU , σ rec_SEFI , σ Unrec_SEFI is the Weibull section, D(λ) is the differential path length within the sensitive volume that deposits Q crit at λ, and F(λ) is the integrated flux of heavy ions with LET > λ.

7. The apparatus of claim 5, wherein, a judging module configured to, before counting the number of error codes and error types of SBS, acquire a total fluence of the second FPGA device every preset time length; ​ determining whether the total dose is greater than a preset threshold; if less than the preset threshold, continuing to irradiate the second FPGA device with a preset particle beam.

8. An electronic device, comprising: The application also provides a computer program product for testing a single event effect of a SerDes module of an FPGA device, comprising a computer program and a computer readable storage medium storing the computer program, wherein when the program is executed by a computer, the single event effect testing method according to any one of claims 1-4 is implemented. The application also provides a computer program product for testing a single event effect of a SerDes module of an FPGA device, comprising a computer program and a computer readable storage medium storing the computer program, wherein when the program is executed by a computer, the single event effect testing method according to any one of claims 1-4 is implemented.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The application also provides a computer program product for testing a single event effect of a SerDes module of an FPGA device, comprising a computer program and a computer readable storage medium storing the computer program, wherein when the program is executed by a computer, the single event effect testing method according to any one of claims 1-4 is implemented.

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