Drive circuit and memory chip

Abstract

The present disclosure provides a driving circuit and a storage chip, wherein the driving circuit comprises: an amplification module, which operates in a first voltage domain; an output module, which operates in a second voltage domain, wherein the supply voltage of the second voltage domain is greater than the supply voltage of the first voltage domain, and the output end of the output module is the output end of the driving circuit; a connection module, which connects the output end of the amplification module with the input end of the output module; and a feedback module, wherein the input end of the feedback module is connected to the output end of the output module, and the output end of the feedback module is connected to the input end of the amplification module. The embodiment of the present disclosure can utilize the input end and the output end of the driving circuit respectively operating in two voltage domains and the feedback module to improve the output voltage accuracy of the driving circuit and reduce the power consumption of the driving circuit.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a driving circuit operating in multiple voltage domains and a memory chip using the driving circuit. Background Art

[0002] In a DRAM (Dynamic Random Access Memory) analog circuit, a driving circuit having both pull-up and pull-down capabilities in a high voltage domain and low power consumption is required.

[0003] In the related art, to meet the requirements for pull-up and pull-down capabilities of the driver circuit, the driver circuit is generally configured to operate in the high-voltage domain. However, because the voltage source in the high-voltage domain of DRAM is generated by a charge pump with an efficiency of less than 50%, this driver circuit typically has high power consumption. To reduce power consumption, the related art also uses a solution that configures the driver circuit to operate in the low-voltage domain. However, this solution only provides pull-down capability and cannot meet the pull-up requirements or the output voltage accuracy requirements of the driver circuit.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a driving circuit operating in multiple voltage domains and a memory chip using the driving circuit, so as to at least to some extent overcome the problems of insufficient driving voltage accuracy, high power consumption, insufficient driving capability, etc. of the driving circuit caused by the limitations and defects of related technologies.

[0006] According to a first aspect of the present disclosure, a driving circuit is provided, comprising: an amplification module, operating in a first voltage domain; an output module, operating in a second voltage domain, wherein the supply voltage of the second voltage domain is greater than the supply voltage of the first voltage domain, and the output end of the output module is the output end of the driving circuit; a connection module, connecting the output end of the amplification module with the input end of the output module; and a feedback module, wherein the input end of the feedback module is connected to the output end of the output module, and the output end of the feedback module is connected to the input end of the amplification module.

[0007] In an exemplary embodiment of the present disclosure, the connection module includes: an N-type common-source transistor, a gate of which is connected to the output end of the amplification module, a drain of which is connected to the first node, and a source of which is grounded.

[0008] In an exemplary embodiment of the present disclosure, the connection module includes: a P-type common-drain transistor, a gate of which is connected to the output end of the amplification module, a source of which is connected to the first node, and a drain of which is grounded.

[0009] In an exemplary embodiment of the present disclosure, the connection module includes: an N-type common-gate transistor, the gate of which is connected to the first supply voltage corresponding to the first voltage domain, and the drain of which is connected to the first node; a P-type common-drain transistor, the gate of which is connected to the output end of the amplification module, the source of which is connected to the source of the N-type common-gate transistor, and the drain of which is grounded.

[0010] In an exemplary embodiment of the present disclosure, the output module is implemented by an AB source follower.

[0011] In an exemplary embodiment of the present disclosure, the output module includes: a load unit, a first end of which is connected to the second supply voltage corresponding to the second supply voltage domain, and a second end of which is connected to the second node; a first transistor, which is an N-type transistor, whose drain and gate are both connected to the second node, and whose source is connected to the third node; a second transistor, which is a P-type transistor, whose source is connected to the third node, and whose drain and gate are both connected to the first node; a third transistor, which is an N-type transistor, whose gate is connected to the second node, whose drain is connected to the second supply voltage, and whose source is connected to a fourth node, and the fourth node is the output end of the output module; a fourth transistor, which is a P-type transistor, whose gate is connected to the first node, whose source is connected to the fourth node, and whose drain is grounded.

[0012] In an exemplary embodiment of the present disclosure, the output module is implemented by AB push-pull output.

[0013] In an exemplary embodiment of the present disclosure, the output module includes: a load unit, a first end of which is connected to the second supply voltage corresponding to the second supply voltage domain, and a second end of which is connected to the second node; a first transistor, which is a P-type transistor, a source connected to the second node, a drain connected to the first node, and a gate connected to a first control signal, and the first control signal is used to provide a bias voltage for the first transistor; a second transistor, which is an N-type transistor, a drain connected to the second node, a source connected to the first node, and a gate connected to a second control signal, and the second control signal is used to provide a bias voltage for the second transistor; a third transistor, which is a P-type transistor, a gate connected to the second node, a source connected to the second supply voltage, and a drain connected to a fourth node, and the fourth node is the output end of the output module; a fourth transistor, which is an N-type transistor, a gate connected to the first node, a drain connected to the fourth node, and a source grounded.

[0014] In an exemplary embodiment of the present disclosure, the load unit includes: a current source, an input end of which is connected to the second supply voltage, and an output end of which is connected to the second node.

[0015] In an exemplary embodiment of the present disclosure, the load unit includes: a load resistor, a first end of which is connected to the second supply voltage, and a second end of which is connected to the second node.

[0016] In an exemplary embodiment of the present disclosure, the feedback module is a resistor voltage divider circuit.

[0017] In an exemplary embodiment of the present disclosure, the resistance divider circuit includes: a first resistance unit, a first end of which is connected to the fourth node, and a second end of which is connected to the fifth node; a second resistance unit, a first end of which is connected to the fifth node, and a second end of which is grounded; wherein the fourth node is the output end of the output module, the fifth node is the output end of the feedback module, and the fifth node is connected to the input end of the amplification module.

[0018] In an exemplary embodiment of the present disclosure, the feedback module is a capacitive voltage divider circuit.

[0019] In an exemplary embodiment of the present disclosure, the feedback module includes: a first capacitor unit, a first end of which is connected to the fourth node, and a second end of which is connected to the fifth node; a second capacitor unit, a first end of which is connected to the fifth node, and a second end of which is grounded; wherein the fourth node is the output end of the output module, the fifth node is the output end of the feedback module, and the fifth node is connected to the input end of the amplification module.

[0020] In an exemplary embodiment of the present disclosure, when the connection module includes an N-type common source tube, the amplification module includes: an error amplifier; when the output module is implemented by an AB source follower, the non-inverting input terminal of the error amplifier is connected to the output terminal of the feedback module, and the inverting input terminal is connected to the reference voltage; when the output module is implemented by an AB push-pull output, the inverting input terminal of the error amplifier is connected to the output terminal of the feedback module, and the non-inverting input terminal is connected to the reference voltage.

[0021] In an exemplary embodiment of the present disclosure, when the connection module includes a P-type common-drain transistor, the amplification module includes: an error amplifier; when the output module is implemented by an AB source follower, the inverting input terminal of the error amplifier is connected to the output terminal of the feedback module, and the non-inverting input terminal is connected to the reference voltage; when the output module is implemented by an AB push-pull output, the non-inverting input terminal of the error amplifier is connected to the output terminal of the feedback module, and the inverting input terminal is connected to the reference voltage.

[0022] In an exemplary embodiment of the present disclosure, the reference voltage in the amplification module is determined according to a resistance ratio of the first resistance unit to the second resistance unit.

[0023] In an exemplary embodiment of the present disclosure, the reference voltage in the amplification module is determined according to a ratio of the capacitances of the first capacitor unit to the second capacitor unit.

[0024] According to a second aspect of the present disclosure, a memory chip is provided, comprising the driving circuit as described in any one of the above items.

[0025] The embodiment of the present disclosure sets the input-end amplification module of the driving circuit in the low-voltage domain and the output module in the high-voltage domain, thereby effectively reducing the power consumption of the driving circuit while ensuring that the driving circuit provides pull-up and pull-down capabilities; by using a feedback module connecting the two voltage domains to sample the output of the high-voltage domain and feed back the sample to the input module of the low-voltage domain, the output voltage accuracy of the driving circuit can be effectively controlled, and the power consumption of the driving circuit can be reduced while ensuring the driving capability of the driving circuit and meeting the high-precision requirements of the driving voltage.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0028] Figure 1 is a schematic diagram of a driving circuit in an exemplary embodiment of the present disclosure.

[0029] Figure 2 FIG. 1 is a schematic diagram of a driving circuit in the first embodiment of the present disclosure.

[0030] Figure 3 FIG. 1 is a schematic diagram of a driving circuit in a second embodiment of the present disclosure.

[0031] Figure 4 FIG. 1 is a schematic diagram of a driving circuit in a third embodiment of the present disclosure.

[0032] Figure 5 FIG. 4 is a schematic diagram of a driving circuit in a fourth embodiment of the present disclosure.

[0033] Figure 6 FIG. 5 is a schematic diagram of a driving circuit in a fifth embodiment of the present disclosure.

[0034] Figure 7 FIG. 1 is a schematic diagram of a driving circuit in a sixth embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or that other methods, components, devices, steps, etc. may be employed. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0036] The accompanying drawings are merely schematic illustrations of the present disclosure. Identical reference numerals in the drawings denote identical or similar components, and thus their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0037] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 FIG. 1 is a schematic structural diagram of a driving circuit in an exemplary embodiment of the present disclosure.

[0039] refer to Figure 1 , the driving circuit 100 may include:

[0040] The amplifier module 11 operates in a first voltage domain A;

[0041] The output module 12 operates in the second voltage domain B. The supply voltage V2 of the second voltage domain B is greater than the supply voltage V1 of the first voltage domain A. The output end of the output module 12 is the output end of the driving circuit 100.

[0042] A connecting module 13 connects the output end of the amplifying module 11 and the input end of the output module 12;

[0043] The feedback module 14 has an input end connected to the output end of the output module 12 , and an output end of the feedback module 14 is connected to the input end of the amplification module 11 .

[0044] exist Figure 1In the illustrated embodiment, since the amplification module 11 operates in a first voltage domain A with a lower voltage, the overall power consumption of the driving circuit 100 can be reduced; since the output module 12 operates in a second voltage domain B with a higher voltage, the pull-up and pull-down capabilities of the driving circuit 100 can be guaranteed; the connection module 13 can be used to enable the output voltage of the amplification module 11 to control the output voltage of the output module 12; the feedback module 14 can be used to feed back the output voltage of the output module 12 in the second voltage domain B to the input end of the amplification module 11 in the first voltage domain A for feedback adjustment, thereby effectively improving the accuracy of the output voltage of the driving circuit 100, while meeting the requirements for the pull-up capability, pull-down capability, low power consumption, and high output voltage accuracy of the driving circuit.

[0045] The following describes various exemplary embodiments of the driving circuit 100. The embodiments provided in the following figures of the present disclosure are only examples. In practical applications, those skilled in the art can Figure 1 The illustrated architecture and the following exemplary embodiments set detailed circuit structures, component types, and component parameters, but the present disclosure is not limited thereto.

[0046] Figure 2 FIG. 1 is a schematic diagram of a driving circuit in the first embodiment of the present disclosure.

[0047] refer to Figure 2 In the driving circuit 200, the implementation of each module can be the following combination.

[0048] The amplification module 11 is implemented by, for example, an error amplifier 111 .

[0049] The connection module 12 may be an N-type common-source transistor 121. The gate of the N-type common-source transistor 121 is connected to the output of the error amplifier 111, the drain and the input of the output module 12 are connected to the first node N1, and the source is grounded. The non-inverting input of the error amplifier 111 is connected to the output of the feedback module 14, and the inverting input is connected to the reference voltage Vref.

[0050] The feedback module 14 can be implemented, for example, by a resistor divider circuit. The resistor divider circuit can include, for example, a first resistor unit 141 and a second resistor unit 142. The first end of the first resistor unit 141 is connected to a fourth node N4, and the second end is connected to a fifth node N5. The first end of the second resistor unit 142 is connected to a fifth node N5, and the second end is grounded. The fourth node N4 is the output terminal of the output module 13, the fifth node N5 is the output terminal of the feedback module 12, and the fifth node N5 is connected to the input terminal of the amplification module 11. The first resistor unit 141 and the second resistor unit 142 can both be implemented by one or more resistive elements, and this disclosure does not impose any particular limitation on this.

[0051] In some other embodiments, the feedback module 14 may also be implemented by a capacitor voltage divider circuit, which may include, for example, a first capacitor unit (not shown) and a second capacitor unit (not shown), wherein a first end of the first capacitor unit is connected to the fourth node N4 and a second end is connected to the fifth node N5; a first end of the second capacitor unit is connected to the fifth node N5 and a second end is grounded. The first capacitor unit and the second capacitor unit may both be implemented by one or more capacitors connected in series or in parallel, and the present disclosure does not impose any particular limitation on this.

[0052] Output circuit 13 can be implemented using an AB source follower. The AB source follower is a type of power amplifier circuit. Power amplifier circuits can be divided into six categories: Class A circuits are used for direct power modulation, Class B circuits are similar to emitter followers and often use a push-pull structure, and Class AB circuits are a combination of Class A and Class B circuits.

[0053] exist Figure 2 In the illustrated embodiment, the output circuit 13 may include a load unit 131 , a first transistor M1 , a second transistor M2 , a third transistor M3 , and a fourth transistor M4 to implement an AB source follower.

[0054] The two ends of the load unit 131 are connected to the second voltage V2 corresponding to the second voltage domain and the second node N2, respectively. The first transistor M1 is an N-type transistor, with its gate and drain connected to the second node N2 and its source connected to the third node N3. The second transistor M2 is a P-type transistor, with its gate and drain connected to the first node N1 and its source connected to the third node N3. The third transistor M3 forms a source follower circuit for providing a pull-up function, with its gate connected to the second node N2, its drain connected to the second voltage V2, and its source connected to a fourth node N4. The fourth node N4 is the output terminal of the output circuit 13 and the drive circuit 100. The gate of the third transistor M3 is controlled by the voltage variation of the second node N2 to output a source voltage Vo, providing a voltage pull-up for the fourth node N4. The fourth transistor M4 forms a source follower circuit for providing a pull-down function, with its gate connected to the first node N1, its drain grounded, and its source connected to the fourth node N4. The gate of the fourth transistor M4 is controlled by the voltage variation of the first node N1 to output a source voltage Vo, providing a voltage pull-down for the fourth node N4. The third transistor M3 and the fourth transistor M4 cooperate to provide an output circuit with high input impedance and low output impedance.

[0055] like Figure 2 As shown, when the amplification module 11 includes an error amplifier 111, the connection module 12 is implemented by an N-type common source tube, the output module 13 is implemented by an AB source follower, and the feedback module 14 is implemented by a resistor voltage divider circuit, the non-inverting input terminal of the error amplifier 111 is connected to the fifth node N5, and the inverting input terminal is connected to the reference voltage.

[0056] The reference voltage connected to the inverting input of the error amplifier 111 can be determined based on the ratio of the first resistor unit 141 to the second resistor unit 142. Assuming that the target output voltage at the output of the output circuit 13 is Vt (Vt is not necessarily equal to the actual output voltage Vo), the resistance of the first resistor unit 141 is R1, and the resistance of the second resistor unit 142 is R2, the reference voltage Vref connected to the inverting input of the error amplifier 111 can be:

[0057]

[0058] When the output voltage Vo of the fourth node N4 fluctuates due to the change of the external load and is not equal to Vt, the voltage of the fifth node N5, i.e., the input voltage Vin of the non-inverting input terminal of the error amplifier 111, is:

[0059]

[0060] As a result, there is a voltage difference between the two input terminals of the error amplifier 111. This voltage difference acts on the gate of the N-type common source transistor 121 through the output terminal of the error amplifier 111, causing the voltage of the first node N1 to change. This voltage change directly acts on the gate of the fourth transistor M4, causing the source voltage of the fourth transistor M4 to change, that is, the output voltage Vo to change.

[0061] When Vo is greater than Vt, the voltage at the fifth node N5 increases, and the voltage at the non-inverting input of the error amplifier 111 becomes greater than the voltage at the inverting input. The output voltage of the error amplifier 111, i.e., the gate voltage of the N-type common source transistor 121, increases, while the drain of the N-type common source transistor 121, i.e., the voltage at the first node N1, decreases. This causes the gate-source voltage difference of the fourth transistor M4 (Vgs of M4) to increase, and the source voltage of the fourth transistor M4, i.e., the voltage Vo at the fourth node N4, to decrease. Simultaneously, the voltage drop at the first node N1 causes the voltage at the second node N2, i.e., the gate voltage of the third transistor M3, to decrease, which in turn causes the source voltage of the third transistor M3, i.e., the voltage Vo at the fourth node N4, to decrease. Under these dual effects, the voltage Vo at the fourth node N4 decreases, causing the voltage Vin at the fifth node N5 to decrease, which is then fed back to the input of the error amplifier 111. This cycle continues until Vo is equal to Vt again, at which point the voltages at the two inputs of the error amplifier 111 become equal, the voltages at each node become stable, and the circuit 200 automatically regulates the output voltage Vo.

[0062] When Vo is less than Vt, the voltage at the fifth node N5 decreases, the voltage at the non-inverting input of the error amplifier 111 is less than the voltage at the inverting input, the output voltage of the error amplifier 111, i.e., the gate voltage of the N-type common source transistor 121, decreases, the drain voltage of the N-type common source transistor 121, i.e., the voltage at the first node N1, increases, the source voltage of the fourth transistor M4, i.e., the voltage Vo at the fourth node N4, increases, and simultaneously, the voltage at the second node N2 increases, and the source voltage of the third transistor M3, i.e., the voltage Vo at the fourth node N4, increases. Under these dual effects, the voltage at the fourth node N4 increases and is fed back to the non-inverting input of the error amplifier 111 through the fifth node N5. This cycle continues until Vo is equal to Vt again, the voltages at the two input terminals of the error amplifier 111 are equal, the voltages at each node are stabilized, and the circuit 200 automatically regulates the output voltage Vo.

[0063] In the embodiment of the present disclosure, the load unit 131, together with the first transistor M1 and the second transistor M2, provides a bias voltage for the third transistor M3 and the fourth transistor M4. Therefore, the load unit 131 can be either a current source having a first end connected to the second voltage V2 and a second end connected to the second node N2, or a load resistor having a first end connected to the second voltage V2 and a second end connected to the second node N2 (the load resistor can be implemented by a single resistor or formed by multiple resistors connected in series and / or in parallel). The specific form of the load unit 131 can be set by those skilled in the art according to actual needs, and the present disclosure does not impose any special restrictions on this.

[0064] Figure 3 is a circuit diagram of a driving circuit in a second embodiment of the present disclosure.

[0065] refer to Figure 3 In the drive circuit 300, the amplification module 11, connection module 12, and feedback module 14 are similar to those in the drive circuit 200, and the output module 13 can be implemented using an AB push-pull output circuit. In this case, the non-inverting input terminal of the error amplifier 111 is connected to the reference voltage Vref, and the inverting input terminal is connected to the fifth node N5.

[0066] exist Figure 3In the illustrated embodiment, the output module 13 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The first transistor M1 is a P-type transistor, with its gate connected to the first control signal Vctrl1, its source connected to the second node N2, and its drain connected to the first node N1. The second transistor M2 is an N-type transistor, with its gate connected to the second control signal Vctrl2, its drain connected to the second node N2, and its source connected to the first node N1. The third transistor M3 is a P-type transistor, with its gate connected to the second node N2, its source connected to the second voltage V2, and its drain connected to a fourth node N4, i.e., the output terminal of the output module 13 and the drive circuit 300. The fourth transistor M4 is an N-type transistor, with its gate connected to the first node N1, its source connected to ground, and its drain connected to a fourth node N4, i.e., the output terminal of the output module 13 and the drive circuit 300.

[0067] Among them, the first control signal Vctrl1 can be calculated based on the parameters of the first transistor M1 and the target output voltage Vt, so as to provide an accurate bias voltage to the gate of the third transistor M3 through the source of the first transistor M1, thereby setting the drain voltage Vo of the third transistor M3 to the target output voltage Vt; the second control signal Vctrl2 can be calculated based on the parameters of the second transistor M2 and the target output voltage Vt, so as to provide an accurate bias voltage to the gate of the fourth transistor M4 through the source of the second transistor M2, thereby setting the drain voltage Vo of the fourth transistor M4 to the target output voltage Vt.

[0068] In the driver circuit 300, when the voltage at the fourth node N4, i.e., the output voltage Vo, is greater than the set voltage Vt, the voltage at the fifth node N5 increases, the voltage at the non-inverting input terminal of the error amplifier 111 becomes less than the voltage at the inverting input terminal, the output voltage of the error amplifier 111, i.e., the gate voltage of the N-type common source transistor 121, decreases, the drain voltage of the N-type common source transistor 121, i.e., the voltage at the first node N1, increases, and the drain voltage Vo of the fourth transistor M4 decreases. Simultaneously, the voltage at the first node N1 is transmitted to the second node N2 via the first transistor M1 and the second transistor M2, the gate voltage of the third transistor M3 increases, and the drain voltage Vo of the third transistor M3 decreases. Thus, the driver circuit 300 achieves reverse regulation when the output voltage Vo increases. Similarly, when the output voltage Vo is lower than the set voltage Vt, the voltage of the fifth node N5 drops, the gate voltage of the N-type common source transistor 121 rises, the voltages of the first node N1 and the second node N2 drop at the same time, and the drain voltages of the fourth transistor M4 and the third transistor M3 rise. The driving circuit 300 implements reverse regulation when the output voltage Vo drops.

[0069] Compared with the driving circuit 200, the driving circuit 300 can more accurately set the voltage Vo of the fourth node N4 to the target output voltage Vt because it uses the first control signal Vctrl1 and the second control signal Vctrl2 to provide static bias voltages for the third transistor M3 and the fourth transistor M4 through the first transistor M1 and the second transistor M2 respectively.

[0070] Figure 4 is a circuit diagram of a driving circuit in a third embodiment of the present disclosure.

[0071] refer to Figure 4 In driver circuit 400, amplification module 11 is implemented by an error amplifier 111, connection module 12 is implemented by a P-type common-drain transistor 122, output module 13 is implemented by an AB source-follower circuit, and feedback module 14 is implemented by a resistor divider feedback circuit. Accordingly, the non-inverting input terminal of error amplifier 111 is connected to a reference voltage Vref, and the inverting input terminal is connected to a fifth node N5.

[0072] Similar to the driver circuit 200, when the voltage Vo at the fourth node N4 rises, the voltage at the fifth node N5, i.e., the inverting input terminal of the error amplifier 111, rises accordingly. The output voltage of the error amplifier 111, i.e., the gate voltage of the P-type common-drain transistor 122, drops, and the source voltage, i.e., the voltage at the first node N1, drops. The fourth transistor M4 is affected by the drop in gate voltage, causing the source voltage Vo to drop. Simultaneously, the voltage at the second node N2 drops, and the third transistor M3 is affected by the drop in gate voltage, causing the source voltage Vo to drop. When the voltage Vo at the fourth node N4 drops, the changes in the voltages of the various nodes are opposite to those described above, and this disclosure will not be repeated here. Thus, the driver circuit 400 achieves reverse regulation of changes in the output voltage Vo.

[0073] Figure 5 is a circuit diagram of a drive circuit in a fourth embodiment of the present disclosure.

[0074] refer to Figure 5 In driver circuit 500, amplification module 11 is implemented by an error amplifier 111, connection module 12 is implemented by a P-type common-drain transistor 122, output module 13 is implemented by an AB push-pull output circuit, and feedback module 14 is implemented by a resistor divider feedback circuit. Unlike driver circuit 400, the inverting input terminal of error amplifier 111 is connected to a reference voltage Vref, and the non-inverting input terminal is connected to a fifth node N5.

[0075] When the output voltage Vo rises and the voltage at the fifth node N5 rises, the output voltage of the error amplifier 111 rises, the source voltage of the P-type common-drain transistor 122 rises, and the fourth transistor M4 is affected by the rising gate voltage, causing the drain voltage Vo to drop. Simultaneously, the voltage at the second node N2 rises, and the third transistor M3 is affected by the rising gate voltage, causing the drain voltage Vo to drop. When the voltage Vo at the fourth node N4 drops, the changes in the voltages at each node are opposite to those described above and are not further described in this disclosure. Thus, the driver circuit 500 achieves reverse regulation of changes in the output voltage Vo.

[0076] Figure 6 is a circuit diagram of a drive circuit in a fifth embodiment of the present disclosure.

[0077] refer to Figure 6 In the drive circuit 600, the amplification module 11 is implemented by an error amplifier 111, the output module 13 is implemented by an AB source follower circuit, and the feedback module 14 is implemented by a resistor voltage divider feedback circuit. The connection module 12 includes a P-type common-drain transistor 122 and an N-type common-gate transistor 123. The gate of the P-type common-drain transistor 122 is connected to the output terminal of the error amplifier 111, the drain is grounded, and the source is connected to the source of the N-type common-gate transistor 123; the drain of the N-type common-gate transistor 123 is connected to the first node N1, and the gate is connected to the first voltage V1. The P-type common-drain transistor 122 and the N-type common-gate transistor 123 together form a common-drain and common-gate structure, which can increase the loop gain. The principle is as follows:

[0078] Assuming that the transconductance of the P-type common-source transistor 122 is gm1, the transconductance of the N-type common-gate transistor 123 is gm2, and the transconductance of the structure after the two are connected is GM, then:

[0079] 1 / GM=1 / gm1+1 / gm2 (3)

[0080] Thus, a two-stage gain is achieved, and the control accuracy of the voltage of the first node N1 can be effectively improved based on the output voltage of the same error amplifier 111, thereby improving the control accuracy of the output voltage Vo.

[0081] At this time, the non-inverting input terminal of the error amplifier 111 is connected to the reference voltage Vref, and the inverting input terminal is connected to the fifth node N5.

[0082] When the voltage Vo at the fourth node N4 rises, the input voltage at the inverting input of the error amplifier 111 rises, and the output voltage at the output terminal drops. The gate voltage drop affects the source voltage of the P-type common-drain transistor 122, causing it to drop. This source voltage is transmitted to the first node N1 via the N-type common-gate transistor 123, causing the voltage at the first node N1 and the voltage at the second node N2 to drop. The third transistor M3 and the fourth transistor M4 are each affected by the gate voltage drop, causing their source voltages Vo to drop. When the voltage Vo at the fourth node N4 drops, the changes in the voltages at each node are opposite to those described above, and this disclosure will not be repeated here. Thus, the driver circuit 600 achieves reverse regulation of the change in the output voltage Vo.

[0083] Figure 7 is a circuit diagram of a drive circuit in a sixth embodiment of the present disclosure.

[0084] refer to Figure 7 In the driving circuit 700, the amplification module 11 is implemented by the error amplifier 111, the connection module 12 is implemented by the P-type common-drain transistor 122 and the N-type common-gate transistor 123, the output module 13 is implemented by the AB push-pull output circuit, and the feedback module 14 is implemented by the resistor voltage divider feedback circuit.

[0085] At this time, the non-inverting input terminal of the error amplifier 111 is connected to the fifth node N5 , and the inverting input terminal is connected to the reference voltage Vref.

[0086] When the output voltage Vo rises, the voltage at the fifth node N5, i.e., the non-inverting input terminal of the error amplifier 111, rises, and the output voltage rises. The rising gate voltage affects the source voltage of the P-type common-drain transistor 122, which then rises. This source voltage is transmitted to the first node N1 via the N-type common-gate transistor 123, causing the voltage at the first node N1 and the voltage at the second node N2 to rise. The third transistor M3 and the fourth transistor M4 are each affected by the rising gate voltage, causing the drain voltage Vo to drop. When the voltage Vo at the fourth node N4 drops, the changes in the voltages of the various nodes are opposite to those described above, and this disclosure will not be repeated here. Thus, the driver circuit 700 achieves reverse regulation of the changes in the output voltage Vo.

[0087] In the first to sixth embodiments, a voltage change of the output voltage Vo causes a voltage change at the input terminal of the error amplifier 111 (i.e., the output terminal fifth node N5 of the feedback module 14), thereby causing a change in the output voltage of the error amplifier 111, i.e., the input voltage of the connection module 12. This further causes a voltage change at the first node N1 through the connection module 12. The voltage change at the first node N1 is transmitted to the second node N2 via the first transistor M1 and the second transistor M2, causing the gate voltages of the third transistor M3 and the fourth transistor M4 to change in the same direction, thereby causing a change in the output voltage Vo. This cycle continues until the voltages at the non-inverting input terminal and the inverting input terminal of the error amplifier 111 are the same, the output terminal voltage of the error amplifier 111 no longer changes, the voltages at the first node N1 and the second node N2, i.e., the gate voltages of the third transistor M3 and the fourth transistor M4, no longer change, and the voltage Vo at the fourth node N4 is stabilized.

[0088] In the above embodiments of the present disclosure, the connection module 12 can be implemented through three schemes: N-type common source tube 121, P-type common drain tube 122, and P-type common drain tube 122 plus N-type common gate tube 123; the output module 13 can be implemented through two schemes: AB source follower circuit and AB push-pull output circuit; the feedback module 14 can be implemented through a resistor voltage divider circuit and a capacitor voltage divider circuit; the amplification module 11 can be implemented through an error amplifier 111, and the input connection method of the error amplifier 111 is set based on the actual circuit form of the connection module 12 and the output module 13. Therefore, in addition to the above embodiments, the present disclosure also has other combination embodiments of the multiple schemes mentioned above. Since the principles and connection relationships of the implementation plans corresponding to each module have been described in detail, Figures 2 to 7 The embodiments are described in detail, and the present disclosure will not elaborate on more solutions here.

[0089] It is understandable that, in addition to the above solutions, the amplification module 11, the connection module 12, the output module 13, and the feedback module 14 can also be implemented in other ways, as long as they can be implemented according to the Figure 1 The driving circuits configured according to the principles shown are all within the scope of protection of this disclosure.

[0090] To sum up, the embodiment of the present disclosure sets the amplification module 11 in the low voltage domain, sets the output module 13 in the high voltage domain, transmits the output voltage of the amplification module 11 to the output module 13 through the connection module 12, and feeds back the output voltage of the output module 13 to the input end of the amplification module 11 through the feedback module 14. This can improve the accuracy of the output voltage while ensuring that the driving circuit has both pull-up and pull-down capabilities, greatly reduce the power consumption of the overall driving circuit, and at the same time meet the requirements of the driving circuit for large driving capability, high output voltage accuracy, and low power consumption.

[0091] It should be noted that although several modules or units of the device for action execution are mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0092] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A driving circuit, characterized in that: include: An amplifying module, operating in a first voltage domain; an output module, operating in a second voltage domain, wherein a supply voltage of the second voltage domain is greater than a supply voltage of the first voltage domain, and an output end of the output module is an output end of the drive circuit; A connecting module, connecting the output end of the amplifying module with the input end of the output module; A feedback module, wherein an input end of the feedback module is connected to an output end of the output module, and an output end of the feedback module is connected to an input end of the amplification module; The connection module comprises: An N-type common source transistor, with a gate connected to the output end of the amplification module, a drain connected to the first node, and a source grounded; The output module is realized by AB push-pull output; The output module comprises: a load unit, a first end of which is connected to a second supply voltage corresponding to the second voltage domain, and a second end of which is connected to a second node; A first transistor is a P-type transistor, a source connected to the second node, a drain connected to the first node, and a gate connected to a first control signal, wherein the first control signal is used to provide a bias voltage for the first transistor; a second transistor, which is an N-type transistor, having a drain connected to the second node, a source connected to the first node, and a gate connected to a second control signal, wherein the second control signal is used to provide a bias voltage for the second transistor; a third transistor, which is a P-type transistor, has a gate connected to the second node, a source connected to the second supply voltage, and a drain connected to a fourth node, and the fourth node is an output end of the output module; The fourth transistor is an N-type transistor, with a gate connected to the first node, a drain connected to the fourth node, and a source connected to the ground.

2. The driving circuit according to claim 1, characterized in that: The load unit comprises: A current source has an input terminal connected to the second supply voltage and an output terminal connected to the second node.

3. The driving circuit according to claim 1, wherein: The load unit comprises: A load resistor, having a first end connected to the second supply voltage, and a second end connected to the second node.

4. The driving circuit according to claim 1, wherein: The feedback module is a resistor voltage divider circuit.

5. The driving circuit according to claim 4, characterized in that: The resistor voltage divider circuit comprises: A first resistor unit, a first end of which is connected to the fourth node, and a second end of which is connected to the fifth node; A second resistance unit, a first end of which is connected to the fifth node, and a second end of which is grounded; The fourth node is the output end of the output module, the fifth node is the output end of the feedback module, and the fifth node is connected to the input end of the amplification module.

6. The driving circuit according to claim 1, characterized in that: The feedback module is a capacitive voltage divider circuit.

7. The driving circuit according to claim 6, characterized in that: The feedback module comprises: A first capacitor unit, a first end of which is connected to the fourth node, and a second end of which is connected to the fifth node; A second capacitor unit, a first end of which is connected to the fifth node and a second end of which is grounded; The fourth node is the output end of the output module, the fifth node is the output end of the feedback module, and the fifth node is connected to the input end of the amplification module.

8. The driving circuit according to claim 1, characterized in that: The amplification module comprises: Error amplifier; When the output module is implemented by an AB source follower, the non-inverting input terminal of the error amplifier is connected to the output terminal of the feedback module, and the inverting input terminal is connected to a reference voltage; When the output module is implemented by AB push-pull output, the inverting input terminal of the error amplifier is connected to the output terminal of the feedback module, and the non-inverting input terminal is connected to the reference voltage.

9. The driving circuit according to claim 5, characterized in that: The reference voltage in the amplification module is determined according to the ratio of the resistance values ​​of the first resistance unit and the second resistance unit.

10. The driving circuit according to claim 7, characterized in that: The reference voltage in the amplification module is determined according to the ratio of the capacitance of the first capacitor unit to the capacitance of the second capacitor unit.

11. A memory chip, characterized in that: Comprising a driving circuit as described in any one of claims 1 to 10.

12. A driving circuit, characterized in that: include: An amplifying module, operating in a first voltage domain; an output module, operating in a second voltage domain, wherein a supply voltage of the second voltage domain is greater than a supply voltage of the first voltage domain, and an output end of the output module is an output end of the drive circuit; A connecting module, connecting the output end of the amplifying module with the input end of the output module; A feedback module, wherein an input end of the feedback module is connected to an output end of the output module, and an output end of the feedback module is connected to an input end of the amplification module; The connection module comprises: A P-type common drain tube, with a gate connected to the output end of the amplification module, a source connected to the first node, and a drain connected to the ground; The output module is realized by AB push-pull output; The output module comprises: a load unit, a first end of which is connected to a second supply voltage corresponding to the second voltage domain, and a second end of which is connected to a second node; A first transistor is a P-type transistor, a source connected to the second node, a drain connected to the first node, and a gate connected to a first control signal, wherein the first control signal is used to provide a bias voltage for the first transistor; a second transistor, which is an N-type transistor, having a drain connected to the second node, a source connected to the first node, and a gate connected to a second control signal, wherein the second control signal is used to provide a bias voltage for the second transistor; a third transistor, which is a P-type transistor, has a gate connected to the second node, a source connected to the second supply voltage, and a drain connected to a fourth node, and the fourth node is an output end of the output module; The fourth transistor is an N-type transistor, with a gate connected to the first node, a drain connected to the fourth node, and a source connected to the ground.

13. A driving circuit, characterized in that: include: An amplifying module, operating in a first voltage domain; an output module, operating in a second voltage domain, wherein a supply voltage of the second voltage domain is greater than a supply voltage of the first voltage domain, and an output end of the output module is an output end of the drive circuit; A connecting module, connecting the output end of the amplifying module with the input end of the output module; A feedback module, wherein an input end of the feedback module is connected to an output end of the output module, and an output end of the feedback module is connected to an input end of the amplification module; The connection module comprises: An N-type common-gate transistor, a gate of which is connected to a first supply voltage corresponding to the first voltage domain, and a drain of which is connected to a first node; A P-type common-drain tube, whose gate is connected to the output end of the amplification module, whose source is connected to the source of the N-type common-gate tube, and whose drain is grounded; The output module is realized by AB push-pull output; The output module comprises: a load unit, a first end of which is connected to a second supply voltage corresponding to the second voltage domain, and a second end of which is connected to a second node; A first transistor is a P-type transistor, a source connected to the second node, a drain connected to the first node, and a gate connected to a first control signal, wherein the first control signal is used to provide a bias voltage for the first transistor; a second transistor, which is an N-type transistor, having a drain connected to the second node, a source connected to the first node, and a gate connected to a second control signal, wherein the second control signal is used to provide a bias voltage for the second transistor; a third transistor, which is a P-type transistor, has a gate connected to the second node, a source connected to the second supply voltage, and a drain connected to a fourth node, and the fourth node is an output end of the output module; The fourth transistor is an N-type transistor, with a gate connected to the first node, a drain connected to the fourth node, and a source connected to the ground.

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