Packaging module, preparation method thereof, base station and electronic equipment

Abstract

The present application discloses a packaging module, a preparation method thereof, a base station and an electronic device. The packaging module includes a substrate, a chip located on the substrate, a first plastic encapsulation layer, a wiring layer located on the plastic encapsulation layer, and a plurality of interconnecting electrodes located on the wiring layer, a second plastic encapsulation layer and a conductive layer. The interconnecting electrode wiring layer is electrically connected, and the conductive layer is located on the second plastic encapsulation layer and includes a grounding pad and a signal transmission pad electrically connected to the plurality of interconnecting electrodes. In the packaging module, the interconnecting electrode can increase the cavity height, thereby avoiding the problem of self-excitation of the power amplifier. The grounding pad in the conductive layer can shield the radio frequency signal on the wiring layer, thereby improving the signal interference problem between the chip and the power amplifier board. In addition, since only a signal transmission pad for providing input / output signals to the chip needs to be set in the conductive layer, and no routing needs to be set, there can be enough area to set the grounding pad, and the occupied area of ​​the packaging module can be not increased.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a packaging module, a preparation method thereof, a base station and an electronic device. Background Art

[0002] The power amplifier (PA) is an important component of wireless communication base stations. With the development of communication technology, the current 5G power amplifier multi-channel communication technology (Massive MIMO) board is gradually evolving towards a board-level architecture. The key technical point to achieve the board-level architecture of the power amplifier board is that the power amplifier outputs the signal from the top and then interconnects the signal with the power amplifier board. The current common method is to use flip-chip technology to package the PA chip. Common packaging structures 1 such as Figure 1 As shown, the PA chip 11 is encapsulated on the substrate 10 by the encapsulation material 12, the wiring layer 13 is located on the encapsulation material 12 and is electrically connected to the PA chip 11, and the signal of the PA chip 11 is output through the pad 14 provided on the wiring layer 13. Then the package structure 1 is electrically connected to the power amplifier board 2, so as to realize the power amplifier board-level architecture.

[0003] However, the current board-level architecture of the power amplifier has the following problems: (1) The cavity height of the resonant cavity formed between the PA chip 11 and the power amplifier board 2 is relatively low, which may cause the power amplifier self-excitation problem; (2) There is a signal crosstalk problem between the RF signal on the PA chip 11 and the signal on the power amplifier board 2; (3) In order to reduce the signal reflection angle, a ground pad needs to be provided on the wiring layer of the packaging structure 1, which will increase the occupied area of ​​the packaging structure 1. Summary of the invention

[0004] The present application provides a packaging module, a preparation method thereof, a base station and an electronic device, which can not only improve the self-excitation problem of the power amplifier and the signal crosstalk problem, but also reduce the signal reflection angle without increasing the occupied area.

[0005] In the first aspect, the present application provides a packaging module, which may include: a substrate, a chip, a first plastic encapsulation layer, a wiring layer, a plurality of interconnecting electrodes, a second plastic encapsulation layer and a conductive layer. The chip is located on the substrate, the first plastic encapsulation layer is used to encapsulate the chip, the wiring layer is located on the side of the first plastic encapsulation layer away from the substrate, and the wiring layer is electrically connected to the chip. The plurality of interconnecting electrodes are located on the side of the wiring layer away from the first plastic encapsulation layer and are electrically connected to the wiring layer, so that they can be electrically connected to the chip through the wiring layer; the second plastic encapsulation layer is located on the side of the wiring layer facing the interconnecting electrodes and is used to encapsulate the plurality of interconnecting electrodes; the conductive layer is located on the side of the second plastic encapsulation layer away from the wiring layer, wherein the conductive layer includes a grounding pad and a signal transmission pad electrically connected to the plurality of interconnecting electrodes, and the signal transmission pad is used to realize the transmission of chip input / output signals.

[0006] The above-mentioned packaging module provided by the embodiment of the present application, when the packaging module is interconnected with the power amplifier board, since interconnection electrodes and conductive layers are also provided on the wiring layer, and since the interconnection electrodes can increase the distance between the chip and the power amplifier board, the cavity height can be adjusted to be higher, thereby avoiding the problem of self-excitation of the power amplifier. In addition, since a grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by the grounding pad, thereby improving the signal interference problem between the chip and the power amplifier board. In addition, since only a signal transmission pad for providing input / output signals to the chip needs to be provided in the conductive layer, unlike the wiring layer where routing lines need to be provided, there can be enough area for providing grounding pads, and there is no need to additionally expand the area of ​​the conductive layer, so that the grounding pad can be provided in the conductive layer without increasing the occupied area of ​​the packaging module, thereby reducing the reflection angle.

[0007] The present application does not limit the function of the chip. For example, the chip may be a power amplifier chip, a radio frequency microwave millimeter wave chip, a processor chip, or an intellectual property (IP) core.

[0008] It should be noted that the chip in the present application can be a bare die or a system-on-chip (SOC). Among them, a bare die is a crystal grain before the chip is packaged, and each bare die is a chip with independent functions that has not been packaged yet, which can be composed of one or more circuits. A system-on-chip is generally a product, an integrated circuit with a dedicated target, which contains a complete system and all the contents of embedded software. In the present application, since interconnect electrodes and a conductive layer are also provided on the wiring layer electrically connected to the chip, the interconnect electrodes can be used to increase the distance between the chip and the subsequently connected circuit board. In addition, since a grounding pad is provided in the conductive layer, the grounding pad can be used to achieve signal shielding. In addition, since the grounding pad is provided in the conductive layer, there is no need to increase the area of ​​the wiring layer.

[0009] In an embodiment of the present application, the chip may include at least one active device and / or at least one passive device. For example, the chip may include at least one active device, or the chip may include at least one passive device, or the chip may include at least one active device and at least one passive device. Among them, active devices refer to electronic components that require power to realize their specific functions. For example, electron tubes, transistors, integrated circuits, etc., are generally used for signal amplification, conversion, etc., which are not limited here. Passive devices refer to electronic components that can realize their characteristics without the need for an external power supply, such as resistors, capacitors, inductors, converters, gradienters, matching networks, resonators, filters, mixers and switches, etc., which are not limited here.

[0010] In the present application, the wiring layer is generally provided with chip pads electrically connected to the input / output pins of the chip and routing electrically connected to the chip, and the routing is generally used to connect the internal devices of the chip. The chip pads are electrically connected to the signal transmission pads through the interconnection electrodes. When the wiring layer is electrically connected to the outside world through the signal transmission pads in the conductive layer, the chip can realize the functions of the chip through the wiring layer.

[0011] In the present application, in order to avoid signal interference between the routing and the power amplifier board, the orthographic projection of the grounding pad on the substrate at least covers part of the routing, that is, for the wiring layer, the grounding pad can shield the signal on the power amplifier board. For the power amplifier board, the grounding pad can shield the signal on the routing. Therefore, in the specific implementation, the larger the coverage area of ​​the grounding pad, the better the shielding effect.

[0012] Exemplarily, multiple chip pads in the wiring layer can be arranged around the routing, that is, the routing is arranged in the central area, and multiple chip pads are arranged in the edge area. Correspondingly, in the conductive layer, multiple signal transmission pads are also arranged around the ground pad.

[0013] It should be noted that the embodiments of the present application do not specifically limit the number, shape, material and other features of the signal transmission pads. For example, the number of signal transmission pads can be designed according to the chip pads in the wiring layer, the signal transmission pads can be round, square, or other shapes, and the conductive layer can be made of tin, copper or other metals with conductive properties.

[0014] In a specific implementation, the wiring layer may include one conductive layer or multiple (at least two) conductive layers. Exemplarily, when the wiring includes multiple conductive layers, an insulating dielectric layer is also provided between adjacent conductive layers, and dielectric perforations are provided in the insulating dielectric layer, and adjacent conductive layers can be electrically connected through the dielectric perforations in the insulating dielectric layer. The conductive layer may include routing, and the chip pad is generally provided in the conductive layer closest to the interconnect electrode in the wiring layer.

[0015] Illustratively, in the present application, the conductive layer can be formed of materials such as gold, silver, aluminum, zinc, copper, chromium, nickel, palladium, etc., which are not limited here.

[0016] The present application does not limit the material of the insulating dielectric layer, and for example, it can be at least one of silicon oxide, silicon nitride, silicon oxynitride, resin material, etc.

[0017] Exemplarily, in order to ensure the consistency of materials between film layers, the material of the insulating dielectric layer may be the same as the material of the first plastic encapsulation layer or the second plastic encapsulation layer, which is not limited here.

[0018] In the present application, the materials of the first plastic encapsulation layer and the second plastic encapsulation layer may be the same, or may be different, which is not limited here.

[0019] Optionally, in the present application, the materials of the insulating dielectric layer, the first plastic encapsulation layer and the second plastic encapsulation layer are all the same.

[0020] For example, in one embodiment, the wiring layer can be electrically connected to the chip through a plurality of metal balls arranged in a stacked manner. The present application does not limit the material of the metal balls, for example, the metal balls can be formed of gold, silver, aluminum, zinc, copper, chromium, nickel, palladium, and the like.

[0021] For example, in another embodiment, the wiring layer may be electrically connected to the chip through a first via hole penetrating the first plastic packaging layer.

[0022] In a specific implementation, the conductive material in the first via hole may be formed of gold, silver, copper or other materials, which are not limited here.

[0023] In a specific implementation, the substrate can be formed by a copper-clad laminate. Of course, any structure with circuits such as a redistribution layer or a silicon interposer can also be used to replace the substrate, which is not limited here.

[0024] In a specific implementation, when it is necessary to electrically connect the wiring layer to the substrate, the wiring layer may be electrically connected to the substrate through a second via hole penetrating the first plastic packaging layer.

[0025] In a specific implementation, the conductive material in the second via hole may be formed of gold, silver, copper or other materials, which are not limited here.

[0026] In specific implementation, the present application does not limit the specific form of the interconnection electrode. Exemplarily, the interconnection electrode can be formed by a metal column or a metal wire.

[0027] The present application does not limit the material of the interconnection pillar, for example, it can be Cu, Ni, Mo, W, tungsten alloy, Cu-Mo alloy, nickel alloy, etc.

[0028] In order to avoid the influence of external signals on the packaging module, optionally, in the packaging module provided in the present application, a shielding layer can also be provided on the side of the packaging module.

[0029] In the second aspect, the embodiment of the present application further provides a base station, including a power amplifier board (a single board including a transceiver (TRX), an intermediate frequency, a power supply, etc.), a heat sink, and a packaging module as described in the first aspect or various embodiments of the first aspect, wherein the power amplifier board and the heat sink are respectively located on both sides of the packaging module. The power amplifier board is located on one side of the conductive layer of the packaging module, and the power amplifier board is electrically connected to the signal transmission pad in the conductive layer; the heat sink is located on one side of the substrate in the packaging module. Thus, an All in One Board (AIOB) architecture is realized, in which the power amplifier board is used to realize the transmission of all signals, and the heat sink is dedicated to heat dissipation to achieve optimal performance and heat dissipation effect.

[0030] Furthermore, in the base station, since interconnecting electrodes and a conductive layer are provided between the power amplifier board and the wiring layer, the interconnecting electrodes can increase the distance between the chip and the power amplifier board, so that the cavity height can be adjusted to avoid the problem of self-excitation of the power amplifier. Furthermore, since a grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by the grounding pad, thereby improving the signal interference problem between the chip and the power amplifier board. In addition, since only a signal transmission pad for providing input / output signals to the chip needs to be provided in the conductive layer, unlike the wiring layer where routing lines need to be provided, there is enough area for providing a grounding pad, and there is no need to additionally expand the area of ​​the conductive layer, so that a grounding pad can be provided in the conductive layer without increasing the occupied area of ​​the packaging module, thereby reducing the reflection angle.

[0031] Optionally, in the present application, the power amplifier board has a grounding pad on one side facing the packaging module, and the grounding pad in the conductive layer is welded to the grounding pad in the power amplifier board, thereby improving the reliability of double-sided welding and ensuring its reliability and safety in application.

[0032] In the present application, the power amplifier board and the packaging module can be welded by means of a land grid array (LGA) packaging method or a ball grid array (BGA) packaging method, which is not limited here.

[0033] In a third aspect, the present application further provides an electronic device, which includes a circuit board, a heat sink, and a packaging module as described in the first aspect or various embodiments of the first aspect, wherein the circuit board and the heat sink are respectively located on both sides of the packaging module. The circuit board is located on one side of the conductive layer of the packaging module, and the circuit board is electrically connected to the signal transmission pad in the conductive layer; the heat sink is located on one side of the substrate in the packaging module. Thus, the circuit board can be used to transmit all signals, and the heat sink is dedicated to heat dissipation to achieve optimal performance and heat dissipation effect.

[0034] In the electronic device, since interconnection electrodes and a conductive layer are provided between the circuit board and the wiring layer, the interconnection electrodes can increase the distance between the chip and the circuit board. Furthermore, since a grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by the grounding pad, thereby improving the signal interference problem between the chip and the circuit board. In addition, since only a signal transmission pad for providing input / output signals to the chip needs to be provided in the conductive layer, unlike the wiring layer where routing lines need to be provided, there is enough area for providing the grounding pad, and there is no need to additionally expand the area of ​​the conductive layer.

[0035] In specific implementation, the electronic equipment includes but is not limited to terminal devices such as smart phones, smart TVs, smart TV set-top boxes, PCs, wearable devices, smart broadband, etc.; telecommunications equipment such as wireless networks, fixed networks, servers, and electronic devices such as chip modules and memories.

[0036] Optionally, the circuit board has a grounding pad on one side facing the package module, and the grounding pad in the conductive layer is welded to the grounding pad in the circuit board, thereby improving the reliability of double-sided welding and ensuring its reliability and safety in application.

[0037] In the fourth aspect, an embodiment of the present application also provides a method for preparing a packaging module, which may include: first, forming a chip, a first plastic encapsulation layer for encapsulating the chip, and a wiring layer located on the side of the first plastic encapsulation layer away from the substrate in sequence on a substrate, and the wiring layer is electrically connected to the chip; then, forming an interconnection electrode electrically connected to the wiring layer on the side of the wiring layer away from the first plastic encapsulation layer; then, forming a second plastic encapsulation layer for encapsulating the interconnection electrode on the side of the wiring layer facing the interconnection electrode; finally, forming a conductive layer on the side of the second plastic encapsulation layer away from the wiring layer; wherein the conductive layer includes a grounding pad and a signal transmission pad electrically connected to the interconnection electrode.

[0038] Optionally, in the present application, after a conductive layer is formed on a side of the second plastic encapsulation layer away from the wiring layer, a shielding layer may also be formed on a side of the formed packaging module.

[0039] In a feasible implementation, a chip, a first plastic encapsulation layer for encapsulating the chip, and a wiring layer located on the side of the first plastic encapsulation layer away from the substrate are sequentially formed on a substrate, which may include: bonding the chip to the substrate; forming the first plastic encapsulation layer for encapsulating the chip; etching the first plastic encapsulation layer to form vias in areas corresponding to the chip; electroplating metal material in the vias; and forming a wiring layer on the first plastic encapsulation layer that is electrically connected to the metal material in the vias.

[0040] In another feasible implementation, a chip, a first plastic encapsulation layer for encapsulating the chip, and a wiring layer located on the side of the first plastic encapsulation layer away from the substrate are sequentially formed on a substrate, which can include: forming by the following methods: bonding the chip to the substrate; forming a plurality of metal balls in a stacked arrangement on the chip; forming a first plastic encapsulation layer for encapsulating the chip and the plurality of metal balls; and forming a wiring layer electrically connected to the plurality of metal balls on the first plastic encapsulation layer.

[0041] The present application does not limit the structure of the wiring layer. Exemplarily, taking the example of a wiring layer including two conductive layers, in the present application, the wiring layer can be formed in the following manner: a first conductive layer is formed on a first plastic encapsulation layer by electroplating, and then the first conductive layer is patterned, and a circuit wiring is formed in the first conductive layer. Then, an insulating dielectric layer covering the first conductive layer is formed, and dielectric perforations are etched in the insulating dielectric layer, and metal materials are electroplated in the dielectric perforations. Finally, a second conductive layer is formed on the insulating dielectric layer, and then the second conductive layer is patterned, and circuit wiring is formed in the second conductive layer, thereby forming a wiring layer having two conductive layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of a board-level structure of a power amplifier in the related art;

[0043] Figure 2 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of the structure of a packaging module provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of the structure of another packaging module provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the structure of another packaging module provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of the structure of another packaging module provided in an embodiment of the present application;

[0048] Figure 7A flowchart of a method for preparing a packaging module provided in an embodiment of the present application;

[0049] Figure 8a to Figure 8h A structural schematic diagram of a process for preparing a packaging module provided in an embodiment of the present application;

[0050] Figures 9a to 9i A structural schematic diagram of a preparation process of another packaging module provided in an embodiment of the present application;

[0051] Figures 10a to 10d A schematic structural diagram of a process for preparing a wiring layer in a packaging module provided in an embodiment of the present application;

[0052] Figures 11a to 11d A structural schematic diagram of a process for preparing a wiring layer in another packaging module provided in an embodiment of the present application;

[0053] Fig.12 A schematic diagram of the structure of a base station provided in an embodiment of the present application;

[0054] Fig.13 A schematic diagram of the structure of another base station provided in an embodiment of the present application;

[0055] Fig.14 A schematic diagram of the structure of another base station provided in an embodiment of the present application;

[0056] Fig.15 A schematic diagram of the structure of another base station provided in an embodiment of the present application;

[0057] Fig.16 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0058] Fig.17 A schematic diagram of the structure of another electronic device provided in an embodiment of the present application;

[0059] Fig.18 A schematic diagram of a 3D stacked packaging structure provided for a basic application embodiment.

[0060] Description of reference numerals:

[0061] 100 package module; 200 heat sink;

[0062] 300 Amplifier board; 400 Circuit board;

[0063] 120 interconnecting electrodes; 130 second plastic sealing layer;

[0064] 140 conductive layer; 150 shielding layer;

[0065] 111 substrate; 112 chip;

[0066] 113 first plastic packaging layer; 114 wiring layer;

[0067] 115 metal ball; 116 first via hole;

[0068] 117 second via hole; 141 ground pad of the conductive layer;

[0069] 142 signal transmission pad; 1121 active device;

[0070] 1122 passive components; 1141 conductive layer in wiring layer;

[0071] 1142 insulating dielectric layer; 1143 dielectric perforation;

[0072] 301 ground pad of the power amplifier board; 401 ground pad of the circuit board;

[0073] 1000 base stations; 2000 electronic devices. DETAILED DESCRIPTION

[0074] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0075] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0076] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The words expressing position and direction described in the present application are all explained using the accompanying drawings as examples, but changes may be made as needed, and all changes are included in the scope of protection of the present invention. The drawings of the present application are only used to illustrate relative positional relationships and do not represent true proportions. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0077] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0078] The solution described in the embodiments of the present application can be used in various communication systems, such as the fifth generation communication system and more possible communication systems that are subsequently evolved. The packaging module provided in the embodiments of the present application can be integrated in any network element device that needs to amplify the power of wireless signals, such as a base station. For example, taking a base station as an example, Figure 2 As shown, the base station includes a power amplifier board (a single board including a transceiver (TRX), an intermediate frequency, a power supply, etc.) 300, a heat sink 200 and a packaging module 100. The power amplifier board 300 and the heat sink 200 are respectively located on both sides of the packaging module 100, and the power amplifier board 300 is electrically connected to the packaging module 100, thereby realizing an All in One Board (AIOB) architecture. The power amplifier board 300 is used to transmit all signals, and the heat sink 200 is dedicated to heat dissipation to achieve optimal performance and heat dissipation effect.

[0079] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0080] See also Figure 3 and Figure 4 , Figure 3 The following is a schematic diagram showing the structure of a packaging module provided by an embodiment of the present application. Figure 4The schematic diagram of the structure of another packaging module provided by an embodiment of the present application is exemplarily shown. The packaging module 100 may include: a substrate 111, a chip 112, a first plastic encapsulation layer 113, a wiring layer 114, a plurality of interconnecting electrodes 120, a second plastic encapsulation layer 130 and a conductive layer 140. The chip 112 is located on the substrate 111, the first plastic encapsulation layer 113 is used to encapsulate the chip 112, the wiring layer 114 is located on the side of the first plastic encapsulation layer 113 away from the substrate 111, and the wiring layer 114 is electrically connected to the chip 112. Multiple interconnect electrodes 120 are located on the side of the wiring layer 114 away from the first plastic encapsulation layer 113 and are electrically connected to the wiring layer 114, so that they can be electrically connected to the chip 112 through the wiring layer 114; the second plastic encapsulation layer 130 is located on the side of the wiring layer 114 facing the interconnect electrodes 120 and is used to encapsulate the multiple interconnect electrodes 120; the conductive layer 140 is located on the side of the second plastic encapsulation layer 130 away from the wiring layer 114, wherein the conductive layer 140 includes a grounding pad 141 and a signal transmission pad 142 electrically connected to the multiple interconnect electrodes 120, and the signal transmission pad 142 is used to realize the transmission of chip input / output signals.

[0081] The above-mentioned packaging module provided by the embodiment of the present application, when the packaging module is interconnected with the power amplifier board, since interconnection electrodes and conductive layers are also provided on the wiring layer, and since the interconnection electrodes can increase the distance between the chip and the power amplifier board, the cavity height can be adjusted to be higher, thereby avoiding the problem of self-excitation of the power amplifier. In addition, since a grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by the grounding pad, thereby improving the signal interference problem between the chip and the power amplifier board. In addition, since only a signal transmission pad for providing input / output signals to the chip needs to be provided in the conductive layer, unlike the wiring layer where routing lines need to be provided, there can be enough area for providing grounding pads, and there is no need to additionally expand the area of ​​the conductive layer, so that the grounding pad can be provided in the conductive layer without increasing the occupied area of ​​the packaging module, thereby reducing the reflection angle.

[0082] The present application does not limit the function of the chip. For example, the chip may be a power amplifier chip, a radio frequency microwave millimeter wave chip, a processor chip, or an intellectual property core.

[0083] It should be noted that the chip in this application can be a bare die or a system-level chip. Among them, a bare die is a crystal grain before the chip is packaged. Each bare die is a chip with independent functions that has not been packaged. It can be composed of one or more circuits. A system-level chip is generally a product, an integrated circuit with a dedicated target, which contains all the contents of a complete system and embedded software.

[0084] In the present application, since interconnection electrodes and a conductive layer are also provided on the wiring layer electrically connected to the chip, the distance between the chip and the subsequently connected circuit board can be increased by using the interconnection electrodes. Furthermore, since a grounding pad is provided in the conductive layer, signal shielding can be achieved by using the grounding pad. In addition, since the grounding pad is provided in the conductive layer, it is not necessary to increase the area of ​​the wiring layer.

[0085] In the present application embodiment, Figure 4 As shown, the chip 112 may include at least one active device 1121 and / or at least one passive device 1122. For example, the chip 112 may include at least one active device 1121, or the chip 112 may include at least one passive device 1122, or the chip 112 may include at least one active device 1121 and at least one passive device 1122. Among them, active devices refer to electronic components that require power to realize their specific functions. For example, electron tubes, transistors, integrated circuits, etc. are generally used for signal amplification, conversion, etc., which are not limited here. Passive devices refer to electronic components that can realize their characteristics without the need for an external power supply, such as resistors, capacitors, inductors, converters, gradienters, matching networks, resonators, filters, mixers and switches, etc., which are not limited here. Figure 4 The example in which the chip 112 includes an active device 1121 and a passive device 1122 is used for illustration.

[0086] In the present application, the wiring layer is generally provided with chip pads electrically connected to the input / output pins of the chip and routing electrically connected to the chip, and the routing is generally used to connect the internal devices of the chip. The chip pads are electrically connected to the signal transmission pads through the interconnection electrodes. When the wiring layer is electrically connected to the outside world through the signal transmission pads in the conductive layer, the chip can realize the functions of the chip through the wiring layer.

[0087] In the present application, in order to avoid signal interference between the wiring layer and the power amplifier board, the orthographic projection of the grounding pad on the substrate at least covers part of the routing, that is, for the wiring layer, the grounding pad can shield the signal on the power amplifier board. For the power amplifier board, the grounding pad can shield the signal on the routing. Therefore, in the specific implementation, the larger the coverage area of ​​the grounding pad, the better the shielding effect.

[0088] Exemplarily, multiple chip pads in the wiring layer can be arranged around the routing, that is, the routing is arranged in the central area, and multiple chip pads are arranged in the edge area. Correspondingly, in the conductive layer, multiple signal transmission pads are also arranged around the ground pad.

[0089] It should be noted that the embodiments of the present application do not specifically limit the number, shape, material and other features of the signal transmission pads. For example, the number of signal transmission pads can be designed according to the chip pads in the wiring layer, the signal transmission pads can be round, square, or other shapes, and the conductive layer can be made of tin, copper or other metals with conductive properties.

[0090] In a specific implementation, the wiring layer may include one conductive layer or multiple (at least two) conductive layers. Figure 3 and Figure 4 When the wiring layer 114 includes multiple conductive layers 1141, an insulating dielectric layer 1142 is further provided between adjacent conductive layers 1141, and dielectric through-holes 1143 are provided in the insulating dielectric layer 1142, and adjacent conductive layers 1141 can be electrically connected through the dielectric through-holes 1143 in the insulating dielectric layer 1142. The conductive layer 1141 may include routing lines, and the chip pad is generally provided in the conductive layer closest to the interconnection electrode in the wiring layer.

[0091] Illustratively, in the present application, the conductive layer can be formed of materials such as gold, silver, aluminum, zinc, copper, chromium, nickel, palladium, etc., which are not limited here.

[0092] The present application does not limit the material of the insulating dielectric layer, and for example, it can be at least one of silicon oxide, silicon nitride, silicon oxynitride, resin material, etc.

[0093] Exemplarily, in order to ensure the consistency of materials between film layers, the material of the insulating dielectric layer may be the same as the material of the first plastic encapsulation layer or the second plastic encapsulation layer, which is not limited here.

[0094] In the present application, the materials of the first plastic encapsulation layer and the second plastic encapsulation layer may be the same, or may be different, which is not limited here.

[0095] Optionally, in the present application, the materials of the insulating dielectric layer, the first plastic encapsulation layer and the second plastic encapsulation layer are all the same.

[0096] It should be noted that the present application does not limit the method of electrical connection between the wiring layer and the chip, and it can be any method that can achieve electrical connection between the two.

[0097] In one possible implementation, Figure 5 As shown, in the present application, the wiring layer 114 can be electrically connected to the chip 112 through a plurality of metal balls 115 arranged in a stacked manner.

[0098] The present application does not limit the material of the metal ball. For example, the metal ball can be made of gold, silver, aluminum, zinc, copper, chromium, nickel, palladium and other materials.

[0099] In another possible implementation, Figure 6 As shown, in the present application, the wiring layer 114 may also be electrically connected to the chip 112 through a first via 116 penetrating the first plastic encapsulation layer 113 .

[0100] In a specific implementation, the conductive material in the first via hole 116 may be formed of gold, silver, copper, or other materials, which are not limited here.

[0101] In a specific implementation, the substrate can be formed by a copper-clad laminate. Of course, any structure with circuits such as a redistribution layer or a silicon interposer can also be used to replace the substrate, which is not limited here.

[0102] In specific implementation, Figure 5 and Figure 6 As shown, when it is necessary to electrically connect the wiring layer to the substrate, the wiring layer can be electrically connected to the substrate 111 through the second via hole 117 penetrating the first plastic encapsulation layer 113 .

[0103] In a specific implementation, the conductive material in the second via hole 117 may be formed of gold, silver, copper, or other materials, which are not limited here.

[0104] In specific implementation, the present application does not limit the specific form of the interconnection electrode. Exemplarily, the interconnection electrode can be formed by a metal column or a metal wire.

[0105] The present application does not limit the material of the interconnection pillar, for example, it can be Cu, Ni, Mo, W, tungsten alloy, Cu-Mo alloy, nickel alloy, etc.

[0106] Continue to see Figure 5 and Figure 6 In order to prevent the impact of external signals on the packaging module, optionally, a shielding layer 150 can be set on the side of the packaging module.

[0107] See also Figure 7 , Figure 7 The present invention exemplifies a method for preparing a packaging module, which may include the following steps:

[0108] Step S101: forming a chip, a first plastic encapsulation layer for encapsulating the chip, and a wiring layer located on a side of the first plastic encapsulation layer away from the substrate in sequence on a substrate, wherein the wiring layer is electrically connected to the chip.

[0109] The present application does not limit the packaging structure of the chip, for example, panel level packaging (PLP), chip embedded packaging, etc. can be used. In a feasible implementation,

[0110] Taking the chip using PLP as an example, the chip can be packaged in the following ways:

[0111] like Figure 8a As shown, a chip 112 is bonded on the substrate 111 .

[0112] In a specific implementation, the chip can be bonded to the substrate through a chip bonding process.

[0113] like Figure 8b As shown, a first plastic encapsulation layer 113 of the plastic encapsulated chip 112 is formed.

[0114] like Figure 8c As shown, the first plastic encapsulation layer 113 is etched to form a first via hole 116 in a region corresponding to the chip 112 .

[0115] Optionally, when it is necessary to electrically connect the substrate to a subsequently formed wiring layer, the second via hole 117 may be further formed when the first via hole 116 is formed.

[0116] like Figure 8d As shown, a conductive material is formed in the first via hole 116 .

[0117] Optionally, when the first plastic encapsulation layer 113 has the second via hole 117 , when forming the conductive material in the first via hole 116 , it is also necessary to form the conductive material in the second via hole 117 .

[0118] Optionally, the conductive material may be a metal material, and the metal material may be electroplated in the via hole by electroplating.

[0119] like Figure 8e As shown, a wiring layer 114 electrically connected to the conductive material in the via hole is formed on the first plastic packaging layer 113 .

[0120] Taking the chip using embedded chip packaging as an example, the chip can be packaged in the following ways:

[0121] like Figure 9a As shown, a chip 112 is bonded on the substrate 111 .

[0122] In a specific implementation, the chip can be bonded to the substrate through a chip bonding process.

[0123] like Figure 9b As shown, a plurality of metal balls 115 are formed on the chip 112 in a stacked manner.

[0124] like Fig.9c As shown, a first plastic encapsulation layer 113 is formed to encapsulate a chip 112 and a plurality of metal balls 115 .

[0125] In a specific implementation, a plurality of metal balls may be encapsulated with a plastic encapsulation material, and then the plastic encapsulation material is ground until the upper surfaces of the plurality of metal balls are exposed, thereby forming a first plastic encapsulation layer.

[0126] Optionally, when it is necessary to electrically connect the substrate to a subsequently formed wiring layer, such as Figure 9d As shown, the first plastic encapsulation layer 113 needs to be etched to form a second via hole 117. Fig.9e As shown, a conductive material is formed in the second via hole 117 .

[0127] Optionally, the conductive material may be a metal material, and the metal material may be electroplated in the via hole by electroplating.

[0128] like Figure 9f As shown, a wiring layer 114 electrically connected to a plurality of metal balls 115 is formed on the first plastic packaging layer 113 .

[0129] The present application does not limit the structure of the wiring layer. For example, taking the wiring layer including two conductive layers as an example, in the present application, the wiring layer 114 can be formed in the following manner:

[0130] like Fig.10a and Fig.11a As shown, a first conductive layer 1141 is formed on the first plastic packaging layer 113 by electroplating, and then the first conductive layer 1141 is patterned to form circuit wiring in the first conductive layer 1141. The circuit wiring is generally provided with routing lines.

[0131] like Fig.10b and Fig.11b As shown, an insulating dielectric layer 1142 is formed to cover the first conductive layer 1141 .

[0132] Exemplarily, the insulating dielectric layer 1142 may be formed of the same material as the first plastic packaging layer, which is not limited herein.

[0133] like Fig.10c and Fig.11c As shown, a dielectric through hole 1143 is etched in the insulating dielectric layer 1142 .

[0134] like Fig.10d and Fig.11d As shown, metal material is electroplated in the dielectric through-hole 1143 .

[0135] In a specific implementation, the metal material in the dielectric through-hole may be the same as the material of the conductive layer, which is not limited here.

[0136] like Figure 8e and Figure 9f As shown, a second conductive layer 1141 is formed on the insulating dielectric layer 1142 , and then the second conductive layer 1141 is patterned to form circuit wiring in the second conductive layer 1141 , thereby forming a wiring layer 114 having two conductive layers 1141 .

[0137] The circuit wiring of the second conductive layer 1141 is generally provided with routing lines and chip pads. The chip pads can be electrically connected to the input / output pins of the chip 112 through the first conductive layer 1141.

[0138] The embodiment of the present application is illustrated by taking the wiring layer 114 having two conductive layers 1141 as an example. Of course, in a specific implementation, the wiring layer may also have one conductive layer 1141, three conductive layers 1141, or more conductive layers 1141, which is not limited here.

[0139] In the embodiment of the present application, the following steps are required after the chip is packaged for the first time:

[0140] Step S102: Figure 8f and Figure 9g As shown, a plurality of interconnect electrodes 120 electrically connected to the wiring layer 114 are formed on a side of the wiring layer 114 away from the first plastic encapsulation layer 113 .

[0141] In a specific implementation, the interconnection electrodes may be formed by metal pillars or metal wires, which are not limited herein.

[0142] For example, an implantation process may be used to implant metal pillars or metal wires on the chip pads.

[0143] Step S103: Figure 8g and Figure 9h As shown, a second plastic encapsulation layer 130 for plastic encapsulating the plurality of interconnection electrodes 120 is formed on the side of the wiring layer 114 facing the interconnection electrodes 120 .

[0144] In a specific implementation, a plurality of interconnected electrodes may be encapsulated with a plastic encapsulation material, and then the plastic encapsulation material is ground until the top ends of the plurality of interconnected electrodes are exposed, thereby forming a second plastic encapsulation layer.

[0145] Step S104: Figure 8h and Figure 9i As shown, a conductive layer 140 is formed on the side of the second plastic encapsulation layer 130 away from the wiring layer 114 ; wherein the conductive layer 140 includes a ground pad 141 and a signal transmission pad 142 electrically connected to the interconnection electrode.

[0146] Optionally, in this application, after step S104, as Figure 5 and Figure 6 As shown, the method may further include step S105, forming a shielding layer 150 on the side of the formed packaging module. For example, the shielding layer 130 may be formed by sputtering or electroplating, which is not limited here.

[0147] The packaging module provided in the embodiment of the present application can fan out the signal from one side of the conductive layer to realize signal interconnection with the circuit board, and the ground pad of the chip can fan out from the substrate side and connect to the heat sink to realize efficient heat dissipation. Therefore, the packaging module can be applied to the field of radio frequency chips, miniaturized digital chips or high-power chips with heat dissipation requirements.

[0148] Based on this, an embodiment of the present application provides a base station, such as Fig.12 and Fig.13 As shown, the base station 1000 includes a power amplifier board (including a single board of transceiver, intermediate frequency, power supply, etc.) 300, a heat sink 200 and any one of the packaging modules 100 provided in the above embodiments of the present application, and the power amplifier board 300 and the heat sink 200 are respectively located on both sides of the packaging module 100. The power amplifier board 300 is located on one side of the conductive layer of the packaging module 100, and the power amplifier board 300 is electrically connected to the signal transmission pad 142 in the conductive layer 140; the heat sink 200 is located on one side of the substrate 111 in the packaging module 100. Thus, a power amplifier board-one-board architecture is realized, and the power amplifier board 300 is used to realize the transmission of all signals, and the heat sink 200 is dedicated to heat dissipation to achieve the best performance and heat dissipation effect.

[0149] Furthermore, in the base station, since interconnecting electrodes and a conductive layer are provided between the power amplifier board and the wiring layer, the interconnecting electrodes can increase the distance between the chip and the power amplifier board, so that the cavity height can be adjusted to avoid the problem of self-excitation of the power amplifier. Furthermore, since a grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by the grounding pad, thereby improving the signal interference problem between the chip and the power amplifier board. In addition, since only a signal transmission pad for providing input / output signals to the chip needs to be provided in the conductive layer, unlike the wiring layer where routing lines need to be provided, there is enough area for providing a grounding pad, and there is no need to additionally expand the area of ​​the conductive layer, so that a grounding pad can be provided in the conductive layer without increasing the occupied area of ​​the packaging module, thereby reducing the reflection angle.

[0150] Optionally, in this application, if Fig.14 and Fig.15 As shown, the power amplifier board 300 has a grounding pad 301 on the side facing the package module 100, and the grounding pad 141 in the conductive layer 140 is welded to the grounding pad 301 in the power amplifier board 300. This can improve the reliability of double-sided welding and ensure its reliability and safety in application.

[0151] In the present application, the power amplifier board 300 and the packaging module 100 are welded by means of a grid array packaging method or a ball grid array packaging method, which is not limited here.

[0152] Accordingly, see Fig.16 and Fig.17The present application also provides an electronic device 2000, which includes: a circuit board 400, a heat sink 200 and any one of the packaging modules 100 provided in the embodiments of the present application, wherein the circuit board 400 and the heat sink 200 are respectively located on both sides of the packaging module 100. The circuit board 400 is located on one side of the conductive layer 140 of the packaging module 100, and the circuit board 400 is electrically connected to the signal transmission pad 142 in the conductive layer 140; the heat sink 200 is located on one side of the substrate 111 in the packaging module 100. Thus, the circuit board 400 is used to transmit all signals, and the heat sink 200 is used exclusively for heat dissipation to achieve optimal performance and heat dissipation effect.

[0153] In the electronic device, since interconnection electrodes and a conductive layer are provided between the circuit board and the wiring layer, the interconnection electrodes can increase the distance between the chip and the circuit board. Furthermore, since a grounding pad is provided in the conductive layer, the radio frequency signal on the wiring layer can be shielded by the grounding pad, thereby improving the signal interference problem between the chip and the circuit board. In addition, since only a signal transmission pad for providing input / output signals to the chip needs to be provided in the conductive layer, unlike the wiring layer where routing lines need to be provided, there is enough area for providing the grounding pad, and there is no need to additionally expand the area of ​​the conductive layer.

[0154] In specific implementation, the electronic equipment includes but is not limited to terminal devices such as smart phones, smart TVs, smart TV set-top boxes, PCs, wearable devices, smart broadband, etc.; telecommunications equipment such as wireless networks, fixed networks, servers, and electronic devices such as chip modules and memories.

[0155] Optionally, continue to see Fig.16 and Fig.17 The circuit board 400 has a grounding pad 401 on the side facing the package module 100, and the grounding pad 141 in the conductive layer 140 is welded to the grounding pad 401 in the circuit board 400. This can improve the reliability of double-sided welding and ensure its reliability and safety in application.

[0156] Of course, in specific implementation, the above-mentioned packaging module provided in the embodiment of the present application can also be applied to a 3D stacked packaging structure, and the packaging module provided in the embodiment of the present application can be stacked with chips of other packaging structures. Of course, at least two packaging modules provided in the embodiment of the present application can also be stacked, for example Fig.18 As shown, when the packaging modules 100 are stacked, adjacent packaging modules 100 may be opposite to each other on the conductive layer 140 side, or on the substrate 111 side. Of course, the substrate 111 side and the conductive layer 140 side may also be opposite to each other. This is not limited here and can be designed according to the actual product.

[0157] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A packaging module, characterized in that: include: substrate; a chip located on the substrate; A first plastic sealing layer for plastic sealing the chip; A wiring layer located on a side of the first plastic encapsulation layer away from the substrate, and the wiring layer is electrically connected to the chip; A plurality of interconnect electrodes located at a side of the wiring layer away from the first plastic packaging layer and electrically connected to the wiring layer; A second plastic sealing layer located at a side of the wiring layer facing the plurality of interconnect electrodes and used for plastic sealing the plurality of interconnect electrodes; A conductive layer is located on a side of the second plastic packaging layer away from the wiring layer, wherein the conductive layer includes a ground pad and a plurality of signal transmission pads electrically connected to the plurality of interconnect electrodes.

2. The packaging module according to claim 1, wherein: The interconnection electrode includes a metal column.

3. The packaging module according to claim 1 or 2, characterized in that: The wiring layer includes a plurality of chip pads electrically connected to the input / output pins of the chip and routing lines electrically connected to the chip; In the conductive layer, the plurality of signal transmission pads are electrically connected to the plurality of chip pads, and the orthographic projection of the ground pad on the substrate at least covers a portion of the routing line.

4. The packaging module according to claim 3, characterized in that: The wiring layer includes one conductive layer or multiple conductive layers; When the wiring layer includes the multiple conductive layers, the wiring layer further includes an insulating dielectric layer located between adjacent conductive layers, and the adjacent conductive layers are electrically connected via dielectric through-holes in the insulating dielectric layer.

5. The packaging module according to any one of claims 1 or 2, characterized in that: The wiring layer is electrically connected to the chip through a plurality of metal balls arranged in a stacked manner.

6. The packaging module according to any one of claims 1 or 2, characterized in that: The wiring layer is electrically connected to the chip through a via hole penetrating the first plastic packaging layer.

7. The packaging module according to any one of claims 1 or 2, characterized in that: The chip is a bare chip or a system-on-chip.

8. The packaging module according to any one of claims 1 or 2, characterized in that: It also includes a shielding layer located on the side of the packaging module.

9. A base station, characterized in that: include: A power amplifier board, a heat sink and a packaging module as claimed in any one of claims 1 to 8; The power amplifier board is located on one side of the conductive layer of the packaging module, and the power amplifier board is electrically connected to the signal transmission pad in the conductive layer; The heat sink is located at one side of the substrate in the packaging module.

10. The base station according to claim 9, characterized in that The power amplifier board has a grounding pad on one side facing the packaging module, and the grounding pad in the conductive layer is welded to the grounding pad in the power amplifier board.

11. An electronic device, characterized in that: include: A circuit board, a heat sink, and a packaging module as claimed in any one of claims 1 to 8; The circuit board is located on one side of the conductive layer of the packaging module, and the circuit board is electrically connected to the signal transmission pad in the conductive layer; The heat sink is located at one side of the substrate in the packaging module.

12. The electronic device according to claim 11, characterized in that: The circuit board has a grounding pad on one side facing the packaging module, and the grounding pad in the conductive layer is welded to the grounding pad in the circuit board.

13. A method for preparing a packaging module, characterized in that: include: A chip, a first plastic encapsulation layer for encapsulating the chip, and a wiring layer located on a side of the first plastic encapsulation layer away from the substrate are sequentially formed on a substrate, and the wiring layer is electrically connected to the chip; forming an interconnection electrode electrically connected to the wiring layer on a side of the wiring layer away from the first plastic encapsulation layer; forming a second plastic sealing layer for plastic sealing the interconnection electrode on a side of the wiring layer facing the interconnection electrode; A conductive layer is formed on a side of the second plastic packaging layer away from the wiring layer; wherein the conductive layer includes a ground pad and a signal transmission pad electrically connected to the interconnect electrode.

14. The preparation method according to claim 13, characterized in that: After forming a conductive layer on a side of the second plastic packaging layer away from the wiring layer, the method further includes: forming a shielding layer on a side of the packaging module.

15. The preparation method according to claim 13 or 14, characterized in that: The method of sequentially forming a chip, a first plastic encapsulation layer for encapsulating the chip, and a wiring layer located on a side of the first plastic encapsulation layer away from the substrate on a substrate includes: Bonding the chip on the substrate; Forming a first plastic encapsulation layer for plastic encapsulating the chip; Etching the first plastic packaging layer to form a via hole in a region corresponding to the chip; electroplating a metal material in the via hole; A wiring layer electrically connected to the metal material in the via hole is formed on the first plastic packaging layer.

16. The preparation method according to claim 13 or 14, characterized in that: The method of sequentially forming a chip, a first plastic encapsulation layer for encapsulating the chip, and a wiring layer located on a side of the first plastic encapsulation layer away from the substrate on a substrate includes: Bonding the chip on the substrate; forming a plurality of metal balls arranged in a stacked manner on the chip; Forming a first plastic encapsulation layer for encapsulating the chip and the plurality of metal balls; A wiring layer electrically connected to the plurality of metal balls is formed on the first plastic packaging layer.

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