Connector connectivity detection system

Abstract

The present invention relates to a connector connectivity detection system, comprising multiple connectors arranged in a preset topology. The connectors may be independently arranged or formed into a connector pair with another connector. The connector pairs are connected by cables, and a preset signal line in each cable is set as the signal line corresponding to a detection channel. Each connector is provided with a detection device, which includes a drive circuit, a receiving circuit, a pull-up resistor, and VCCIO. One end of the pull-up resistor is connected to VCCIO, and the other end is connected to the drive circuit and the receiving circuit. The present invention improves the efficiency and accuracy of connector connectivity detection in a hardware simulation platform.

Description

Technical Field

[0001] The present invention relates to the technical field of connector connectivity detection, and in particular to a connector connectivity detection system. Background Art

[0002] Existing hardware simulation platforms, such as large-scale hardware emulators or prototype verification platforms, typically use numerous cables to connect multiple connectors on multiple hardware motherboards. To detect whether a large-scale hardware emulator or prototype verification platform is connected according to a preset topology, existing technologies often require complex detection methods to establish the existing cable connection topology, resulting in low detection efficiency and uncertainty about detection accuracy. Therefore, improving the efficiency and accuracy of connector connectivity detection in hardware simulation platforms has become a pressing technical issue. Summary of the Invention

[0003] The present invention aims to provide a connector connectivity detection system, which improves the efficiency and accuracy of connector connectivity detection in a hardware simulation platform.

[0004] According to one aspect of the present invention, a connector connectivity detection system is provided, comprising a plurality of connectors arranged in a preset topology, wherein the connectors are arranged independently or form a connector pair with another connector, the connector pairs being connected by cables, and a preset signal line in each cable being set as a signal line corresponding to a detection channel;

[0005] A detection device is arranged in each of the connectors, the detection device including a driving circuit, a receiving circuit, a pull-up resistor, and VCCIO, one end of the pull-up resistor is connected to VCCIO, and the other end is connected to the driving circuit and the receiving circuit;

[0006] The driving circuit includes a first storage unit, a sending unit, and an output driver, wherein one end of the sending unit is connected to the first storage unit, and the other end is connected to the enable end of the output driver, the input end of the output driver is grounded, and the output end of the output driver is connected to the pull-up resistor;

[0007] The receiving circuit includes an input driver, a receiving unit and a second storage unit, one end of the receiving unit is connected to the second storage unit, and the other end is connected to the output end of the input driver, and the input end of the input driver is connected to the pull-up resistor;

[0008] The path formed by the VCCIO, the pull-up resistor and the receiving unit constitutes the detection channel.

[0009] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the connector connectivity detection system provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value. It has at least the following advantages:

[0010] The present invention realizes the circuit structure of connector connectivity detection, has the advantages of simple structure, low cost, high reliability and short detection process time, thereby improving the efficiency and accuracy of connector connectivity detection in a hardware simulation platform.

[0011] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, which can be implemented in accordance with the contents of the specification, and to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites preferred embodiments and describes them in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of an independently configured connector according to an embodiment of the present invention;

[0013] Figure 2 A schematic diagram of a connector pair having a connection relationship provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] To further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following, in conjunction with the accompanying drawings and preferred embodiments, describes in detail the specific implementation and effects of a connector connectivity detection system proposed in accordance with the present invention.

[0015] The embodiment of the present invention provides a connector connectivity detection system, comprising a plurality of connectors arranged according to a preset topological structure, wherein the connectors are independently arranged, such as Figure 1 As shown, or with another connector to form a connector pair, such as Figure 2 The connector pairs are connected by cables, and a preset signal line in each cable is set as the signal line corresponding to the detection channel. It should be noted that a cable includes multiple signal lines, and in the present invention, the same signal line can be selected as the signal line corresponding to the detection channel.

[0016] like Figure 1 or Figure 2 In the example shown, a detection device is arranged in each connector, and the detection device includes a driving circuit, a receiving circuit, a pull-up resistor 4 and VCCIO. One end of the pull-up resistor 4 is connected to VCCIO, and the other end is connected to the driving circuit and the receiving circuit. It should be noted that Figure 2In this example, the pull-up resistor 4 and VCCIO for two connected connectors are simplified into one. It's understandable that each connector actually has a corresponding set of pull-up resistors 4 and VCCIO, but each set of pull-up resistors 4 and VCCIO are identical. VCCIO refers to the VccIO IO voltage, which is the voltage applied to the FPGA's IO module (the same as the IO pin). This voltage should match the voltage of other devices connected to the FPGA.

[0017] like Figure 1 or Figure 2 In the example shown, the driving circuit includes a first storage unit 1, a sending unit 2, and an output driver 3. One end of the sending unit 2 is connected to the first storage unit 1, and the other end is connected to the enable end of the output driver 3. The input end of the output driver 3 is grounded, and the output end of the output driver 3 is connected to the pull-up resistor 4.

[0018] like Figure 1 or Figure 2 In the example shown, the receiving circuit includes an input driver 5, a receiving unit 6, and a second storage unit 7. One end of the receiving unit 6 is connected to the second storage unit 7, and the other end is connected to the output end of the input driver 5. The input end of the input driver 5 is connected to the pull-up resistor 4. The path formed by the VCCIO, the pull-up resistor 4, and the receiving unit 6 constitutes the detection channel.

[0019] As an embodiment, the system sends a clock signal 9 to the detection devices of all connectors. Before starting the detection, the system first sends a reset signal 10 to the detection devices, resets the second storage units 7 of all connectors based on the reset signal 10, and then sends a global detection enable signal 11 to the detection devices of all connectors to synchronously turn on the detection devices of all connectors. Then, the detection devices of all connectors enter the connector connectivity detection process.

[0020] As an embodiment, the detection frequency of the detection device is configured as a preset frequency, which is the minimum value of the target detection frequencies corresponding to all connectors. The target detection frequency is inversely proportional to the cable length corresponding to the connector, thereby meeting the detection requirements of all connectors.

[0021] As an embodiment, the first storage unit 1 is used to store a connector identifier, and the connector identifier is an M-bit sequence composed of 0 and 1, where M is a positive integer greater than or equal to 2. It should be noted that each connector has a unique connector identifier, which can be generated based on the board ID, FPGA ID and connector ID, and then written into the first storage unit 1 by hardware or software. The first storage unit 1 can be set as an M-bit register. The sending unit 2 reads the connector identification bit information bit by bit by parallel-serial conversion. The parallel-serial conversion specifically shifts the M-bit sequence stored in the first storage unit 1 left or right to a one-bit output port and reads it bit by bit. It should be noted that if it is determined to be a left shift, all connectors in the system will read the M-bit sequence by shifting in the left-shift manner. If it is determined to be a right shift, all connectors in the system will read the M-bit sequence by shifting in the right-shift manner. When the read identification bit information is 0, a low-level drive signal is sent to the output driver 3, and the output driver 3 is turned off. At this time, the output driver 3 will not drive the level change of the detection path; when the read identification bit information is 1, a high-level drive signal is sent to the output driver 3, and the output driver 3 sends high and low level drive signals to the detection path to drive the detection path to a low level.

[0022] As an example, Figure 1 As shown in the independent arrangement of the connector, the detection path can only be affected by one output driver 3, that is, when the output driver 3 is turned off, the detection path is at a high level, and when the output driver 3 outputs a high-level driving signal, the detection path is driven to a low level. Figure 2 In the connector pair shown, the detection circuit is always simultaneously driven by both output drivers 3. The detection path is initially high. When receiving a high-level drive signal from one output driver 3 or receiving two high-level drive signals simultaneously, the detection path is driven low. When both output drivers 3 are off, the detection path is high.

[0023] As an embodiment, the receiving unit 6 obtains the signal level of the detection path through the input driver 5, and after inversion, stores it in the second storage unit 7 via serial-to-parallel conversion. Serial-to-parallel conversion means that the newly input bit value of the second storage unit 7 becomes the lowest bit of the original data, and the highest bit of the original data is discarded. The number of storage bits of the second storage unit 7 is the same as the number of storage bits of the first storage unit 1, and can be specifically implemented by setting an M-bit register. The second storage unit 7 also includes a loop counter, and the maximum number of times recorded by the loop counter is the same as the number of bits of the second storage unit 7. For example, if the number of storage bits of the first storage unit 1 is M = 4, then the maximum number of times recorded by the loop counter is 4, and the recorded value can be set to 0-3.

[0024] As an embodiment, the detection process of the system includes a first detection stage and a second detection stage. The first detection stage is the stage from the start of detection to the completion of the first round of counting by the cycle counters in all connectors. The second detection stage is the stage from the end of the first detection stage to the completion of the first round of counting by all the opened cycle counters in all connectors. It should be noted that, in the first detection stage, the cycle counters of all connectors are all turned on. In the second detection stage, the second storage unit 7 corresponding to the connector whose sending unit 2 is stopped in the first detection stage is turned off, and the corresponding cycle counter no longer works in the second detection stage.

[0025] As an embodiment, the sending unit 2 and the receiving unit 6 are connected via an information transmission channel, and a status recording unit 8 is further provided between the sending unit 2 and the receiving unit 6. The status recording unit 8 is used to store a status identifier. In the first detection phase, the receiving unit 6 directly obtains the level of the detection path and obtains the driving signal level via the information transmission channel. The receiving unit 6 inverts the signal level of the detection path and compares it with the driving signal level. If they are consistent, the status identifier is set to an on identifier. If the sending unit 2 reads an on identifier from the status recording unit 8, the operation of reading the identifier bit information is continued. If they are inconsistent, the identifier stored in the status recording unit 8 is set to a stop identifier. If the sending unit 2 reads a stop identifier from the status recording unit 8, the operation of reading the identifier bit information is stopped.

[0026] As an embodiment, in the second detection phase: the status identifier in the status recording unit 8 corresponding to the sending unit 2 that was stopped in the first detection phase is set to a start identifier, the sending unit 2 restarts the reading of the identification bit information operation, and the corresponding second storage unit 7 is closed. It should be noted that the sending unit 2 restarts the reading of the identification bit information operation, which means that the connector identification sequence is read from the first position determined by the preset shift direction until the entire sequence is read; the corresponding second storage unit 7 is closed, and the closed second storage unit 7 maintains the storage result of the first detection phase unchanged, and the corresponding loop counter is also in the closed state during this phase. The status identifier in the status recording unit 8 corresponding to the sending unit 2 that was not stopped in the second detection phase is set to a stop identifier, and the reading of the identification bit information operation is stopped.

[0027] As an embodiment, the system also includes a detection module for reading the identification sequence in the first storage unit 1 and the identification sequence in the second storage unit 7 in each connector after the second detection phase, and comparing them with the preset topology structure information to perform connectivity detection on all connectors.

[0028] It should be noted that if the connection is normal, then after the first detection phase is completed, Figure 1 The identification sequence stored in the second storage unit 7 of the connector separately provided in the embodiment is the connector identification of the connector itself. Figure 2 In the two interconnected connectors, the second storage unit 7 of the connector at the end where the sending unit 2 is stopped in the first detection phase stores the identifier of the opposite connector, that is, the identifier of the connector at the end where the sending unit 2 is not stopped. In the second storage unit 7 at the end where the sending unit 2 is not stopped in the first detection phase, the identifier of the connector itself is stored. After the second detection phase is completed, Figure 1 The identification sequence stored in the second storage unit 7 of the connector separately provided in the embodiment is still the connector identification of the connector itself. Figure 2 In the case of two interconnected connectors, the second storage unit 7 of the connector at the end where the sending unit 2 is stopped during the first detection phase stores the identifier of the opposite connector, i.e., the identifier of the connector at the end where the sending unit 2 is not stopped during the first detection phase. The second storage unit 7 of the connector at the end where the sending unit 2 is not stopped during the first detection phase also stores the identifier of the opposite connector, i.e., the identifier of the connector at the end where the sending unit 2 is stopped during the first detection phase. The detection module reads the identifier sequence in the first storage unit 1 and the identifier sequence in the second storage unit 7 of each of all connectors and compares them with the preset topology information. If the result matches the result obtained under the above-mentioned normal connection condition, the connection is correct. If the result does not match the result obtained under the above-mentioned normal connection condition, the connection is abnormal.

[0029] The system described in the embodiment of the present invention realizes connector connectivity detection with a simple circuit structure, low cost, high reliability, and a short detection process time, thereby improving the efficiency and accuracy of connector connectivity detection in a hardware simulation platform.

[0030] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A connector connectivity detection system, characterized in that: The device comprises a plurality of connectors arranged in a preset topological structure, wherein the connectors are arranged independently or form a connector pair with another connector, wherein the connector pairs are connected by cables, and a preset signal line in each cable is set as a signal line corresponding to the detection path; A detection device is arranged in each of the connectors, the detection device including a driving circuit, a receiving circuit, a pull-up resistor, and VCCIO, one end of the pull-up resistor is connected to VCCIO, and the other end is connected to the driving circuit and the receiving circuit; The driving circuit includes a first storage unit, a sending unit, and an output driver, wherein one end of the sending unit is connected to the first storage unit, and the other end is connected to the enable end of the output driver, the input end of the output driver is grounded, and the output end of the output driver is connected to the pull-up resistor; The receiving circuit includes an input driver, a receiving unit and a second storage unit, one end of the receiving unit is connected to the second storage unit, and the other end is connected to the output end of the input driver, and the input end of the input driver is connected to the pull-up resistor; The path formed by the VCCIO, the pull-up resistor and the receiving unit constitutes the detection path; The initial level of the detection path is a high level; For an independently provided connector, when the output driver is turned off, the detection path is at a high level, and when the output driver outputs a high-level driving signal, the detection path is driven to a low level; For the connector pair, when one output driver receives a high-level driving signal or two high-level driving signals are received simultaneously, the detection path is driven to a low level; when both output drivers are turned off, the detection path is driven to a high level.

2. The system according to claim 1, wherein: The first storage unit is used to store a connector identifier, which is an M-bit sequence consisting of 0s and 1s. The sending unit reads the connector identifier bit information bit by bit using a parallel-to-serial conversion method. When the read identifier bit information is 0, a low-level drive signal is sent to the output driver, and the output driver is turned off; when the read identifier bit information is 1, a high-level drive signal is sent to the output driver, and the output driver sends a high-level drive signal to the detection path to drive the detection path to a low level.

3. The system according to claim 2, characterized in that The receiving unit obtains the signal level of the detection path through the input driver, and stores it in the second storage unit in a serial-to-parallel conversion manner after inversion. The storage bit number of the second storage unit is the same as that of the first storage unit.

4. The system according to claim 3, characterized in that The second storage unit further includes a loop counter, wherein the maximum number of times recorded by the loop counter is the same as the number of bits of the second storage unit.

5. The system according to claim 4, characterized in that The detection process of the system includes a first detection stage and a second detection stage. The first detection phase is from the start of detection to the completion of the first round of counting by the cycle counters in all connectors, and the second detection phase is from the end of the first detection phase to the completion of the first round of counting by all enabled cycle counters in all connectors.

6. The system according to claim 5, characterized in that The sending unit and the receiving unit are connected via an information transmission channel. A status recording unit is further provided between the sending unit and the receiving unit, and the status recording unit is used to store a status identifier; In the first detection phase, the receiving unit directly obtains the level of the detection path and obtains the driving signal level through the information transmission channel. The receiving unit inverts the signal level of the detection path and compares it with the driving signal level: If they are consistent, the state flag is set to the open flag, and the sending unit reads the open flag in the state recording unit, and then continues to perform the read flag information operation; If they are inconsistent, the flag stored in the status recording unit is set to a stop flag, and the sending unit stops executing the read flag information operation if the flag stored in the status recording unit is a stop flag.

7. The system according to claim 6, characterized in that In the second detection phase: Setting the status flag in the status recording unit corresponding to the sending unit that was stopped in the first detection phase as a start flag, the sending unit restarts the reading of the flag bit information operation, and closes the corresponding second storage unit; The state flag in the state recording unit corresponding to the sending unit that is not stopped in the second detection phase is set as a stop flag, and the operation of reading the flag bit information is stopped.

8. The system according to claim 5, wherein: The system further includes a detection module for reading the identification sequence in the first storage unit and the identification sequence in the second storage unit of each connector after the second detection phase is completed, and comparing the identification sequence with the preset topology information to perform connectivity detection on all connectors.

9. The system according to claim 1, wherein: The system sends a clock signal to the detection devices of all connectors. Before starting detection, it first sends a reset signal to the detection devices, resets the second storage units of all connectors based on the reset signal, and then sends a global detection enable signal to the detection devices of all connectors to synchronously turn on the detection devices of all connectors.

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