Low-pollution cache prefetching system and method based on instruction stream mixed mode learning

Abstract

The present invention provides a low-pollution cache prefetch system based on instruction stream mixed mode learning, including a branch prediction module, which predicts the instruction stream and writes it into an instruction fetch address queue; a memory access instruction recording module, which records the information of the submitted memory access instruction and writes it into the memory access instruction buffer; and simultaneously obtains the memory access instruction sequence by querying; a memory access mode learning module, which records the memory access instruction sequence in its memory access history buffer for learning, predicts the memory access physical address of the memory access instruction and writes it into the memory access address queue; a prefetch request generation module, which retrieves the instruction fetch address queue and the memory access address queue, and generates a prefetch request for the first-level cache; and a prefetch request write-back module, which temporarily stores the prefetch request for obtaining data, and waits for write-back or writes back immediately according to the instruction submission situation. The present invention also provides a corresponding method. The low-pollution cache prefetch system of the present invention reduces the uncertainty faced in the memory access sequence prediction process and improves the accuracy of prefetch address prediction.

Description

Technical Field

[0001] The present invention relates to the technical field of computer architecture, and in particular to a low-pollution cache prefetching system and method based on instruction stream hybrid mode learning. Background Art

[0002] Cache is an important mechanism in modern processors. It copies frequently used data from memory to cache. Subsequent data access can be directly read from cache, thereby reducing the number of accesses to slow DRAM memory and improving processor performance. The capacity of cache is limited, and cache failure is inevitable in actual use. Cache prefetching technology predicts the data that the program will use and reads this data into cache in advance, reducing the number of cache failures.

[0003] Cache access behavior is complex, and the memory access sequence received by the cache system in the processor will be disturbed by the processor's out-of-order execution. At the same time, memory access instructions of different modes will be intertwined with each other, further increasing the difficulty of predicting memory access behavior in the cache system. Existing cache prefetching methods cannot effectively solve the problem of difficulty in predicting future memory access sequences. Summary of the invention

[0004] The object of the present invention is to provide a low-pollution cache prefetch system and method based on instruction stream hybrid mode learning, so as to reduce the uncertainty faced in the memory access sequence prediction process and improve the accuracy of prefetch address prediction.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a low-pollution cache prefetch system based on instruction stream mixed mode learning, including a main pipeline and a branch prediction sub-pipeline, wherein the branch prediction sub-pipeline includes a branch prediction module, an instruction fetch address queue, a memory access instruction recording module, a memory access mode learning module, a memory access address queue, a prefetch request generation module and a prefetch request write-back module; the branch prediction module is configured to use an advance prediction technology to predict the instruction stream of the target program and write the prediction result into the instruction fetch address queue; the memory access instruction recording module is configured to record the information of the submitted memory access instructions in sequence and write the information of these memory access instructions into its memory access instruction buffer; at the same time, whenever a new entry item is written into the instruction fetch address queue, the memory access instruction buffer is queried with the starting address of the instruction block corresponding to the entry item, so as to obtain the memory access instruction sequence through query attempts and output it to the memory access instruction learning module and the memory access address queue. address queue; the memory access mode learning module is configured to record the memory access instruction sequence in its memory access history buffer, learn the memory access mode of the memory access instruction according to the historical information stored in the memory access history buffer, and predict the memory access physical address of each memory access instruction in the memory access instruction sequence according to the learned memory access mode and write it into the memory access address queue; the prefetch request generation module is configured to retrieve the instruction fetch address queue and the memory access address queue when the first-level data cache receives a new request, generate prefetch requests for the first-level instruction cache and the first-level data cache for the instruction block that is about to enter the mainstream pipeline and send them to the cache system to obtain the prefetch request for obtaining data; the prefetch request write back module is configured to temporarily store the prefetch request for obtaining data in its prefetch queue, so that the prefetch request for obtaining data at the head of the prefetch queue waits for write-back or immediately writes back to the first-level cache according to the instruction submission status before the prefetch request.

[0006] The branch prediction module is configured to write the prediction result into the instruction fetch address queue with instruction block as the granularity; and the branch prediction module is configured to execute:

[0007] A1: In each cycle, the instruction block where the current prediction address is located is taken as the current instruction block, and the current prediction address is taken as the prediction start address of the current instruction block; a fixed prediction window starting from the current instruction block is determined according to the prediction start address of the current instruction block;

[0008] A2: After obtaining the predicted starting address of the current instruction block, search and predict the branch instruction in the current instruction block to determine whether the current instruction block hits the branch instruction to jump;

[0009] A3: According to the judgment result, if the current instruction block does not hit the branch instruction to jump, it means that there is no branch instruction in the current instruction block or none of the identified branch instructions jump, then the information of the current instruction block is written into the instruction fetch address queue as the prediction result of the branch prediction module; then, the predicted starting address of the next instruction block is determined, and the next instruction block is used as the new current instruction block, and the process returns to step A2 until the current instruction block is the last instruction block in the fixed prediction window, at which time the current prediction address is incremented according to the number of instruction blocks in the fixed prediction window to enter the next cycle;

[0010] Otherwise, the first jump branch instruction with the smallest linear address is selected from the hit jump branch instructions as the end address of the current instruction block, the information of the current instruction block is written into the instruction fetch address queue as the prediction result, and the current prediction address is updated to the jump address of the first jump branch instruction to enter the next cycle;

[0011] Alternatively, the branch prediction module is configured to write the prediction result into the instruction fetch address queue with instruction blocks as the granularity; and the branch prediction module is configured to execute:

[0012] Step A1': in each cycle, the instruction block where the current prediction address is located is taken as the current instruction block, and the current prediction address is taken as the prediction start address of the current instruction block; then, the prediction start addresses of all instruction blocks in the fixed prediction window starting from the current instruction block are determined according to the prediction start address of the current instruction block;

[0013] Step A2': searching and predicting branch instructions in each instruction block according to the predicted starting address of each instruction block, so as to determine whether each instruction block hits the branch instruction for jumping;

[0014] Step A3': According to the judgment result, if all instruction blocks do not hit the branch instruction of the jump, the information of all instruction blocks is written into the instruction fetch address queue in sequence as the prediction result of the branch prediction module; the current prediction address is incremented according to the number of instruction blocks in the fixed prediction window to enter the next cycle;

[0015] Otherwise, if there is at least one instruction block that hits at least one jump branch instruction, the first jump branch instruction with the smallest linear address is selected from the hit jump branch instructions as the end address of the current instruction block, and the information of the current instruction block and all the previous instruction blocks are written into the instruction fetch address queue as the prediction results, and the current predicted address is updated to the jump address of the first jump branch instruction to enter the next cycle.

[0016] The main pipeline includes an instruction fetch unit, a decoding unit, an execution unit, a memory access unit and a write-back unit connected in sequence, and in the branch prediction module, the bit width of the instruction block is equal to the bit width of the instruction fetch unit when fetching instructions;

[0017] The information of the instruction block includes the row linear address, row physical address, starting offset, ending offset and jump bit of the instruction block; when writing the information of the instruction block into the instruction fetch address queue, the predicted starting address of the instruction block is split into a high-order row linear address and a low-order starting offset, and the row physical address is obtained by querying the TLB through the row linear address, and the obtained row linear address, row physical address and starting offset are written into the corresponding fields in the entry item of the instruction fetch address queue; in addition, if the instruction block hits a jump branch instruction, the end byte offset of the first jump branch instruction is written into the instruction fetch address queue as the ending offset; otherwise, the ending offset in the instruction fetch address queue is set to 63.

[0018] The structure of each entry in the instruction fetch address queue is:

[0019] <valid,line_addr,phys_addr,begin_offset,end_offset,taken> ,

[0020] Among them, valid represents the valid bit; line_addr represents the line linear address; phys_addr represents the line physical address; begin_offset represents the starting offset; end_offset represents the ending offset; taken represents the jump bit;

[0021] The instruction fetch address queue is also provided with a commit pointer, a read pointer and a write pointer; the commit pointer of the instruction fetch address queue points to the entry item of the instruction block where the next instruction to be committed is located in the instruction fetch address queue; the read pointer of the instruction fetch address queue points to the entry item of the instruction block where the next instruction to be read is located in the instruction fetch address queue; the write pointer of the instruction fetch address queue points to the position where the branch prediction module will write next; after the mainstream pipeline of the processor is refreshed, the read pointer and the write pointer of the instruction fetch address queue are rolled back to the position of the branch refresh or the position of the commit pointer according to the refresh type;

[0022] The structure of each entry in the memory access instruction buffer is:

[0023] <LineAddr,PhyAddr,InstType,Memlen> ,

[0024] Wherein, LineAddr indicates the instruction linear address of the memory access instruction; PhyAddr indicates the memory access physical address of the memory access instruction at the last execution; InstType indicates the type of the memory access instruction, InstType∈{DirectInst,InDirectInst}, where DirectInst indicates a direct memory access instruction and InDirectInst indicates an indirect memory access instruction; Memlen indicates the memory access length of the memory access instruction;

[0025] The memory access history buffer is an array indexed by the PC of the memory access instruction, and each entry in the memory access history buffer records the physical addresses of the past 12 memory accesses of the same memory access instruction;

[0026] And the structure of each entry in the memory access address queue is:

[0027] <valid,inst_line_addr,mem_phys_addr,memlen,inst_queue_index> ,

[0028] Among them, valid represents the valid bit; inst_line_addr represents the instruction linear address; mem_phys_addr represents the memory access physical address; memlen represents the memory access length; inst_queue_index represents the instruction fetch address queue index;

[0029] The memory access address queue has a commit pointer, a read pointer and a write pointer; when a branch refresh occurs in the main pipeline, the read pointer and the write pointer of the memory access address queue are rolled back to the position of the branch refresh.

[0030] The branch prediction module is configured to: suspend the prediction process if the instruction fetch address queue is full; whether the instruction fetch address queue is full is determined based on a combination of a write pointer and a commit pointer of the instruction fetch address queue.

[0031] In the memory access instruction recording module, the information of the memory access instruction includes the PC of the memory access instruction, the instruction linear address, the memory access address, the type and the memory access length of the memory access instruction;

[0032] The memory access instruction recording module is configured to use the instruction linear addresses of the memory access instructions in all table entries of the memory access instruction buffer to perform a hit judgment during the query process, and obtain the position and type of the memory access instruction in the memory access instruction buffer when the memory access instruction hits, thereby attempting to obtain the position and type of the memory access instruction in the memory access instruction buffer by querying all the memory access instructions in the memory access instruction buffer; when performing a hit judgment, when there is a memory access instruction in the memory access instruction buffer whose instruction linear address has a high-order tag that is the same as the row linear address of the instruction block corresponding to the new entry, and its low-order offset is greater than or equal to the starting offset of the instruction block and less than or equal to the ending offset of the instruction block, then the memory access instruction hits, and the position and type of the memory access instruction in the memory access instruction buffer are obtained.

[0033] The memory access pattern learning module includes a step length predictor and a time association predictor, so that the memory access pattern learning module can learn and predict the step length pattern and the time association pattern through the step length predictor and the time association predictor based on the memory access history buffer;

[0034] Each entry of the step length predictor is used to record a step length mode, and the step length mode refers to a step length memory access sequence; each entry of the step length predictor includes a tag of a step length memory access sequence, a previous address, a previous step length, a trusted counter, a current mode, a first address, a maximum counter and a direction;

[0035] Each entry of the time correlation predictor is used to record a time correlation pattern, which refers to a time correlation memory access sequence. Each entry of the time correlation predictor includes the time correlation pattern, the time correlation sequence length and the time correlation sequence.

[0036] The pre-fetch request generation module determines the instruction block that is about to enter the main pipeline according to the read pointer of the instruction fetch address queue;

[0037] The pre-fetch request generation module is configured to perform the following steps:

[0038] B1: After receiving the message that the first-level data cache has received a new request, the instruction fetch address queue is retrieved to obtain the position of its read pointer, and the position after adding a prefetch advance amount to the read pointer is used as the prefetch start, and the consecutive N prefetch instruction blocks with the prefetch start as the first prefetch instruction block are used as the instruction blocks that are about to enter the main pipeline, and the corresponding first-level instruction cache prefetch request is generated for the instruction blocks that are about to enter the main pipeline;

[0039] B2: Receive pointers of each prefetch instruction block fed back by the instruction fetch address queue, use the pointers of these prefetch instruction blocks to retrieve the instruction fetch address queue index in the memory access address queue, obtain the memory access instructions and their memory access physical addresses contained in each prefetch instruction block, and generate a prefetch request for the first-level data cache according to the memory access physical addresses of the memory access instructions;

[0040] B3: Send both the prefetch request of the first-level instruction cache and the prefetch request of the first-level data cache to the cache system to obtain the prefetch request for obtaining data.

[0041] The prefetch request write-back module is configured as follows: for a prefetch request located at the head of the prefetch queue, the uncommitted instruction set of the memory access address queue after its commit pointer and before the prefetch request is retrieved, and it is determined whether there are other memory access instructions in the same group as the prefetch request in the first-level cache array in the uncommitted instruction set, and the determination result is used as the instruction submission status before the prefetch request; if it is determined that there are other memory access instructions in the same group as the prefetch request, and the number of memory access instructions in the same group as the prefetch request is at least the number of ways of the cache array, the prefetch request is put on hold for write-back, otherwise, the prefetch request is immediately written back to the first-level cache.

[0042] On the other hand, the present invention provides a low-pollution cache prefetching method based on instruction stream mixed mode learning, comprising:

[0043] S1: Use the branch prediction module and the advance prediction technology to predict the instruction stream of the target program and write the prediction results into the instruction fetch address queue; if the instruction fetch address queue is full, the prediction process is suspended;

[0044] S2: using a memory access instruction recording module to record information of submitted memory access instructions, and writing the information of these memory access instructions into a memory access instruction buffer; whenever a new entry is written into the instruction fetch address queue, querying the memory access instruction buffer with the starting address of the instruction block corresponding to the entry, so as to obtain a memory access instruction sequence through querying and output it to the memory access instruction learning module and the memory access address queue;

[0045] S3: using a memory access instruction learning module, recording a memory access instruction sequence in a memory access history buffer, learning a memory access mode of the memory access instruction according to historical information stored in the memory access history buffer, and predicting a memory access physical address of each memory access instruction in the memory access instruction sequence according to the learned memory access mode, and writing the memory access physical address of each memory access instruction into a memory access address queue;

[0046] S4: using the pre-fetch request generation module, when the first-level data cache receives a new request, searching the instruction fetch address queue and the memory access address queue, respectively generating pre-fetch requests for the first-level instruction cache and the first-level data cache for the instruction block that is about to enter the main pipeline and sending them to the cache system, so as to obtain the pre-fetch request for obtaining the data;

[0047] S5: Using the prefetch request write-back module, the prefetch request that obtains data is temporarily stored in its prefetch queue, so that the prefetch request that obtains data at the head of the prefetch queue waits for write-back or is immediately written back to the first-level cache according to the instruction submission status before the prefetch request.

[0048] The prediction object of the low-pollution cache prefetch system based on instruction stream mixed pattern learning of the present invention is specific to each memory access instruction, and historical information is recorded separately for each memory access instruction, so what is learned is the instruction-level memory access behavior, which reduces the complexity of prediction; and pattern learning is performed based on the sequence composed of the submitted memory access instructions fed back by the write-back unit of the processor mainstream, and the prediction object is a single independent memory access instruction with simple behavior, which can avoid the interference of out-of-order execution and improve the accuracy of memory access sequence prediction. In summary, the low-pollution cache prefetch system based on instruction stream mixed pattern learning of the present invention reduces the uncertainty faced in the memory access sequence prediction process through the above-mentioned method, significantly reduces the number of cache failures, and improves the accuracy of prefetch address prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a structural schematic diagram of one of the processor micro-architectures to which the low-pollution cache prefetching system and method based on instruction stream mixed mode learning of the present invention is applicable.

[0050] Figure 2 It is a structural schematic diagram of another processor micro-architecture applicable to the low-pollution cache prefetching system and method based on instruction stream hybrid mode learning of the present invention.

[0051] Figure 3 It is an overall framework diagram of a low-pollution cache prefetching system based on instruction stream hybrid mode learning according to an embodiment of the present invention.

[0052] Figure 4 Yes Figure 3 The prediction flow chart of the branch prediction module of the low-pollution cache prefetch system based on instruction stream mixing pattern learning is shown.

[0053] Figure 5 It is a schematic diagram of the positional relationship of the instruction fetch address queue and the commit pointer, read pointer and write pointer of the low-pollution cache prefetch system based on instruction stream mixed mode learning of the present invention.

[0054] Figure 6It is a schematic diagram of the query process of the memory access instruction buffer of the low-pollution cache prefetch system based on instruction stream mixed mode learning of the present invention.

[0055] FIG7( a ) is a schematic diagram of a conventional time-correlated prefetching algorithm.

[0056] FIG. 7( b ) is a schematic diagram of the memory access pattern learning process based on memory access history buffering in the low-pollution cache prefetching system based on instruction stream mixed pattern learning of the present invention.

[0057] Figure 8 It is a structural schematic diagram of the entry items of the step size predictor of the low-pollution cache prefetch system based on instruction stream mixed mode learning of the present invention.

[0058] Fig. 9 It is a working principle diagram of the prefetch request generation module of the low-pollution cache prefetch system based on instruction stream mixed mode learning of the present invention.

[0059] Fig.10 It is a principle diagram of the write-back waiting process of the prefetch request of the primary data cache of the low-pollution cache prefetch system based on instruction stream mixed mode learning of the present invention. DETAILED DESCRIPTION

[0060] The present invention is further described in detail below through specific implementation examples.

[0061] The low-pollution cache prefetching system and method based on instruction stream mixed mode learning of the present invention are applicable to Figure 1 The processor microarchitecture shown in the figure. The processor microarchitecture at least includes five stages: instruction fetch, decoding, execution, memory access and write back. These five stages correspond to the instruction fetch unit 100, decoding unit 200, execution unit 300, memory access unit 400 and write back unit 500 respectively. The above-mentioned instruction fetch unit 100, decoding unit 200, execution unit 300, memory access unit 400 and write back unit 500 constitute the main pipeline. The first-level cache is divided into a first-level instruction cache and a first-level data cache, wherein the first-level instruction cache is located in the instruction fetch unit 100 in the main pipeline of the CPU, and the first-level data cache is located in the memory access unit 400 in the main pipeline of the CPU.

[0062] The present invention is also applicable to Figure 1 In a more complex processor microarchitecture with the functions shown, a certain stage may be refined in a more complex processor microarchitecture. For example, the execution stage can be split into three sub-stages: renaming, scheduling, and execution.

[0063] like Figure 2As shown, according to the advance prediction technology in the prior art, the processor microarchitecture may also include a branch prediction unit 600, and the branch prediction unit 600 may interact with the instruction fetch unit through a prediction queue. Specifically, the branch prediction unit 600 predicts the future program instruction stream, and writes the prediction result into the prediction queue 700 with the aligned instruction block as the granularity. Each entry in the prediction queue 700 contains the starting address, the ending address and other branch instruction information of the instruction block. The relationship between the branch prediction unit 600 and the instruction fetch unit 100 is similar to that of a producer-consumer. The instruction fetch unit 100 reads an entry from the prediction queue 700 per cycle, and reads the corresponding instruction block data from the cache system according to the read entry, and then sends the instruction block data to the subsequent units of the main pipeline (i.e., the decoding unit 200, the execution unit 300, the memory access unit 400 and the write-back unit 500) to execute the instructions contained in the instruction block. When the low-pollution cache prefetching method based on instruction stream hybrid mode learning of the present invention is applied to a processor microarchitecture including a branch prediction unit 600, the branch prediction unit 600 and the prediction queue 700 can be used as the branch prediction module and instruction fetch address queue of the system of the present invention, respectively, thereby reducing the workload of specific implementation.

[0064] Figure 3 1 is an overall framework diagram of a low-pollution cache prefetching system based on instruction stream mixed mode learning according to an embodiment of the present invention. Figure 3As shown, the low-pollution cache prefetch system based on instruction stream mixed mode learning, based on the existing processor micro-architecture (including the instruction fetch unit 100, the decoding unit 200, the execution unit 300, the memory access unit 400 and the write-back unit 500), also includes seven modules: a branch prediction module 10, an instruction fetch address queue 20, a memory access instruction recording module 30, a memory access mode learning module 40, a memory access address queue 50, a prefetch request generation module 60 and a prefetch request write-back module 70. These seven modules together constitute a prediction sub-pipeline with an execution rate faster than the main pipeline, and run independently outside the main pipeline of the processor (i.e., the sequential execution of the instruction fetch unit 100, the decoding unit 200, the execution unit 300, the memory access unit 400 and the write-back unit 500). The execution order of each module in the prediction sub-pipeline is branch prediction module 10→instruction fetch address queue 20→memory access instruction recording module 30→memory access mode learning module 40→memory access address queue 50. The prefetch request generation module 60 and the prefetch request write-back module 70 are relatively independent modules. The prefetch request generation module 60 is configured to select an appropriate time to retrieve the instruction fetch address queue and the memory access address queue, generate prefetch requests for the primary instruction cache and the primary data cache, and send the prefetch requests to the cache system (such as the secondary and tertiary caches). The prefetch request write-back module 70 temporarily stores the prefetch requests that have already obtained the data. These prefetch requests have data written into the primary cache, but in order to prevent the cache items with a reuse distance smaller than the prefetch request from being kicked out of the primary cache during the writing process, the prefetch requests need to wait in the queue of the prefetch request write-back module 70 for the time when they can be written back. The relationship between the prefetch request generation module 60 and the other five prediction sub-pipeline components is similar to that of a producer-consumer. The instruction fetch address queue 20 and the memory access address queue 50 are filled by the prediction sub-pipeline, and the prefetch request generation module 60 retrieves these two queues.

[0065] (I) Branch prediction module 10

[0066] The branch prediction module 10 is the starting point of the prediction sub-pipeline. The branch prediction module 10 is configured to: use the advance prediction technology to predict the instruction flow of the target program and write the prediction results into the instruction fetch address queue 20 with instruction blocks as the granularity (i.e., in the form of aligned instruction blocks); when the instruction fetch address queue 20 is full, the prediction process is suspended.

[0067] Therefore, the instruction fetch address queue stores instruction blocks (including additional branch instruction information). Since the instruction fetch unit accesses the primary instruction cache in the form of fixed-bit-width (64B) instruction blocks, the entries in the instruction fetch address queue 20 are used as the future access sequence of the primary instruction cache in the instruction fetch unit 100, that is, the predicted result of the access sequence of the instruction stream of the target program.

[0068] The branch prediction module 10 predicts the instruction flow of the target program by judging whether there is a branch instruction to jump in all instruction blocks of the fixed prediction window in each cycle, and predicts the instruction flow of the target program according to the judgment result. The prediction process in each cycle is performed based on the current prediction address, and the current prediction address is updated to enter the next cycle. A very important function of the branch prediction module 10 is to maintain the current prediction address, which is a 48-bit linear address.

[0069] Maintaining the current predicted address includes: if a branch instruction of a jump is predicted, the jump address of the branch instruction of the jump will be updated to the current predicted address; that is, the branch prediction module 10 is a self-looping branch prediction unit, and in addition to writing the prediction result of the branch prediction module 10 into the instruction fetch address queue 20, the jump address of the branch instruction of the jump in the prediction result will be returned to the branch prediction module 10 itself as the current predicted address, as the starting address of the next prediction cycle. In addition, during the initialization phase of the processor or when the main pipeline is refreshed, the instruction fetch unit will send the initialization address or the refresh address to the branch prediction module 10 to update the current predicted address.

[0070] Figure 4 The prediction process of the branch prediction module 10 is shown. The fixed prediction window of the branch prediction module is the width of multiple instruction blocks, that is, multiple consecutive instruction blocks can be predicted per cycle, and the bit width of the instruction block is equal to the bit width of the instruction fetch unit 100 when fetching instructions, which facilitates the interaction with the instruction fetch unit 100.

[0071] The fixed prediction window of the branch prediction module is multiple 64B instruction blocks, that is, multiple consecutive 64B instruction blocks can be predicted per cycle. The 64B instruction blocks are selected to match the bandwidth of the instruction fetch unit 100 when accessing the first-level instruction cache.

[0072] like Figure 4 As shown, the branch prediction module 10 is configured to perform the following steps:

[0073] Step A1: In each cycle (i.e., when the current predicted address is initialized or updated), the instruction block where the current predicted address in the first-level instruction cache is located is used as the current instruction block, and the current predicted address is used as the predicted starting address of the current instruction block; a fixed prediction window starting from the current instruction block is determined according to the predicted starting address of the current instruction block;

[0074] Since the prediction of the instruction stream of the target program is based on the granularity of aligned instruction blocks, the fixed prediction window of each cycle is the width of multiple instruction blocks, that is, multiple instruction blocks can be predicted per cycle, such as a fixed prediction window of 32B can be split into two 16B instruction blocks for parallel prediction. In this embodiment, assuming that the current prediction address is 5, the fixed prediction window of each cycle of the branch prediction module 10 is 128B, that is, 2 aligned 64B instruction blocks are predicted per cycle. The predicted starting address of the first 64B instruction block is the current prediction address (that is, 5), and the instruction block range is [5,63]; the predicted starting address of the second 64B instruction block is 64, and the instruction block range is [64,127]. Since it is an aligned instruction block, the default starting address of each instruction block is an integer multiple of 64B. However, considering that the starting address of the first instruction block in the prediction process may not be an integer multiple of 64B, because this address may be jumped from a branch instruction, there is no way to ensure that this address is strictly aligned; therefore, the starting address of the second instruction block (and the third, fourth, etc.) in the prediction process must be an integer multiple of 64B.

[0075] Step A2: after obtaining the predicted starting address of the current instruction block, searching and predicting the branch instruction in the current instruction block to determine whether the current instruction block hits the branch instruction for jumping;

[0076] Among them, the branch prediction module 10 needs to use an existing branch prediction algorithm to realize the prediction of branch instructions. The present invention does not rely on a specific branch prediction algorithm, and the existing branch prediction algorithms are applicable to the branch prediction module. Taking the common TAGE branch prediction algorithm as an example, first use the predicted starting address of the current instruction block to retrieve the BTB (branchtarget buffer), and identify all branch instructions contained in the current instruction block according to the branch instruction location stored in the BTB. This identification process may hit multiple branch instructions. Then predict the jump direction and jump address of each identified branch instruction to determine whether there is a branch instruction for jumping among these branch instructions.

[0077] Step A3: According to the judgment result, if the current instruction block does not hit the branch instruction for jumping, it means that there is no branch instruction in the current instruction block or none of the identified branch instructions jump, then the information of the current instruction block is written into the instruction fetch address queue as the prediction result of the branch prediction module 10; then, the predicted starting address of the next instruction block is determined, and the next instruction block is used as the new current instruction block, and the process returns to step A2 until the current instruction block is the last instruction block in the fixed prediction window. At this time, the current prediction address is incremented according to the number of instruction blocks in the fixed prediction window, thereby updating the current prediction address and entering the next cycle;

[0078] Otherwise, that is, the current instruction block hits the branch instruction that jumps, which means that the branch instruction identified in the instruction block has one or more predicted jumps, then the first jump branch instruction with the smallest linear address is selected from the hit jump branch instructions as the end address of the current instruction block, and the information of the current instruction block is written into the instruction fetch address queue as the prediction result, and the current predicted address is updated to the jump address of the first jump branch instruction to enter the next cycle.

[0079] That is to say, Figure 4 As shown, in this embodiment, the multiple instruction blocks predicted by the branch prediction module in each cycle are predicted one by one in serial order, that is, each time the predicted starting address of the next instruction block is calculated according to the predicted starting address of the current instruction block.

[0080] The information of the instruction block includes the row linear address, row physical address, start offset, end offset, jump bit, etc. of the instruction block.

[0081] The addresses used by the branch prediction module 10 in the prediction process of each cycle (such as the predicted starting address of the current instruction block, etc.) are all in the form of linear addresses. However, the addresses stored in the instruction fetch address queue 20 are in the form of physical addresses. This is because the addresses used in the cache system are all physical addresses, and the cache replacement decision module 60 will use the physical address of the candidate to retrieve the instruction fetch address queue and the memory access address queue. Therefore, the addresses stored in the instruction fetch address queue 20 need to be physical addresses corresponding to the linear addresses.

[0082] Therefore, the row linear address and starting offset of the current instruction block can be determined based on the predicted starting address of the current instruction block. When the row linear address in the information of the current instruction block is written into the instruction fetch address queue, it is first necessary to search through the TLB (translation lookaside buffer) to obtain the row physical address, and both the row linear address and the row physical address are saved in the instruction fetch address queue 20.

[0083] Specifically, when writing the information of the instruction block into the instruction fetch address queue 20, it is necessary to split the predicted starting address of the 48-bit instruction block into a high 42-bit row linear address and a low 6-bit starting offset, and query the TLB through the 42-bit row linear address to obtain a 34-bit row physical address, and write the obtained row linear address, row physical address and starting offset into the corresponding fields in the entry item of the instruction fetch address queue 20. In addition, if the instruction block hits a branch instruction of a jump, the end byte offset of the first branch instruction of the jump is written into the instruction fetch address queue 20 as the end offset; otherwise, the end offset in the instruction fetch address queue 20 is set to 63. In addition, if the current instruction block hits a branch instruction of a jump, the jump position in the entry item of the instruction fetch address queue 20 is set to 1.

[0084] Because the prediction of each instruction block is relatively independent, in other embodiments, the predicted starting addresses of multiple instruction blocks may be predicted simultaneously in a parallel manner.

[0085] Accordingly, the branch prediction module 10 is configured to perform the following steps:

[0086] Step A1': In each cycle (i.e., when the current prediction address is initialized or updated), the instruction block where the current prediction address is located is taken as the current instruction block, and the current prediction address is taken as the prediction start address of the current instruction block; then, the prediction start addresses of all instruction blocks in the fixed prediction window starting from the current instruction block are determined according to the prediction start address of the current instruction block;

[0087] As mentioned above, if the range of the first instruction block is [5,63], the range of the second instruction block is [64,127], and the range of the third instruction block is [128,191]. Except for the first instruction block, the starting addresses of other instruction blocks are all 64B aligned.

[0088] Step A2': searching and predicting branch instructions in each instruction block according to the predicted starting address of each instruction block, so as to determine whether each instruction block hits the branch instruction for jumping;

[0089] Step A3': according to the judgment result, if all instruction blocks do not hit the branch instruction of the jump, the information of all instruction blocks is sequentially written into the instruction fetch address queue as the prediction result of the branch prediction module 10; the current prediction address is incremented according to the number of instruction blocks in the fixed prediction window;

[0090] Otherwise, if there is at least one instruction block that hits at least one jump branch instruction, the first jump branch instruction with the smallest linear address is selected from the hit jump branch instructions as the end address of the current instruction block, and the information of the current instruction block and all the previous instruction blocks are written into the instruction fetch address queue as the prediction results, and the current predicted address is updated to the jump address of the first jump branch instruction.

[0091] (II) Instruction fetch address queue 20

[0092] See also Figure 3 The instruction fetch address queue 20 is set to store the prediction results written by the branch prediction module 10 in units of instruction blocks. In the design of the present invention, the instruction fetch address queue has 4096 entries. In this embodiment, each entry in the instruction fetch address queue represents the prediction result of a 64B instruction block. The 64B width is to match the 64B bandwidth of the instruction fetch unit 100 when accessing the first-level instruction cache.

[0093] The structure of each entry in the instruction fetch address queue can be expressed as:

[0094] <valid,line_addr,phys_addr,begin_offset,end_offset,taken> ,

[0095] Among them, valid represents the valid bit; line_addr represents the row linear address; phys_addr represents the row physical address; begin_offset represents the starting offset; end_offset represents the ending offset; taken represents the jump bit.

[0096] Among them, the row linear address, the starting offset and the ending offset determine the range of valid bytes in the 64B instruction block. This range of valid bytes is used to retrieve the memory access instruction recording module 30 to query the memory access instructions in the instruction block. Each entry item in the instruction fetch address queue represents an instruction block. Each instruction block contains a starting offset and an ending offset. The order of each instruction block is connected to form the instruction stream of the target program. The row physical address is used for address matching calculation when the cache replacement decision module 60 queries the reuse distance of the replacement candidate. The jump bit is used to indicate whether the data block corresponding to the current entry item has a branch instruction for jumping.

[0097] like Figure 5 As shown, the instruction fetch address queue 20 is further provided with a commit pointer, a read pointer and a write pointer. These three pointers each point to one of the entries in the instruction fetch address queue. Each pointer can be regarded as a number in the range of [0, 4095].

[0098] The commit pointer of the instruction fetch address queue 20 points to the entry item in the instruction fetch address queue 20 of the instruction block where the next instruction to be submitted is located. When all instructions in a certain instruction block are submitted in the mainstream pipeline, the entry item corresponding to the instruction block can be removed from the instruction fetch address queue, and the commit pointer is increased by 1. Specifically, the write-back unit 500 in the mainstream pipeline is configured to feedback the number of the instruction being submitted in the instruction fetch address queue 20 to the instruction fetch address queue 20 in each cycle. When this number is greater than the commit pointer, it can be confirmed that all instructions in the instruction block pointed to by the commit pointer have been submitted in the mainstream pipeline, and the commit pointer is increased by 1. The entry item before the commit pointer does not need to be actively cleared. The prediction result of the branch prediction module 10 can only be written into the entry item before the commit pointer, thereby automatically overwriting the entry item before the commit pointer.

[0099] The read pointer of the instruction fetch address queue 20 points to the entry of the instruction block where the next instruction to be read is located in the instruction fetch address queue. When all instructions in the instruction block currently read by the instruction fetch unit 100 are read, the read pointer is incremented by 1 to ensure that the read pointer of the instruction fetch address queue 20 always points to the entry of the instruction block where the next instruction to be read is located in the instruction fetch address queue.

[0100] That is, the instruction block between the instruction fetch address queue commit pointer and the read pointer is already in the main pipeline of the processor (ie, the execution flow from the instruction fetch unit 100 to the write-back unit 500).

[0101] The write pointer of the instruction fetch address queue 20 points to the location where the branch prediction module 10 will write next, and is used to determine the write location when the branch prediction module 10 writes a new entry. The write pointer is set to increase by 1 each time the branch prediction module 10 writes a new entry. Therefore, the instruction block between the read pointer and the write pointer is a valid predicted instruction block, and the write pointer and the commit pointer can be combined to determine the empty or full status of the instruction fetch address queue 20 (i.e., whether the instruction fetch address queue 20 is full).

[0102] After the main pipeline of the processor is refreshed, the read and write pointers will roll back to the position of the branch refresh or the position of the commit pointer according to the refresh type. Specifically, when a branch refresh occurs (i.e., the refresh type is branch refresh), the execution unit 300 in the main pipeline will feedback the number of the refreshed branch instruction in the instruction fetch address queue 20 to the instruction fetch address queue 20 as the branch instruction refresh pointer, and the read and write pointers will roll back to the position of the branch refresh. When a write-back refresh occurs (i.e., the refresh type is write-back refresh), the read and write pointers roll back to the position of the commit pointer. It should be noted that the refresh process does not actively clear the data in the queue, but only changes the assignment of the read and write pointers. Branch prediction is not 100% accurate, so the prediction result in the instruction fetch address queue may be wrong. At this time, it is necessary to use the refresh process to roll back the read and write pointers, so as to clear the wrong data and rewrite the correct data.

[0103] (III) Memory access instruction recording module 30

[0104] See also Figure 3 The memory access instruction recording module 30 is configured to receive the memory access instruction information fed back by the write-back unit 500, sequentially record the information of the submitted memory access instructions, and write the information of the memory access instructions into a memory access instruction buffer 31. Thus, it is possible to determine whether the instruction block contains a memory access instruction.

[0105] The memory access instruction recording module 30 has a memory access instruction buffer 31, whose storage structure is a table structure, which has 4096 table entries.

[0106] The information of the memory access instruction (ie, the information of the memory access instruction that has been submitted) includes the PC of the memory access instruction, the linear address, the memory access address, the type and the memory access length of the memory access instruction.

[0107] The structure of each entry of the memory access instruction buffer 31 is represented as follows:

[0108] <LineAddr,PhyAddr,InstType,Memlen> ,

[0109] Among them, LineAddr represents the instruction linear address of the memory access instruction; PhyAddr represents the memory access physical address of the memory access instruction when it was last executed; InstType indicates the type of the memory access instruction, InstType∈{DirectInst,InDirectInst}, where DirectInst represents a direct memory access instruction and InDirectInst represents an indirect memory access instruction; Memlen indicates the memory access length of the memory access instruction.

[0110] The memory access instruction recording module 30 is also configured to: whenever a new entry is written to the instruction fetch address queue 20, the starting address (i.e., row linear address + starting offset) of the instruction block corresponding to the entry is used to query the memory access instruction buffer 31, so as to try to obtain the instruction linear address (i.e., position) LineAddr and type InstType of the memory access instruction through the query, and output them in turn as the instruction fetch address queue index of the memory access instruction in the memory access instruction sequence to the memory access instruction learning module 40 and the memory access address queue 50. That is, if the instruction block contains multiple memory access instructions, they are arranged in order according to the instruction linear address (i.e., position) of the memory access instruction to be added to the instruction fetch address queue 20. The instruction linear address LineAddr (i.e., position) of the memory access instruction corresponding to the newly added entry of the instruction fetch address queue 20 will be sent to the memory access instruction recording module 40 as the instruction fetch address queue index for query, and this instruction fetch address queue index will be sent to the memory access address queue 50 in the subsequent process to record the position of the memory access instruction. The type of the memory access instruction is used for the memory access instruction learning module 40 to select between multiple modes.

[0111] Therefore, through the memory access instruction recording module 30 , the memory access instruction sequence of the program can be obtained according to the instruction block sequence of the program predicted by the branch prediction module 10 .

[0112] Among them, the memory access instruction recording module 30 is configured to use the instruction linear addresses of the memory access instructions in all table entries of the memory access instruction buffer 31 for hit judgment during the query process, and obtain the position and type of the memory access instruction in the memory access instruction buffer 31 when the memory access instruction hits, thereby trying to obtain the instruction linear address (i.e., position) and type of the memory access instruction by querying all the memory access instructions in the memory access instruction buffer 31.

[0113] The query process of the memory access instruction buffer 31 is as follows Figure 6 As shown. Figure 6 As shown, the hit judgment of the memory access instruction buffer 31 is an inclusion relationship judgment. Each entry item in the instruction fetch address queue 20 corresponds to an instruction block, which is an interval range; therefore, when performing a hit judgment, it is necessary to determine whether the instruction linear address of each memory access instruction is within the interval range where the new entry item is written in the instruction fetch address queue 20. If there is a memory access instruction within the said interval range, the memory access instruction query hits, otherwise, the query hit fails, that is, no memory access instruction is hit, indicating that there is no memory access instruction in the instruction block corresponding to the new entry item, and no operation is performed at this time.

[0114] In this embodiment, the newly added entry item of the instruction fetch address queue 20 includes the 48-bit starting address and 48-bit ending address of the instruction block, which can be converted into the high-order label of the high-order 42-bit linear address (i.e., the row linear address) and the low-order 6-bit starting offset and ending offset. Therefore, in the query process, the label and offset of the instruction block are used to query all the memory access instructions in the memory access instruction buffer 31. When there is a memory access instruction in the memory access instruction buffer 31 whose high-order label of the instruction linear address is the same as the row linear address of the instruction block corresponding to the new entry item, and its low-order offset is greater than or equal to the starting offset of the instruction block and less than or equal to the ending offset of the instruction block, it means that the memory access instruction is located in the instruction block, that is, the memory access instruction query hits, and the instruction linear address (i.e., position) and type of the memory access instruction are obtained.

[0115] In addition, the present invention further adds a step size predictor and a time correlation predictor based on the memory access instruction buffer 31. These predictors are included in the memory access pattern learning module 40 which will be described in detail below, so as to predict the memory access instructions that conform to a specific pattern.

[0116] (IV) Access Mode Learning Module 40

[0117] See also Figure 3 The memory access mode learning module 40 is configured to record the memory access instruction sequence sent by the memory access instruction recording module 30 in a memory access history buffer, learn the memory access mode of the memory access instruction according to the historical information stored in the memory access history buffer, and predict the memory access physical address of each memory access instruction in the memory access instruction sequence according to the learned memory access mode, and write the memory access physical address of each memory access instruction as a prediction result into the memory access address queue 50.

[0118] The memory access mode learning module 40 includes a memory access history buffer, which is configured to receive memory access instruction information (including PC, type and memory access physical address) fed back by the processor during the write back phase, and write the memory access physical address of the memory access instruction into the table entry corresponding to the memory access instruction in the memory access history buffer according to the PC of the memory access instruction, where each table entry is a piece of historical information.

[0119] It should be noted that the memory access instruction buffer 31 of the memory access instruction recording module 30 and the memory access history buffer of the memory access mode learning module 40 have certain similarities. The difference between the two is that the memory access instruction buffer 31 in the memory access instruction recording module 30 stores instruction-related information, such as the instruction linear address of the memory access instruction, the memory access instruction type, etc.; the memory access instruction buffer also stores the memory access physical address, but only records the result of the last memory access physical address. The memory access history buffer in the memory access mode learning module 40 is mainly used to record the past memory access history, and records the past 12 memory access physical addresses. Only on this basis can the memory access mode be learned. Since the two storage arrays of the memory access instruction buffer 31 and the memory access history buffer do have certain similarities, the two arrays are designed to be equal in size. Although the memory access instruction buffer 31 and the memory access history buffer are logically two arrays, in the specific implementation, the memory access instruction buffer 31 and the memory access history buffer can be uniformly stored in the same hardware location to be merged together.

[0120] The memory access history buffer is an array indexed by the PC of the memory access instruction, with a total of 4096 entries. Each entry in the memory access history buffer is a 12-entry circular queue that records the physical addresses of the past 12 memory accesses of the same memory access instruction. Memory access instructions with the same PC are considered to be the same memory access instruction.

[0121] The memory access mode learning process based on the memory access history buffer in the present invention is significantly different from the existing algorithm. As shown in FIG7(a), the traditional time-related prefetch algorithm acquires the memory access mode based on the global invalidation buffer rather than the memory access history buffer. In the time-related prefetch algorithm, cache invalidation is the trigger condition for generating the prefetch request. The address A of the cache invalidation is used to search the global invalidation buffer to obtain the address sequence {A, B, C, D} with address A as the first address. The three addresses {B, C, D} are the prefetch candidates of address A, and A, B, C, and D can all be used to send prefetch requests. In order to ensure that the prefetch request can cover more cache invalidation scenarios, the longest match principle is generally adopted when retrieving the address sequence with address A as the first address, so that more prefetch requests can be issued. And in order to prevent excessive prefetch requests from wasting the cache system bandwidth, the number of prefetch requests issued is usually restricted by the prefetch depth (degree). For traditional algorithms, the length of the address sequence (i.e., the prefetch depth) does not affect the accuracy of the prediction, and the length only plays a role in controlling the prefetch advance amount.

[0122] As shown in FIG. 7( b ), the instruction block where the memory access instruction M in the present invention is located may appear multiple times in the instruction fetch address queue 20, and the present invention needs to independently perform address prediction for each occurrence of the memory access instruction M. If the behavior of the memory access physical address of the memory access instruction M conforms to the pattern {A, B, C, D}, and A, B, C, and D are all the memory access physical addresses of the memory access instruction M, then the present invention must learn that the length of the step pattern is 4 before it can accurately predict that the memory access physical address of the memory access instruction M when it appears for the fifth time is A. Therefore, the step pattern of the memory access pattern obtained through learning is a factor that must be considered in the learning stage of the present invention.

[0123] Therefore, the memory access pattern learning module 40 includes a step length predictor and a time correlation predictor, so that the memory access pattern learning module 40 can realize the learning and prediction of multiple memory access patterns such as step length pattern, time correlation pattern, etc. through the step length predictor and the time correlation predictor based on the memory access history buffer.

[0124] The step length predictor of the present invention is based on the traditional IBSP (intelligent blind signal processing method) algorithm. In this embodiment, each entry of the step length predictor is used to record a step length mode, and the step length mode refers to the step length memory access sequence. The structure of the entry is as follows: Figure 8As shown, each entry of the step length predictor includes a tag of a step length memory access sequence, a previous address, a previous step length, a trusted counter, a current mode, a first address, a maximum counter and a direction. That is to say, on the basis of the traditional IBSP algorithm, the entry of the step length predictor of the present invention extends the trusted counter, the current mode, the first address and the maximum counter. The original IBSP algorithm only needs to record the step length information, because the pre-fetch operation of the data is only calculated based on the current memory access physical address. For a sequence of memory access physical addresses with a fixed step length mode such as the step length memory access sequence {A, A+K, A+2K,..., A+NK}, the step length predictor of the present invention not only records its step length K, but also records the starting address A of the step length memory access sequence and the maximum count value N. Therefore, in order to increase the accuracy of the step length predictor, the step length predictor adds a trusted counter and a current mode. Specifically, when the previous step length is the same as the current step length, the trusted counter is increased by one, otherwise the trusted counter is reset to zero. When the value of the trusted counter is greater than a certain threshold, the current mode is set to 1, indicating that the behavior of the current memory access instruction is indeed in line with the step mode. If the current mode is 0, it means that it is still in the learning stage, and the step predictor in the learning stage does not output the prediction result. The step predictor also includes the step and direction bits. The step is always a positive value, and the direction bit determines whether the step memory access sequence is increasing or decreasing. When the step predictor allocates entries for memory access instructions, the first address of the entry is set to the current memory access physical address. During the step mode counting process, the first address is not updated, and only the last address is updated to the current latest memory access physical address. In this way, the first address of a step memory access sequence is saved. When the step predictor is updated for a memory access instruction that conforms to the step memory access sequence, it is found that the memory access physical address of the current memory access instruction is exactly equal to the first address of the current step memory access sequence in the step predictor, indicating that the step memory access sequence corresponding to the first address has been executed again. At this time, the value of the trusted counter is updated to the maximum counter so that the head and tail of the step length memory access sequence are recorded.

[0125] The following is an exemplary step size pattern recognition algorithm.

[0126] Algorithm 1. Step pattern recognition algorithm

[0127] Input: submitted memory access instruction PC and physical address PhysAddr;

[0128] Output: Is it step mode?

[0129] if (current mode == step mode);

[0130] if (the current direction and step size do not match the historical record)

[0131] if(PhysAddr == first address &&(max counter == 0 || trusted counter != max counter))

[0132] Maximum counter = trusted counter;

[0133] else

[0134] Clear the step length related information;

[0135] end if

[0136] else

[0137] TrustedCounter++;

[0138] if (max counter != 0 && trusted counter > max counter)

[0139] Maximum counter = trusted counter;

[0140] end if

[0141] end if

[0142] else

[0143] if (the current direction and step size do not match the historical record)

[0144] Clear the step length related information;

[0145] else

[0146] Trusted counter +1;

[0147] if (trusted counter > learning threshold)

[0148] Current mode = step mode;

[0149] end if

[0150] end if

[0151] end if

[0152] Each entry of the time correlation predictor is used to record a time correlation pattern. The time correlation pattern refers to a memory access sequence that appears repeatedly in a fixed order, that is, a time correlation memory access sequence. Each entry of the time correlation predictor includes a time correlation pattern, a time correlation sequence length, and a time correlation sequence. For example, after we observe a memory access sequence like {A, B, C, D, A, B, C, D}, a sequence like {B, C, D} has a high probability of appearing immediately after A. There are also time correlation patterns in instruction-level memory access behavior.

[0153] Algorithm 2. Temporal Correlation Pattern Recognition

[0154] Input: The physical addresses of the last 12 memory accesses;

[0155] Output: time-related information;

[0156] Record the physical addresses of the past 12 memory accesses in the memory access history buffer [11:0];

[0157] if(Access history buffer [3n-1:0] matches

[0158] {A1,A2,…,A n ,A1,A2,…,A n ,A1,A2,…,A n})

[0159] Time correlation mode = 1;

[0160] Time correlation sequence length = n;

[0161] Time-related sequence = access history buffer [n-1:0];

[0162] end if

[0163] The time correlation predictor relies on the physical addresses of the past 12 memory accesses of each memory access instruction recorded in the memory access history buffer, and identifies the time correlation pattern based on the 12 historical information. In the algorithm of the present invention, the same memory access sequence must be repeated 3 times to be confirmed as a time correlation pattern, and supports time correlation patterns with a sequence length of no more than 4.

[0164] In addition to this basic time association pattern, the algorithm of the present invention also supports a "step-time association pattern" such as {A, B, C, A+n, B+n, C+n, A+2n, B+2n, C+2n, ...}.

[0165] (V) Memory access address queue 50

[0166] See also Figure 3 The memory access address queue 50 is used to store the prediction results of the memory access instruction recording module 30 and the memory access mode learning module 40, that is, the memory access instruction sequence output by the memory access instruction recording module 30 and the memory access physical address of each memory access instruction output by the memory access mode learning module 40. The content in the memory access address queue 50 can be regarded as the future access sequence of the first-level data cache.

[0167] The memory access address queue 50 has a plurality of entries, each of which corresponds to information of a memory access instruction and corresponds to an entry in the instruction fetch address queue 20. The memory access address queue 50 has a commit pointer, a read pointer, and a write pointer corresponding to the entries pointed to by the commit pointer, the read pointer, and the write pointer in the instruction fetch address queue 20. Specifically, the commit pointer of the memory access address queue 50 points to the entry of the next instruction to be committed in the memory access address queue 50, the read pointer of the memory access address queue 50 points to the entry of the next instruction to be read in the memory access address queue 50, and the write pointer of the memory access address queue 50 points to the location where the memory access instruction recording module 30 and the memory access mode learning module 40 will write next.

[0168] In this embodiment, the memory access address queue 50 has 65536 entries. 65536 is obtained on the basis that the instruction fetch address queue 20 has 4096 entries. Since each entry of the instruction fetch address queue 20 represents a 64B aligned instruction block, we assume that there are at most 16 memory access instructions in each instruction block, so 4096 instruction blocks contain at most 65536 memory access instructions. Each entry in the memory access address queue 50 corresponds to the information of a memory access instruction, and an entry in each instruction fetch address queue 20 may correspond to 0 to 16 entries of the memory access address queue 50. At this time, since not all 64B instruction blocks have 16 memory access instructions, the capacity of the memory access address queue 50 has design redundancy.

[0169] The structure of each entry in the memory access address queue 50 is represented as follows:

[0170] <valid,inst_line_addr,mem_phys_addr,memlen,inst_queue_index> ,

[0171] Among them, valid represents the valid bit; inst_line_addr represents the instruction linear address; mem_phys_addr represents the memory access physical address; memlen represents the memory access length, and cross-line memory access instructions can be identified based on the memory access physical address and memory access length; inst_queue_index represents the instruction fetch address queue index, which is convenient for synchronous refresh of the instruction fetch address queue and the memory access address queue when the pipeline is refreshed.

[0172] Among them, the instruction linear address inst_line_addr, the memory access length memlen and the instruction fetch address queue index inst_queue_index come from the memory access instruction buffer 31 in the memory access instruction recording module 30, and the memory access physical address mem_phys_addr comes from the memory access mode learning module 40 or the memory access instruction recording module 30. If the memory access mode learning module 40 identifies the step mode and / or time association mode to which the memory access instruction belongs, the memory access physical address of the memory access instruction is given by the corresponding predictor in the memory access mode learning module 40; otherwise, it means that the memory access instruction does not belong to a specific mode, and the memory access physical address comes from the physical address of the memory access instruction in the memory access instruction buffer 31 when it was last executed.

[0173] The following describes the principle of the refresh process of the memory access address queue 50 when a branch refresh occurs in the mainstream pipeline. When a branch refresh occurs in the mainstream pipeline, the execution unit of the mainstream pipeline feeds back the number of the branch instruction in the instruction fetch address queue 20 to the instruction fetch address queue 20, and the read and write pointers of the instruction fetch address queue 20 are rolled back to the branch refresh position according to the number of the branch instruction as the branch instruction refresh pointer. At the same time, the number of the branch instruction in the instruction fetch address queue 20 will also be sent to the memory access address queue 50. The memory access address queue 50 first traverses the queue from the position of the commit pointer, finds the position of the first entry item whose instruction fetch address queue index inst_queue_index is equal to the number of the branch instruction in the instruction fetch address queue 20, which is the position of the branch refresh, and then rolls back the read and write pointers of the memory access address queue 50 to the branch refresh position.

[0174] (VI) Prefetch Request Generation Module 60

[0175] The prefetch request generation module 60 is configured as follows: when the first-level data cache receives a new request, the instruction fetch address queue 20 and the memory access address queue 50 are retrieved, and prefetch requests for the first-level instruction cache and the first-level data cache are generated for the instruction blocks that are about to enter the mainstream pipeline, respectively, and the prefetch requests for the first-level instruction cache and the first-level data cache are sent to the cache system to obtain prefetch requests to obtain data.

[0176] The first-level cache in the processor is divided into a first-level instruction cache and a first-level data cache. The instruction fetch address queue and the memory access address queue are the future memory access sequences of the first-level instruction cache and the first-level data cache, respectively. The instruction fetch address queue 20 stores a complete instruction sequence, including branch instructions, operation instructions, and memory access instructions. The memory access address queue 50 needs to separate the memory access instructions from the complete instruction stream, so the instruction fetch address queue 20 is the basis of the memory access address queue 50.

[0177] like Fig. 9The figure shows the working principle of the pre-fetch request generation module 60. When a new read / write access request arrives at the primary data cache in the memory access unit 400, a message is sent to the pre-fetch request generation module 60 to notify that a new read / write occurs, which serves as a triggering event for the pre-fetch process. The triggering of the pre-fetch process requires a sufficiently frequent event, and as long as the processor is running, there will be access to the primary data cache, so selecting a read / write access request as a triggering condition can ensure the timeliness of pre-fetching.

[0178] According to the above, the memory access physical address of the memory access instruction that is about to enter the main pipeline of the processor is stored in the memory access address queue 50, so each entry of the memory access address queue 50 is a pre-fetch request candidate. However, the prediction bandwidth (128B) of the prediction sub-pipeline is greater than the instruction fetch bandwidth (64B) of the main pipeline of the CPU, and when the main pipeline of the CPU is blocked for some reason, the prediction sub-pipeline can still continue to work, so the prediction sub-pipeline predicts a lot in advance relative to the main pipeline, and the execution rate of the branch prediction sub-pipeline will be far ahead of the execution rate of the main pipeline of the CPU in most cases. The memory access instruction written into the memory access address queue 50 is likely to be executed by the program a long time later. Therefore, the most appropriate time to send the pre-fetch request to the cache system is not the moment when the instruction is written into the memory access address queue 50, but the moment when the instruction block corresponding to the instruction is about to enter the main pipeline. Specifically, the pre-fetch request generation module 60 determines the instruction block that is about to enter the main pipeline according to the read pointer of the instruction fetch address queue 20.

[0179] Therefore, the pre-fetch request generating module 60 is configured to perform the following steps:

[0180] Step B1: After receiving the message that the first-level data cache has received a new request, retrieve the instruction fetch address queue 20 to obtain the position of its read pointer, add a prefetch advance amount to the read pointer as the prefetch start, and use the N consecutive prefetch instruction blocks with the prefetch start as the first prefetch instruction block as the instruction blocks that are about to enter the main pipeline, and generate the corresponding first-level instruction cache prefetch request for the instruction blocks that are about to enter the main pipeline. In this way, preparation is made for implementing the sending process of the first-level instruction cache prefetch request.

[0181] Among them, the instruction blocks after the read pointer of the instruction fetch address queue 20 are all about to enter the pipeline. A prefetch advance amount is added on the basis of the read pointer as the start of the prefetch instruction block (i.e., the prefetch start). The prefetch advance amount is a fixed value, which is measured by the experimental link according to the optimal effect, and the prefetch advance amount does not change the position of the read pointer itself. In this embodiment, the actual value of the prefetch advance amount is 120. Each prefetch process will send a prefetch request for N consecutive prefetch instruction blocks. N is the prefetch number, and the prefetch number N controls the number of prefetch requests that can be issued each time. In this embodiment, the value of the prefetch number N is 4.

[0182] In step B1, the number of valid predicted instruction blocks in the instruction fetch address queue 20 is counted - the distance between the write pointer and the read pointer is used as the number of valid predicted instruction blocks, and whether to continue the prefetch request generation process is determined based on the statistical result. Specifically, only when the statistical result shows that the number of valid predicted instruction blocks is greater than the sum of the prefetch advance amount and the prefetch number N, the prefetch request generation of the first-level instruction cache is continued.

[0183] The arrival of a new request to the first-level data cache is the trigger condition for the prefetch process and is the main switch. The prefetch advance amount and the prefetch number N are similar to a threshold in the control logic, and this threshold can be adjusted.

[0184] Step B2: Receive the pointers of each prefetch instruction block fed back by the instruction fetch address queue 20 (i.e., the number of the prefetch instruction block in the instruction fetch address queue 20), use these prefetch instruction block pointers to retrieve the instruction fetch address in the memory access address queue 50, and the prefetch request for obtaining data at the head of the prefetch queue waits for write-back or immediately writes back to the first-level cache according to the instruction submission status before the prefetch request.

[0185] These prefetch requests that obtain data have data to be written into the first-level cache, but if the prefetch request immediately writes the data back to the cache array after obtaining it, it is possible that the valid data in the cache will be kicked out. Therefore, in order to prevent the cache items with a smaller reuse distance than the prefetch request from being kicked out of the first-level cache during the writing process, the prefetch requests need to be stored in the prefetch queue in chronological order, and the prefetch requests need to wait in the prefetch queue for the time when they can be written back.

[0186] The prefetch queue is a circular queue of 50 items. At the head of the prefetch queue is the prefetch request for the data to be written into the cache. The prefetch request will first wait for the write-back moment in the prefetch queue until it is confirmed that there is a replaceable item in the array of the first-level cache, at which time it is written back to the first-level cache. Among them, if the instruction submission status before the prefetch request is that other instructions in the same group as the prefetch instruction in the array of the first-level cache in the memory access address queue 50 have not been submitted before the prefetch request, it is confirmed that there is a replaceable item in the array of the first-level cache, and the prefetch instruction is written back to the first-level cache.

[0187] Among them, the array of the first-level cache adopts the most common structure, namely the set-associative structure. The array of the first-level cache of 64 items is represented by a 16*4 matrix, where the rows of the matrix are "groups" and the columns of the matrix are "ways". The structure of the 64-item cache array can be described as 16 groups and 4 ways. When performing a write operation, the cache array with a set-associative structure first obtains the group number based on the physical address, and then selects the write way number based on the cache replacement policy to write the pre-fetched requested data.

[0188] like Fig.10 The diagram shows a schematic diagram of the write-back waiting process of a prefetch request, taking a prefetch request of a primary data cache as an example. According to the above, the prefetch request generation module 60 determines the prefetch start according to the prefetch advance amount in the instruction fetch address queue 20, sends the prefetch request M corresponding to the prefetch start in the memory access address queue 50 to the cache system, and obtains the prefetch request to obtain the data. The prefetch request write-back module 70 is configured to temporarily store the prefetch request that obtains data in its prefetch queue; for the prefetch request M at the head of the prefetch queue, the uncommitted instruction set of the memory access address queue 50 after its commit pointer and before the prefetch request M (the uncommitted instruction set includes the commit pointer but does not include the prefetch request M) is retrieved to determine whether there are other memory access instructions in the same group as the prefetch request M in the array of the first-level data cache in the uncommitted instruction set, and based on the determination result (the determination result is that the instruction submission status before the prefetch request), if it is determined that there are other memory access instructions in the same group as the prefetch request M, and the number of memory access instructions in the same group as the prefetch request M is at least the number of ways of the cache array, then the prefetch request M is put on hold for write-back, otherwise, the prefetch request M is immediately written back to the first-level data cache.

[0189] like Fig. 9The addresses of the four memory access instructions A, B, C, and D are in the same group as the prefetch request M. Assuming that the cache array has only 4 way numbers, and the number of instructions in the same group is exactly equal to the number of way numbers in the cache array, then the replacement of any one of the instructions A, B, C, and D by the prefetch request M will affect the performance. At this time, it is necessary to find the position L of the first instruction A in the instruction fetch address queue. Only when the commit pointer of the instruction fetch address queue exceeds L can the prefetch request M be written into the cache array. Therefore, when the commit pointer of the instruction fetch address queue exceeds L, it can be determined that instruction A must have been executed in the main flow of the processor. At this time, the data of the first instruction A is still in the cache array, but because it has been used, replacing the first instruction A with the data of the prefetch request M will not cause performance loss. On the contrary, if the data of the prefetch request M is used to replace the first instruction A before the first instruction A is executed, the first instruction A will generate additional cache failures when it is executed.

[0190] If the prefetch request is a prefetch request for the first-level instruction cache, then it is only necessary to retrieve the instruction fetch address queue 20 accordingly. During program execution, the number of misses in the first-level instruction cache is much less than that in the first-level data cache. The cache prefetch method of the present invention focuses more on the prefetching of data requests. Therefore, the experimental link of the present invention also only experiments on the first-level data cache, because the number of first-level instruction cache failures of many spec programs is 0, and there is no experimental significance in prefetching the first-level instruction cache.

[0191] The low-pollution cache prefetch system based on instruction stream mixed mode learning of the present invention assumes that the prediction of the memory access address queue is accurate. If the prediction is wrong, the logic here may cause some performance loss.

[0192] Based on the low-pollution cache prefetching system based on instruction stream mixed mode learning described above, the low-pollution cache prefetching method based on instruction stream mixed mode learning implemented includes:

[0193] Step S1: using a branch prediction module 10 and an advance prediction technique to predict the instruction stream of the target program and write the prediction result into the instruction fetch address queue; if the instruction fetch address queue 20 is full, the prediction process is suspended;

[0194] The step S1 comprises:

[0195] Step A1: In each cycle, the instruction block where the current prediction address is located is used as the current instruction block, and the current prediction address is used as the prediction start address of the current instruction block; a fixed prediction window starting from the current instruction block is determined according to the prediction start address of the current instruction block;

[0196] Step A2: after obtaining the predicted starting address of the current instruction block, searching and predicting the branch instruction in the current instruction block to determine whether the current instruction block hits the branch instruction for jumping;

[0197] Step A3: According to the judgment result, if the current instruction block does not hit the branch instruction for jumping, it means that there is no branch instruction in the current instruction block or none of the identified branch instructions jump, then the information of the current instruction block is written into the instruction fetch address queue as the prediction result of the branch prediction module 10; then, the predicted starting address of the next instruction block is determined, and the next instruction block is used as the new current instruction block, and the process returns to step A2 until the current instruction block is the last instruction block in the fixed prediction window. At this time, the current prediction address is incremented according to the number of instruction blocks in the fixed prediction window, thereby updating the current prediction address and entering the next cycle;

[0198] Otherwise, the first jump branch instruction with the smallest linear address is selected from the hit jump branch instructions as the end address of the current instruction block, the information of the current instruction block is written into the instruction fetch address queue as the prediction result, and the current predicted address is updated to the jump address of the first jump branch instruction to enter the next cycle.

[0199] Alternatively, the step S1 includes:

[0200] Step A1': In each cycle (i.e., when the current prediction address is initialized or updated), the instruction block where the current prediction address is located is taken as the current instruction block, and the current prediction address is taken as the prediction start address of the current instruction block; then, the prediction start addresses of all instruction blocks in the fixed prediction window starting from the current instruction block are determined according to the prediction start address of the current instruction block;

[0201] Step A2': searching and predicting branch instructions in each instruction block according to the predicted starting address of each instruction block, so as to determine whether each instruction block hits the branch instruction for jumping;

[0202] Step A3': according to the judgment result, if all instruction blocks do not hit the branch instruction of the jump, the information of all instruction blocks is sequentially written into the instruction fetch address queue as the prediction result of the branch prediction module 10; the current prediction address is incremented according to the number of instruction blocks in the fixed prediction window to enter the next cycle;

[0203] Otherwise, if there is at least one instruction block that hits at least one jump branch instruction, the first jump branch instruction with the smallest linear address is selected from the hit jump branch instructions as the end address of the current instruction block, and the information of the current instruction block and all the previous instruction blocks are written into the instruction fetch address queue as the prediction results, and the current predicted address is updated to the jump address of the first jump branch instruction to enter the next cycle.

[0204] Step S2: using a memory access instruction recording module 30 to record information of submitted memory access instructions, and writing the information of these memory access instructions into a memory access instruction buffer; whenever a new entry is written into the instruction fetch address queue 20, the memory access instruction buffer is queried with the starting address of the instruction block corresponding to the entry, so as to obtain a memory access instruction sequence through query attempts and output it to the memory access instruction learning module and the memory access address queue;

[0205] Step S3: using the memory access instruction learning module 40, recording the memory access instruction sequence in the memory access history buffer, learning the memory access mode of the memory access instruction according to the historical information stored in the memory access history buffer, and predicting the memory access physical address of each memory access instruction in the memory access instruction sequence according to the learned memory access mode, and writing the memory access physical address of each memory access instruction into a memory access address queue;

[0206] Step S4: using the pre-fetch request generation module 60, when the primary data cache receives a new request, the instruction fetch address queue and the memory access address queue are retrieved, and pre-fetch requests for the primary instruction cache and the primary data cache are generated for the instruction block that is about to enter the main pipeline, and sent to the cache system to obtain the pre-fetch request for obtaining the data;

[0207] In step S4, the pre-fetch request generation module 60 determines the instruction block that is about to enter the main pipeline according to the read pointer of the instruction fetch address queue 20;

[0208] Step S4 includes:

[0209] Step B1: after receiving a message that the primary data cache has received a new request, the instruction fetch address queue is retrieved to obtain the position of its read pointer, and the position after adding a prefetch advance amount to the read pointer is used as the prefetch start, and the consecutive N prefetch instruction blocks with the prefetch start as the first prefetch instruction block are used as the instruction blocks that are about to enter the main pipeline, and a corresponding primary instruction cache prefetch request is generated for the instruction blocks that are about to enter the main pipeline;

[0210] Step B2: receiving pointers of each prefetch instruction block fed back by the instruction fetch address queue, using the pointers of these prefetch instruction blocks to retrieve the instruction fetch address queue index in the memory access address queue, obtaining the memory access instructions and their memory access physical addresses contained in each prefetch instruction block, and generating a prefetch request for the primary data cache according to the memory access physical addresses of the memory access instructions;

[0211] Step B3: Send both the prefetch request of the first-level instruction cache and the prefetch request of the first-level data cache to the cache system to obtain the prefetch request for obtaining data.

[0212] Step S5: using the prefetch request write-back module 70, temporarily storing the prefetch request that obtains data in its prefetch queue, so that the prefetch request that obtains data at the head of the prefetch queue waits for write-back or immediately writes back to the primary cache according to the instruction submission status before the prefetch request.

[0213] In step S5, for the prefetch request at the head of the prefetch queue, the uncommitted instruction set of the memory access address queue 50 after its commit pointer and before the prefetch request is retrieved, and it is determined whether there are other memory access instructions in the same group as the prefetch request in the first-level cache array in the uncommitted instruction set, and the determination result is used as the instruction submission status before the prefetch request; if it is determined that there are other memory access instructions in the same group as the prefetch request, and the number of memory access instructions in the same group as the prefetch request is at least the number of ways of the cache array, the prefetch request is waited for to be written back, otherwise, the prefetch request M is immediately written back to the first-level cache.

[0214] Experimental verification of the present invention:

[0215] The GEM5 simulator is used as the basic experimental environment, and the alpha instruction set is used. The DerivO3CPU fine-grained CPU model is used, the branch prediction algorithm is TAGE_L, the first-level cache is 32KB, the second-level cache is 256KB, the instruction fetch width is 64B, and the memory is 4GB. The SPEC2006 test program is selected to compare the performance of the method of the present invention with other methods.

[0216] Table 1 Comparison of the number of read operation failures of different spec programs Queue index (i.e., inst_queue_index field) obtains the memory access instructions and their memory access physical addresses contained in each prefetch instruction block, and generates a prefetch request for the first-level data cache based on the memory access physical addresses of the memory access instructions; thereby, preparing for the sending process of the first-level data cache prefetch request.

[0217] Step B3: Send both the prefetch request of the first-level instruction cache and the prefetch request of the first-level data cache to the cache system to obtain the prefetch request for obtaining data.

[0218] Among them, the prefetch request will read 64B aligned data from the memory according to the address, write it into the cache system and finally write it into the first-level cache. Therefore, the data obtained here refers to the 64B data read from the memory.

[0219] (VII) Prefetch request write-back module 70

[0220] The pre-fetch request write-back module 70 is configured to temporarily store the pre-fetch request that obtains the data in its pre-fetch queue so that the bit

[0221] Not prefetched STeMS BOP ISB STRIDE IFBTS lbm 493947 494368 381635 494291 187410 153940 Bzip2 180765 184835 184124 177324 177003 172128 GemsFDTD 586680 586701 553972 586635 510435 123719 gobmk 67463 69636 68240 66167 51302 58829 astar 91 89 90 91 91 74 H264ref 261561 263830 215465 260042 91558 61381 hmmer 43410 44040 43019 43199 41924 4352 Soplex 813733 811522 624612 813817 287799 230243 Bwaves 578612 578703 372337 578611 174377 88849 sjeng 10160 12003 11090 9908 10475 11458

[0222] Table 2 Comparison of write operation failure times of different spec programs

[0223] Not prefetched STeMS BOP ISB STRIDE IFBTS lbm 427392 423352 358226 393252 153874 140457 Bzip2 18306 18247 17967 18248 15809 15655 GemsFDTD 3 3 3 3 3 3 gobmk 58343 58857 58022 56175 47325 53317 astar 65564 65564 59548 65564 39296 18915 H264ref 4611 4685 5291 4614 4426 3017 hmmer 168577 168488 165541 168519 153174 6492 Soplex 106596 106552 89808 106605 73147 51185 bwaves 23 23 23 23 23 23 sjeng 27395 27873 29417 27252 24206 28584

[0224] When performing performance comparison, we counted the number of cache failures for read / write operations of the first-level data cache. As shown in Tables 1 and 2, for read operations, the method of the present invention reduces the number of cache failures by an average of 28.26%, 51.47%, 47.28%, and 48.75% compared with STRIDE, STeMS, BOP, and ISB algorithms, respectively; for write operations, the method of the present invention reduces the number of cache failures by an average of 18.84%, 34.28%, 33.49%, and 33.26% compared with STRIDE, STeMS, BOP, and ISB algorithms, respectively.

[0225] That is to say, currently, the performance of high-performance processors cannot be fully utilized due to the bottleneck of the cache system, and the system and method of the present invention have a significant effect on improving processor performance.

[0226] The method of the present invention is applicable to all processor microarchitectures and is not limited to specific branch prediction algorithms and instruction sets. Of course, due to differences in instruction sets and specific processor microarchitectures, the specific implementation process may vary slightly, but it also falls within the scope of protection of the present invention.

[0227] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. A person skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A low-pollution cache prefetching system based on instruction stream mixed mode learning, characterized in that: It includes a main pipeline and a branch prediction sub-pipeline, wherein the branch prediction sub-pipeline includes a branch prediction module, an instruction fetch address queue, a memory access instruction recording module, a memory access mode learning module, a memory access address queue, a prefetch request generation module and a prefetch request write-back module; The branch prediction module is configured to use an advance prediction technique to predict the instruction stream of the target program and write the prediction result into the instruction fetch address queue; The memory access instruction recording module is configured to sequentially record information of submitted memory access instructions and write the information of the memory access instructions into its memory access instruction buffer; at the same time, whenever a new entry is written into the instruction fetch address queue, the memory access instruction buffer is queried with the starting address of the instruction block corresponding to the entry, so as to obtain a memory access instruction sequence through query attempts and output it to the memory access instruction learning module and the memory access address queue; The memory access mode learning module is configured to record the memory access instruction sequence in its memory access history buffer, learn the memory access mode of the memory access instruction according to the historical information stored in the memory access history buffer, and predict the memory access physical address of each memory access instruction in the memory access instruction sequence according to the learned memory access mode and write it into the memory access address queue; The pre-fetch request generation module is configured to retrieve the instruction fetch address queue and the memory access address queue when the first-level data cache receives a new request, and respectively generate pre-fetch requests for the first-level instruction cache and the first-level data cache for the instruction block that is about to enter the main pipeline and send them to the cache system to obtain the pre-fetch request to obtain the data; The prefetch request write-back module is configured to temporarily store the prefetch request that obtains data in its prefetch queue, so that the prefetch request that obtains data at the head of the prefetch queue waits for write-back or immediately writes back to the primary cache according to the instruction submission status before the prefetch request.

2. The low-pollution cache prefetching system based on instruction stream mixed mode learning according to claim 1, characterized in that: The branch prediction module is configured to write the prediction result into the instruction fetch address queue with instruction block as the granularity; and the branch prediction module is configured to execute: Step A1: In each cycle, the instruction block where the current prediction address is located is used as the current instruction block, and the current prediction address is used as the prediction start address of the current instruction block; a fixed prediction window starting from the current instruction block is determined according to the prediction start address of the current instruction block; Step A2: after obtaining the predicted starting address of the current instruction block, searching and predicting the branch instruction in the current instruction block to determine whether the current instruction block hits the branch instruction for jumping; Step A3: According to the judgment result, if the current instruction block does not hit the branch instruction to jump, it means that there is no branch instruction in the current instruction block or the identified branch instructions do not jump, then the information of the current instruction block is written into the instruction fetch address queue as the prediction result of the branch prediction module; then, the predicted starting address of the next instruction block is determined, and the next instruction block is used as the new current instruction block, and the process returns to step A2 until the current instruction block is the last instruction block in the fixed prediction window, at which time the current prediction address is incremented according to the number of instruction blocks in the fixed prediction window to enter the next cycle; Otherwise, the first jump branch instruction with the smallest linear address is selected from the hit jump branch instructions as the end address of the current instruction block, the information of the current instruction block is written into the instruction fetch address queue as the prediction result, and the current prediction address is updated to the jump address of the first jump branch instruction to enter the next cycle; Alternatively, the branch prediction module is configured to write the prediction result into the instruction fetch address queue with instruction blocks as the granularity; and the branch prediction module is configured to execute: Step A1': in each cycle, the instruction block where the current prediction address is located is taken as the current instruction block, and the current prediction address is taken as the prediction start address of the current instruction block; then, the prediction start addresses of all instruction blocks in the fixed prediction window starting from the current instruction block are determined according to the prediction start address of the current instruction block; Step A2': searching and predicting branch instructions in each instruction block according to the predicted starting address of each instruction block, so as to determine whether each instruction block hits the branch instruction for jumping; Step A3': According to the judgment result, if all instruction blocks do not hit the branch instruction of the jump, the information of all instruction blocks is written into the instruction fetch address queue in sequence as the prediction result of the branch prediction module; the current prediction address is incremented according to the number of instruction blocks in the fixed prediction window to enter the next cycle; Otherwise, if there is at least one instruction block that hits at least one jump branch instruction, the first jump branch instruction with the smallest linear address is selected from the hit jump branch instructions as the end address of the current instruction block, and the information of the current instruction block and all the previous instruction blocks are written into the instruction fetch address queue as the prediction results, and the current predicted address is updated to the jump address of the first jump branch instruction to enter the next cycle.

3. The low-pollution cache prefetching system based on instruction stream mixed mode learning according to claim 2, characterized in that: The main pipeline includes an instruction fetch unit, a decoding unit, an execution unit, a memory access unit and a write-back unit connected in sequence, and in the branch prediction module, the bit width of the instruction block is equal to the bit width of the instruction fetch unit when fetching instructions; The information of the instruction block includes a row linear address, a row physical address, a start offset, an end offset and a jump bit of the instruction block; when writing the information of the instruction block into the instruction fetch address queue, the predicted start address of the instruction block is split into a high-order row linear address and a low-order start offset, and the row physical address is obtained by querying the TLB through the row linear address, and the obtained row linear address, row physical address and start offset are written into the corresponding fields in the entry item of the instruction fetch address queue; In addition, if the instruction block hits a jump branch instruction, the end byte offset of the first jump branch instruction is written into the instruction fetch address queue as the end offset; otherwise, the end offset in the instruction fetch address queue is set to 63.

4. The low-pollution cache prefetching system based on instruction stream mixed mode learning according to claim 1, characterized in that: The structure of each entry in the instruction fetch address queue is: <valid,line_addr,phys_addr,begin_offset,end_offset,taken> , Among them, valid represents the valid bit; line_addr represents the line linear address; phys_addr represents the line physical address; begin_offset represents the starting offset; end_offset represents the ending offset; taken represents the jump bit; The instruction fetch address queue is also provided with a commit pointer, a read pointer and a write pointer; the commit pointer of the instruction fetch address queue points to the entry item of the instruction block where the next instruction to be committed is located in the instruction fetch address queue; the read pointer of the instruction fetch address queue points to the entry item of the instruction block where the next instruction to be read is located in the instruction fetch address queue; the write pointer of the instruction fetch address queue points to the position where the branch prediction module will write next; after the mainstream pipeline of the processor is refreshed, the read pointer and the write pointer of the instruction fetch address queue are rolled back to the position of the branch refresh or the position of the commit pointer according to the refresh type; The structure of each entry in the memory access instruction buffer is: <LineAddr,PhyAddr,InstType,Memlen> , Wherein, LineAddr indicates the instruction linear address of the memory access instruction; PhyAddr indicates the memory access physical address of the memory access instruction at the last execution; InstType indicates the type of the memory access instruction, InstType∈{DirectInst,InDirectInst}, where DirectInst indicates a direct memory access instruction and InDirectInst indicates an indirect memory access instruction; Memlen indicates the memory access length of the memory access instruction; The memory access history buffer is an array indexed by the PC of the memory access instruction, and each entry in the memory access history buffer records the physical addresses of the past 12 memory accesses of the same memory access instruction; And the structure of each entry in the memory access address queue is: <valid,inst_line_addr,mem_phys_addr,memlen,inst_queue_index> , Among them, valid represents the valid bit; inst_line_addr represents the instruction linear address; mem_phys_addr represents the memory access physical address; memlen represents the memory access length; inst_queue_index represents the instruction fetch address queue index; The memory access address queue has a commit pointer, a read pointer and a write pointer; when a branch refresh occurs in the main pipeline, the read pointer and the write pointer of the memory access address queue are rolled back to the position of the branch refresh.

5. The low-pollution cache prefetching system based on instruction stream mixed mode learning according to claim 4, characterized in that: The branch prediction module is configured to: suspend the prediction process if the instruction fetch address queue is full; whether the instruction fetch address queue is full is determined based on a combination of a write pointer and a commit pointer of the instruction fetch address queue.

6. The low-pollution cache prefetching system based on instruction stream mixed mode learning according to claim 1, characterized in that: In the memory access instruction recording module, the information of the memory access instruction includes the PC of the memory access instruction, the instruction linear address, the memory access address, the type and the memory access length of the memory access instruction; The memory access instruction recording module is configured to use the instruction linear addresses of the memory access instructions in all table entries of the memory access instruction buffer to perform a hit judgment during the query process, and obtain the position and type of the memory access instruction in the memory access instruction buffer when the memory access instruction hits, thereby attempting to obtain the position and type of the memory access instruction in the memory access instruction buffer by querying all the memory access instructions in the memory access instruction buffer; when performing a hit judgment, when there is a memory access instruction in the memory access instruction buffer whose instruction linear address has a high-order tag that is the same as the row linear address of the instruction block corresponding to the new entry, and its low-order offset is greater than or equal to the starting offset of the instruction block and less than or equal to the ending offset of the instruction block, then the memory access instruction hits, and the position and type of the memory access instruction in the memory access instruction buffer are obtained.

7. The low-pollution cache prefetching system based on instruction stream mixed mode learning according to claim 1, characterized in that: The memory access pattern learning module includes a step length predictor and a time association predictor, so that the memory access pattern learning module can learn and predict the step length pattern and the time association pattern through the step length predictor and the time association predictor based on the memory access history buffer; Each entry of the step length predictor is used to record a step length mode, and the step length mode refers to a step length memory access sequence; each entry of the step length predictor includes a tag of a step length memory access sequence, a previous address, a previous step length, a trusted counter, a current mode, a first address, a maximum counter and a direction; Each entry of the time correlation predictor is used to record a time correlation pattern, which refers to a time correlation memory access sequence. Each entry of the time correlation predictor includes the time correlation pattern, the time correlation sequence length and the time correlation sequence.

8. The low-pollution cache prefetching system based on instruction stream mixed mode learning according to claim 1, characterized in that: The pre-fetch request generation module determines the instruction block that is about to enter the main pipeline according to the read pointer of the instruction fetch address queue; The pre-fetch request generation module is configured to perform the following steps: Step B1: after receiving a message that the primary data cache has received a new request, the instruction fetch address queue is retrieved to obtain the position of its read pointer, and the position after adding a prefetch advance amount to the read pointer is used as the prefetch start, and the consecutive N prefetch instruction blocks with the prefetch start as the first prefetch instruction block are used as the instruction blocks that are about to enter the main pipeline, and a corresponding primary instruction cache prefetch request is generated for the instruction blocks that are about to enter the main pipeline; Step B2: receiving pointers of each prefetch instruction block fed back by the instruction fetch address queue, using the pointers of these prefetch instruction blocks to retrieve the instruction fetch address queue index in the memory access address queue, obtaining the memory access instructions and their memory access physical addresses contained in each prefetch instruction block, and generating a prefetch request for the primary data cache according to the memory access physical addresses of the memory access instructions; Step B3: Send both the prefetch request of the first-level instruction cache and the prefetch request of the first-level data cache to the cache system to obtain the prefetch request for obtaining data.

9. The low-pollution cache prefetching system based on instruction stream mixed mode learning according to claim 1, characterized in that: The prefetch request write-back module is configured as follows: for a prefetch request located at the head of the prefetch queue, the uncommitted instruction set of the memory access address queue after its commit pointer and before the prefetch request is retrieved, and it is determined whether there are other memory access instructions in the same group as the prefetch request in the first-level cache array in the uncommitted instruction set, and the determination result is used as the instruction submission status before the prefetch request; if it is determined that there are other memory access instructions in the same group as the prefetch request, and the number of memory access instructions in the same group as the prefetch request is at least the number of ways of the cache array, the prefetch request is put on hold for write-back, otherwise, the prefetch request is immediately written back to the first-level cache.

10. A low-pollution cache prefetching method based on instruction stream mixed mode learning, characterized in that: include: Step S1: using a branch prediction module and an advance prediction technique, predicting the instruction stream of the target program and writing the prediction result into an instruction fetch address queue; If the instruction fetch address queue is full, the prediction process is suspended; Step S2: using the memory access instruction recording module to record the information of the memory access instructions that have been submitted, and writing the information of the memory access instructions into a memory access instruction buffer; whenever a new entry is written into the instruction fetch address queue, querying the memory access instruction buffer with the starting address of the instruction block corresponding to the entry, so as to obtain the memory access instruction sequence through querying and output it to the memory access instruction learning module and the memory access address queue; Step S3: using a memory access instruction learning module, recording a memory access instruction sequence in a memory access history buffer, learning a memory access mode of the memory access instruction according to the historical information stored in the memory access history buffer, and predicting a memory access physical address of each memory access instruction in the memory access instruction sequence according to the learned memory access mode, and writing the memory access physical address of each memory access instruction into a memory access address queue; Step S4: using the pre-fetch request generation module, when the primary data cache receives a new request, the instruction fetch address queue and the memory access address queue are retrieved, and pre-fetch requests for the primary instruction cache and the primary data cache are generated for the instruction block that is about to enter the main pipeline, and sent to the cache system to obtain the pre-fetch request for obtaining the data; Step S5: using the prefetch request write-back module, temporarily storing the prefetch request that obtains data in its prefetch queue, so that the prefetch request that obtains data at the head of the prefetch queue waits for write-back or immediately writes back to the primary cache according to the instruction submission status before the prefetch request.

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