Display substrate, manufacturing method and display device

Abstract

The present invention provides a display substrate, a manufacturing method and a display device. The display substrate includes a pixel circuit; the display substrate includes a first conductive layer, a semiconductor layer and a first gate metal layer; the pixel circuit includes a light-emitting element, a data writing circuit and a driving circuit; the data writing circuit includes a first transistor; the second gate of the first transistor is included in the first conductive layer, and the first gate of the first transistor is included in the first gate metal layer; the active layer of the first transistor is included in the semiconductor layer; the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first end of the driving circuit; the second end of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to drive the light-emitting element to emit light. The present invention can improve the abnormal display phenomenon of black screens and improve the reliability of display products.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate, a manufacturing method and a display device. Background Art

[0002] Compared with mobile phone display products, vehicle-mounted OLED (organic light-emitting diode) display products have a harsh working environment and display static images for a long time, which greatly tests the reliability of vehicle-mounted OLED display products. In actual operation, vehicle-mounted OLED display products are prone to abnormal black screen display. Related vehicle-mounted OLED display products use a typical 7T1C pixel circuit. When the vehicle-mounted OLED display product displays a black screen for a long time, the gate-source voltage of the transistor used for data writing is closer to the threshold voltage. Therefore, if the threshold voltage of the transistor used for data writing is positively shifted, it will cause the transistor used for data writing to be unable to be turned off during the display stage, causing the potential of the data writing node (the data writing node is electrically connected to the first end of the driving circuit included in the pixel circuit) to be pulled up, resulting in abnormal light emission when the black screen is displayed. Summary of the invention

[0003] The main purpose of the present invention is to provide a display substrate, a manufacturing method and a display device to solve the problem of abnormal display when the related display device displays a black screen.

[0004] In order to achieve the above-mentioned object, an embodiment of the present invention provides a display substrate, comprising a base substrate, and a plurality of rows and columns of pixel circuits arranged in a display area of ​​the base substrate; the display substrate comprises a first conductive layer, a semiconductor layer and a first gate metal layer stacked in sequence in a direction away from the base substrate;

[0005] The pixel circuit includes a light emitting element, a data writing circuit and a driving circuit; the data writing circuit includes a first transistor;

[0006] The first gate of the first transistor is electrically connected to the scan line, and the second gate of the first transistor is electrically connected to the control voltage line; the second gate of the first transistor is included in the first conductive layer, and the first gate of the first transistor is included in the first gate metal layer; the active layer of the first transistor is included in the semiconductor layer;

[0007] A first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to a first end of the driving circuit;

[0008] The second end of the driving circuit is electrically connected to the light emitting element, and the driving circuit is used to drive the light emitting element to emit light.

[0009] Optionally, the control voltage line is a DC voltage line; the display substrate further comprises a source-drain metal layer disposed on a side of the first gate metal layer facing away from the base substrate; the DC voltage line is included in the source-drain metal layer;

[0010] The second gate of the first transistor is electrically connected to the DC voltage line through a via hole.

[0011] Optionally, the control voltage line and the scan line are connected to the same scan signal; the scan line is included in the first gate metal layer;

[0012] The control voltage line and the second gate of the first transistor are located in the same layer, and the control voltage line is electrically connected to the second gate of the first transistor.

[0013] Optionally, the orthographic projection of the second gate of the first transistor on the substrate covers the orthographic projection of the channel region included in the active layer of the first transistor on the substrate.

[0014] Optionally, the first conductive layer is a molybdenum metal layer or an aluminum alloy layer.

[0015] Optionally, the conductive layer is reused as a light shielding layer.

[0016] Optionally, the pixel circuit further includes a first initialization circuit and a compensation control circuit; the first initialization circuit includes a second transistor, and the compensation control circuit includes a third transistor; the first gate of the second transistor and the second gate of the second transistor are both electrically connected to a reset control line, the first electrode of the second transistor is electrically connected to an initial voltage line, and the second electrode of the second transistor is electrically connected to a control end of the drive circuit; the first gate of the third transistor and the second gate of the third transistor are electrically connected to the scan line, the first electrode of the third transistor is electrically connected to the control end of the drive circuit, and the second electrode of the third transistor is electrically connected to the second end of the drive circuit;

[0017] The first gate of the second transistor, the second gate of the second transistor, the first gate of the third transistor and the second gate of the third transistor are all included in the first gate metal layer;

[0018] An active layer of the second transistor and an active layer of the third transistor are both included in the semiconductor layer.

[0019] Optionally, the driving circuit includes a driving transistor, a gate of the driving transistor is a control terminal of the driving circuit, and a second electrode of the driving transistor is a second terminal of the driving circuit;

[0020] The reset control line and the scan line are both included in a first gate metal layer; the display substrate further includes a second gate metal layer and a source-drain metal layer which are sequentially stacked on a side of the first gate metal layer away from the base substrate; the initial voltage line is included in the second gate metal layer;

[0021] The first electrode of the second transistor, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the third transistor, the first electrode of the driving transistor, and the second electrode of the driving transistor are included in the semiconductor layer;

[0022] The first electrode of the second transistor is electrically connected to a first conductive connection pattern, the first conductive connection pattern is included in the source-drain metal layer, and the first conductive connection pattern is electrically connected to the initial voltage line, so that the first electrode of the second transistor is electrically connected to the initial voltage line;

[0023] The gate of the driving transistor is included in the first gate metal layer, the second electrode of the second transistor is electrically connected to the second conductive connection pattern, the second conductive connection pattern is included in the source-drain metal layer, and the second conductive connection pattern is electrically connected to the gate of the driving transistor, so that the second electrode of the second transistor is electrically connected to the gate of the driving transistor;

[0024] The first electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the third transistor is connected to the second electrode of the driving transistor.

[0025] Optionally, the driving circuit includes a driving transistor, and the first electrode of the driving transistor is the first end of the driving circuit; the display substrate further includes a source-drain metal layer arranged on a side of the first gate metal layer away from the base substrate;

[0026] The data line is included in the source-drain metal layer, and the first electrode of the first transistor, the second electrode of the first transistor and the first electrode of the driving transistor are included in the semiconductor layer;

[0027] The first electrode of the first transistor is electrically connected to the data line through a via hole, and the second electrode of the first transistor is connected to the first electrode of the driving transistor.

[0028] Optionally, the pixel circuit further includes a first light-emitting control circuit and a second light-emitting control circuit; the driving circuit includes a driving transistor; the first light-emitting control circuit includes a fourth transistor, and the second light-emitting control circuit includes a fifth transistor; the display substrate further includes a source-drain metal layer and an anode layer stacked in sequence on a side of the first gate metal layer away from the base substrate;

[0029] The gate of the fourth transistor, the light emitting control line, the gate of the fifth transistor and the gate of the driving transistor are all included in the first gate metal layer;

[0030] The first voltage line is included in the source-drain metal layer; the first electrode of the fourth transistor, the second electrode of the fourth transistor, the first electrode of the fifth transistor and the second electrode of the fifth transistor are all included in the semiconductor layer;

[0031] The gate of the fourth transistor is electrically connected to the light emitting control line, the first electrode of the fourth transistor is electrically connected to the first voltage line, and the second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0032] The gate of the fifth transistor is electrically connected to the light-emitting control line, the first electrode of the fifth transistor is connected to the second electrode of the driving transistor, the second electrode of the fifth transistor is electrically connected to a third conductive connection pattern, the third conductive connection pattern is included in the source-drain metal layer, and the third conductive connection pattern is electrically connected to the anode of the light-emitting element; the anode of the light-emitting element is included in the anode layer.

[0033] Optionally, the control voltage line is the first voltage line;

[0034] The second gate of the first transistor is electrically connected to the first voltage line through a via hole.

[0035] Optionally, the pixel circuit further includes a second initialization circuit and a storage circuit; the second initialization circuit includes a sixth transistor; the storage circuit includes a storage capacitor; the display substrate further includes a second gate metal layer disposed between the first gate metal layer and the source-drain metal layer;

[0036] The gate of the sixth transistor and the scan line are both included in the first gate metal layer; the first electrode of the sixth transistor and the second electrode of the sixth transistor are both included in the semiconductor layer;

[0037] The gate of the driving transistor is reused as the first plate of the storage capacitor;

[0038] The gate of the sixth transistor is electrically connected to the scan line, and the first electrode of the sixth transistor is connected to the first electrode of the second transistor, so that the first electrode of the sixth transistor is electrically connected to the initial voltage line;

[0039] The second electrode plate of the storage capacitor is included in the second gate metal layer, and the second electrode plate of the storage capacitor is electrically connected to the first voltage line.

[0040] An embodiment of the present invention further provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate. The method for manufacturing the display substrate includes:

[0041] A first conductive layer is formed on one surface of the substrate, and a patterning process is performed on the first conductive layer to form a second gate of the first transistor;

[0042] A semiconductor layer is formed on a side of the first conductive layer facing away from the substrate; a first gate metal layer is formed on a side of the semiconductor layer facing away from the first conductive layer, and the first gate metal layer is patterned to form a first gate of the first transistor and gates of other transistors included in the pixel circuit except the first transistor;

[0043] Using the first gate of the first transistor as a mask, the portion of the semiconductor layer that is not covered by the first gate of the first transistor and the gates of other transistors included in the pixel circuit except the first transistor is doped, so that the portion of the semiconductor layer that is not covered by the first gate of the first transistor and the gates of other transistors included in the pixel circuit except the first transistor is formed as a conductive portion, and the portion of the semiconductor layer that is covered by the first gate of the first transistor and the gates of other transistors included in the pixel circuit except the first transistor is formed as a channel region.

[0044] An embodiment of the present invention further provides a display device, comprising the above-mentioned display substrate.

[0045] The display substrate, manufacturing method and display device described in the embodiments of the present invention can make the characteristics of the first transistor negatively biased to a safe range by simply adding a first conductive layer without changing the TFT (thin film transistor) related processes, thereby improving the abnormal display phenomenon of black screens and improving the reliability of display products. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1A is a structural diagram of a pixel circuit included in a display substrate according to at least one embodiment of the present invention;

[0047] Figure 1B is a structural diagram of a pixel circuit included in a display substrate according to at least one embodiment of the present invention;

[0048] Figure 2 is a circuit diagram of a pixel circuit included in a display substrate according to at least one embodiment of the present invention;

[0049] Figure 3 is Figure 2 A schematic diagram of adding labels for each electrode on the basis of FIG.

[0050] Figure 4 yes Fig. 9 A layout diagram of a first conductive layer in;

[0051] Figure 5 yes Fig. 9 A layout diagram of a semiconductor layer in FIG.

[0052] Figure 6 yes Fig. 9 A layout diagram of a first gate metal layer in FIG.

[0053] Figure 7 yes Fig. 9 A layout diagram of a second gate metal layer in FIG.

[0054] Figure 8 yes Fig. 9 Layout diagram of source and drain metal layers in FIG.

[0055] Fig. 9 is a layout diagram of a display substrate according to at least one embodiment of the present invention;

[0056] Fig.10 yes Fig. 9 A cross-sectional view of at least one embodiment of a display substrate shown;

[0057] Fig.11A is a schematic diagram of a threshold voltage of the first transistor when a 0V voltage signal is connected to the second gate of the first transistor;

[0058] Fig. 11B is a schematic diagram of a threshold voltage of the first transistor when a second gate of the first transistor is connected to a 4.6V voltage signal;

[0059] Fig. 11C is a schematic diagram of the threshold voltage of the first transistor when the second gate of the first transistor is connected to a 7V voltage signal;

[0060] Fig.11D is a schematic diagram of the threshold voltage of the first transistor when the second gate of the first transistor is connected to a scan signal. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] The transistors used in all embodiments of the present invention can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one electrode is called the first electrode and the other electrode is called the second electrode.

[0063] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0064] The display substrate described in the embodiment of the present invention comprises a base substrate, and a plurality of rows and columns of pixel circuits arranged in a display area of ​​the base substrate; the display substrate comprises a first conductive layer, a semiconductor layer and a first gate metal layer stacked in sequence in a direction away from the base substrate;

[0065] The pixel circuit includes a light emitting element, a data writing circuit and a driving circuit; the data writing circuit includes a first transistor;

[0066] The first gate of the first transistor is electrically connected to the scan line, and the second gate of the first transistor is electrically connected to the control voltage line; the second gate of the first transistor is included in the first conductive layer, and the first gate of the first transistor is included in the first gate metal layer; the active layer of the first transistor is included in the semiconductor layer;

[0067] A first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to a first end of the driving circuit;

[0068] The second end of the driving circuit is electrically connected to the light emitting element, and the driving circuit is used to drive the light emitting element to emit light.

[0069] In at least one embodiment of the present invention, the active layer of the first transistor includes a channel region of the first transistor, a first electrode of the first transistor, and a second electrode of the first transistor.

[0070] In an embodiment of the present invention, the display substrate may include a plurality of rows and columns of pixel circuits arranged in a display area, the pixel circuits include a data writing circuit, and the data writing circuit includes a first transistor; the first electrode of the first transistor is a top gate, the second electrode of the first transistor is a bottom gate, and the second electrode of the first transistor is included in a first conductive layer. The second electrode of the first transistor is electrically connected to a control voltage line to achieve Vth negative bias control, wherein Vth is a threshold voltage of the first transistor. The embodiment of the present invention can make the characteristics of the first transistor negatively biased to a safe range by only adding a first conductive layer without changing the TFT (thin film transistor) related process, and the structure is simple and controllable.

[0071] In an embodiment of the present invention, the characteristic negative bias control of the first transistor can improve the abnormal display phenomenon of the black screen when the characteristic of the vehicle-mounted OLED (organic light emitting diode) pixel circuit is forward biased under a long-term forward bias voltage, thereby extending the life of the display product and improving the reliability of the display product.

[0072] In the related art, when the 7T1C pixel circuit is used to display a black screen, the voltage value of the data voltage can be 6.5V, then the gate-source voltage of the transistor used to initialize the gate of the driving transistor can be between 2.5V and 3V, the gate-source voltage of the transistor used for threshold voltage compensation can be greater than or equal to 2.5V and less than or equal to 3V, the gate-source voltage of the transistor used for data writing can be greater than or equal to 0V and less than or equal to 5V, the threshold voltage of the transistor used to initialize the gate of the driving transistor and the threshold voltage of the transistor used for threshold voltage compensation are greater than or equal to -3V and less than or equal to -2V, and the threshold voltage offset risk of the transistor used for data writing is higher. Based on this, the embodiment of the present invention adds a first conductive layer to make the characteristics of the first transistor (the first transistor is a transistor used for data writing) negatively biased to a safe range.

[0073] Optionally, the control voltage line may be a DC voltage line; or, the control voltage line and the scan line are connected to the same scan signal.

[0074] According to a specific embodiment, the control voltage line is a DC voltage line; the display substrate further comprises a source-drain metal layer disposed on a side of the first gate metal layer facing away from the base substrate; the DC voltage line is included in the source-drain metal layer;

[0075] The second gate of the first transistor is electrically connected to the DC voltage line through a via hole.

[0076] In a specific implementation, the control voltage line can be a DC voltage line. For example, the DC voltage signal provided by the control voltage line can be the first voltage line VDD or the second voltage line VGH. The voltage value of the first voltage signal provided by the first voltage line VDD can be 4.6V, and the voltage value of the second voltage signal provided by the second voltage line VGH can be 7V, but is not limited to this.

[0077] According to another specific implementation, the control voltage line and the scan line are connected to the same scan signal; the scan line is included in the first gate metal layer; the substrate further includes a peripheral area; the peripheral area surrounds the display area;

[0078] The control voltage line is located in the same layer as the second gate of the first transistor and is electrically connected to the second gate of the first transistor. The control voltage line extends to the peripheral area; in the peripheral area, the control voltage line is electrically connected to the scan line.

[0079] In a specific implementation, the control voltage line can be connected to the same scan signal as the scan line, and in the peripheral area, the control voltage line is electrically connected to the scan line.

[0080] In at least one embodiment of the present invention, the orthographic projection of the second gate of the first transistor on the substrate covers the orthographic projection of the channel region in the active layer of the first transistor on the substrate, which helps to make the characteristics of the active layer uniform and is beneficial to the uniformity of the characteristics of the first transistor.

[0081] Optionally, the first conductive layer is a molybdenum metal layer or an aluminum alloy layer.

[0082] In at least one embodiment of the present invention, the conductive layer can be reused as a light shielding layer to prevent the transistor from having characteristic deviation under light.

[0083] like Figure 1A As shown, the pixel circuit included in the display substrate according to at least one embodiment of the present invention may include a light emitting element EL, a data writing circuit 11, a driving circuit 10, a first initialization circuit 12, a compensation control circuit 13, a second initialization circuit 14, a first light emitting control circuit 15, a second light emitting control circuit 16 and an energy storage circuit 17;

[0084] The data writing circuit 11 includes a first transistor T1;

[0085] The data writing circuit 11 is electrically connected to the scan line Gate, the control voltage line V0, the data line Data and the first end of the driving circuit 10 respectively, and is used to control the connection or disconnection between the first end of the driving circuit 10 and the data line Data under the control of the scan signal provided by the scan line Gate and the control voltage provided by the control voltage line V0;

[0086] like Figure 1B As shown, the first gate of the first transistor T1 is electrically connected to the scan line Gate, the second gate of the first transistor T1 is electrically connected to the control voltage line V0, the first electrode of the first transistor T1 is electrically connected to the data line Data, and the second electrode of the first transistor T1 is electrically connected to the first end of the driving circuit 10; the first gate of the first transistor T1 is a top gate, and the second gate of the first transistor T1 is a bottom gate;

[0087] The first initialization circuit 12 is electrically connected to the reset control line Reset, the initial voltage line I1 and the control end of the driving circuit 10 respectively, and is used to control the initial voltage Vi provided by the initial voltage line I1 to be written into the control end of the driving circuit 10 under the control of the reset control signal provided by the reset control line Reset;

[0088] The compensation control circuit 13 is electrically connected to the scan line Gate, the control end of the drive circuit 10 and the second end of the drive circuit 10 respectively, and is used to control the control end of the drive circuit 10 to be connected to the second end of the drive circuit 10 under the control of the scan signal provided by the scan line Gate;

[0089] The first light emitting control circuit 15 is electrically connected to the light emitting control line EM, the first voltage line VDD and the first end of the driving circuit 10 respectively, and is used to control the connection between the first voltage line VDD and the first end of the driving circuit 10 under the control of the light emitting control signal provided by the light emitting control line EM;

[0090] The second light emitting control circuit 16 is electrically connected to the light emitting control line EM, the second end of the driving circuit 10 and the first electrode of the light emitting element EL respectively, and is used to control the second end of the driving circuit 10 to be connected to the first electrode of the light emitting element EL under the control of the light emitting control signal;

[0091] The second initialization circuit 14 is electrically connected to the scan line Gate, the initial voltage line I1 and the first electrode of the light emitting element EL respectively, and is used to write the initial voltage Vi provided by the initial voltage line I1 into the first electrode of the light emitting element EL under the control of the scan signal; the second electrode of the light emitting element EL is electrically connected to the third voltage line VSS;

[0092] The first end of the energy storage circuit 17 is electrically connected to the control end of the driving circuit 10, the second end of the energy storage circuit 17 is electrically connected to the first voltage line VDD, and the energy storage circuit 17 is used to store electric energy;

[0093] The driving circuit 10 is used to generate a driving current for driving the light emitting element EL under the control of the potential of the control terminal thereof.

[0094] exist Figure 1A , Figure 1B In at least one embodiment of the pixel circuit shown, the first voltage line VDD may be a high voltage line, and the third voltage line VSS may be a low voltage line;

[0095] The light emitting element may be an organic light emitting diode, the first electrode of the light emitting element may be an anode, and the second electrode of the light emitting element may be a cathode.

[0096] In the related art, when the vehicle-mounted OLED pixel circuit is actually used, the product displays a certain pattern for a long time, such as displaying the L0 screen (black screen), which will cause the first transistor in the data writing circuit of the vehicle-mounted OLED pixel circuit to be under positive stress for a long time, and the threshold voltage of the first transistor is continuously positively biased, and the risk of abnormal display of a black screen is extremely high. Based on the above analysis, in order to ensure that the first transistor is normal when the vehicle-mounted display product is used, it is necessary to ensure that the threshold voltage of the first transistor is about 2V negative than the threshold voltage of other transistors, but it is not limited to this.

[0097] In at least one embodiment of the present invention, the first transistor T1 is designed as a dual-gate transistor, wherein the first gate of the first transistor T1 is a top gate and the second gate of the first transistor T1 is a bottom gate, so that the threshold voltage of the first transistor T1 can be negatively biased by 1V-2V, thereby ensuring that the first transistor T1 is normal when the vehicle-mounted display product is used.

[0098] like Figure 2 As shown, in Figure 1B Based on at least one embodiment of the pixel circuit shown, the first initialization circuit 12 includes a second transistor T2, the compensation control circuit 13 includes a third transistor T3; the driving circuit 10 includes a driving transistor T0; the light emitting element is an organic light emitting diode O1;

[0099] The first gate of the second transistor T2 and the second gate of the second transistor T2 are both electrically connected to the reset control line Reset, the first electrode of the second transistor T2 is electrically connected to the initial voltage line I1, and the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor T0;

[0100] The first gate of the third transistor T3 and the second gate of the third transistor T3 are electrically connected to the scan line Gate, the first electrode of the third transistor T3 is electrically connected to the gate of the driving transistor T0, and the second electrode of the third transistor T3 is electrically connected to the second electrode of the driving transistor T0;

[0101] The first gate of the second transistor T2 and the second gate of the second transistor T2 are both top gates, and the first gate of the third transistor T3 and the second gate of the third transistor T3 are both top gates;

[0102] The first light emitting control circuit 15 includes a fourth transistor T4, the second light emitting control circuit 16 includes a fifth transistor T5, and the second initialization circuit 14 includes a sixth transistor T6; the energy storage circuit 17 includes a storage capacitor C1;

[0103] The gate of the fourth transistor T4 is electrically connected to the light emitting control line EM, the first electrode of the fourth transistor T4 is electrically connected to the first voltage line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the driving transistor T0;

[0104] The gate of the fifth transistor T5 is electrically connected to the light emitting control line EM, the first electrode of the fifth transistor T5 is electrically connected to the second electrode of the driving transistor T0, and the second electrode of the fifth transistor T5 is electrically connected to the anode of the organic light emitting diode O1;

[0105] The gate of the sixth transistor T6 is electrically connected to the scan line Gate, the first electrode of the sixth transistor T6 is electrically connected to the initial voltage line I1, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

[0106] The first plate of the storage capacitor C1 is electrically connected to the gate of the driving transistor T0 , and the second plate of the storage capacitor C1 is electrically connected to the first voltage terminal VDD.

[0107] exist Figure 2 In at least one embodiment of the pixel circuit shown, all transistors are p-type thin film transistors, but the present invention is not limited thereto.

[0108] In at least one embodiment of the present invention, at least one of the second transistor T2 and the third transistor T3 may also be a single-gate transistor.

[0109] Figure 3 is Figure 2 Schematic diagram of labeling each electrode and plate based on the above.

[0110] exist Figure 3 , the one labeled G0 is the gate of T0, the one labeled S0 is the first electrode of T0, and the one labeled D0 is the second electrode of T0;

[0111] The first gate of T1 is labeled G11, the second gate of T1 is labeled G12, the first electrode of T1 is labeled S1, and the second electrode of T1 is labeled D1;

[0112] The first gate of T2 is labeled G21, the second gate of T2 is labeled G22, the first electrode of T2 is labeled S2, and the second electrode of T2 is labeled D2;

[0113] The first gate of T3 is labeled G31, the second gate of T3 is labeled G32, the first electrode of T3 is labeled 32, and the second electrode of T3 is labeled D3;

[0114] The gate electrode of T4 is labeled G4, the first electrode of T4 is labeled S4, and the second electrode of T4 is labeled D4;

[0115] The gate electrode of T5 is labeled G5, the first electrode of T5 is labeled S5, and the second electrode of T5 is labeled D5;

[0116] The gate electrode of T6 is labeled G6, the first electrode of T6 is labeled S6, and the second electrode of T6 is labeled D6;

[0117] The first electrode plate of C1 is labeled C1a, and the second electrode plate of C1 is labeled C1b.

[0118] Optionally, the pixel circuit further includes a first initialization circuit and a compensation control circuit; the first initialization circuit includes a second transistor, and the compensation control circuit includes a third transistor; the first gate of the second transistor and the second gate of the second transistor are both electrically connected to a reset control line, the first electrode of the second transistor is electrically connected to an initial voltage line, and the second electrode of the second transistor is electrically connected to a control end of the drive circuit; the first gate of the third transistor and the second gate of the third transistor are electrically connected to the scan line, the first electrode of the third transistor is electrically connected to the control end of the drive circuit, and the second electrode of the third transistor is electrically connected to the second end of the drive circuit;

[0119] The first gate of the second transistor, the second gate of the second transistor, the first gate of the third transistor and the second gate of the third transistor are all included in the first gate metal layer;

[0120] The active layer of the second transistor and the active layer of the third transistor are both included in the semiconductor layer;

[0121] The first gate of the second transistor, the second gate of the second transistor, the first gate of the third transistor, and the second gate of the third transistor are all top gates.

[0122] In at least one embodiment of the present invention, the active layer of the second transistor may include the channel region of the second transistor, the first electrode of the second transistor and the second electrode of the second transistor, and the active layer of the third transistor includes the channel region of the third transistor, the first electrode of the third transistor and the second electrode of the third transistor.

[0123] like Figure 4 As shown, the second gate of the first transistor T1 is labeled G12;

[0124] like Figure 5 As shown, the channel region labeled N1 is T1;

[0125] like Figure 6 As shown, the first gate of the first transistor T1 is labeled G11; the scanning line is labeled Gate; the orthographic projection of the first gate G11 of the first transistor T1 on the substrate is within the orthographic projection of the scanning line Gate on the substrate;

[0126] like Fig. 9 As shown, the orthographic projection of the second gate G12 of the first transistor T1 on the substrate covers the orthographic projection of the channel region N1 of T1 on the substrate.

[0127] like Figure 8 As shown, the first voltage line VDD is included in the source-drain metal layer, and the first voltage line VDD extends vertically.

[0128] like Fig. 9 As shown, in at least one embodiment of the present invention, the second gate G12 of the first transistor T1 may be electrically connected to the first voltage line VDD through a first via H1.

[0129] like Figure 5 As shown, the first electrode S1 of the first transistor T1, the second electrode D1 of the first transistor T1 and the first electrode S0 of the driving transistor T0 are all included in the semiconductor layer.

[0130] like Figure 8 As shown, the data line Data is included in the source-drain metal layer.

[0131] like Figure 5As shown, the second electrode D1 of the first transistor T1 is connected to the first electrode S0 of the driving transistor T0, so that the second electrode D1 of the first transistor T1 is electrically connected to the first electrode S0 of the driving transistor T0;

[0132] The first electrode S1 of the first electrode T1 is electrically connected to the data line Data through the second via hole H2.

[0133] like Figure 6 As shown, the first gate of T2 is labeled G21, the second gate of T2 is labeled G22, the first gate of T3 is labeled G31, and the second gate of T3 is labeled G32;

[0134] G21, G22, G31 and G32 are all included in the first gate metal layer;

[0135] like Figure 5 As shown, the first channel portion of T2 is labeled N21, the second channel portion of T2 is labeled N22, and the channel region of T2 includes the first channel portion N21 of T2 and the second channel portion N22 of T2;

[0136] The first channel portion of T3 is labeled N31 , the second channel portion of T3 is labeled N32 , and the channel region of T3 includes the first channel portion N31 of T3 and the second channel portion N32 of T3 .

[0137] Optionally, the driving circuit includes a driving transistor, a gate of the driving transistor is a control terminal of the driving circuit, and a second electrode of the driving transistor is a second terminal of the driving circuit;

[0138] The reset control line and the scan line are both included in a first gate metal layer; the display substrate further includes a second gate metal layer and a source-drain metal layer which are sequentially stacked on a side of the first gate metal layer away from the base substrate; the initial voltage line is included in the second gate metal layer;

[0139] The first electrode of the second transistor, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the third transistor, the first electrode of the driving transistor, and the second electrode of the driving transistor are included in the semiconductor layer;

[0140] The first electrode of the second transistor is electrically connected to a first conductive connection pattern, the first conductive connection pattern is included in the source-drain metal layer, and the first conductive connection pattern is electrically connected to the initial voltage line, so that the first electrode of the second transistor is electrically connected to the initial voltage line;

[0141] The gate of the driving transistor is included in the first gate metal layer, the second electrode of the second transistor is electrically connected to the second conductive connection pattern, the second conductive connection pattern is included in the source-drain metal layer, and the second conductive connection pattern is electrically connected to the gate of the driving transistor, so that the second electrode of the second transistor is electrically connected to the gate of the driving transistor;

[0142] The first electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the third transistor is connected to the second electrode of the driving transistor.

[0143] like Figure 6 As shown, the gate of the driving transistor T0 is labeled G0, the reset control line is labeled Reset, and the scan line is labeled Gate;

[0144] like Figure 7 As shown, the line labeled I1 is the initial voltage line;

[0145] like Figure 5 As shown, S2 is the first electrode of the second transistor T2, D2 is the second electrode of the second transistor T2, S3 is the first electrode of the third transistor T3, and D3 is the second electrode of the third transistor T3.

[0146] like Fig. 9 As shown, the first electrode S2 of the second transistor T2 is electrically connected to the first conductive connection pattern L1 through the third via H3, and the first conductive connection pattern L1 is electrically connected to the initial voltage line I1 through the fourth via H4, so that the first electrode S2 of the second transistor T2 is electrically connected to the initial voltage line I1.

[0147] like Figure 8 As shown, the first conductive connection pattern is labeled L1.

[0148] like Fig. 9 As shown, the second electrode D2 of the second transistor T2 is electrically connected to the second conductive connection pattern L2 through the fifth via H5, and the second conductive connection pattern L2 is electrically connected to the gate G0 of the driving transistor T0 through the sixth via H6, so that the second electrode D2 of the second transistor T2 is electrically connected to the gate G0 of the driving transistor T0.

[0149] like Figure 8 As shown, the second conductive connection pattern is labeled L2.

[0150] like Figure 5As shown, the first electrode S3 of the third transistor T3 is connected to the second electrode D2 of the second transistor T2, and the second electrode D3 of the third transistor T3 is connected to the second electrode D0 of the driving transistor T0.

[0151] Optionally, the driving circuit includes a driving transistor, and the first electrode of the driving transistor is the first end of the driving circuit; the display substrate further includes a source-drain metal layer arranged on a side of the first gate metal layer away from the base substrate;

[0152] The data line is included in the source-drain metal layer, and the first electrode of the first transistor, the second electrode of the first transistor and the first electrode of the driving transistor are included in the semiconductor layer;

[0153] The first electrode of the first transistor is electrically connected to the data line through a via hole, and the second electrode of the first transistor is connected to the first electrode of the driving transistor.

[0154] like Figure 8 As shown, the data line Data is included in the first source-drain metal layer, and the data line Data extends along a vertical direction.

[0155] like Figure 5 As shown, the first electrode S1 of the first transistor T1, the second electrode D1 of the first transistor T1 and the first electrode S0 of the driving transistor T0 are included in the semiconductor layer.

[0156] like Figure 5 As shown, the second electrode D1 of the first transistor T1 is connected to the first electrode S0 of the driving transistor T0.

[0157] Optionally, the pixel circuit further includes a first light-emitting control circuit and a second light-emitting control circuit; the driving circuit includes a driving transistor; the first light-emitting control circuit includes a fourth transistor, and the second light-emitting control circuit includes a fifth transistor; the display substrate further includes a source-drain metal layer and an anode layer stacked in sequence on a side of the first gate metal layer away from the base substrate;

[0158] The gate of the fourth transistor, the light emitting control line, the gate of the fifth transistor and the gate of the driving transistor are all included in the first gate metal layer;

[0159] The first voltage line is included in the source-drain metal layer; the first electrode of the fourth transistor, the second electrode of the fourth transistor, the first electrode of the fifth transistor and the second electrode of the fifth transistor are all included in the semiconductor layer;

[0160] The gate of the fourth transistor is electrically connected to the light emitting control line, the first electrode of the fourth transistor is electrically connected to the first voltage line, and the second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0161] The gate of the fifth transistor is electrically connected to the light-emitting control line, the first electrode of the fifth transistor is connected to the second electrode of the driving transistor, the second electrode of the fifth transistor is electrically connected to a third conductive connection pattern, the third conductive connection pattern is included in the source-drain metal layer, and the third conductive connection pattern is electrically connected to the anode of the light-emitting element; the anode of the light-emitting element is included in the anode layer.

[0162] like Figure 6 As shown, the gate G4 of the fourth transistor T4, the light emitting control line EM, the gate G5 of the fifth transistor T5 and the gate G0 of the driving transistor T0 are all included in the first gate metal layer;

[0163] like Figure 8 As shown, the first voltage line VDD is formed with the source-drain metal layer;

[0164] like Figure 5 As shown, the first electrode S4 of the fourth transistor T4, the second electrode D4 of the fourth transistor T4, the first electrode S5 of the fifth transistor T5, and the second electrode D5 of the fifth transistor T5 are all included in the semiconductor layer.

[0165] like Figure 6 As shown, the orthographic projection of the gate G4 of the fourth transistor T4 on the substrate is within the orthographic projection of the light emitting control line EM on the substrate, and the orthographic projection of the gate G5 of the fifth transistor T5 on the substrate is within the orthographic projection of the light emitting control line EM on the substrate.

[0166] like Fig. 9 As shown, the first electrode S4 of the fourth transistor T4 is electrically connected to the first voltage line VDD through the seventh via hole H7.

[0167] like Figure 5 As shown, the second electrode D4 of the fourth transistor T4 is connected to the first electrode S0 of the driving transistor T0 , and the first electrode S5 of the fifth transistor T5 is connected to the second electrode D0 of the driving transistor T0 .

[0168] like Fig. 9 As shown, the second electrode D5 of the fifth transistor T5 is electrically connected to the third conductive connection pattern L3 through the eighth via hole H8. Figure 8 As shown, the third conductive connection pattern L3 is included in the source-drain metal layer;

[0169] The third conductive connection pattern L3 is electrically connected to the anode of the light emitting element; the anode of the light emitting element is included in the anode layer.

[0170] In at least one embodiment of the present invention, the control voltage line is the first voltage line;

[0171] The second gate of the first transistor is electrically connected to the first voltage line through a via hole.

[0172] In a specific implementation, the control voltage line may be a first voltage line, and the second gate of the first transistor is electrically connected to the first voltage line.

[0173] Optionally, the pixel circuit further includes a second initialization circuit and a storage circuit; the second initialization circuit includes a sixth transistor; the storage circuit includes a storage capacitor; the display substrate further includes a second gate metal layer disposed between the first gate metal layer and the source-drain metal layer;

[0174] The gate of the sixth transistor and the scan line are both included in the first gate metal layer; the first electrode of the sixth transistor and the second electrode of the sixth transistor are both included in the semiconductor layer;

[0175] The gate of the driving transistor is reused as the first plate of the storage capacitor;

[0176] The gate of the sixth transistor is electrically connected to the scan line, and the first electrode of the sixth transistor is connected to the first electrode of the second transistor, so that the first electrode of the sixth transistor is electrically connected to the initial voltage line;

[0177] The second electrode plate of the storage capacitor is included in the second gate metal layer, and the second electrode plate of the storage capacitor is electrically connected to the first voltage line.

[0178] like Figure 6 As shown, the gate G6 of the sixth transistor T6 and the scan line Gate are both included in the first gate metal layer, and the gate G0 of the driving transistor T0 is reused as the first electrode plate C1a of the storage capacitor C1.

[0179] like Figure 6 As shown, the orthographic projection of the gate G6 of the sixth transistor T6 on the substrate is within the orthographic projection of the scan line Gate on the substrate.

[0180] like Figure 5As shown, the first electrode S6 of the sixth transistor T6 and the second electrode D6 of the sixth transistor T6 are both included in the semiconductor layer, and the first electrode S6 of the sixth transistor T6 is connected to the first electrode S2 of the second transistor T2, so that the first electrode S6 of the sixth transistor T6 is electrically connected to the initial voltage line I1.

[0181] like Figure 7 As shown, the second plate C1b of the storage capacitor C1 is included in the second gate metal layer, and the second plate C1b of the storage capacitor C1 is electrically connected to the first voltage line VDD through a ninth via H9.

[0182] In at least one embodiment of the present invention, a first conductive layer, a semiconductor layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer are sequentially stacked on a substrate. Fig. 9 It is a layout diagram of a display substrate according to at least one embodiment of the present invention. Figure 4 yes Fig. 9 Layout diagram of the first conductive layer in Figure 5 yes Fig. 9 The layout of the semiconductor layers in Figure 6 yes Fig. 9 The layout diagram of the first gate metal layer in Figure 7 yes Fig. 9 The layout diagram of the second gate metal layer in Figure 8 yes Fig. 9 Layout diagram of the source and drain metal layers.

[0183] exist Fig. 9 In at least one embodiment of the display substrate shown, the control voltage line is the first voltage line VDD, but the present invention is not limited thereto.

[0184] In making Fig. 9 In at least one embodiment of the display substrate shown,

[0185] Firstly, a first conductive layer is formed on one surface of the substrate, and a patterning process is performed on the first conductive layer to form a second gate G12 of the first transistor T1;

[0186] Fabricating a semiconductor layer on a side of the first conductive layer facing away from the substrate;

[0187] Forming a first gate metal layer on a side of the semiconductor layer facing away from the first conductive layer;

[0188] The first gate metal layer is patterned to form a first gate G11 of the first transistor T1, a first gate G21 of the second transistor T2, a second electrode G22 of the second transistor T2, a first gate G31 of the third transistor T3, a second gate G32 of the third transistor T3, a gate G4 of the fourth transistor T4, a gate G5 of the fifth transistor T5, a gate G6 of the sixth transistor T6, a gate G0 of the driving transistor T0, a light emitting control line EM, a scanning line Gate, and a reset control line Reset; the gate G0 of the driving transistor T0 is reused as a first plate of the storage capacitor C1;

[0189] Using the first gate G11 of the first transistor and the gates of other transistors included in the pixel circuit except the first transistor T1 as masks, doping the portion of the semiconductor layer not covered by the first gate G11 of the first transistor T1 and the gates of other transistors included in the pixel circuit except the first transistor T1, so that the portion of the semiconductor layer not covered by the first gate G11 of the first transistor T1 and the gates of other transistors included in the pixel circuit except the first transistor T1 is formed as a conductive portion, and the portion of the semiconductor layer covered by the first gate G11 of the first transistor T1 and the gates of other transistors included in the pixel circuit except the first transistor T1 is formed as a channel region;

[0190] Forming a second gate metal layer on a side of the first gate metal layer facing away from the semiconductor layer;

[0191] Performing a patterning process on the second gate metal layer to form a second plate of the first storage capacitor and an initial voltage line I1;

[0192] Forming a source-drain metal layer on a side of the second gate metal layer facing away from the first gate metal layer;

[0193] The source-drain metal layer is patterned to form a data line Data, a first voltage line VDD, a first conductive connection pattern L1, a second conductive connection pattern L2, and a third conductive connection pattern L3.

[0194] like Figure 6 As shown, the light emitting control line EM, the scanning line Gate and the reset control line Reset extend along a first direction, and the first direction may be a horizontal direction;

[0195] like Figure 7 As shown, the initial voltage line I1 extends along a first direction;

[0196] like Figure 8As shown, the data line Data and the first voltage line VDD both extend along a second direction, the second direction intersects with the first direction, and the second direction may be a vertical direction.

[0197] like Figure 5 As shown, the active layer of T1 , the active layer of T2 , the active layer of T3 , the active layer of T4 , the active layer of T5 , the active layer of T6 , and the active layer of T0 are continuous with each other.

[0198] like Figure 5 As shown, the active layer of T1 includes the channel region N1 of T1, the first first conductive portion and the first second conductive portion; the first first conductive portion is multiplexed as the first electrode S1 of T1, and the second first conductive portion is multiplexed as the second electrode D1 of T1;

[0199] The active layer of T2 includes a first channel portion N21 of T2, a second channel portion N22 of T2, a second first conductive portion and a second second conductive portion; the second first conductive portion is multiplexed as a first electrode S2 of T2, and the second second conductive portion is multiplexed as a second electrode D2 of T2;

[0200] The active layer of T3 includes a first channel portion N31 of T3, a second channel portion N32 of T3, a third first conductive portion and a third second conductive portion; the third first conductive portion is multiplexed as a first electrode S3 of T3, and the second second conductive portion is multiplexed as a second electrode D3 of T3;

[0201] The active layer of T4 includes a channel region N4 of T4, a fourth first conductive portion and a fourth second conductive portion; the fourth first conductive portion is multiplexed as a first electrode S4 of T4, and the fourth second conductive portion is multiplexed as a second electrode D4 of T4;

[0202] The active layer of T5 includes a channel region N5 of T5, a fifth first conductive portion and a fifth second conductive portion; the fifth first conductive portion is multiplexed as a first electrode S5 of T5, and the fifth second conductive portion is multiplexed as a second electrode D5 of T5;

[0203] The active layer of T6 includes a channel region N6 of T6, a sixth first conductive portion and a sixth second conductive portion; the sixth first conductive portion is multiplexed as a first electrode S6 of T6, and the sixth second conductive portion is multiplexed as a second electrode D6 of T6;

[0204] The active layer of T0 includes the channel region N0 of T0, the seventh first conductive portion and the seventh second conductive portion; the seventh first conductive portion is multiplexed as the first electrode S0 of T0, and the seventh second conductive portion is multiplexed as the second electrode D0 of T0.

[0205] exist Figure 4-Figure 9 In at least one embodiment of the display substrate shown, each first conductive portion included in the active layer is multiplexed as a first electrode of a corresponding transistor, each second conductive portion included in the active layer is multiplexed as a second electrode of a corresponding transistor, and the first electrode and the second electrode are included in the active layer.

[0206] Fig.10 yes Fig. 9 A cross-sectional view of at least one embodiment of a display substrate is shown.

[0207] like Fig.10 As shown, in the display substrate described in at least one embodiment of the present invention, the base substrate includes a first substrate PI1, a first barrier layer B1, a second substrate PI2, a second barrier layer B2, a first conductive layer LS, a buffer layer B0, a semiconductor layer P0, a first gate insulation layer GI1, a first gate metal layer GL1, a second gate insulation layer GI2, a second gate metal layer GL2, an interlayer dielectric layer I0 and a source / drain metal layer SD.

[0208] exist Fig.10 In the figure, the left side schematically shows a cross-sectional view of each layer of the first transistor, the middle side schematically shows a cross-sectional view of the storage capacitor, and the right side schematically shows a cross-sectional view of a transistor included in the pixel circuit except the first transistor.

[0209] Fig.11A is a schematic diagram of a threshold voltage of the first transistor when a 0V voltage signal is connected to the second gate of the first transistor;

[0210] Fig. 11B is a schematic diagram of a threshold voltage of the first transistor when a second gate of the first transistor is connected to a 4.6V voltage signal;

[0211] Fig. 11C is a schematic diagram of the threshold voltage of the first transistor when the second gate of the first transistor is connected to a 7V voltage signal;

[0212] Fig.11D is a schematic diagram of the threshold voltage of the first transistor when the second gate of the first transistor is connected to a scan signal.

[0213] In a specific implementation, the negative offset of the threshold unit of the first transistor can be adjusted by the voltage value of the voltage signal connected to the control voltage line. According to the width-to-length ratio design of the first transistor, the first control voltage line can be selected to connect different voltage signals to adjust the negative offset of the threshold voltage of the first transistor. Without changing the characteristics of other TFTs (thin film transistors), the product life of the vehicle-mounted OLED (organic light-emitting diode) pixel circuit under long-term forward bias voltage characteristics can be extended to improve product reliability.

[0214] The method for manufacturing a display substrate according to an embodiment of the present invention is used to manufacture the above-mentioned display substrate, and the method for manufacturing the display substrate includes:

[0215] A first conductive layer is formed on one side of the substrate, and a patterning process is performed on the first conductive layer to form a second gate of the first transistor;

[0216] A semiconductor layer is formed on a side of the first conductive layer facing away from the substrate; a first gate metal layer is formed on a side of the semiconductor layer facing away from the first conductive layer, and the first gate metal layer is patterned to form a first gate of the first transistor and gates of other transistors included in the pixel circuit except the first transistor;

[0217] Using the first gate of the first transistor as a mask, the portion of the semiconductor layer that is not covered by the first gate of the first transistor and the gates of other transistors included in the pixel circuit except the first transistor is doped, so that the portion of the semiconductor layer that is not covered by the first gate of the first transistor and the gates of other transistors included in the pixel circuit except the first transistor is formed as a conductive portion, and the portion of the semiconductor layer that is covered by the first gate of the first transistor and the gates of other transistors included in the pixel circuit except the first transistor is formed as a channel region.

[0218] The display device described in the embodiment of the present invention includes the above-mentioned display substrate.

[0219] The display device described in at least one embodiment of the present invention may be a vehicle-mounted display device, but is not limited thereto.

[0220] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0221] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: It comprises a base substrate, and a plurality of rows and columns of pixel circuits arranged in a display area of ​​the base substrate; the display substrate comprises a first conductive layer, a semiconductor layer and a first gate metal layer which are sequentially stacked in a direction away from the base substrate; The pixel circuit includes a light emitting element, a data writing circuit and a driving circuit; the data writing circuit includes a first transistor; The first gate of the first transistor is electrically connected to the scan line, and the second gate of the first transistor is electrically connected to the control voltage line; the second gate of the first transistor is included in the first conductive layer, and the first gate of the first transistor is included in the first gate metal layer; the active layer of the first transistor is included in the semiconductor layer; A first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to a first end of the driving circuit; The second end of the driving circuit is electrically connected to the light emitting element, and the driving circuit is used to drive the light emitting element to emit light; The orthographic projection of the second gate of the first transistor on the substrate covers the orthographic projection of the channel region included in the active layer of the first transistor on the substrate; The first conductive layer is multiplexed as a light shielding layer.

2. The display substrate according to claim 1, wherein: The control voltage line is a DC voltage line; the display substrate further comprises a source-drain metal layer disposed on a side of the first gate metal layer facing away from the base substrate; the DC voltage line is included in the source-drain metal layer; The second gate of the first transistor is electrically connected to the DC voltage line through a via hole.

3. The display substrate according to claim 1, wherein: The control voltage line and the scan line are connected to the same scan signal; the scan line is included in the first gate metal layer; The control voltage line and the second gate of the first transistor are located in the same layer, and the control voltage line is electrically connected to the second gate of the first transistor.

4. The display substrate according to any one of claims 1 to 3, characterized in that: The first conductive layer is a molybdenum metal layer or an aluminum alloy layer.

5. The display substrate according to any one of claims 1 to 3, characterized in that: The pixel circuit further includes a first initialization circuit and a compensation control circuit; the first initialization circuit includes a second transistor, and the compensation control circuit includes a third transistor; the first gate of the second transistor and the second gate of the second transistor are both electrically connected to a reset control line, the first electrode of the second transistor is electrically connected to an initial voltage line, and the second electrode of the second transistor is electrically connected to a control terminal of the drive circuit; the first gate of the third transistor and the second gate of the third transistor are electrically connected to the scan line, the first electrode of the third transistor is electrically connected to the control terminal of the drive circuit, and the second electrode of the third transistor is electrically connected to a second terminal of the drive circuit; The first gate of the second transistor, the second gate of the second transistor, the first gate of the third transistor and the second gate of the third transistor are all included in the first gate metal layer; An active layer of the second transistor and an active layer of the third transistor are both included in the semiconductor layer.

6. The display substrate according to claim 5, wherein: The driving circuit comprises a driving transistor, a gate of the driving transistor is a control terminal of the driving circuit, and a second electrode of the driving transistor is a second terminal of the driving circuit; The reset control line and the scan line are both included in a first gate metal layer; the display substrate further includes a second gate metal layer and a source-drain metal layer which are sequentially stacked on a side of the first gate metal layer away from the base substrate; the initial voltage line is included in the second gate metal layer; The first electrode of the second transistor, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the third transistor, the first electrode of the driving transistor, and the second electrode of the driving transistor are included in the semiconductor layer; The first electrode of the second transistor is electrically connected to a first conductive connection pattern, the first conductive connection pattern is included in the source-drain metal layer, and the first conductive connection pattern is electrically connected to the initial voltage line, so that the first electrode of the second transistor is electrically connected to the initial voltage line; The gate of the driving transistor is included in the first gate metal layer, the second electrode of the second transistor is electrically connected to the second conductive connection pattern, the second conductive connection pattern is included in the source-drain metal layer, and the second conductive connection pattern is electrically connected to the gate of the driving transistor, so that the second electrode of the second transistor is electrically connected to the gate of the driving transistor; The first electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the third transistor is connected to the second electrode of the driving transistor.

7. The display substrate according to claim 1, wherein: The driving circuit includes a driving transistor, and the first electrode of the driving transistor is the first end of the driving circuit; the display substrate also includes a source-drain metal layer arranged on a side of the first gate metal layer away from the base substrate; The data line is included in the source-drain metal layer, and the first electrode of the first transistor, the second electrode of the first transistor and the first electrode of the driving transistor are included in the semiconductor layer; The first electrode of the first transistor is electrically connected to the data line through a via hole, and the second electrode of the first transistor is connected to the first electrode of the driving transistor.

8. The display substrate according to claim 6, wherein: The pixel circuit further includes a first light-emitting control circuit and a second light-emitting control circuit; the driving circuit includes a driving transistor; the first light-emitting control circuit includes a fourth transistor, and the second light-emitting control circuit includes a fifth transistor; the display substrate further includes a source-drain metal layer and an anode layer stacked in sequence on a side of the first gate metal layer away from the base substrate; The gate of the fourth transistor, the light emitting control line, the gate of the fifth transistor and the gate of the driving transistor are all included in the first gate metal layer; The first voltage line is included in the source-drain metal layer; the first electrode of the fourth transistor, the second electrode of the fourth transistor, the first electrode of the fifth transistor and the second electrode of the fifth transistor are all included in the semiconductor layer; The gate of the fourth transistor is electrically connected to the light emitting control line, the first electrode of the fourth transistor is electrically connected to the first voltage line, and the second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The gate of the fifth transistor is electrically connected to the light-emitting control line, the first electrode of the fifth transistor is connected to the second electrode of the driving transistor, the second electrode of the fifth transistor is electrically connected to a third conductive connection pattern, the third conductive connection pattern is included in the source-drain metal layer, and the third conductive connection pattern is electrically connected to the anode of the light-emitting element; the anode of the light-emitting element is included in the anode layer.

9. The display substrate according to claim 8, wherein: The control voltage line is the first voltage line; The second gate of the first transistor is electrically connected to the first voltage line through a via hole.

10. The display substrate according to claim 8, wherein: The pixel circuit further includes a second initialization circuit and a storage circuit; the second initialization circuit includes a sixth transistor; the storage circuit includes a storage capacitor; the display substrate further includes a second gate metal layer disposed between the first gate metal layer and the source-drain metal layer; The gate of the sixth transistor and the scan line are both included in the first gate metal layer; the first electrode of the sixth transistor and the second electrode of the sixth transistor are both included in the semiconductor layer; The gate of the driving transistor is reused as the first plate of the storage capacitor; The gate of the sixth transistor is electrically connected to the scan line, and the first electrode of the sixth transistor is connected to the first electrode of the second transistor, so that the first electrode of the sixth transistor is electrically connected to the initial voltage line; The second electrode plate of the storage capacitor is included in the second gate metal layer, and the second electrode plate of the storage capacitor is electrically connected to the first voltage line.

11. A method for manufacturing a display substrate, used for manufacturing the display substrate according to any one of claims 1 to 10, characterized in that: The manufacturing method of the display substrate comprises: A first conductive layer is formed on one surface of the substrate, and a patterning process is performed on the first conductive layer to form a second gate of the first transistor; A semiconductor layer is formed on a side of the first conductive layer facing away from the substrate; a first gate metal layer is formed on a side of the semiconductor layer facing away from the first conductive layer, and the first gate metal layer is patterned to form a first gate of the first transistor and gates of other transistors included in the pixel circuit except the first transistor; Using the first gate of the first transistor as a mask, doping a portion of the semiconductor layer that is not covered by the first gate of the first transistor and the gates of other transistors included in the pixel circuit except the first transistor, so that the portion of the semiconductor layer that is not covered by the first gate of the first transistor and the gates of other transistors included in the pixel circuit except the first transistor is formed as a conductive portion, and the portion of the semiconductor layer that is covered by the first gate of the first transistor and the gates of other transistors included in the pixel circuit except the first transistor is formed as a channel region; Setting the orthographic projection of the second gate of the first transistor on the substrate to cover the orthographic projection of the channel region included in the active layer of the first transistor on the substrate; The first conductive layer is multiplexed as a light shielding layer.

12. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 10.

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