A memory and its preparation method and storage system

Abstract

The present invention discloses a memory and a preparation method thereof and a storage system. A stop layer covering a step structure is first formed, and the stop layer includes an isolation structure extending along a first direction and a stop structure. Then, a gate line gap penetrating the isolation structure and the step structure is formed, and the gate line gap extends along the first direction and is separated from the stop structure by an isolation structure. Then, an interlayer sacrificial layer is replaced with an interlayer gate layer through the gate line gap, and finally a contact hole penetrating the stop structure is formed. Since the gate line gap is separated from the stop structure by an isolation structure, and the gate line gap is in contact with the interlayer sacrificial layer, the stop layer will not be removed in the replacement process, and can be used as an etching stop layer for subsequently forming a contact hole, so as to reduce the process difficulty of etching the contact hole.

Description

Technical Field

[0001] The present invention generally relates to the field of electronic devices, and more specifically, to a memory and a preparation method thereof and a storage system. Background Art

[0002] In 3D NAND, a step structure and a dielectric layer covering the step structure are generally formed first, and then the dielectric layer is etched on each step to form a contact hole, and then a conductive material is filled in the contact hole to form a word line contact.

[0003] As the number of 3D NAND layers increases, the process of contact hole etching becomes more and more difficult. For example, the etching selectivity requirements for the gate layer (such as tungsten) and the dielectric layer (such as silicon oxide) are getting higher and higher, so that the etching of the contact hole can stop in each gate layer.

[0004] How to reduce the difficulty of the contact hole etching process is a problem that needs to be solved urgently. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a memory and a manufacturing method thereof and a storage system, aiming to reduce the process difficulty of contact hole etching.

[0006] In a first aspect, an embodiment of the present invention provides a method for preparing a memory, comprising:

[0007] providing a substrate;

[0008] forming a stacked layer on the substrate, wherein the stacked layer comprises interlayer insulating layers and interlayer sacrificial layers that are alternately stacked, and the stacked layer comprises a step region and presents a step structure in the step region;

[0009] forming a stop layer covering the step structure, wherein the stop layer includes an isolation structure and a stop structure extending along a first direction;

[0010] forming a gate line gap penetrating the isolation structure and the step structure, wherein the gate line gap extends along the first direction, and the isolation structure is spaced between the stop structure and the gate line gap;

[0011] Replacing the interlayer sacrificial layer with an interlayer gate layer through the gate line gap;

[0012] A contact hole is formed penetrating the stop structure, wherein the bottom of the contact hole is located on the interlayer gate layer at each step of the step structure.

[0013] Furthermore, the isolation structure and the stop structure are alternately arranged along a second direction, and the second direction is parallel to the substrate and perpendicular to the first direction; the isolation structure includes a first isolation part and a second isolation part respectively located on both sides of the gate line gap in the second direction, the first isolation part is located between the stop structure and the gate line gap, and the second isolation part is located between the stop structure and the gate line gap.

[0014] Furthermore, the step of forming a stop layer covering the step structure includes:

[0015] forming a stop material layer covering the step structure, wherein the stop material layer includes an isolation region extending along a first direction;

[0016] removing the stop material layer located in the isolation region, and the remaining stop material layer serves as the stop structure;

[0017] The isolation structure is formed in the isolation region.

[0018] Furthermore, the step of forming an isolation structure in the isolation area includes:

[0019] An isolation material is deposited in the isolation region to form the isolation structure.

[0020] Further, the step of forming an isolation structure in the isolation area includes:

[0021] forming a dielectric layer covering the stop layer and filling the isolation region;

[0022] Wherein, the dielectric layer filling the isolation region forms the isolation structure.

[0023] Furthermore, the step of forming a contact hole penetrating the stop structure includes:

[0024] Etching the dielectric layer and part of the stop structure on each step to form a contact hole, wherein the bottom of the contact hole is located in the stop structure;

[0025] Continue etching the contact hole so that the bottom of the contact hole is located on the interlayer gate layer at each step;

[0026] A conductive material is filled in the contact hole to form a word line contact.

[0027] Furthermore, before the step of forming a stop layer covering the step structure, the method for preparing the memory further includes:

[0028] An isolation layer is formed between the step structure and the stop layer.

[0029] Furthermore, an etching selectivity ratio of the isolation structure to the interlayer sacrificial layer is less than 1.

[0030] Furthermore, an etching selectivity ratio of the stop structure relative to the dielectric layer is less than 1.

[0031] Furthermore, the thickness of the stop layer is greater than the thickness of the isolation layer.

[0032] In a second aspect, an embodiment of the present invention provides a memory, the memory comprising:

[0033] Semiconductor layer;

[0034] A stacked structure, located on the semiconductor layer and comprising a step region, wherein the stacked structure is a step structure in the step region;

[0035] A stop structure, covering at least a portion of the step structure and extending along a first direction;

[0036] A gate line gap structure, which penetrates the step structure, passes through the stop structure and has a spacing area between the gate line gap structure and the stop structure;

[0037] an isolation structure, covering a portion of the step structure and located in the spacing area, the isolation structure extending along the first direction;

[0038] The word line contact is located on each step of the step structure and passes through the stop structure.

[0039] Furthermore, the isolation structure and the stop structure are alternately arranged along a second direction, and the second direction is parallel to the semiconductor layer and perpendicular to the first direction; the isolation structure includes a first isolation part and a second isolation part respectively located on both sides of the gate line gap structure in the second direction, the first isolation part is located between the stop structure and the gate line gap structure, and the second isolation part is located between the stop structure and the gate line gap structure.

[0040] Furthermore, the stacked structure includes interlayer insulating layers and interlayer gate layers that are alternately stacked; and the memory further includes:

[0041] a dielectric layer, covering the stop structure and the isolation structure;

[0042] The word line contact penetrates the dielectric layer and the stop structure, and the bottom of the word line contact is connected to the interlayer gate layer at each step.

[0043] Furthermore, the isolation structure and the interlayer insulating layer include the same material.

[0044] Furthermore, an etching selectivity ratio of the stop structure relative to the dielectric layer is less than 1.

[0045] Furthermore, the memory further comprises:

[0046] An isolation layer is located between the step structure and the stop structure, and between the step structure and the isolation structure.

[0047] Furthermore, the isolation layer and the isolation structure include the same material.

[0048] Furthermore, the thickness of the stop structure is greater than the thickness of the isolation layer.

[0049] In a third aspect, an embodiment of the present invention provides a storage system, including:

[0050] A memory as described in any one of items 11 to 18 above;

[0051] A controller is electrically connected to the memory and is used to control the memory to store data.

[0052] The beneficial effects of the embodiments of the present invention are as follows: a memory device and a preparation method thereof and a storage system are provided, wherein a stop layer covering a step structure is first formed, the stop layer comprising an isolation structure extending along a first direction and a stop structure. Then, a gate line gap penetrating the isolation structure and the step structure is formed, the gate line gap extending along the first direction and having an isolation structure between the gate line gap and the stop structure. Then, the interlayer sacrificial layer is replaced with an interlayer gate layer through the gate line gap, and finally, a contact hole penetrating the stop structure is formed. Since the gate line gap and the stop structure are separated by an isolation structure, and the gate line gap is in contact with the interlayer sacrificial layer, the stop layer will not be removed in the replacement process, and can be used as an etching stop layer for the subsequent formation of contact holes, so as to reduce the process difficulty of contact hole etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0054] Figure 1 is a schematic flow chart of a method for preparing a memory provided by an embodiment of the present invention;

[0055] Figure 2a-2n is a schematic diagram of the structure of a memory provided by an embodiment of the present invention during the preparation process;

[0056] Figure 3 is a schematic diagram of the structure of a memory provided by an embodiment of the present invention;

[0057] Figure 4 It is a schematic diagram of the structure of a storage system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0059] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present invention.

[0060] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0061] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.

[0062] This article uses a Cartesian coordinate system (expressed as X, Y and Z) to represent the cross-section of the memory in various directions, wherein the direction of the XY plane is parallel to the substrate and the Z direction is perpendicular to the substrate.

[0063] It should be noted that the diagrams provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Although the diagrams only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0064] The memory in the embodiment of the present invention may be a wafer or a three-dimensional memory. The three-dimensional memory may be applied to communication products, consumer electronics products, automotive products, aerospace products, artificial intelligence products or big data, etc. Among them, consumer electronics products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses or game products, etc.

[0065] See also Figure 1 , Figure 1 is a flow chart of a method for preparing a memory provided by an embodiment of the present invention. Figure 2a-2n , Figure 2a-2n The memory manufacturing method includes the following steps S1-S7.

[0066] See also Figure 1 Steps S1-S2 and Figure 2a .

[0067] Step S1: providing a substrate 10 .

[0068] The substrate 10 may be a semiconductor substrate, for example, silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI) or germanium on insulator (GOI), etc. The semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si / SiGe, etc.

[0069] Step S2: forming a stacked layer 20 on the substrate 10 , wherein the stacked layer 20 includes interlayer insulating layers 21 and interlayer sacrificial layers 22 that are alternately stacked, and the stacked layer 20 includes a step region and presents a step structure in the step region.

[0070] Specifically, interlayer insulating layers 21 and interlayer sacrificial layers 22 are alternately deposited on the substrate 10. The exemplary material of the interlayer insulating layers 21 may be silicon oxide, and the exemplary material of the interlayer sacrificial layers 22 may be silicon nitride. The interlayer insulating layers 21 and the interlayer sacrificial layers 22 have different etching selectivities. The stacked layer 20 formed may include a core region 20A and a step region 20B. The step region 20B may be located around the core region 20A or in the middle of the core region 20A. Then, the stacked layer 20 located in the step region 20B is further etched to form a Figure 2a The step structure shown in the figure can expose each interlayer sacrificial layer 22 at each step, that is, the interlayer sacrificial layer 22 covers the interlayer insulating layer 21 at each step.

[0071] In another embodiment, the interlayer insulating layer 21 may cover the interlayer sacrificial layer 22 at each step of the step structure. The method for manufacturing the memory may further include: forming a spacer layer between the substrate 10 and the stacked layer 20 .

[0072] See also Figure 2b After step S2, the preparation of the memory may further include: forming an isolation layer 30 (e.g., silicon oxide) covering the step structure. Specifically, the isolation layer 30 may be first deposited on the stacked layer 20, and then the isolation layer 30 in the core area 20A may be removed to form an isolation layer 30 located in the step area 20B and covering the step structure. The main function of the isolation layer 30 is to isolate the stop layer formed in step S3 from the interlayer sacrificial layer 22 in the step structure, so as to avoid affecting the stop layer when replacing the interlayer sacrificial layer 22.

[0073] See also Figure 1 Step S3 and Figure 2c-2d .

[0074] Step S3: forming a stop material layer 40 covering the stepped structure, wherein the stop material layer 40 includes an isolation region 41 extending along a first direction (X).

[0075] In one embodiment, if Figure 2c As shown, a stop material layer 40 may be deposited on the isolation layer 30. Specifically, the stop material layer 40 may be first deposited on the stacked layer 20 and the isolation layer 30 in the core region 20A, and then the stop material layer 40 located in the core region 20A may be removed to form a stop material layer 40 covering the step structure and located on the isolation layer 30. The deposition method includes, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0076] Figure 2d yes Figure 2c The top view of the structure of FIG. 4 shows that the stop material layer 40 includes an isolation region 41 extending along a first direction, wherein the first direction may be an X direction parallel to the substrate 10. Figure 2c As shown, the height direction of the step structure is the Z direction, and the width direction of the step structure is the Y direction, so the first direction is actually parallel to the substrate 10 and perpendicular to the width direction of the step structure.

[0077] In one embodiment, the thickness of the stop material layer 40 is greater than the thickness of the isolation layer 30. For example, the thickness of the isolation layer 30 may be The thickness of the stop material layer 40 may be 80-200 nm. The thickness of the stop material layer 40 may be adjusted as required, for example, may be changed according to the subsequent etching process requirements of the contact hole.

[0078] See also Figure 1 Step S4 and Figure 2e .

[0079] Step S4 : removing the stop material layer 40 located in the isolation region 41 .

[0080] Specifically, a hard mask layer and a photoresist layer can be formed on the stop material layer 40, and then the photoresist layer is subjected to a photolithography process using a mask template to form a patterned photoresist layer, and then the hard mask layer is etched based on the patterned photoresist layer to form a patterned hard mask layer, and finally the stop material layer 40 is patterned etched based on the patterned hard mask layer to remove the stop material layer 40 located in the isolation area 41, and retain the stop material layer 40 in other areas, and the retained stop material layer 40 is the stop structure 43.

[0081] It can be understood that, in some embodiments, the stop layer can be directly patterned and etched based on the patterned photoresist layer, that is, the hard mask layer can be omitted.

[0082] See also Figure 1 Step S5 and Figure 2f .

[0083] Step S5 : forming an isolation structure 42 in the isolation region 41 .

[0084] In one embodiment, an isolation material may be deposited in the isolation region 41 to form the isolation structure 42, and any of the above-mentioned deposition methods may be used. The etching selectivity of the isolation structure 42 relative to the interlayer sacrificial layer 22 is less than 1, for example, the isolation material may include insulating materials such as silicon oxide. Both the isolation structure 42 and the stop structure 43 cover the step structure and form a stop layer 40'. That is, the stop layer 40' includes an isolation structure 42 and a stop structure 43 extending along a first direction (X). Among them, the isolation structure 42 and the stop structure 43 are alternately arranged along a second direction (Y), and the second direction (Y) is parallel to the substrate and perpendicular to the first direction (X).

[0085] See also Figure 2g After forming the isolation structure 42, the method for preparing the memory may further include: forming a dielectric layer 50 covering the stop layer 40'. The etching selectivity of the stop material layer 40 (or the stop structure 43) relative to the dielectric layer 50 is less than 1. For example, the stop material layer 40 may include silicon nitride, and the material of the dielectric layer 50 may include insulating materials such as silicon oxide.

[0086] In another embodiment, a dielectric layer 50 covering the stop layer 40 ′ and filling the isolation region 41 may be directly formed, wherein the dielectric layer 50 filling the isolation region 41 becomes the isolation structure 42 , thereby saving a deposition process for forming the isolation structure 42 separately.

[0087] See also Figure 1 Step S6 and Figure 2g-Figure 2i .

[0088] Step S6: forming a gate line gap 60 penetrating the isolation structure 42 and the step structure, wherein the gate line gap 60 extends along the first direction (X), and the isolation structure 42 is spaced between the stop structure 43 and the gate line gap 60 .

[0089] In this embodiment, the gate line gap 60 may be formed after the dielectric layer 50 is formed. Figure 2g The structure of the gate line gap 60 is not shown in FIG. Figure 2h The structure of the gate line gap 60 is described in FIG. Figure 2h yes Figure 2g A schematic diagram of the cross-sectional structure at A-A1. The gate line gap 60 penetrating the dielectric layer 50, the isolation structure 42 and the step structure can be formed by an etching process.

[0090] like Figure 2h and Figure 2i As shown, Figure 2i yes Figure 2h In the cross-sectional structural diagram at B-B1, the gate line gap 60 extends in the first direction (X), and the isolation structure 42 is spaced between the stop structure 43 and the gate line gap 60. Specifically, the isolation structure 42 includes a first isolation portion 421 and a second isolation portion 422 respectively located on both sides of the gate line gap 60 in the second direction (Y), the first isolation portion 421 is located between the stop structure 43 and the gate line gap 60, and the second isolation portion 422 is located between the stop structure 43 and the gate line gap 60.

[0091] In 3D NAND, the gate line gap 60 is mainly used to isolate the memory block or the memory finger, so the position of the gate line gap 60 is determined according to the structure of the memory. The isolation region 41 (or isolation structure 42) in this embodiment is arranged parallel to the gate line gap 60 in the first direction (X), and the gate line gap 60 must pass through the isolation structure 42, so the position of the isolation region 41 is also arranged according to the preset position of the gate line gap 60, except that the width of the isolation region 41 in the second direction (Y) is greater than the width of the gate line gap 60 in the second direction (Y).

[0092] See also Figure 1 Step S7 and Figure 2j-2k .

[0093] Step S7: replacing the interlayer sacrificial layer 22 with an interlayer gate layer 22 a through the gate line gap 60 .

[0094] Since the interlayer sacrificial layer 22 and the interlayer insulating layer 21 have different etching selectivities, the interlayer sacrificial layer 22 can be removed by an etching process to form a cavity, and then the interlayer gate layer 22a is deposited in the cavity. The interlayer gate layer 22a can be composed of a combination of multiple film layers, for example, a barrier layer (such as aluminum oxide), an adhesion layer (such as titanium nitride) and a conductive layer (such as metal tungsten) deposited in sequence. After the interlayer sacrificial layer 22 is replaced by the interlayer gate layer 22a, the interlayer insulating layer 21 and the interlayer gate layer 22a form a stacked structure 20a.

[0095] In this embodiment, since an isolation structure 42 is formed between the gate line gap 60 and the stop structure 43 , the stop structure 43 will not be etched when the interlayer sacrificial layer 22 is removed, so the stop structure 43 is retained for subsequent formation of contact holes.

[0096] See also Figure 2l-Figure 2n .

[0097] After forming the interlayer gate layer 22a, the preparation method of the memory further includes: 1) Figure 2l As shown, the dielectric layer 50 and part of the stop structure 43 on each step are etched (when the structure in the figure is a cross-section along the stop structure 43, the stop layer 40' shown in the figure is the stop structure 43) to form a contact hole 70, and the bottom of the contact hole 70 is located in the stop structure 43; 2) as shown in FIG. Figure 2m As shown, the contact hole 70 is further etched so that the bottom of the contact hole 70 is located on or in the interlayer gate layer 22a at each step; 3) as shown Figure 2n As shown, finally, a conductive material (such as tungsten) is filled in the contact hole 70 to form a word line contact 71 .

[0098] like Figure 2l As shown, since the etching selectivity of the dielectric layer 50 and the stop structure 43 is very large, the first etching can make all the contact holes 70 stop in the stop structure 43, wherein the depths of the contact holes 70 formed by the first etching are different, and the depth of the contact holes 70 on the bottom step is the largest. Figure 2m As shown, all the contact holes 70 are then etched for a second time. This time, the etching time can be the same so that the contact holes 70 have the same depth. Thus, the bottom of each contact hole 70 can be located on the interlayer gate layer 22a. This can reduce the etching difficulty of the contact hole 70 and increase the process window of the contact hole 70.

[0099] The method for preparing a memory provided by an embodiment of the present invention first forms a stop material layer 40 on a step structure, then forms an isolation structure 42 with a larger width and a stop structure 43 at a preset position of a gate line gap 60, and then forms a gate line gap 60 that penetrates the isolation structure 42 and the step structure. The isolation structure 42 includes a first isolation portion 421 and a second isolation portion 422 located on both sides of the gate line gap 60 in the second direction (Y), respectively, and the first isolation portion 421 and the second isolation portion 422 are both located between the stop structure 43 and the gate line gap 60. In this way, when the interlayer sacrificial layer 22 is replaced to form an interlayer gate layer 22a, the stop structure 43 will not be removed, so the stop structure 43 can reduce the etching difficulty and process cost when forming a contact hole 70. Moreover, the thickness of the stop structure 43 can be adjusted according to the process. Compared with the process of directly etching the dielectric layer 50 and the interlayer gate layer 22a to form the contact hole 70, by increasing the thickness of the stop structure 43, the requirements for the etching selectivity can be reduced, and the process window for etching the contact hole 70 can be increased.

[0100] See also Figure 3 and Figure 2n , Figure 3 1 is a schematic diagram of the structure of a memory provided by an embodiment of the present invention. The memory 100 includes a semiconductor layer 10', a stacked structure 20a, a stop structure 43, an isolation structure 42 and a gate line gap structure 61. The stacked structure 20a is located on the semiconductor layer 10' and includes a step area, the stacked structure 20a is a step structure in the step area, the stop structure 43 covers at least part of the step structure and extends along the first direction (X). The gate line gap structure 61 passes through the step structure and extends along the first direction (X). The gate line gap structure 61 passes through the stop structure 43 and has a spacing area 40a between the stop structure 43, the spacing 40a area surrounds the gate line gap structure 61 and is surrounded by the stop structure 43. The isolation structure 42 covers part of the step structure and is located in the spacing area 40a, and the isolation structure 42 extends along the first direction (X). That is, the orthographic projection of the isolation structure 42 on the semiconductor layer 10' overlaps with the orthographic projection of the interlayer insulating layer 21 or the interlayer gate layer 22a in the stacked structure 20a on the semiconductor layer 10'. In other words, the stop structure 43 covers a portion of the step structure, and the isolation structure 42 covers the remaining portion of the step structure.

[0101] In this embodiment, the isolation structure 42 and the interlayer insulating layer 21 may include the same material, for example, both may include oxide (such as silicon oxide). In this way, in the process of replacing the interlayer sacrificial layer with the interlayer gate layer 22a, the isolation structure 42 can isolate the stop structure 43, so that the stop structure 43 is not etched.

[0102] In one embodiment, the memory 100 further includes an isolation layer 30, and the isolation layer 30 is located between the step structure and the stop structure 43, and also between the step structure and the isolation structure 42. The isolation layer 30 may include the same material as the isolation structure 42 (for example, both may include silicon oxide). The thickness of the isolation layer 30 may be less than the thickness of the stop structure 43.

[0103] In this embodiment, the isolation structure 42 and the stop structure 43 are alternately arranged along the second direction (Y), and the second direction (Y) is parallel to the semiconductor layer 10' and perpendicular to the first direction (X). The isolation structure 42 includes a first isolation portion 421 and a second isolation portion 422 respectively located on both sides of the gate line gap structure 61 in the second direction (Y), the first isolation portion 421 is located between the stop structure 43 and the gate line gap structure 61, and the second isolation portion 422 is located between the stop structure 43 and the gate line gap structure 61.

[0104] The stacked structure 20a includes interlayer insulating layers 21 and interlayer gate layers 22a that are alternately stacked. An exemplary material of the interlayer insulating layers 21 is silicon oxide, and an exemplary material of the interlayer gate layers 22a is tungsten.

[0105] In this embodiment, the memory 100 further includes a dielectric layer 50 and a word line contact 71, and the dielectric layer 50 covers the stop structure 43 and the isolation structure 42. The word line contact 71 is located on each step and penetrates the dielectric layer 50 and the stop structure 43, and the bottom of the word line contact 71 is connected to the interlayer gate layer 22a at each step.

[0106] The etching selectivity ratio of the stop structure 43 to the dielectric layer 50 is less than 1. For example, the material of the stop structure 43 may include silicon nitride, and the material of the dielectric layer 50 may include silicon oxide.

[0107] In the memory 100 provided by the embodiment of the present invention, the stop structure 43 located on the step structure is separated from the gate line gap structure 61 by an isolation structure 42, so the stop structure 43 will not be removed during the process of replacing the interlayer sacrificial layer with the interlayer gate layer 22a. Therefore, the stop structure 43 is used as an etching stop structure 43 when forming the word line contact 71, which can reduce the difficulty of the etching process in the process of forming the word line contact 71 and increase the process window.

[0108] See also Figure 4 , Figure 43 is a schematic diagram of the structure of a storage system provided in an embodiment of the present invention. The storage system 300 includes a memory 301 and a controller 302. The memory 301 may be a memory in any of the above embodiments. The controller 302 is electrically connected to the memory 301 and is used to control the memory 301 to store data. The memory 301 may perform an operation of storing data based on the control of the controller 302.

[0109] In some embodiments, the storage system may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0110] The memory 301 includes: a semiconductor layer; a stacked structure located on the semiconductor layer, the stacked structure including a step area and presenting a step structure in the step area; a stop structure covering at least a portion of the step structure and extending along a first direction; a gate line gap structure passing through the step structure, the gate line gap structure passing through the stop structure and having a spacing area between the gate line gap structure and the stop structure; an isolation structure covering a portion of the step structure and located in the spacing area, the isolation structure extending along the first direction; and word line contacts located on each step of the step structure and passing through the stop structure.

[0111] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a memory, characterized in that: include: providing a substrate; forming a stacked layer on the substrate, wherein the stacked layer comprises interlayer insulating layers and interlayer sacrificial layers that are alternately stacked, and the stacked layer comprises a step region and presents a step structure in the step region; forming a stop layer covering the step structure, wherein the stop layer includes an isolation structure and a stop structure extending along a first direction; forming a gate line gap penetrating the isolation structure and the step structure, wherein the gate line gap extends along the first direction, and the isolation structure is spaced between the stop structure and the gate line gap; Replacing the interlayer sacrificial layer with an interlayer gate layer through the gate line gap; A contact hole is formed penetrating the stop structure, wherein the bottom of the contact hole is located on the interlayer gate layer at each step of the step structure.

2. The method for preparing a memory according to claim 1, characterized in that: The isolation structure and the stop structure are alternately arranged along a second direction, which is parallel to the substrate and perpendicular to the first direction; the isolation structure includes a first isolation part and a second isolation part respectively located on both sides of the gate line gap in the second direction, the first isolation part is located between the stop structure and the gate line gap, and the second isolation part is located between the stop structure and the gate line gap.

3. The method for preparing a memory according to claim 1, characterized in that: The step of forming a stop layer covering the step structure comprises: forming a stop material layer covering the step structure, wherein the stop material layer includes an isolation region extending along a first direction; removing the stop material layer located in the isolation region, and the remaining stop material layer serves as the stop structure; The isolation structure is formed in the isolation region.

4. The method for preparing a memory according to claim 3, characterized in that: The step of forming an isolation structure in the isolation area comprises: An isolation material is deposited in the isolation region to form the isolation structure.

5. The method for preparing a memory according to claim 3, characterized in that: The step of forming an isolation structure in the isolation area comprises: forming a dielectric layer covering the stop layer and filling the isolation region; Wherein, the dielectric layer filling the isolation region forms the isolation structure.

6. The method for preparing a memory according to claim 5, characterized in that: The step of forming a contact hole penetrating the stop structure comprises: Etching the dielectric layer and part of the stop structure on each step to form a contact hole, wherein the bottom of the contact hole is located in the stop structure; Continue etching the contact hole so that the bottom of the contact hole is located on the interlayer gate layer at each step; A conductive material is filled in the contact hole to form a word line contact.

7. The method for preparing a memory according to any one of claims 1 to 6, characterized in that: Before the step of forming a stop layer covering the step structure, the method for preparing the memory further includes: An isolation layer is formed between the step structure and the stop layer.

8. The method for preparing a memory according to any one of claims 1 to 6, characterized in that: An etching selectivity ratio of the isolation structure to the interlayer sacrificial layer is less than 1.

9. The method for preparing a memory according to claim 6, characterized in that: An etching selectivity ratio of the stop structure relative to the dielectric layer is less than 1.

10. The method for preparing a memory according to claim 7, characterized in that: The thickness of the stop layer is greater than the thickness of the isolation layer.

11. A memory, characterized in that: The memory comprises: Semiconductor layer; A stacked structure, located on the semiconductor layer and comprising a step region, wherein the stacked structure is a step structure in the step region; A stop structure, covering at least a portion of the step structure and extending along a first direction; A gate line gap structure, which penetrates the step structure, passes through the stop structure and has a spacing area between the gate line gap structure and the stop structure; an isolation structure, covering a portion of the step structure and located in the spacing area, the isolation structure extending along the first direction; The word line contact is located on each step of the step structure and passes through the stop structure.

12. The memory according to claim 11, characterized in that: The isolation structure and the stop structure are alternately arranged along a second direction, which is parallel to the semiconductor layer and perpendicular to the first direction; the isolation structure includes a first isolation part and a second isolation part respectively located on both sides of the gate line gap structure in the second direction, the first isolation part is located between the stop structure and the gate line gap structure, and the second isolation part is located between the stop structure and the gate line gap structure.

13. The memory according to claim 11, characterized in that: The stacked structure includes interlayer insulating layers and interlayer gate layers that are alternately stacked; the memory further includes: a dielectric layer, covering the stop structure and the isolation structure; The word line contact penetrates the dielectric layer and the stop structure, and the bottom of the word line contact is connected to the interlayer gate layer at each step.

14. The memory according to claim 13, characterized in that: The isolation structure and the interlayer insulating layer include the same material.

15. The memory according to claim 13, characterized in that: An etching selectivity ratio of the stop structure relative to the dielectric layer is less than 1.

16. The memory according to claim 11, characterized in that: The memory also includes: An isolation layer is located between the step structure and the stop structure, and between the step structure and the isolation structure.

17. The memory according to claim 16, characterized in that: The isolation layer and the isolation structure include the same material.

18. The memory according to claim 16, characterized in that: The thickness of the stopping structure is greater than the thickness of the isolation layer.

19. A storage system, characterized in that: include: The memory as claimed in any one of claims 11 to 18; A controller is electrically connected to the memory and is used to control the memory to store data.

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