Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the structure comprising: a substrate; a first metal layer located on the substrate, the first metal layer comprising a plurality of first regions, the plurality of first regions being evenly distributed around the center point of the first metal layer; a plurality of rows of first plugs located on the first regions, the plurality of rows of first plugs being arranged in a direction from the center point to the edge of the first metal layer, the center lines of two adjacent rows of first plugs not overlapping, the center lines passing through the center point. The impact resistance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the continuous improvement of the performance of ultra-large-scale integrated circuits, the gradual reduction of device size and the continuous increase in density, in the back-end metal process of the semiconductor process, the industry uses copper and low dielectric constant materials as back-end metal interconnects and inter-metal dielectric materials (IMD, Inter-Metal Dielectric) to reduce the resistance and capacitance delay (RC Delay) of the interconnection.

[0003] However, the performance of the existing back-end process and the semiconductor structure formed therefrom still needs to be improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a first metal layer located on the substrate, the first metal layer includes a plurality of first regions, and the plurality of first regions are evenly distributed around a center point of the first metal layer; a plurality of rows of first plugs located on the first regions, the plurality of rows of first plugs are arranged in a direction from the center point to an edge of the first metal layer, the center lines of two adjacent rows of first plugs do not overlap, and the center line passes through the center point.

[0006] Optionally, the first metal layer further includes a plurality of second regions, and the second regions are located between adjacent first regions.

[0007] Optionally, it also includes: a plurality of second plugs located on the second area, wherein the plurality of second plugs are arranged in parallel from the center point to the edge of the first metal layer.

[0008] Optionally, the shape of the first metal layer projected onto the substrate surface is rectangular or circular.

[0009] Optionally, when the shape of the first metal layer projected onto the substrate surface is a rectangle, the symmetry axis of the second region is a diagonal line of the first metal layer.

[0010] Optionally, a shape of the second plug projected onto the substrate surface is a rectangle.

[0011] Optionally, when a shape of a rectangle projected by the second plugs on the substrate surface is a rectangle, a long side of the rectangle is perpendicular to an arrangement direction of the second plugs.

[0012] Optionally, a shape of the first plug projected onto the substrate surface is a rectangle.

[0013] Optionally, when a shape of the first plug projected onto the substrate surface is a rectangle, the long side of the rectangle is perpendicular to the symmetry axis of the first region.

[0014] Optionally, it also includes: a second metal layer located on the first plug and the second plug, the second metal layer being electrically connected to the first metal layer through the first plug and the second plug; and a dielectric structure located on the substrate, the first metal layer, the second metal layer, the first plug and the second plug being located within the dielectric structure.

[0015] Optionally, it also includes: an insulating layer located on the second metal layer; an opening located in the insulating layer, wherein the opening exposes a portion of the surface of the second metal layer; an electrical contact layer located in the opening; and a conductive connecting line electrically connected to the electrical contact layer.

[0016] Optionally, the substrate includes: a base; a device layer located on the base, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a combination of one or more of a transistor, a diode, a triode, a capacitor, an inductor and a conductive structure; and the first metal layer is electrically connected to the device structure.

[0017] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first metal layer on the substrate, the first metal layer comprising a plurality of first regions, the plurality of first regions being evenly distributed around a center point of the first metal layer; forming a plurality of rows of first plugs on the first regions, the plurality of rows of first plugs being arranged in a direction from the center point to an edge of the first metal layer, the center lines of two adjacent rows of first plugs not overlapping, and the center line passing through the center point.

[0018] Optionally, the first metal layer further includes a plurality of second regions, and the second regions are located between adjacent first regions.

[0019] Optionally, the method further includes: forming a plurality of second plugs on the second region, wherein the plurality of second plugs are arranged in parallel from the center point to the edge of the first metal layer.

[0020] Optionally, the shape of the first metal layer projected onto the substrate surface is rectangular or circular.

[0021] Optionally, when the shape of the first metal layer projected onto the substrate surface is a rectangle, the symmetry axis of the second region is a diagonal line of the first metal layer.

[0022] Optionally, a shape of the second plug projected onto the substrate surface is a rectangle.

[0023] Optionally, when a shape of a rectangle projected by the second plugs on the substrate surface is a rectangle, a long side of the rectangle is perpendicular to an arrangement direction of the second plugs.

[0024] Optionally, a shape of the first plug projected onto the substrate surface is a rectangle.

[0025] Optionally, when a shape of the first plug projected onto the substrate surface is a rectangle, the long side of the rectangle is perpendicular to the symmetry axis of the first region.

[0026] Optionally, it also includes: forming a second metal layer on the first plug and the second plug, the second metal layer being electrically connected to the first metal layer through the first plug and the second plug; forming a dielectric structure on the substrate, the first metal layer, the second metal layer, the first plug and the second plug being located within the dielectric structure.

[0027] Optionally, the method further includes: forming an insulating layer on the second metal layer; forming an opening in the insulating layer, wherein the opening exposes a portion of the surface of the second metal layer; forming an electrical contact layer in the opening; and forming a conductive connecting line electrically connected to the electrical contact layer.

[0028] Optionally, the substrate includes: a base; a device layer located on the base, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a combination of one or more of a transistor, a diode, a triode, a capacitor, an inductor and a conductive structure; and the first metal layer is electrically connected to the device structure.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] In the semiconductor structure of the technical solution of the present invention, the first metal layer includes a plurality of first regions, the plurality of first regions are evenly distributed around the center point of the first metal layer, and the first region has a plurality of rows of first plugs, the plurality of rows of first plugs are arranged in the direction from the center point to the edge of the first metal layer, the center lines of two adjacent rows of first plugs do not overlap, and the center lines pass through the center point. Thus, the plurality of first plugs can be arranged in a staggered manner from inside to outside around the center point of the first metal layer, and when subsequently subjected to shear force in a direction parallel to the substrate surface, the shear force in any direction can be effectively blocked, thereby enhancing the impact resistance of the first plugs, thereby improving the reliability of the semiconductor structure.

[0031] Furthermore, the shape of the first plug projected onto the substrate surface is a rectangle, and the shape of the second plug projected onto the substrate surface is a rectangle, and the rectangle has a larger surface area, so that the first plug and the second plug can have a larger force-bearing area in a direction parallel to the substrate surface, thereby enhancing the impact resistance of the first plug and the second plug, thereby improving the reliability of the semiconductor structure.

[0032] Furthermore, a plurality of the second plugs are arranged in parallel from the center point to the edge of the first metal layer, so that the second plugs and the first plugs can have a larger force-bearing area in all directions parallel to the substrate surface, thereby enhancing the impact resistance of the second plugs and the first plugs, thereby improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 and Figure 2 is a schematic cross-sectional view and a top view of a semiconductor structure in one embodiment;

[0034] Figures 3 to 8 is a cross-sectional structural schematic diagram and a top view of a semiconductor structure forming process according to an embodiment of the present invention;

[0035] Fig. 9 FIG. 4 is a top view of a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0036] As described in the background art, the performance of the existing back-end process and the semiconductor structure formed therefrom still needs to be improved.

[0037] Figure 1 and Figure 2 It is a schematic diagram of the cross-sectional structure and a top view of a semiconductor structure in one embodiment.

[0038] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic diagram of the cross-sectional structure of a semiconductor structure. Figure 2 for Figure 1The top view omitting the connection structure, the insulating layer 106, the electrical contact layer 107, the second metal layer 105 and the dielectric structure 104 comprises: a substrate 100; a device layer 101 located on the substrate 100, the device layer 101 comprising an isolation structure (not shown) and a device structure (not shown) located in the isolation structure, the device structure comprising a combination of one or more of a transistor, a diode, a triode, a capacitor, an inductor and a conductive structure; a first metal layer 102 located on the device layer 101; a plurality of plugs 103 located on the first metal layer 102; a plurality of first plugs 103 located on the plurality of first plugs 103; a plurality of second ... Two metal layers 105; a dielectric structure 104 located on the device layer 101, wherein the first metal layer 102, the plug 103 and the second metal layer 105 are located in the dielectric structure 104; an insulating layer 106 located on the dielectric structure 104 and the second metal layer 105; an electric contact layer 107 located in the insulating layer 106, wherein the electric contact layer 107 is electrically connected to the second metal layer 105; a connection structure located on the electric contact layer 107, wherein the connection structure includes a connection layer 108 and a connection line 109 electrically connected to the connection layer 108, wherein the connection structure is electrically connected to the electric contact layer 107.

[0039] In the semiconductor structure, the pattern of the plug 103 projected on the substrate 100 is usually circular, and a plurality of the plugs 103 are usually arranged in an array on the first metal layer 102. The dielectric structure 104 is usually a low-K dielectric material to reduce the parasitic capacitance of the semiconductor structure. When forming a connection structure electrically connected to the electrical contact layer 107, the material of the connection layer 108 is usually solder to connect the connection line 109 to the electrical contact layer 107.

[0040] However, during the spot soldering process, the solder bar cannot contact the electrical contact layer 107 in a direction perpendicular to the surface of the substrate 100, so the angle between the spot soldering force and the surface of the electrical contact 107 is not a right angle. Therefore, the spot soldering force will be decomposed into shear forces in two directions along the direction perpendicular to the surface of the substrate 100 and the direction parallel to the surface of the substrate 100. When a shear force in a direction parallel to the surface of the substrate 100 acts on the semiconductor structure, on the one hand, since the low-K dielectric material of the dielectric structure 104 has more pores and the material of the dielectric structure 104 is brittle, the dielectric structure 104 is prone to fracture and delamination under the shear force in a direction parallel to the surface of the substrate 100; on the other hand, since the projection of the plug 103 onto the substrate 100 is a circle and a plurality of the plugs 103 are usually arranged in an array on the first metal layer 102, the force-bearing area of ​​the plug 103 is small, and the pressure borne by the plug 103 is large. In both cases, delamination and fracture are prone to occur between the plug 103 and the dielectric structure 104, thereby affecting the performance of the semiconductor structure.

[0041] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure, wherein the first metal layer includes a plurality of first regions, the plurality of first regions are evenly distributed around the center point of the first metal layer, the first region has a plurality of rows of first plugs, the plurality of rows of first plugs are arranged along the direction from the center point to the edge of the first metal layer, the center lines of two adjacent rows of first plugs do not overlap, and the center lines pass through the center point. Thus, the plurality of first plugs can be arranged staggered from inside to outside around the center point of the first metal layer, and when subsequently subjected to shear force in a direction parallel to the substrate surface, the shear force in any direction can be effectively blocked, thereby enhancing the impact resistance of the first plugs, thereby improving the reliability of the semiconductor structure.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 3 to 8 It is a cross-sectional structural schematic diagram and a top view of a semiconductor structure forming process in one embodiment of the present invention.

[0044] Please refer to Figure 3 , providing a substrate.

[0045] The substrate includes: a base 200; a device layer 201 located on the base 200, the device layer 201 includes an isolation structure (not shown) and a device structure (not shown) located within the isolation structure, and the device structure includes a combination of one or more of a transistor, a diode, a triode, a capacitor, an inductor and a conductive structure.

[0046] In this embodiment, the material of the substrate 200 is silicon.

[0047] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0048] Please refer to Figure 4 and Figure 5 , Figure 5 for Figure 4 The top view of the first metal layer 202 is shown in FIG. 1 . The first metal layer 202 is formed on the substrate. The first metal layer 202 includes a plurality of first regions I. The plurality of first regions I are evenly distributed around a center point O of the first metal layer 202.

[0049] The first metal layer 202 is electrically connected to the device structure.

[0050] In this embodiment, the first metal layer 202 further includes a plurality of second regions II, and the second regions II are located between adjacent first regions I.

[0051] The shape of the first metal layer 202 projected onto the substrate surface is rectangular or circular.

[0052] In this embodiment, when the shape of the first metal layer 202 projected onto the substrate surface is a rectangle, the symmetry axis of the second region II is the diagonal line of the first metal layer 202 .

[0053] The first regions I are evenly distributed around a center point O of the first metal layer 202 , and the number of the first regions I is at least two.

[0054] In this embodiment, the shape of the first metal layer 202 projected onto the substrate surface is a rectangle, and the number of the first regions I is four.

[0055] In other embodiments, the shape of the first metal layer projected onto the substrate surface is circular, and the number of the first regions I is multiple.

[0056] The material of the first metal layer 202 includes metal, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0057] The method for forming the first metal layer 202 includes: forming a first dielectric layer (not shown) on a substrate; forming a first groove (not shown) in the first dielectric layer, wherein the first groove exposes a surface of the device structure; forming a first metal material layer (not shown) in the first groove and on the first dielectric layer; and planarizing the first metal material layer until the surface of the substrate is exposed to form the first metal layer 202.

[0058] The material of the first dielectric layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0059] In this embodiment, the dielectric constant of the material of the first dielectric layer is less than 2.8. The dielectric constant of the material of the first dielectric layer is relatively small, so the parasitic capacitance of the semiconductor structure can be reduced and the performance of the semiconductor structure can be improved.

[0060] Please refer to Figure 6 and Figure 7 , Figure 7 for Figure 6In the top view of the distribution of the first plugs 203 and the second plugs on the first metal layer 202, the second dielectric layer 204 is omitted. A plurality of rows of first plugs 203 are formed on the first region I, and the plurality of rows of first plugs 203 are arranged in a direction from the center point O to the edge of the first metal layer 202. The center lines of two adjacent rows of first plugs 203 do not overlap, and the center lines pass through the center point O. A plurality of second plugs 205 are formed on the second region II, and the plurality of second plugs 205 are arranged in parallel from the center point O to the edge of the first metal layer 202.

[0061] The plurality of first plugs 203 in the arrangement can be arranged in a staggered manner from the inside to the outside around the center point O of the first metal layer 202, and when subsequently subjected to shear force in a direction parallel to the substrate surface, the shear force in any direction can be effectively blocked, thereby enhancing the impact resistance of the first plugs 203, thereby improving the reliability of the semiconductor structure; the second plugs 205 and the first plugs 203 in the arrangement can have a large force-bearing area in all directions parallel to the substrate surface, thereby enhancing the impact resistance of the second plugs 205 and the first plugs 203, thereby improving the reliability of the semiconductor structure.

[0062] In this embodiment, the shape of the first plug 203 projected on the substrate surface is a rectangle. The rectangle has a large surface area, so that the first plug 203 can have a large force-bearing area in a direction parallel to the substrate surface, thereby enhancing the impact resistance of the first plug 203 and improving the reliability of the semiconductor structure.

[0063] In this embodiment, the shape of the second plug 205 projected on the substrate surface is a rectangle. The rectangle has a large surface area, so that the second plug 205 can have a large force-bearing area in a direction parallel to the substrate surface, thereby enhancing the impact resistance of the second plug 205 and improving the reliability of the semiconductor structure.

[0064] When the shape of the first plug 203 projected on the substrate surface is a rectangle, the long side of the rectangle is perpendicular to the symmetry axis of the first region I.

[0065] When the shape of the second plugs 205 projected onto the substrate surface is a rectangle, the long side of the rectangle is perpendicular to the arrangement direction of the second plugs 205 .

[0066] In this embodiment, the first plug 203 and the second plug 205 are formed simultaneously. In other embodiments, the first plug and the second plug can be formed at different times.

[0067] The method for forming the first plug 203 and the second plug 205 includes: forming a second dielectric layer 204 on the first dielectric layer and the first metal layer 202; forming a second groove (not shown) in the second dielectric layer 204, wherein the second groove exposes the surface of the first metal layer 202; forming a plug material layer (not shown) in the second groove and on the second dielectric layer 204; and planarizing the plug material layer until the surface of the second dielectric layer 204 is exposed, thereby forming the first plug 203 and the second plug 205.

[0068] The material of the first plug 203 includes metal, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum. The material of the second plug 205 includes metal, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum. The second plug 205 is located in the second dielectric layer 204.

[0069] The material of the second dielectric layer 204 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0070] In this embodiment, the dielectric constant of the material of the second dielectric layer 204 is less than 2.8. The dielectric constant of the material of the second dielectric layer 204 is relatively small, so the parasitic capacitance of the semiconductor structure can be reduced and the performance of the semiconductor structure can be improved.

[0071] Please refer to Figure 8 A second metal layer 206 is formed on the first plug 203 and the second plug 205 , and the second metal layer 206 is electrically connected to the first metal layer 202 through the first plug 203 and the second plug 205 .

[0072] The method for forming the second metal layer 206 includes: forming a third dielectric layer (not shown) on the second dielectric layer 204, on the first plug 203 and on the second plug 205; forming a third groove (not shown) in the third dielectric layer, wherein the third groove exposes the surfaces of the first plug 203 and the second plug 205; forming a second metal material layer (not shown) in the third groove and on the third dielectric layer; and planarizing the second metal material layer until the surface of the third dielectric layer is exposed to form the second metal layer 206.

[0073] The material of the second metal layer 206 includes metal, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0074] The material of the third dielectric layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0075] In this embodiment, the dielectric constant of the material of the third dielectric layer is less than 2.8. The dielectric constant of the material of the third dielectric layer is small, so the parasitic capacitance of the semiconductor structure can be reduced and the performance of the semiconductor structure can be improved.

[0076] The first dielectric layer, the second dielectric layer 204 and the third dielectric layer constitute a dielectric structure.

[0077] Please continue to refer to Figure 8 , forming an insulating layer 207 on the second metal layer 206; forming an opening (not shown) in the insulating layer 207, wherein the opening exposes a portion of the surface of the second metal layer 206; forming an electrical contact layer 208 in the opening; and forming a conductive connection line 210 electrically connected to the electrical contact layer 208.

[0078] The material of the electrical contact layer 208 includes metal, and the metal includes copper.

[0079] The conductive connection wires 210 are used for electrical connection between conductive devices in a semiconductor package.

[0080] In this embodiment, the conductive connection line 210 is electrically connected to the electrical contact layer 208 via a solder ball 209. The material of the solder ball 209 includes tin.

[0081] Since the plurality of first plugs 203 can be arranged in a staggered manner from the inside to the outside around the center point O of the first metal layer 202, and the plurality of second plugs 205 are arranged in parallel from the center point O to the edge of the first metal layer 202, when the solder ball 209 is formed on the electrical contact layer 208, the semiconductor structure is subjected to a shear force in a direction parallel to the substrate surface, and the first plugs 203 and the second plugs 205 can effectively block the shear force in any direction, thereby enhancing the impact resistance of the first plugs 203 and the second plugs 205, thereby improving the reliability of the semiconductor structure.

[0082] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 8 ,include:

[0083] substrate;

[0084] A first metal layer 202 located on the substrate, the first metal layer 202 includes a plurality of first regions I, and the plurality of first regions I are evenly distributed around a center point O of the first metal layer 202;

[0085] Several rows of first plugs 203 are located on the first area I, and the rows of first plugs 203 are arranged in the direction from the center point O to the edge of the first metal layer 202. The center lines of two adjacent rows of first plugs 203 do not overlap, and the center lines pass through the center point O.

[0086] In this embodiment, the first metal layer 202 further includes a plurality of second regions II, and the second regions II are located between adjacent first regions I.

[0087] In this embodiment, it further includes: a plurality of second plugs 205 located on the second region II, and the plurality of second plugs 205 are arranged in parallel from the center point O to the edge of the first metal layer 202 .

[0088] In this embodiment, the shape of the first metal layer 202 projected onto the substrate surface is rectangular or circular.

[0089] In this embodiment, when the shape of the first metal layer 202 projected onto the substrate surface is a rectangle, the symmetry axis of the second region II is the diagonal line of the first metal layer 202 .

[0090] In this embodiment, the shape of the second plug 205 projected onto the substrate surface is a rectangle.

[0091] In this embodiment, when the shape of the second plugs 205 projected on the substrate surface is a rectangle, the long side of the rectangle is perpendicular to the arrangement direction of the second plugs 205 .

[0092] In this embodiment, the shape of the first plug 203 projected onto the substrate surface is a rectangle.

[0093] In this embodiment, when the shape of the first plug 203 projected on the substrate surface is a rectangle, the long side of the rectangle is perpendicular to the symmetry axis of the first region I.

[0094] In this embodiment, it also includes: a second metal layer 206 located on the first plug 203 and the second plug 205, and the second metal layer 206 is electrically connected to the first metal layer 202 through the first plug 203 and the second plug 205; and a dielectric structure located on the substrate, wherein the first metal layer 202, the second metal layer 206, the first plug 203 and the second plug 205 are located in the dielectric structure.

[0095] In this embodiment, it also includes: an insulating layer 207 located on the second metal layer 206; an opening located in the insulating layer 207, wherein the opening exposes a portion of the surface of the second metal layer 206; an electrical contact layer 208 located in the opening; and a conductive connection line 210 electrically connected to the electrical contact layer 208.

[0096] In this embodiment, the substrate includes: a base 200; a device layer 201 located on the base, the device layer 201 includes an isolation structure and a device structure located within the isolation structure, the device structure includes a combination of one or more of a transistor, a diode, a triode, a capacitor, an inductor and a conductive structure; the first metal layer is electrically connected to the device structure.

[0097] In the semiconductor structure, the first metal layer 202 includes a plurality of first regions I, the plurality of first regions I are evenly distributed around the center point O of the first metal layer 202, and the first region I has a plurality of rows of first plugs 203, the plurality of rows of first plugs 203 are arranged in a direction from the center point O to the edge of the first metal layer 202, the center lines of two adjacent rows of first plugs 203 do not overlap, and the center lines pass through the center point O. Thus, the plurality of first plugs 203 can be arranged in a staggered manner from inside to outside around the center point O of the first metal layer 202, and when subsequently subjected to a shear force in a direction parallel to the substrate surface, the shear force in any direction can be effectively blocked, thereby enhancing the impact resistance of the first plugs 203, thereby improving the reliability of the semiconductor structure.

[0098] Furthermore, the shape of the first plug 203 projected onto the substrate surface is a rectangle, and the shape of the second plug 205 projected onto the substrate surface is a rectangle, and the rectangle has a larger surface area, so that the first plug 203 and the second plug 205 can have a larger force-bearing area in a direction parallel to the substrate surface, thereby enhancing the impact resistance of the first plug 203 and the second plug 205, thereby improving the reliability of the semiconductor structure.

[0099] Furthermore, a plurality of the second plugs 205 are arranged in parallel from the center point O to the edge of the first metal layer 202. Thus, the second plugs 205 and the first plugs 203 can have a large force-bearing area in all directions parallel to the substrate surface, thereby enhancing the impact resistance of the second plugs 205 and the first plugs 203, thereby improving the reliability of the semiconductor structure.

[0100] Fig. 9 FIG. 4 is a top view of a semiconductor structure according to another embodiment of the present invention.

[0101] Please refer to Fig. 9 A first metal layer 302 is formed on a substrate, wherein the first metal layer 302 includes a plurality of first regions I, which are evenly distributed around a center point O of the first metal layer 302; the first metal layer 302 also includes a plurality of second regions II, which are located between adjacent first regions I.

[0102] In this embodiment, the shape of the first metal layer 302 projected on the substrate surface is circular. At this time, the symmetry axis of the second region II is the radius of the first metal layer 302. The first regions I are evenly distributed around the center point O of the first metal layer 302. The number of the first regions I is several, and 4 are schematically shown in the figure.

[0103] The method for forming the first metal layer 302 can be found in Figure 4 and Figure 5 , I will not go into details here.

[0104] In other embodiments, the shape of the first metal layer projected onto the substrate surface may also be any desired shape, such as an ellipse.

[0105] Please continue to refer to Fig. 9 , a plurality of rows of first plugs 303 are formed on the first area I, and the plurality of rows of first plugs 303 are arranged in a direction from the center point O to the edge of the first metal layer 302, and the center lines of two adjacent rows of first plugs 303 do not overlap, and the center lines pass through the center point O; a plurality of second plugs 305 are formed on the second area II, and the plurality of second plugs 305 are arranged in parallel from the center point O to the edge of the first metal layer 302.

[0106] The formation process of the first plug 303 and the second plug 305 can be referred to Figure 6 and Figure 7 , I will not go into details here.

[0107] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A first metal layer located on the substrate, the first metal layer comprising a plurality of first regions and a plurality of second regions, the plurality of first regions being evenly distributed around a center point of the first metal layer, and the second regions being located between adjacent first regions; A plurality of rows of first plugs are located on the first region, the plurality of rows of first plugs are arranged in a direction from the center point to an edge of the first metal layer, the center lines of two adjacent rows of first plugs do not overlap, the center lines pass through the center point, the first plugs are projected onto the substrate surface in a rectangular shape, and the long side of the rectangle is perpendicular to the symmetry axis direction of the first region; A plurality of second plugs are located on the second area, and the plurality of second plugs are arranged in parallel from the center point to the edge of the first metal layer. The projection of the second plugs on the substrate surface is a rectangle, and the long side of the rectangle is perpendicular to the arrangement direction of the plurality of second plugs. The arrangement of the plurality of second plugs and the plurality of first plugs is different.

2. The semiconductor structure according to claim 1, wherein: The shape of the first metal layer projected onto the substrate surface is rectangular or circular.

3. The semiconductor structure according to claim 2, wherein: When the shape of the first metal layer projected onto the substrate surface is a rectangle, the symmetry axis of the second region is the diagonal line of the first metal layer.

4. The semiconductor structure according to claim 1, wherein: Also includes: a second metal layer located on the first plug and the second plug, the second metal layer being electrically connected to the first metal layer through the first plug and the second plug; A dielectric structure is located on a substrate, wherein the first metal layer, the second metal layer, the first plug and the second plug are located in the dielectric structure.

5. The semiconductor structure according to claim 4, characterized in that Also includes: an insulating layer located on the second metal layer; an opening in the insulating layer, wherein the opening exposes a portion of the surface of the second metal layer; an electrical contact layer located within the opening; A conductive connecting line electrically connected to the electrical contact layer.

6. The semiconductor structure according to claim 1, wherein: The substrate includes: a base; a device layer located on the base, the device layer includes an isolation structure and a device structure located within the isolation structure, the device structure includes a combination of one or more of a transistor, a diode, a triode, a capacitor, an inductor and a conductive structure; the first metal layer is electrically connected to the device structure.

7. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Forming a first metal layer on a substrate, wherein the first metal layer includes a plurality of first regions and a plurality of second regions, wherein the plurality of first regions are evenly distributed around a center point of the first metal layer, and the second regions are located between adjacent first regions; A plurality of rows of first plugs are formed on the first region, the plurality of rows of first plugs are arranged in a direction from the center point to the edge of the first metal layer, the center lines of two adjacent rows of first plugs do not overlap, the center line passes through the center point, the first plugs are projected onto the substrate surface in a rectangular shape, and the long side of the rectangle is perpendicular to the symmetry axis direction of the first region; A plurality of second plugs are formed on the second area, and the plurality of second plugs are arranged in parallel from the center point to the edge of the first metal layer. The shape of the second plugs projected on the substrate surface is a rectangle, and the long side of the rectangle is perpendicular to the arrangement direction of the plurality of second plugs. The arrangement of the plurality of second plugs and the plurality of first plugs is different.

8. The method for forming a semiconductor structure according to claim 7, wherein: The shape of the first metal layer projected onto the substrate surface is rectangular or circular.

9. The method for forming a semiconductor structure according to claim 8, wherein: When the shape of the first metal layer projected onto the substrate surface is a rectangle, the symmetry axis of the second region is the diagonal line of the first metal layer.

10. The method for forming a semiconductor structure according to claim 7, wherein: Also includes: forming a second metal layer on the first plug and the second plug, wherein the second metal layer is electrically connected to the first metal layer through the first plug and the second plug; A dielectric structure is formed on a substrate, wherein the first metal layer, the second metal layer, the first plug and the second plug are located in the dielectric structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: forming an insulating layer on the second metal layer; forming an opening in the insulating layer, wherein the opening exposes a portion of the surface of the second metal layer; forming an electrical contact layer in the opening; A conductive connection line is formed that is electrically connected to the electrical contact layer.

12. The method for forming a semiconductor structure according to claim 7, wherein: The substrate includes: a base; a device layer located on the base, the device layer includes an isolation structure and a device structure located within the isolation structure, the device structure includes a combination of one or more of a transistor, a diode, a triode, a capacitor, an inductor and a conductive structure; the first metal layer is electrically connected to the device structure.

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