Method for manufacturing on-board capacitor and printed circuit board

Abstract

The present invention provides a method for manufacturing an on-board capacitor and a printed circuit board. Based on the present invention, a stacked body with a preset capacitance value can be formed in the capacitor packaging area of ​​the printed circuit board by alternately printing a dielectric insulating layer and an electrode layer of opposite polarity that is staggered and stacked across the dielectric insulating layer, and the stacked body can be protected by a protective layer, thereby directly growing a finished on-board capacitor on the printed circuit board. On the one hand, the on-board capacitor is formed by growing on the printed circuit board without the need for a welding process, thereby being able to avoid welding defects such as cold soldering or welding short circuits; on the other hand, growing the on-board capacitor on the printed circuit board can eliminate the need for the selection and procurement of finished capacitor components, which helps to shorten the delivery cycle of the finished circuit board. In addition, the on-board capacitor grown on the printed circuit board may not be restricted by the capacitance value standard, and may support the customization of the capacitance value of the on-board capacitor produced by the manufacture.

Description

Technical Field

[0001] The present invention relates to capacitor technology, and in particular to a method for manufacturing an on-board capacitor and a printed circuit board (PCB). Background Art

[0002] Capacitors are components commonly used in printed circuit boards, and can be arranged in a capacitor packaging area of ​​the printed circuit board by welding.

[0003] However, welding defects such as cold solder joints or solder short circuits are prone to occur when welding capacitors on printed circuit boards, resulting in low connection reliability of the capacitors on the printed circuit boards.

[0004] Moreover, before the capacitor is welded, a preparation period such as capacitor device selection and procurement is involved, and such a preparation period may cause a delay in the delivery period of the finished printed circuit board assembly (PCBA).

[0005] It can be seen that how to improve the connection reliability of capacitors on printed circuit boards and shorten the delivery cycle of finished printed circuit boards has become a technical problem to be solved in the prior art. Summary of the invention

[0006] The embodiments of the present invention provide a method for manufacturing an on-board capacitor and a printed circuit board with a capacitor, which are helpful to improve the connection reliability of the capacitor on the printed circuit board and shorten the delivery cycle of the finished printed circuit board of the printed circuit board.

[0007] In one embodiment, a method for manufacturing an on-board capacitor is provided, comprising:

[0008] Providing a bare board of a printed circuit board, wherein the bare board has a capacitor packaging area;

[0009] A stacked body is formed in the capacitor packaging area by alternately printing staggered stacked electrode layers of opposite polarities and dielectric insulating layers separated between adjacent electrode layers of opposite polarities, wherein the sum of the capacitance values ​​between every two adjacent electrode layers of opposite polarities separated by the dielectric insulating layer in the stacked body reaches a preset capacitance value;

[0010] A protective layer is formed which fully covers the stacked body.

[0011] Optionally, alternately printing staggered stacked electrode layers with opposite polarities and dielectric insulating layers separated between adjacent electrode layers with opposite polarities to form a stacked body in the capacitor packaging area, including: printing first electrode layers and second electrode layers alternately staggered across the dielectric insulating layers in the capacitor packaging area, wherein: first pads and second pads spaced apart in a first direction in the capacitor packaging area are at least partially located outside the boundaries of the dielectric insulating layer on opposite sides in the first direction, the first electrode layer has a first staggered offset that protrudes outside the boundary of the dielectric insulating layer in the first direction and partially overlaps with the first pad, and , the first electrode layer is electrically isolated from the second electrode layer and the second pad by the dielectric insulating layer; the second electrode layer has a second offset that protrudes beyond the boundary of the dielectric insulating layer in the first direction and partially overlaps with the second pad, and the second electrode layer is electrically isolated from the first electrode layer and the first pad by the dielectric insulating layer; the capacitance value between each two adjacent electrode layers of opposite polarity separated by the dielectric insulating layer is associated with the area of ​​the overlapping part of the first electrode layer and the second electrode layer separated by the dielectric insulating layer, as well as the thickness of the dielectric insulating layer and the dielectric constant of the dielectric insulating layer.

[0012] Optionally, the first electrode layer and the second electrode layer that are alternately staggered across the dielectric insulating layer are printed in the capacitor packaging area, comprising: when the dielectric insulating layer is about to be printed, an insulating layer screen having an insulating layer screen pattern is positioned, and a fluid insulating material is applied to the positioned insulating layer screen so that the fluid insulating material passes through the insulating layer screen pattern to form an insulating material film layer pattern, and the dielectric insulating layer is formed after being cured; when the first electrode layer or the second electrode layer is about to be printed, an electrode layer screen having an electrode layer screen pattern is positioned, and a fluid conductive material is applied to the positioned electrode layer screen so that the fluid conductive material passes through the electrode layer screen pattern to form a conductive material film layer pattern, and the first electrode layer or the second electrode layer is formed after being cured.

[0013] Optionally, a stack is formed in the capacitor packaging area by alternately printing staggered stacked electrode layers of opposite polarity and dielectric insulating layers separated between adjacent electrode layers of opposite polarity, further comprising: printing a base insulating layer in the capacitor packaging area before alternately printing staggered stacked electrode layers of opposite polarity and dielectric insulating layers separated between adjacent electrode layers of opposite polarity; wherein the first solder pad and the second solder pad are at least partially located outside the opposite side boundaries of the base insulating layer in the first direction; and the first electrode layer and the second electrode layer partially overlap with the first solder pad and the second solder pad via the base insulating layer.

[0014] Optionally, printing a base insulating layer in the capacitor packaging area includes: positioning an insulating layer screen having an insulating layer screen pattern, and applying a fluid insulating material to the positioned insulating layer screen, so that the fluid insulating material passes through the insulating layer screen pattern to form an insulating material film layer pattern, and then forms the base insulating layer after curing.

[0015] Optionally, the first electrode layer and the second electrode layer that are alternately staggered across the dielectric insulating layer are printed in the capacitor packaging area, comprising: when the dielectric insulating layer is about to be printed, the dielectric insulating layer screen is positioned to the same positioning position as that for brushing the base insulating layer, and the positioned dielectric insulating layer screen is used to brush a fluid insulating material so that the fluid insulating material passes through the dielectric insulating layer screen pattern to form an insulating material film layer pattern, and after curing, the dielectric insulating layer that is aligned and overlapped with the base insulating layer is formed; when the first electrode layer or the second electrode layer is about to be printed, the electrode layer screen having the electrode layer screen pattern is positioned, and the positioned electrode layer screen is used to brush a fluid conductive material so that the fluid conductive material passes through the electrode layer screen pattern to form a conductive material film layer pattern, and after curing, the first electrode layer or the second electrode layer is formed.

[0016] Optionally, forming a protective layer that fully covers the stack includes: coating a protective paint with electrical insulation and anti-corrosion properties at least on the capacitor packaging area where the stack is formed, so as to form the protective layer that blocks gas and liquid.

[0017] Optionally, electrode layers that are staggered and stacked with opposite polarities and dielectric insulating layers separated between adjacent electrode layers of opposite polarities are alternately printed to form a stacked body in the capacitor packaging area, including: synchronously performing the alternating printing in the first capacitor packaging area and the second capacitor packaging area until a first stacked body with a preset first capacitance value is completed in the first capacitor packaging area; and selectively continuing to perform the alternating printing in the second capacitor packaging area until a second stacked body with a capacitance value increased to a preset second capacitance value is formed in the second capacitor packaging area.

[0018] In another embodiment, there is provided a printed circuit board, comprising:

[0019] A bare board, wherein the bare board has a capacitor packaging area;

[0020] A stacked body, wherein the stacked body is formed in the capacitor packaging area by alternately printing staggered stacked electrode layers of opposite polarities and dielectric insulating layers separated between adjacent electrode layers of opposite polarities, wherein the sum of the capacitance values ​​between every two adjacent electrode layers of opposite polarities separated by the dielectric insulating layer in the stacked body reaches a preset capacitance value;

[0021] A protective layer completely covers the stacked body.

[0022] Optionally, the preset capacitance is p×10q farads, wherein p is an integer greater than 0 or a non-integer, and q is an integer.

[0023] Based on the above embodiments, a stacked body with a preset capacitance value can be formed in the capacitor packaging area of ​​the bare board of the printed circuit board by alternately printing dielectric insulating layers and electrode layers of opposite polarities that are staggered and stacked across the dielectric insulating layers, and the stacked body can be protected by a protective layer, thereby directly growing the finished board capacitor on the printed circuit board.

[0024] On the one hand, the on-board capacitors are grown directly on the printed circuit board without the need for a welding process, thus avoiding welding defects such as cold solder joints or solder short circuits, and helping to improve the connection reliability of the capacitors on the printed circuit board; on the other hand, growing the finished on-board capacitors on the printed circuit board can avoid the selection and procurement of finished capacitor components, helping to shorten the delivery cycle of the finished printed circuit board assembly (PCBA); in addition, the on-board capacitors grown on the printed circuit board may not be restricted by the capacitance value standards like the finished capacitor components, thereby supporting the customization of capacitance values ​​(for example, supporting the customization of the capacitance values ​​of the on-board capacitors produced by manufacturing), thereby avoiding the problem of increased circuit area and inaccurate capacitance values ​​caused by the combination of multiple standard value capacitors to build an equivalent circuit when non-standard capacitance values ​​are required. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The following drawings are only used to illustrate and explain the present invention, and do not limit the scope of the present invention:

[0026] Figure 1 is a schematic diagram of an exemplary process of a method for manufacturing an on-board capacitor in one embodiment;

[0027] Figure 2a and Figure 2b To utilize Figure 1 The manufacturing method shown is a schematic diagram of a minimum capacitance unit of a capacitor grown on a printed circuit board;

[0028] Figure 3 To utilize Figure 1 The manufacturing method shown is based on an example schematic diagram of a capacitor on a pad growth board in a capacitor packaging area of ​​a printed circuit board;

[0029] Figure 4a to Figure 4g For Figure 3 A schematic top view of the capacitor on the plate in the example shown;

[0030] Figure 5 For Figure 1 The manufacturing method shown is suitable for Figure 3 A schematic diagram of the process flow of the example shown;

[0031] Figure 6a and Figure 6b For application Figure 5 A schematic diagram of the process of the process shown;

[0032] Figure 7 To utilize Figure 1 The fabrication method shown is based on a schematic diagram of an extended example of a capacitor on a pad growth plate;

[0033] Figure 8 For Figure 7 The on-board capacitor in the illustrated example further includes a schematic top view of a base insulating layer;

[0034] Figure 9a to Figure 9g For Figure 7 A schematic top view of the capacitors on the plates in the example shown;

[0035] Fig.10 like Figure 1 The manufacturing method shown is suitable for Figure 7 A schematic diagram of the process flow of the example shown;

[0036] Fig.11a and Fig.11b For application Fig.10 A schematic diagram of the process of the process shown;

[0037] Fig.12 For Figure 1 The manufacturing method shown is a schematic flow chart of growing multiple on-board capacitors on the same printed circuit board;

[0038] Fig.13a and Fig.13b To support Fig.12 Schematic diagram of the process for growing multiple on-board capacitors. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0040] Figure 1 FIG. 1 is a schematic diagram of an exemplary process of manufacturing a plate capacitor in an embodiment. Figure 1 In this embodiment, the method for manufacturing the on-board capacitor may include:

[0041] S100: providing a bare board of a printed circuit board, wherein the bare board has a capacitor packaging area;

[0042] S110: forming a stacked body in the capacitor packaging area by alternately printing staggered stacked electrode layers with opposite polarities and dielectric insulating layers separated between adjacent electrode layers with opposite polarities, wherein the sum of the capacitance values ​​between every two adjacent electrode layers with opposite polarities separated by the dielectric insulating layer in the stacked body reaches a preset capacitance value;

[0043] S120: forming a protective layer that fully covers the stacked body.

[0044] In this step, a protective paint with electrical insulation and anti-corrosion properties, such as waterproof, dustproof and anti-corrosion three-proof paint, may be applied at least on the capacitor packaging area where the stack is formed, so as to form a protective layer that blocks gas and liquid, and is used to prevent moisture, dust particles, corrosive substances, etc. in the environment from contacting the stack. For example, after the bare board forms the stack and before other components are installed on the bare board, the capacitor packaging area may be partially sprayed with a protective paint that covers the stack. Alternatively, after the bare board forms the stack and other components are installed on the bare board, the entire board surface of the printed circuit board may be sprayed or dipped with a protective paint.

[0045] Of course, the method of forming the protective layer in this step is not limited to spraying or dipping the protective paint, and the protective layer can also be formed by laying a protective film that partially covers the stack or covers the entire printed circuit board.

[0046] At this point, a growth process of the on-board capacitance of the printed circuit board is completed.

[0047] Based on the above process, a stacked body with a preset capacitance value can be formed in the capacitor packaging area of ​​the bare board of the printed circuit board by alternately printing the dielectric insulating layer and the electrode layers of opposite polarities that are staggered and stacked with the dielectric insulating layer between them. That is, both the dielectric insulating layer and the electrode layer can be formed by a unified printing process, and the stacked body can be protected by a protective layer, thereby directly growing the finished board capacitor on the printed circuit board.

[0048] On one hand, the on-board capacitor is directly grown on the printed circuit board without the need for a soldering process, thus avoiding soldering defects such as cold soldering or solder short circuits, and helping to improve the connection reliability of the capacitor on the printed circuit board;

[0049] On the other hand, by growing capacitors on the finished printed circuit board, the selection and purchase of finished capacitor components can be avoided, so that the capacitors can be arranged at any time after the bare board processing of the printed circuit board is completed, which helps to shorten the delivery cycle of the finished product manufacturing of the printed circuit board. For example, it is not necessary to modify the layout design of the printed circuit board due to design changes in the capacitance value (and at the same time, it is limited by the standard capacitance value of the optional finished capacitor components, resulting in the need to modify the series-parallel capacitor equivalent circuit); it can also avoid delays in the processing cycle of the finished circuit board due to inventory shortages of finished capacitor components or poor logistics;

[0050] Moreover, the protective layer is covered on the outermost layer of the stack to form an airtight protective layer for the stack to avoid the influence of adverse factors in the working environment that may cause damage to the stack or a significant change in capacitance, including but not limited to: preventing corrosive air (such as salt spray, etc.) from entering the stack formed by the printing process and causing various damages to the internal electrical structure of the stack, preventing moisture in the environment from entering the stack or dust from adhering to the stack to cause a significant change in the capacitance of the stack, thereby avoiding the resulting failure or performance degradation of the related circuits.

[0051] In addition, since the capacitance value of the stack obtained by the printing process is related to the number of printed electrode layers and dielectric insulating layers, the area of ​​the overlapping part of the first electrode layer and the second electrode layer separated by the dielectric insulating layer, the thickness of the dielectric insulating layer and the dielectric constant of the dielectric insulating layer, and the number of printed layers is basically not limited by the process, the area of ​​the overlapping part of the first electrode layer and the second electrode layer separated by the dielectric insulating layer, the thickness of the dielectric insulating layer, and the dielectric constant of the dielectric insulating layer are all controllable, therefore, the on-board capacitor grown on the printed circuit board may not be restricted by the capacitance value standard like the finished capacitor components, thereby supporting the customization of the capacitance value (for example, supporting the customization of the capacitance value of the on-board capacitor produced by manufacturing), thereby avoiding the problem of increased circuit area and inaccurate capacitance value caused by the combination of multiple standard value capacitors to build an equivalent circuit when non-standard capacitance values ​​are required.

[0052] Figure 2a and Figure 2b To utilize Figure 1 The manufacturing method shown is a schematic diagram of the minimum capacitance unit of the on-board capacitor grown on the printed circuit board. The minimum capacitance unit can also be understood as a minimum stack, and the minimum stack can be the minimum capacitance unit in the stack.

[0053] See also Figure 2a , each two electrode layers 210 and 220 of opposite polarity adjacent to each other through the dielectric insulating layer 200 can be regarded as the minimum capacitance unit of the plate capacitor, and the equivalent capacitance value ΔC of each minimum capacitance unit can be expressed as the following expression (1):

[0054]

[0055] The unit of the equivalent capacitance value ΔC of the minimum capacitance unit is Farad (F); S is the effective area of ​​the minimum capacitance unit, which can be the overlapping area of ​​a pair of electrode layers of opposite polarities stacked alternately through a dielectric insulating layer (the dielectric insulating layer is preferably set to extend the boundary outward from one or more directions based on the overlapping portion of a pair of electrode layers of opposite polarities stacked alternately, and the area of ​​the dielectric insulating layer is larger than the overlapping area of ​​the pair of electrode layers), and the unit can be square meters (m 2 );d is the distance between a pair of electrode layers of opposite polarity stacked alternately with dielectric insulating layers, that is, the thickness of the dielectric insulating layer sandwiched between the pair of electrode layers of opposite polarity, and its unit can be meter (m); ε is the relative dielectric constant of the dielectric insulating layer in the solid state, and its unit is F / m; ε 0 is the vacuum dielectric constant, which can be 8.86×10 -12 , the unit is F / m.

[0056] Assuming that the sum of the number of electrode layers of opposite polarity is K (K is a natural number), if the number of electrode layers of different polarity is the same (when K is an even number) or the difference in the number of electrode layers of different polarity is 1 (when K is an odd number), and the number of dielectric insulating layers is K-1, then K-1 pairs of electrode layers of opposite polarity stacked alternately with dielectric insulating layers separated can be formed. At this time, the equivalent capacitance C of the stack can be the series value of the equivalent capacitance value ΔC of K-1 minimum capacitance units, and can be expressed as the following expression (2):

[0057]

[0058] See also Figure 2b In actual processing, due to positioning errors, the effective areas S_i and S_j of different minimum capacitance units and / or the thicknesses d_i and d_j of different dielectric insulating layers may be slightly different. In this case, the equivalent capacitance C of the stack can also be more accurately expressed as the following expression (3):

[0059]

[0060] Alternatively, the equivalent capacitance C of the stack can also be approximately expressed as the following expression (4):

[0061]

[0062] Wherein, S_avg represents the average value of overlapping areas S_k of K-1 pairs of electrode layers of opposite polarities stacked alternately with dielectric insulating layers therebetween, and d_avg represents the average value d_k of the thickness of K-1 dielectric insulating layers.

[0063] Regardless of how the equivalent capacitance C of the stack is expressed, it can be regarded as an accumulated value with the equivalent capacitance value ΔC as the granularity. Therefore, the capacitance value of the on-board capacitor can be customized with the equivalent capacitance value ΔC as the granularity.

[0064] The customization described in this article is relative to the IEC (International Electrotechnical Commission) standard value of MLCC (Multi-layer Ceramic Capacitors), which is the most widely used chip in the electronics industry.

[0065] Specifically, the IEC standard capacitance value of MLCC is expressed as the product of a fixed value C_std with two significant digits and 10 to the power of n, for example, C_std×10 n , where C_std is a selected value from the following set of constants:

[0066] {1.0, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 2.0, 2.2, 2.4, 2.7, 3.0, 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1}

[0067] If there is no C_std × 10 n If non-standard capacitance values ​​are required, then:

[0068] It is necessary to build a capacitor equivalent circuit by connecting multiple standard value capacitors in series, parallel, or series-parallel, which makes the circuit design complicated and occupies the layout space of the printed circuit board;

[0069] Alternatively, embedded capacitors need to be processed on printed circuit boards. However, the manufacturing process of printed circuit boards with embedded capacitors is complicated, the cost is greatly increased, and the failure rate of printed circuit boards during use is easily increased (for example, thermal expansion and contraction may cause the vias of embedded capacitors to break, etc.).

[0070] In the above embodiment, since the on-board capacitor is not subject to the capacitance value standard restriction like the finished component, the capacitor that does not meet C_std×10 n To meet the demand for non-standard capacitance values, there is no need to use MLCC capacitors with standard capacitance values ​​to build equivalent circuits, nor is there any need to manufacture embedded capacitors during printed circuit board processing.

[0071] That is, the preset capacitance of the stack can be expressed as p×10q Farad (F), where p is any integer or non-integer greater than 0, and q is an integer (positive or negative).

[0072] In order to better understand the technical solution of the above embodiment, it is described in detail below with reference to specific examples.

[0073] Figure 3 To utilize Figure 1 The manufacturing method shown is based on an example schematic diagram of a capacitor on a pad growth board in a capacitor packaging area of ​​a printed circuit board. Figure 4a to Figure 4g For Figure 3 Schematic top view of the on-board capacitors in the example shown.

[0074] See also Figure 3 Combined with Figure 4a to Figure 4g In this example, a first pad 310 and a second pad 320 of opposite polarities are spaced apart in a first direction of the capacitor packaging area 300, wherein the electrode layer electrically connected to the first pad 310 and electrically isolated from the second pad 320 can be referred to as a first electrode layer 410, and the electrode layer electrically connected to the second pad 320 and electrically isolated from the first pad 310 can be referred to as a second electrode layer 420.

[0075] In this example, the overlapping area of ​​the first electrode layer 410 and the second electrode layer 420 of opposite polarities stacked alternately across the dielectric insulating layer 400 is represented as S30, and the overlapping area S30 can be located in the interval between the first pad 310 and the second pad 320 in the first direction, that is, the opposite side boundaries of the dielectric insulating layer 400 in the first direction at least extend a certain distance from the opposite side boundaries of the overlapping area S30 in the first direction. In addition, at least one side boundary of the opposite side boundaries of the dielectric insulating layer 400 in the second direction intersecting (e.g., perpendicular to) the first direction extends a certain distance from the corresponding side boundary of the opposite side boundaries of the overlapping area S30 in the second direction.

[0076] One end of the first electrode layer 410 close to the first pad 310 extends out of the boundary of the dielectric insulating layer 400 in the first direction and partially overlaps with the first pad 310, so as to achieve electrical connection with the first pad 310; and the other end of the first electrode layer 410 close to the second pad 320 is retracted within the boundary of the dielectric insulating layer 400 at the interval between the first pad 310 and the second pad 320, so as to be electrically isolated from the second electrode layer 420 and the second pad 320 through the dielectric insulating layer 400;

[0077] One end of the second electrode layer 420 close to the second pad 320 protrudes beyond the boundary of the dielectric insulating layer 400 in the first direction and partially overlaps with the second pad 320 to achieve electrical connection with the second pad 320; and the other end of the second electrode layer 420 close to the first pad 310 is retracted within the boundary of the dielectric insulating layer 400 at the interval between the first pad 310 and the second pad 320 to be electrically isolated from the first electrode layer 410 and the first pad 310 through the dielectric insulating layer 400.

[0078] Figure 4a to Figure 4g What is shown is a preferred manner, that is, the boundaries of the dielectric insulating layer 400 in the first direction and the second direction can be respectively located outside the boundaries of the overlapping region S30 in the first direction and the second direction, so that the boundary of the dielectric insulating layer 400 can completely surround the overlapping region S30.

[0079] exist Figure 4a to Figure 4g In the embodiment, the size of the overlapping area S30 in the first direction is smaller than the spacing distance between the first pad 310 and the second pad 320. In this case:

[0080] The dimension L40 of the dielectric insulating layer 400 in the first direction may be equal to (eg Figure 4a to Figure 4g The spacing distance between the first pad 310 and the second pad 320 is shown in the solid dimension line L40, so that the first pad 310 and the second pad 320 are all located outside the boundary of the dielectric insulating layer 400 in the first direction;

[0081] Alternatively, the dimension L40 of the dielectric insulating layer 400 in the first direction may also be greater than (eg Figure 4a to Figure 4g The spacing distance between the first solder pad 310 and the second solder pad 320 is shown by the dotted arrows on both sides of the dimension line L40 in the figure, and only the first solder pad 310 and the second solder pad 320 are partially covered in the first direction, so that the parts of the first solder pad 310 and the second solder pad 320 that are not overlapped with the dielectric insulating layer 400 are respectively located outside the two boundaries of the dielectric insulating layer 400 in the first direction.

[0082] Thus, the first pads 310 and the second pads 320 spaced apart in the first direction of the capacitor packaging region 300 may be at least partially located outside the boundaries of the dielectric insulating layer 400 on opposite sides in the first direction.

[0083] exist Figure 4a to Figure 4g middle:

[0084] The boundary of the overlapping area S30 in the second direction may be as follows: Figures 4a to 4c As shown, the first pad 310 and the second pad 320 are located within the boundary of the first pad 310 and the second pad 320 in the second direction ( Figure 4b and Figure 4cIt is used to indicate that the sizes of the first electrode layer 410 and the second electrode layer 420 in the first direction and / or the second direction may be different). In this case, the boundary of the dielectric insulating layer 400 in the second direction is located outside the boundary of the overlapping area S30 in the second direction, and may be located within the boundary of the first pad 310 and the second pad 320 in the second direction, or may extend to outside the boundary of the first pad 310 and the second pad 320 in the second direction as shown by the dotted arrow, or may even extend to outside the boundary of the capacitor packaging area 300 in the second direction;

[0085] Alternatively, the boundary of the overlapping area S30 in the second direction may be as follows: Figure 4d and Figure 4e As shown in FIG. 1 , the boundary between the first pad 310 and the second pad 320 in the second direction ( Figure 4e It is used to indicate that the first electrode layer 410 and the second electrode layer 420 may have different sizes in the first direction) are aligned. In this case, the boundary of the dielectric insulating layer 400 in the second direction may be outside the boundary of the first pad 310 and the second pad 320 in the second direction, or may extend to outside the boundary of the capacitor packaging area 300 in the second direction as indicated by the dotted arrow;

[0086] Alternatively, the boundary of the overlapping area S30 in the second direction may also be as follows: Figure 4f and Figure 4g As shown, the boundary between the first pad 310 and the second pad 320 in the second direction and the boundary of the capacitor packaging area 300 in the second direction ( Figure 4g Used to indicate that the sizes of the first electrode layer 410 and the second electrode layer 420 in the first direction and / or the second direction may be different). In this case, the boundary of the dielectric insulating layer 400 in the second direction may be flush with the boundary of the capacitor packaging area 300 in the second direction, or may extend beyond the boundary of the capacitor packaging area 300 in the second direction as indicated by the dotted arrow.

[0087] exist Figure 4a to Figure 4g Although only the opposite ends of the first electrode layer 410 and the second electrode layer 420 are shown to be located within the boundary of the first pad 310 and the second pad 320 in the first direction, it can be understood that the opposite ends of the first electrode layer 410 and the second electrode layer 420 can also extend to the boundary of the capacitor packaging area 300 on the first side as shown by the dotted arrows.

[0088] In addition, Figure 4a to Figure 4g In the example, the capacitor packaging area 300 is a rectangle. In this case, the first direction of the capacitor packaging area 300 may be the length direction of the rectangle, and the second direction may be the width direction of the capacitor packaging area 300. Figures 4a to 4e The example in which the first solder pad 310 and the second solder pad 320, the first electrode layer 410, the second electrode layer 420 and the dielectric insulating layer 400 are all rectangles is also taken, but it can be understood that such a view expression is only for the convenience of intuitively distinguishing the boundaries of different structures, and should not constitute unnecessary limitations on the shapes of the capacitor packaging area 300, the first solder pad 310 and the second solder pad 320, the first electrode layer 410, the second electrode layer 420 and the dielectric insulating layer 400.

[0089] Figure 5 For Figure 1 The manufacturing method shown is suitable for Figure 3 Schematic diagram of the process flow of the example shown. Figure 5 , the manufacturing method in this embodiment may specifically include:

[0090] S500: providing a bare board of a printed circuit board, wherein the bare board has a capacitor packaging area;

[0091] S510: printing staggered and stacked first and second electrode layers with opposite polarities and a dielectric insulating layer separated between adjacent first and second electrode layers with opposite polarities in a capacitor packaging region, wherein:

[0092] (1) A first pad and a second pad are arranged in a first direction of the capacitor packaging region at intervals, and are at least partially located outside two opposite sides of the dielectric insulating layer in the first direction;

[0093] (2) The first electrode layer has a first offset that extends beyond the boundary of the dielectric insulating layer in the first direction and partially overlaps with the first pad, and the first electrode layer is electrically isolated from the second electrode layer and the second pad by the dielectric insulating layer;

[0094] (3) The second electrode layer has a second offset that extends beyond the boundary of the dielectric insulating layer in the first direction and partially overlaps with the second pad, and the second electrode layer is electrically isolated from the first electrode layer and the first pad by the dielectric insulating layer;

[0095] (4) The capacitance between each two adjacent electrode layers of opposite polarity separated by a dielectric insulating layer is related to the area of ​​the overlapping portion of the first electrode layer and the second electrode layer separated by the dielectric insulating layer, the thickness of the dielectric insulating layer, and the dielectric constant of the dielectric insulating layer.

[0096] S520: forming a protective layer that fully covers the stacked body.

[0097] At this point, a growth process of the on-board capacitance of the printed circuit board is completed.

[0098] Figure 6a and Figure 6bFor application Figure 5 Schematic diagram of the process of the process shown.

[0099] See also Figure 6a ,like Figure 5 S510 in the process shown may use a screen with a screen pattern, namely:

[0100] S510a: when the first electrode layer 410 is about to be printed, the first electrode layer screen 61 having the first electrode layer screen pattern 610 is positioned, and the fluid conductive material is applied to the positioned first electrode layer screen 61, so that the fluid conductive material passes through the first electrode layer screen pattern 610 to form a conductive material film layer pattern (first conductive material film layer pattern), and the first electrode layer 410 is formed after being cured;

[0101] S510b: when the dielectric insulating layer 400 is to be printed, the insulating layer screen 60 having the insulating layer screen pattern 600 is positioned, and the fluid insulating material is applied to the positioned insulating layer screen 60, so that the fluid insulating material passes through the insulating layer screen pattern 600 to form an insulating material film layer pattern, and the dielectric insulating layer 400 is formed after being cured;

[0102] S510c: when the second electrode layer 420 is about to be printed, the second electrode layer screen 62 having the second electrode layer screen pattern 620 is positioned, and the fluid conductive material is applied to the positioned second electrode layer screen 62, so that the fluid conductive material passes through the second electrode layer screen pattern 620 to form a conductive material film layer pattern (second conductive material film layer pattern), and the second electrode layer 420 is formed after being cured;

[0103] S510d: When the dielectric insulating layer 400 is about to be printed again, the insulating layer screen 60 having the insulating layer screen pattern 600 is positioned, and the fluid insulating material is applied to the positioned insulating layer screen 60 so that the fluid insulating material passes through the insulating layer screen pattern 600 to form an insulating material film layer pattern, and the dielectric insulating layer 400 is formed after curing.

[0104] S510e: When the first electrode layer 410 is about to be printed again, the first electrode layer screen 61 having the first electrode layer screen pattern 610 is positioned, and the fluid conductive material is applied to the positioned first electrode layer screen 61 so that the fluid conductive material passes through the first electrode layer screen pattern 610 to form a conductive material film layer pattern (first conductive material film layer pattern), and the first electrode layer 410 is formed after curing.

[0105] After executing S510a once:

[0106] After performing the complete cycle of S510b to S510e for several times, S520 may be performed to form a protective layer 430 that fully covers the stacked body;

[0107] Alternatively, after performing several complete cycles of S510b to S510e, a half cycle of S510b to S510c may be performed, and then S520 may be performed to form the protective layer 430 that fully covers the stacked body.

[0108] See also Figure 6b If the first electrode layer 410 and the second electrode layer 420 have the same shape and size, the first electrode layer 410 and the second electrode layer 420 can be printed using the same screen. Figure 5 S510 in the illustrated process may include:

[0109] S510a': when the first electrode layer 410 is about to be printed, the electrode layer screen 63 having the reusable electrode layer screen pattern 630 is positioned, and the fluid conductive material is applied to the positioned reusable electrode layer screen 63, so that the fluid conductive material passes through the reusable electrode layer screen pattern 630 to form a conductive material film layer pattern (first conductive material film layer pattern), and the first electrode layer 410 is formed after being cured;

[0110] S510b: when the dielectric insulating layer 400 is to be printed, the insulating layer screen 60 having the insulating layer screen pattern 600 is positioned, and the fluid insulating material is applied to the positioned insulating layer screen 60, so that the fluid insulating material passes through the insulating layer screen pattern 600 to form an insulating material film layer pattern, and the dielectric insulating layer 400 is formed after being cured;

[0111] S510c': when the second electrode layer 420 is about to be printed, the reusable electrode layer screen 63 having the reusable electrode layer screen pattern 630 is positioned at a different position from that when the first electrode layer 410 is printed, and the fluid conductive material is applied to the positioned reusable electrode layer screen 63 so that the fluid conductive material passes through the reusable electrode layer screen pattern 630 to form a conductive material film layer pattern (a second conductive material film layer pattern), and the second electrode layer 420 is formed after being cured;

[0112] S510d: When the dielectric insulating layer 400 is about to be printed again, the insulating layer screen 60 having the insulating layer screen pattern 600 is positioned, and the fluid insulating material is applied to the positioned insulating layer screen 60 so that the fluid insulating material passes through the insulating layer screen pattern 600 to form an insulating material film layer pattern, and the dielectric insulating layer 400 is formed after curing.

[0113] S510e': When the first electrode layer 410 is about to be printed again, the reusable electrode layer screen 63 having the reusable electrode layer screen pattern 630 is positioned at the same printing positioning position as in step S510a', and the fluid conductive material is applied to the positioned reusable electrode layer screen 63 so that the fluid conductive material passes through the reusable electrode layer screen pattern 630 to form a conductive material film layer pattern (first conductive material film layer pattern), and the first electrode layer 410 is formed after curing.

[0114] After executing S510a' once:

[0115] After performing several complete cycles of S510b' to S510e', S520 may be performed to form a protective layer 430 that fully covers the stacked body;

[0116] Alternatively, after performing several complete cycles of S510b' to S510e', a half cycle of S510b' to S510c' may be performed, and then S520 may be performed to form the protective layer 430 that fully covers the stacked body.

[0117] In such Figure 6a or Figure 6b In the process flow shown, insulating ink can be used as the fluid insulating material, and conductive ink can be used as the fluid conductive material.

[0118] If the thickness of the dielectric insulating layer 400 formed by curing the insulating ink is too small, it is easy to cause holes in the dielectric insulating layer 400, resulting in short-circuit contact or insufficient voltage resistance between the two adjacent first electrode layers 410 and the second electrode layer 420 above and below it; if the thickness of the dielectric insulating layer 400 formed by curing the insulating ink is too large, it is easy to cause the distance d between the two adjacent first electrode layers 410 and the second electrode layer 420 above and below it to be too large, resulting in a decrease in the capacitance value of the minimum capacitor unit, thereby resulting in too many stacked minimum capacitor units when the stack meets the preset capacitance value, too high overall height, or a real capacitance value that is smaller than the preset capacitance value when the expected stacking height is met. Similarly, the thickness of the first electrode layer 410 and the second electrode layer 420 formed by curing the conductive ink should not be too large or too small.

[0119] The ink thickness can be controlled by controlling the following technical parameters so that the dielectric insulating layer 400, the first electrode layer 410 and the second electrode layer 420 reach the desired thickness: the diluent content of the ink, the hole density (mesh count) of the screen, the running speed of the printing scraper, the distance between the insulating layer screen or the electrode layer screen and the surface to be coated, etc.

[0120] After brushing, the insulating material film layer pattern and the conductive material film layer pattern formed can be solidified by a baking process or an ultraviolet irradiation process.

[0121] Among them, the baking process used to solidify each layer of insulating material film layer pattern and conductive material film layer pattern can last for a preset baking time (for example, 10 to 30 minutes) and a preset baking temperature (for example, 150±10°C); the ultraviolet irradiation process used to solidify each layer of insulating material film layer pattern and conductive material film layer pattern, the preset irradiation time can be set according to the light intensity.

[0122] In addition, when silver paste ink is selected as the fluid conductive material, due to the poor light transmittance of metallic silver powder, it is preferably cured by a baking process.

[0123] Figure 7 To utilize Figure 1 The fabrication method shown is based on a schematic diagram of an extended example of a capacitor on a pad growth plate. Figure 8 For Figure 7 The on-board capacitor in the illustrated example further includes a schematic top view of a base insulating layer. Figure 9a to Figure 9g For Figure 7 A top view of the capacitors on the board in the example shown. Figure 7 Combined with Figure 8 as well as Figure 9a to Figure 9g In this extended example, in the first direction of the capacitor packaging area 300, it is still like Figure 3 As shown in the example, a first pad 310 and a second pad 320 of opposite polarities are arranged at intervals, and the electrode layer electrically connected to the first pad 310 and electrically isolated from the second pad 320 can be referred to as a first electrode layer 710, and the electrode layer electrically connected to the second pad 320 and electrically isolated from the first pad 310 can be referred to as a second electrode layer 720.

[0124] But unlike Figure 3 The example shown is that in Figure 7 In the extended example shown, the overlapping area S70 of the first electrode layer 710 and the second electrode layer 720 of opposite polarities stacked alternately via the dielectric insulating layer 400 spans the interval between the first pad 310 and the second pad 320 in the first direction and forms a partial overlap with both the first pad 310 and the second pad 320.

[0125] Please pay special attention Figure 8 In order to avoid the first electrode layer 710 at the bottom of the stack from making conductive contact with the second pad 320 of opposite polarity, Figure 7In the extended example shown, before printing the first electrode layer 710 and the second electrode layer 720 alternately staggered across the dielectric insulating layer 700 in the capacitor packaging area 300, it is necessary to first additionally print the base insulating layer 800 in the capacitor packaging area 300. The first electrode layer 710 and the second electrode layer 720 printed subsequently partially overlap the first pad 310 and the second pad 320 across the base insulating layer 800, across the overlapping portion S70 of the dielectric insulating layer 700.

[0126] The base insulating layer 800 may partially cover the first pad 310 and the second pad 320 in the first direction, and the base insulating layer 800 may partially cover or fully cover the first pad 310 and the second pad 320 in the second direction. The scalability of the coverage range of the base insulating layer 800 is as follows: Figure 8 Indicated by dotted arrows.

[0127] In actual design, the shape and size of the base insulating layer 800 may be the same as the shape and size of the dielectric insulating layer 700, or may be different from the shape and size of the dielectric insulating layer 700. For the convenience of description and graphic expression, in this extended example, it is taken that the shape and size of the base insulating layer 800 may be the same as the shape and size of the dielectric insulating layer 700.

[0128] In this case, the boundary between the base insulating layer 800 and the dielectric insulating layer 700 in the first direction is at least flush with the boundary of the overlapping region S70 in the first direction, or preferably, the two opposite side boundaries of the base insulating layer 800 in the first direction can at least expand and extend beyond the corresponding side boundaries of the overlapping region S70 in the first direction. In addition, the boundary between the base insulating layer 800 and the dielectric insulating layer 700 in a second direction intersecting (e.g., perpendicular to) the first direction is at least flush with the boundary of the overlapping region S70 in the second direction, or preferably, at least one side boundary of the two opposite side boundaries of the base insulating layer 800 in the second direction can expand and extend beyond the corresponding side boundary of the overlapping region S70 in the second direction.

[0129] One end of the first electrode layer 710 close to the first pad 310 extends out to the outside of the boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction and partially overlaps with the first pad 310, so as to realize electrical connection with the first pad 310; and the other end of the first electrode layer 710 close to the second pad 320 is retracted above the second pad 320 within the boundary of the base insulating layer 800 and the dielectric insulating layer 700, so as to be electrically isolated from the second electrode layer 720 and the second pad 320 by at least one of the base insulating layer 800 and the dielectric insulating layer 700;

[0130] One end of the second electrode layer 720 close to the second solder pad 320 protrudes beyond the boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction and partially overlaps with the second solder pad 320 to achieve electrical connection with the second solder pad 320; and, the other end of the second electrode layer 720 close to the first solder pad 310 is retracted above the first solder pad 310 within the boundary of the base insulating layer 800 and the dielectric insulating layer 700 to be electrically isolated from the first electrode layer 710 and the first solder pad 310 through at least one of the base insulating layer 800 and the dielectric insulating layer 700.

[0131] By further printing the base insulating layer 800, the capacitor packaging area 300 of the bare board of the printed circuit board can be flattened. For example, there will be a concave gap (similar to a "groove") with a width of about 0.1 mm between the boundary of the solder mask layer (commonly known as "green oil") in the capacitor packaging area 300 of the bare board of the printed circuit board and the boundary of the copper foil layer on the surface of the first pad 310 and the second pad 320. The printed base insulating layer 800 can make the surface unevenness caused by the concave gap tend to be flattened, which helps to flatten the stack.

[0132] Figure 9a to Figure 9g What is shown is a preferred manner, that is, the boundaries of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction and the second direction can be respectively located outside the boundaries of the overlapping area S70 in the first direction and the second direction, thereby, the boundary of the base insulating layer 800 and the dielectric insulating layer 700 can completely surround the overlapping area S70.

[0133] exist Figure 9a to Figure 9g In the embodiment, the size of the overlapping area S70 in the first direction is greater than (or may be equal to) the spacing distance between the first pad 310 and the second pad 320. In this case, the size L70 of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction may be greater than (eg Figure 9a to Figure 9g The spacing distance between the first pad 310 and the second pad 320 (as shown by the solid dimension line L70) is such that the first pad 310 and the second pad 320 are only partially located outside the boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction.

[0134] The size L70 of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction can be adjusted according to actual needs, that is, Figure 9a to Figure 9g As shown by the dotted arrows on both sides of the dimension line L70, it is sufficient as long as the base insulating layer 800 and the dielectric insulating layer 700 only partially cover the first pad 310 and the second pad 320 in the first direction.

[0135] exist Figure 9a to Figure 9g middle:

[0136] The boundary of the overlapping area S70 in the second direction may be as follows: Figures 9a to 9c As shown, the first pad 310 and the second pad 320 are located within the boundary of the first pad 310 and the second pad 320 in the second direction ( Figure 9b and Fig.9c It is used to indicate that the sizes of the first electrode layer 710 and the second electrode layer 720 in the first direction and / or the second direction may be different). In this case, the boundary between the base insulating layer 800 and the dielectric insulating layer 700 in the second direction is located outside the boundary of the overlapping area S70 in the second direction, and may be located within the boundary of the first pad 310 and the second pad 320 in the second direction, or may extend to outside the boundary of the first pad 310 and the second pad 320 in the second direction as indicated by the dotted arrow, or may even extend to outside the boundary of the capacitor packaging area 300 in the second direction;

[0137] Alternatively, the boundary of the overlapping area S70 in the second direction may be as follows: Figure 9d and Fig.9e As shown in FIG. 1 , the boundary between the first pad 310 and the second pad 320 in the second direction ( Fig.9e It is used to indicate that the sizes of the first electrode layer 710 and the second electrode layer 720 in the first direction may be different) aligned, in which case, the boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the second direction may be outside the boundary of the first pad 310 and the second pad 320 in the second direction, or may extend to outside the boundary of the capacitor packaging area 300 in the second direction as indicated by the dotted arrow;

[0138] Alternatively, the boundary of the overlapping area S70 in the second direction may also be as follows: Figure 9f and Figure 9g As shown, the boundary between the first pad 310 and the second pad 320 in the second direction and the boundary of the capacitor packaging area 300 in the second direction ( Figure 9g Used to indicate that the sizes of the first electrode layer 710 and the second electrode layer 720 in the first direction and / or the second direction may be different). In this case, the boundary between the base insulating layer 800 and the dielectric insulating layer 700 in the second direction may be flush with the boundary of the capacitor packaging area 300 in the second direction, or may extend beyond the boundary of the capacitor packaging area 300 in the second direction as indicated by the dotted arrow.

[0139] exist Figure 9a to Figure 9gAlthough only the opposite ends of the first electrode layer 710 and the second electrode layer 720 are shown to be located within the boundary of the first pad 310 and the second pad 320 in the first direction, it can be understood that the opposite ends of the first electrode layer 710 and the second electrode layer 720 can also extend to the boundary of the capacitor packaging area 300 on the first side as shown by the dotted arrows.

[0140] In addition, Figure 4a to Figure 4g Similarly, in Figure 9a to Figure 9g The rectangular view expression used in the drawing should not constitute unnecessary limitation on the shapes of the capacitor packaging area 300 , the first pad 310 , the second pad 320 , the first electrode layer 710 , the second electrode layer 720 , the base insulating layer 800 , and the dielectric insulating layer 700 .

[0141] It is understandable that if Figure 3 The example shown does not exclude the arrangement of the base insulating layer 800. Figure 3 In the example shown, the first pads 310 and the second pads 320 spaced apart in the first direction of the capacitor packaging region 300 may be at least partially located outside the boundary of the base insulating layer 800 and the dielectric insulating layer 400 in the first direction.

[0142] Fig.10 like Figure 1 The manufacturing method shown is suitable for Figure 7 Schematic diagram of the process flow of the example shown. Fig.10 , the manufacturing method in this embodiment may specifically include:

[0143] S1000: providing a bare board of a printed circuit board, wherein the bare board has a capacitor packaging area;

[0144] S1011: printing a base insulating layer in a capacitor packaging region, wherein the first pad and the second pad are at least partially located outside two opposite side boundaries of the base insulating layer in a first direction;

[0145] S1012: printing the first electrode layers and the second electrode layers which are stacked and staggered and have opposite polarities and the dielectric insulating layer which is separated between the adjacent first electrode layers and the second electrode layers with opposite polarities in the capacitor packaging area where the base insulating layer is formed,

[0146] in:

[0147] (1) A first pad and a second pad are arranged in a first direction of the capacitor packaging region at intervals, and are at least partially located outside two opposite sides of the dielectric insulating layer in the first direction;

[0148] (2) The first electrode layer has a first offset that extends beyond the boundary of the base insulating layer and the dielectric insulating layer in the first direction and partially overlaps with the first pad, and the first electrode layer is electrically isolated from the second electrode layer and the second pad by the base insulating layer and the dielectric insulating layer;

[0149] (3) The second electrode layer has a second offset that extends beyond the boundary of the base insulating layer and the dielectric insulating layer in the first direction and partially overlaps with the second pad, and the second electrode layer is electrically isolated from the first electrode layer and the first pad by the base insulating layer and the dielectric insulating layer;

[0150] (4) The overlapping portion of the first electrode layer and the second electrode layer through the dielectric insulating layer partially overlaps the first pad and the second pad through the base insulating layer;

[0151] (5) The capacitance between each two adjacent electrode layers of opposite polarity separated by a dielectric insulating layer is related to the area of ​​the overlapping portion of the first electrode layer and the second electrode layer separated by the dielectric insulating layer, the thickness of the dielectric insulating layer, and the dielectric constant of the dielectric insulating layer.

[0152] S1020: forming a protective layer that fully covers the stack.

[0153] At this point, a growth process of the on-board capacitance of the printed circuit board is completed.

[0154] Fig.11a and Fig.11b For application Fig.10 Schematic diagram of the process of the process shown.

[0155] See also Fig.11a ,like Fig.10 Both S1011 and S1012 in the process shown can use screens with silk screen patterns, namely:

[0156] S1011: positioning the insulating layer screen 110 having the insulating layer screen pattern 1100, and applying a fluid insulating material to the positioned insulating layer screen 110, so that the fluid insulating material passes through the insulating layer screen pattern 1100 to form an insulating material film layer pattern, and after curing, a base insulating layer 800 is formed;

[0157] Then, after executing S1012a once and several complete cycles of S1012b to S1012e, or after executing S1012a once, several complete cycles of S1012b to S1012e, and one half cycle of S1012b to S1012c, S1120 may be executed to form a protective layer 730 that fully covers the stack.

[0158] Fig.11aS1012a to S1012e in can be used as Figure 6a The S510a and S510e shown are basically the same, as follows:

[0159] S1012a: When the first electrode layer 710 is about to be printed, the first electrode layer screen 111 having the first electrode layer screen pattern 1110 is positioned, and the fluid conductive material is applied to the positioned first electrode layer screen 111, so that the fluid conductive material passes through the first electrode layer screen pattern 1110 to form a conductive material film layer pattern (first conductive material film layer pattern), and after curing, the first electrode layer 710 partially overlaps with the base insulating layer 800 is formed;

[0160] S1012b: When the dielectric insulating layer 700 is about to be printed, the insulating layer screen 110 for printing the base insulating layer 800 can be reused, and the insulating layer screen 110 is positioned to the same positioning position as the base insulating layer 800, and the fluid insulating material is applied to the positioned insulating layer screen 110, so that the fluid insulating material passes through the insulating layer screen pattern 1100 to form an insulating material film layer pattern, and after curing, the dielectric insulating layer 700 that is substantially completely overlapped with the base insulating layer 800 is formed;

[0161] S1012c: when the second electrode layer 720 is about to be printed, the second electrode layer screen 112 having the second electrode layer screen pattern 1120 is positioned, and the fluid conductive material is applied to the positioned second electrode layer screen 112, so that the fluid conductive material passes through the second electrode layer screen pattern 1120 to form a conductive material film layer pattern (second conductive material film layer pattern), and the second electrode layer 720 is formed after being cured;

[0162] S1012d: When the dielectric insulating layer 700 is about to be printed again, the insulating layer screen 110 is still positioned to the same positioning position as that for the base insulating layer 800, and the fluid insulating material is applied to the positioned insulating layer screen 110 so that the fluid insulating material passes through the insulating layer screen pattern 1100 to form an insulating material film layer pattern, and after curing, a dielectric insulating layer 700 that is substantially completely overlapped with the base insulating layer 800 is formed.

[0163] S1012e: When the first electrode layer 710 is about to be printed again, the electrode layer screen 111 having the first electrode layer screen pattern 1110 is positioned at the same printing positioning position as in step S1012a, and the fluid conductive material is applied to the positioned electrode layer screen 111 to allow the fluid conductive material to pass through the first electrode layer screen pattern 1110 to form a conductive material film layer pattern (first conductive material film layer pattern), and then the first electrode layer 710 is formed after curing.

[0164] See also Fig.11b ,and Figure 6b Similarly, if the first electrode layer 710 and the second electrode layer 720 have the same shape and size, the first electrode layer 710 and the second electrode layer 720 can be printed using a reusable electrode layer screen 113 having a reusable electrode layer screen pattern 1130. In addition, after performing one S1012a' and several complete cycles of S1012b' to S1012e', or after performing one S1012a', several complete cycles of S1012b' to S1012e', and one half cycle of S1012b' to S1012c', S1120 can be performed to form a protective layer 730 that fully covers the stack.

[0165] In such Fig.11a or Fig.11b In the process flow shown, the fluid insulating material can be insulating ink, and the fluid conductive material can be conductive ink. In addition, by adjusting the diluent content of the ink, the hole density (mesh count) of the screen, the running speed of the printing scraper, the distance between the insulating layer screen or the electrode layer screen and the surface to be painted, etc., the thickness of the ink layer printed on the printed circuit board can be controlled so that the base insulating layer 800, the dielectric insulating layer 700, the first electrode layer 710 and the second electrode layer 720 reach the desired thickness. In addition, after painting, the curing of the insulating material film layer pattern and the conductive material film layer pattern formed can be achieved through a baking process or an ultraviolet light irradiation process.

[0166] The above is an explanation of growing a single on-board capacitor on a printed circuit board. When the manufacturing method in the embodiment is actually used to grow capacitors on a printed circuit board, multiple on-board capacitors can also be grown simultaneously on a printed circuit board through a printing process.

[0167] If the stacking number of layers of multiple on-board capacitors grown simultaneously on the bare board of the same printed circuit board is to be equal, the silk screen pattern for each on-board capacitor can be made at different positions of the same insulating layer screen and the same electrode layer screen, and then the above-mentioned process can be used to simultaneously print and grow them.

[0168] If the stacking numbers of multiple capacitors grown simultaneously on the bare board of the same printed circuit board are not all the same, multiple sets of insulating layer screens and electrode layer screens can be prepared according to the number of stacking layers, where:

[0169] For the first set of insulating layer screens and electrode layer screens, different positions of the same insulating layer screen and the same electrode layer screen may have screen patterns for each capacitor on the board;

[0170] For the second set of insulating layer screens and electrode layer screens, different positions of the same insulating layer screen and the same electrode layer screen may have screen patterns of the remaining on-board capacitors except the on-board capacitor with the least number of stacked layers;

[0171] For the third set of insulating layer screens and electrode layer screens, different positions of the same insulating layer screen and the same electrode layer screen may have screen patterns of the remaining on-board capacitors except for the two on-board capacitors with the least and second least stacked layers;

[0172] By analogy, in the direction of increasing number of stacked layers, each set of insulating layer screens and electrode layer screens reduces the screen patterns of on-board capacitors with the previous level of stacked layers compared to the previous set of insulating layer screens and electrode layer screens, until the last set of insulating layer screens and electrode layer screens, the same insulating layer screen and the same electrode layer screen can only have the screen patterns of on-board capacitors with the largest number of stacked layers.

[0173] Fig.12 For Figure 1 The manufacturing method shown is a schematic diagram of the process of growing multiple on-board capacitors on the same printed circuit board. Fig.12 , as Figure 1 When the manufacturing method shown is used to grow multiple on-board capacitors, for every two on-board capacitors with adjacent stacking layers, the manufacturing method may include the following steps (assuming that the capacitance value generated in the first packaging area is required to be a first capacitance value and has a first number of stacking layers, and the capacitance value generated in the second packaging area is a second capacitance value and has a second number of stacking layers, and the second number of stacking layers is greater than the first number of stacking layers):

[0174] S1200: selectively printing a base insulating layer in the first capacitor packaging area and the second capacitor packaging area;

[0175] S1210: Synchronously and alternately print electrode layers of opposite polarities that are adjacent and staggered and stacked across dielectric insulating layers and dielectric insulating layers separated between adjacent electrode layers of opposite polarities in the first capacitor packaging area and the second capacitor packaging area, until the number of stacking layers in the first capacitor packaging area and the second capacitor packaging area both reach the first number of stacking layers, and a first stacked body with a preset first capacitance value is formed in the first capacitor packaging area.

[0176] S1220: Selectively and alternately print dielectric insulating layers separated between adjacent electrode layers of opposite polarities and adjacent and staggered electrode layers of opposite polarities stacked across the dielectric insulating layers in the second capacitor packaging area until the number of stacking layers in the second capacitor packaging area increases from the first number of stacking layers to the second number of stacking layers, and a second stack having a preset second capacitance value is formed in the second capacitor packaging area.

[0177] If the overlapping area of ​​a pair of electrode layers of opposite polarities stacked alternately with dielectric insulating layers in the first stack is the same as the overlapping area of ​​a pair of electrode layers of opposite polarities stacked alternately with dielectric insulating layers in the second stack, then, after S1210, the capacitance values ​​of the first stack having the first number of stacking layers and the second stack can both be the first capacitance value; after S1220, the capacitance value of the second stack can increase from the first capacitance value to the second capacitance value after passing through S1220, that is, the second capacitance value can be greater than the first capacitance value.

[0178] If the overlapping area of ​​a pair of electrode layers of opposite polarities stacked alternately with dielectric insulating layers in the first stack is different from the overlapping area of ​​a pair of electrode layers of opposite polarities stacked alternately with dielectric insulating layers in the second stack, then, after S1210, the capacitance value of the first stack with the first number of stacking layers may be the first capacitance value, and the capacitance value of the second stack may be different from the first capacitance value and has not yet reached the second capacitance value; after S1220, the capacitance value of the second stack may increase to the second capacitance value after passing through S1220, and the second capacitance value may be less than, equal to, or greater than the first capacitance value.

[0179] S1200 in the above process is an optional step.

[0180] Fig.13a and Fig.13b To support Fig.12 Schematic diagram of the process of growing multiple on-board capacitors. Fig.13a and Fig.13b In the present invention, it is assumed that the printed circuit board needs to grow on-board capacitors in a first capacitor packaging area having a pair of pads 1311 and 1312, and in a second capacitor packaging area having another pair of pads 1321 and 1322, wherein the preset capacitance value of the on-board capacitors in the first capacitor packaging area is C1 (the stack of on-board capacitors in the first capacitor packaging area has a first number of stacking layers), and the preset capacitance value of the on-board capacitors in the second capacitor packaging area is C2 (the stack of on-board capacitors in the second capacitor packaging area has a second number of stacking layers greater than the first number of stacking layers).

[0181] A set of insulating layer screens 1910 and electrode layer screens 1911 and 1912 are provided, which are denoted as the α screen group, wherein the insulating layer screen 1910 has an insulating layer screen pattern 1910a for forming a base insulating layer 1500 and a dielectric insulating layer 1400 in a first capacitor packaging area, and an insulating layer screen pattern 1910b for forming a base insulating layer 1800 and a dielectric insulating layer 1700 in a second capacitor packaging area, the electrode layer screen 1911 has an electrode layer screen pattern 1911a for forming a first electrode layer 1410 in the first capacitor packaging area, and an electrode layer screen pattern 1911b for forming a first electrode layer 1710 in the second capacitor packaging area, and the electrode layer screen 1912 has an electrode layer screen pattern 1912a for forming a second electrode layer 1420 in the second capacitor packaging area, and an electrode layer screen pattern 1912b for forming a second electrode layer 1720 in the second capacitor packaging area.

[0182] In addition, another set of insulating layer screen 1920 and electrode layer screens 1921 and 1922 are provided, which are denoted as β screen group, wherein the insulating layer screen 1920 only has an insulating layer screen pattern 1920b for forming a dielectric insulating layer 1700 in the second capacitor packaging area, the electrode layer screen 1921 only has an electrode layer screen pattern 1921b for forming a first electrode layer 1710 in the second capacitor packaging area, and the electrode layer screen 1912 only has an electrode layer screen pattern 1922b for forming a second electrode layer 1720 in the second capacitor packaging area.

[0183] Thus, according to Fig.12 The process shown:

[0184] First, the insulating layer screen 1910 in the α screen group is used to synchronously print the base insulating layers 1500 and 1800 in the first capacitor packaging area and the second capacitor packaging area respectively;

[0185] Then, using the insulating layer screen 1910 and the electrode layer screens 1911 and 1912 in the α screen group, the dielectric insulating layer 1400 and the first electrode layer 1410 and the second electrode layer 1420 that are staggered and stacked across the dielectric insulating layer 1400 are alternately printed in the first capacitor packaging area, and the dielectric insulating layer 1700 and the first electrode layer 1710 and the second electrode layer 1720 that are staggered and stacked across the dielectric insulating layer 1700 are alternately printed in the second capacitor packaging area, until the number of stacked layers in the first capacitor packaging area reaches the first number of stacked layers, and the number of stacked layers in the second capacitor packaging area also reaches the first number of stacked layers, at which point the sum of the capacitance values ​​between every two first electrode layers 1410 and the second electrode layers 1420 of opposite polarities that are adjacent to each other across the dielectric insulating layer 1400 in the first capacitor packaging area reaches the preset first capacitance value C1, but the sum of the capacitance values ​​between every two first electrode layers 1710 and the second electrode layers 1720 of opposite polarities that are adjacent to each other across the dielectric insulating layer 1700 in the second capacitor packaging area has not yet reached the preset second capacitance value C2;

[0186] Thereafter, the insulating layer screen 1920 and the electrode layer screens 1921 and 1922 in the β screen group are used to alternately print the dielectric insulating layer 1700 and every two adjacent first electrode layers 1710 and second electrode layers 1720 separated by the dielectric insulating layer 1700 in the second capacitor packaging area until the number of stacking layers of the dielectric insulating layer 1700 and the first electrode layers 1710 and second electrode layers 1720 stacked in the second capacitor packaging area increases from the first number of stacking layers to the second number of stacking layers. At this time, the sum of the capacitance values ​​between every two adjacent first electrode layers 1710 and second electrode layers 1720 of opposite polarities separated by the dielectric insulating layer 1700 in the second capacitor packaging area increases to a preset second capacitance value C2.

[0187] in addition, Fig.13a The first capacitor packaging region including the pads 1311 and 1312 does not necessarily need to form the base insulating layer 1500, but the base insulating layer 1500 is formed in the first capacitor packaging region in order to avoid additionally increasing the number of insulating layer screens and to improve insulation reliability.

[0188] See also Fig.13b If the base insulating layer 1500 is not formed in the first capacitor packaging area, the base insulating layer 1800 can be selectively printed in the second capacitor packaging area using the insulating layer screen 1920 in the β screen group, and then Fig.12 In S1210 and S1220 in the process shown, the α plate group and the β screen group are used to complete the subsequent printing.

[0189] The above Fig.13a and Fig.13bThe first capacitor packaging area and the second capacitor packaging area shown can be multiple at different positions of the bare board of the same printed circuit board, that is, as long as the stack of on-board capacitors of the printed circuit board has only two designs of stacking layers, then no matter how many capacitor packaging areas there are, only two screen groups can be provided. If the stack of on-board capacitors of the printed circuit board has more than two designs of stacking layers, then the number of screen groups can be increased in the manner described above.

[0190] In another embodiment, a printed circuit board is provided, comprising:

[0191] A bare board having (one or more) capacitor packaging areas;

[0192] By alternately printing staggered stacked electrode layers with opposite polarities and dielectric insulating layers separated between adjacent electrode layers with opposite polarities, (one or more) stacks (such as Figure 3 as well as Figures 4a to 4e As shown or Figure 7 as well as Figures 9a to 9e As shown), wherein the sum of the capacitance values ​​between each two electrode layers of opposite polarities adjacent to each other through the dielectric insulating layer in the stack reaches a preset capacitance value, and when there is more than one stack, for each stack, the number of stacked layers may not be completely the same, or the preset capacitance value reached by the sum of the capacitance values ​​between each two electrode layers of opposite polarities adjacent to each other through the dielectric insulating layer may not be completely the same;

[0193] A protective layer that fully covers the stack (such as the protective paint or protective film mentioned above).

[0194] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing an on-board capacitor, characterized in that: include: A bare board of a printed circuit board is provided, wherein the bare board has a capacitor packaging area, and a first pad and a second pad are arranged at intervals in a first direction of the capacitor packaging area; The first electrode layer and the second electrode layer, which are stacked staggered with the dielectric insulating layer separated therefrom, and the dielectric insulating layer separated therefrom, are alternately printed in the capacitor packaging area to form a stacked body in the capacitor packaging area, wherein the first electrode layer and the second electrode layer have opposite polarities, the first electrode layer is electrically connected to the first pad, the first electrode layer is electrically isolated from the second electrode layer and the second pad through the dielectric insulating layer, the second electrode layer is electrically connected to the second pad, the second electrode layer is electrically isolated from the first electrode layer and the first pad through the dielectric insulating layer, and the sum of the capacitance values ​​between every two adjacent first electrode layers and the second electrode layers of opposite polarities separated therefrom in the stacked body reaches a preset capacitance value; forming a protective layer that fully covers the stack; in: When the dielectric insulating layer is about to be printed, an insulating layer screen having an insulating layer screen pattern is positioned, and a fluid insulating material is applied to the positioned insulating layer screen so that the fluid insulating material passes through the insulating layer screen pattern to form an insulating material film layer pattern, and the dielectric insulating layer is formed after being cured; When the first electrode layer or the second electrode layer is about to be printed, an electrode layer screen having an electrode layer screen pattern is positioned, and a fluid conductive material is applied to the positioned electrode layer screen so that the fluid conductive material passes through the electrode layer screen pattern to form a conductive material film layer pattern, and the first electrode layer or the second electrode layer is formed after being cured; The curing includes a baking process or an ultraviolet irradiation process.

2. The manufacturing method according to claim 1, characterized in that: The first pad and the second pad are at least partially located outside the boundaries of the dielectric insulating layer on opposite sides in the first direction. The first electrode layer has a first offset that extends beyond the boundary of the dielectric insulating layer in the first direction and partially overlaps with the first pad; The second electrode layer has a second offset that extends beyond the boundary of the dielectric insulating layer in the first direction and partially overlaps with the second pad; The capacitance value between each two adjacent first electrode layers and second electrode layers separated by the dielectric insulating layer is associated with the area of ​​the overlapping portion of the first electrode layer and the second electrode layer separated by the dielectric insulating layer, the thickness of the dielectric insulating layer, and the dielectric constant of the dielectric insulating layer.

3. The manufacturing method according to claim 1, characterized in that: When the first electrode layer or the second electrode layer is to be printed, positioning an electrode layer screen having an electrode layer screen pattern comprises: When the first electrode layer is about to be printed, positioning a reusable electrode layer screen having a reusable electrode layer screen pattern; When the second electrode layer is to be printed, the reusable electrode layer screen is positioned at a position different from that when the first electrode layer is printed.

4. The manufacturing method according to claim 2, characterized in that: The manufacturing method further comprises, before alternately printing the first electrode layer and the second electrode layer stacked in a staggered manner through the dielectric insulating layer in the capacitor packaging area: Printing a base insulating layer in the capacitor packaging area; The first pad and the second pad are at least partially located outside the boundaries of the base insulating layer on opposite sides in the first direction, and the first electrode layer and the second electrode layer partially overlap with the first pad and the second pad via the base insulating layer.

5. The manufacturing method according to claim 4, characterized in that: Printing a base insulating layer in the capacitor packaging area includes: An insulating layer screen having an insulating layer screen pattern is positioned, and a fluid insulating material is brushed on the positioned insulating layer screen so that the fluid insulating material passes through the insulating layer screen pattern to form an insulating material film layer pattern, and the base insulating layer is formed after being cured.

6. The manufacturing method according to claim 5, characterized in that: When the dielectric insulating layer is about to be printed, the dielectric insulating layer screen is positioned to the same positioning position as that of the base insulating layer, so that the dielectric insulating layer is aligned and overlapped with the base insulating layer.

7. The manufacturing method according to claim 1, characterized in that: Forming a protective layer that fully covers the stacked body, comprising: A protective paint having electrical insulation and anti-corrosion properties is coated at least on the capacitor packaging area where the stacked body is formed, so as to form the protective layer for blocking gas and liquid.

8. The manufacturing method according to any one of claims 1 to 7, characterized in that: The capacitor packaging area includes a first capacitor packaging area and a second capacitor packaging area, and the stacked body includes a first stacked body and a second stacked body; The first electrode layer and the second electrode layer are alternately printed in the capacitor packaging area and are stacked in a staggered manner through a dielectric insulating layer, comprising: Synchronously performing the alternating printing in the first capacitor packaging area and the second capacitor packaging area until the first stacked body having a preset first capacitance value is completed in the first capacitor packaging area; The alternating printing is selectively continued in the second capacitor packaging area until the second stacked body with a capacitance value increased to a preset second capacitance value is formed in the second capacitor packaging area.

9. The manufacturing method according to any one of claims 1 to 7, characterized in that: The preset capacitance value is p×10 q Farad, where p is an integer greater than 0 or a non-integer, and q is an integer.

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