First-in-first-out (FIFO) circuit

Abstract

This invention discloses a first-in, first-out (FIFO) data circuit, comprising a buffer unit, multiple data multiplexers, and an output multiplexer. The buffer unit includes multiple decoders and N+ buffers. The decoders are used to output multiple decoded signals in response to multiple corresponding input control signals and at least one input start signal. The N+ buffers are configured to receive input data in response to corresponding decoded signals from corresponding decoders. Each of the multiple data multiplexers is coupled to M of the multiple buffers, where N and M are positive integers, N equal to or greater than 4, M equal to or greater than 2, and N greater than M. The output multiplexer, coupled to the multiple data multiplexers, is used to sequentially provide corresponding outputs from the multiple data multiplexers.

Description

Technical Field

[0001] This invention relates to a first-in first-out (FIFO) circuit, and more particularly to a data FIFO circuit for use in memory devices operating in high-speed data rate applications. Background Technology

[0002] Multiple first-in-first-out (FIFO) circuits can be used to temporarily store information for transfer between two different circuits operating at different clock rates. These FIFO circuits and their variations are widely used in various electronic applications, such as memory devices, storage devices, network devices, and audio / video storage applications. In memory device applications, for example, non-volatile memory modules such as double data rate (DDR) series (e.g., DDR2, DDR3, DDR4, etc.) synchronous dynamic random access memory (SDRAM) are essential for electronic devices such as personal computers and servers, requiring input or output interfaces based on different FIFO circuits for data conversion between the memory chip and the host. These input or output interfaces are used for memory write or read operations and are typically implemented based on FIFO circuits for data conversion, operating in a high-speed and reliable manner to meet the requirements of the memory interface specifications.

[0003] As a result, the structure and operation of the FIFO circuit are of concern for the requirements of the memory interface specification. Taking DDR3 memory devices as an example, the latency between the read command and the time when data is available is 16 (i.e., the Column Access Strobe (CAS) latency or CL equals 16 (in clock cycles)). A conventional FIFO circuit, such as... Figure 1 As shown, this is a construction block that can be used as an output FIFO circuit in the DDR3 memory device. Figure 1 In the FIFO circuit, eight buffers are represented by R, and an 8-to-1 multiplexer (MUX) is represented by M1. When multiple read commands are processed by the memory module, the multiple buffers R can be controlled using input control signals represented by ZI[0] to ZI[7], such that each buffer R stores 4-bit data from the FIFO input (e.g., 4-bit data at a time) sequentially. To meet the requirement of CL = 16, the 8-to-1 multiplexer M1 can be controlled by output control signals represented by ZO[0] to ZO[7], so that the respective data provided by the multiple buffers R are output sequentially as the CL delay time of each read command expires.

[0004] With advancements in memory technology, next-generation memory systems will operate at higher data rates. For example, compared to the 400 and 1067MHz frequencies of DDR3 SDRAM, DDR4 SDRAM operates between 800 and 1600MHz (DDR4-1600 to DDR4-3200). Due to the higher CL value of DDR4 SDRAM, more FIFOs are required in the memory chips. This can be achieved by using... Figure 1 The FIFO circuit of the DDR4 SDRAM is implemented with a similar structure and operation to the FIFO circuit described in the previous example (not shown). In this case, the FIFO circuit of the DDR4 SDRAM requires a 16-to-1 multiplexer instead of an 8-to-1 multiplexer M1 to sequentially output 4 bits of data from the multiple caches, resulting in a faster response time than the previous example. Figure 1 The FIFO circuit requires a greater number (e.g., 16) of multiple output control signals. Furthermore, the number of multiple output control signals used to control the multiple buffers depends on the data size (e.g., 4-bit or 8-bit) of the multiple buffers used to receive the FIFO input. Thus, the number of traces for the multiple input control signals and the multiple output control signals inevitably increases the circuit complexity of the FIFO circuit, which hinders its compactness.

[0005] Furthermore, the FIFO circuitry used in DDR4 SDRAM may be subject to signal overload from a 16-to-1 multiplexer based on transmission gates. In the worst case, signal overload can cause the multiplexer to output incorrect data or output conversion signal levels at a lower rotation rate, thereby reducing the reliability of the memory module.

[0006] Therefore, implementing the FIFO circuit in memory devices, especially in high-speed data rate applications, is a challenge. Summary of the Invention

[0007] One object of the present invention is to provide a first-in first-out (FIFO) circuit that facilitates the application of memory devices with high data rates.

[0008] To at least achieve the above objectives, the present invention provides a first-in-first-out (FIFO) circuit, including a buffer unit, multiple data multiplexers, and an output multiplexer. The buffer unit includes multiple decoders and N+ buffers. The multiple decoders are configured to output multiple decoded signals in response to multiple corresponding output control signals and at least one input start signal. The N+ buffers are configured to receive input data in response to corresponding decoded signals from the multiple corresponding decoders. Each of the multiple data multiplexers is coupled to M of the multiple buffers, where N and M are positive integers, N equal to or greater than 4, M equal to or greater than 2, and N greater than M. The output multiplexer, coupled to the multiple data multiplexers, is used to sequentially provide corresponding outputs from the multiple data multiplexers.

[0009] Optionally, the N plurality of buffers are configured to receive the input data sequentially according to the corresponding decoding signals.

[0010] Optionally, each of the plurality of data multiplexers provides corresponding data to the output multiplexer in response to at least an output start signal, and the output multiplexer provides corresponding outputs from the plurality of data multiplexers in response to a plurality of corresponding output control signals.

[0011] Optionally, the first of the plurality of data multiplexers is configured to receive a first portion of the corresponding output from the first buffer of the corresponding M buffers.

[0012] Optionally, the second of the plurality of data multiplexers is configured to receive a second portion of the corresponding output from the first buffer of the corresponding M buffers.

[0013] Optionally, in response to at least one output start signal, the output start signal representing the start of providing the corresponding output of the first buffer, the first portion and the second portion of the first and second data multiplexers providing the corresponding outputs respectively serve as two inputs of the output multiplexer.

[0014] Optionally, in response to a plurality of corresponding input control signals representing the selection of the first buffer, the output multiplexer sequentially provides the two inputs.

[0015] Optionally, the output multiplexer is a first output multiplexer, and the data FIFO circuit further includes a second output multiplexer coupled to the first output multiplexer, the second output multiplexer being used to selectively output a portion of the data output by the first output multiplexer.

[0016] Optionally, M is equal to or greater than four, and each of the plurality of data multiplexers is coupled to M of the plurality of buffers.

[0017] Optionally, the plurality of data multiplexers includes a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer. The first multiplexer is configured to receive a first portion of a corresponding output from a first buffer of the corresponding M buffers. The second multiplexer is configured to receive a second portion of a corresponding output from the first buffer of the corresponding M buffers. The third multiplexer is configured to receive a first portion of a corresponding output from a second buffer of the corresponding M buffers. The fourth multiplexer is configured to receive a second portion of a corresponding output from the second buffer of the corresponding M buffers. The output multiplexer is configured to receive multiple outputs from the plurality of data multiplexers and sequentially output data from one of the plurality of data multiplexers.

[0018] Optionally, in response to at least one output start signal, the output start signal representing the start of providing the plurality of corresponding outputs of the first and fourth buffers, the first to fourth multiplexers respectively provide a first portion and a second portion of the corresponding output from the first buffer and a first portion and a second portion of the corresponding output from the second buffer as inputs to the output multiplexer.

[0019] Optionally, in response to a plurality of corresponding output control signals representing selection of the first and second buffers, the output multiplexer sequentially provides the plurality of inputs.

[0020] Optionally, the first multiplexer is further configured to receive a first portion of the corresponding output from the corresponding M third buffers; the second buffer is further configured to receive a second portion of the corresponding output from the corresponding M third buffers; the third multiplexer is further configured to receive the first portion of the corresponding output from the corresponding M fourth buffers. The fourth multiplexer is further configured to receive the second portion of the corresponding output from the corresponding M fourth buffers, wherein the output multiplexer is configured to receive output from the data multiplexer and sequentially output data from one of the plurality of data multiplexers.

[0021] Optionally, in response to at least one output start signal, the output start signal representing the start of providing the output of the corresponding first buffer and the second buffer, the first to the fourth multiplexers, in response to at least one output start signal, the output start signal representing the start of providing the output of the corresponding first buffer and the second buffer, respectively, take a first part and a second part of the corresponding output from the third buffer and a first part and a second part of the corresponding output from the fourth buffer as inputs to the output multiplexer.

[0022] Optionally, in response to a plurality of corresponding output control signals representing the selection of the plurality of third and fourth buffers, the output multiplexer sequentially provides the plurality of inputs.

[0023] To further understand the features and technical content of this invention, please refer to the following detailed description and accompanying drawings. However, this description and accompanying drawings are only for illustrating the invention and are not intended to limit the scope of the invention in any way. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This illustrates a conventional FIFO circuit in a memory chip within a memory system, based on existing technology.

[0026] Figure 2 This is a block diagram illustrating a data FIFO circuit according to an embodiment of the present invention;

[0027] Figure 3 This illustrates an embodiment of the present invention. Figure 2 A schematic timing diagram illustrating the operation of a data FIFO circuit;

[0028] Figure 4 It is shown Figure 2 A schematic diagram of an embodiment of a data multiplexer;

[0029] Figure 5 It is shown Figure 2 A schematic diagram of an embodiment of an output multiplexer;

[0030] Figure 6 This illustrates a memory device based on, for example Figure 2A schematic diagram of an embodiment of the data FIFO unit of the data FIFO circuit shown;

[0031] Figure 7 This is a block diagram illustrating a data FIFO circuit according to another embodiment of the present invention;

[0032] Figure 8 This illustrates an embodiment of the present invention. Figure 7 A schematic timing diagram illustrating the operation of a data FIFO circuit;

[0033] Figure 9 This is a schematic timing diagram illustrating the operation of a FIFO according to an embodiment of the present disclosure.

[0034] Explanation of reference numerals in the attached figures:

[0035] 1. Data FIFO circuit

[0036] 2 Data FIFO Unit

[0037] 3. Data FIFO Circuit

[0038] 10 Buffer Units

[0039] 21 Data Multiplexer

[0040] 22 Data Multiplexer

[0041] 23 Data Multiplexer

[0042] 24 Data Multiplexer

[0043] 30 Output Multiplexer

[0044] 10A Buffer Unit

[0045] 21A Data Multiplexer

[0046] 22A Data Multiplexer

[0047] 23A Data Multiplexer

[0048] 24A Data Multiplexer

[0049] 30A Output Multiplexer

[0050] 35A Output Multiplexer

[0051] CLK clock signal

[0052] CMD command

[0053] D0-D7 decoder

[0054] D[0:15] 16-bit data

[0055] DQ data signal

[0056] DQS data strobe signal

[0057] F1-FP Data FIFO Circuit

[0058] M1 8-to-1 multiplexer

[0059] QI[0]-QI[3] Input control signals

[0060] QIE input start signal

[0061] QO[0]-QO[3] Output control signals

[0062] QOE output start signal

[0063] R Cache

[0064] R0A-R7A Buffer

[0065] R0-R7 Caches

[0066] RD read command

[0067] T0-T71 clock cycle

[0068] ZI[0]-ZI[7] Input control signals

[0069] ZI[0:3] Input control signal

[0070] ZIE input start signal

[0071] ZIE' input start signal

[0072] ZO[0:1], ZO[0:3], ZO[0:7] Output control signals

[0073] ZOE[0:3] outputs the start signal.

[0074] ZOE1[0:3] Output control signal

[0075] ZOE2[0:3] outputs start signal Detailed Implementation

[0076] To facilitate understanding of the objectives, features, and effects of the present invention, embodiments and drawings are provided for the detailed description of the invention.

[0077] A first-in-first-out (FIFO) circuit will be provided, which facilitates the application of memory devices with high data rates. As shown below, the data FIFO circuit can help reduce circuit complexity and increase the reliability of the memory device.

[0078] refer to Figure 2 As shown, a data FIFO circuit according to an embodiment of the present invention is illustrated in block diagram form. (As in...) Figure 2 As shown, the first-in first-out (FIFO) circuit 1 includes a buffer unit 10, multiple data multiplexers (e.g., represented by 21-24), and an output multiplexer 30.

[0079] The buffer unit 10 includes a plurality of decoders (e.g., represented by D0-D7) and N plurality of buffers (e.g., R0-R7). The plurality of decoders (e.g., D0-D7) are configured to output a plurality of decoded signals in response to a plurality of corresponding output control signals (e.g., ZI[0] to ZI[3]) and at least one input start signal (e.g., ZIE or ZIE'). The N plurality of (e.g., 8) buffers (e.g., R0-R7) are configured to receive input data in response to the plurality of corresponding decoded signals from the plurality of corresponding decoders (e.g., D0-D7).

[0080] Each of the plurality of data multiplexers (e.g., represented by 21-24) is coupled to M (e.g., 4) buffers, where N and M are positive integers. Figure 2 In the illustrated embodiment, N and M take values ​​of 8 and 4, respectively. Of course, the implementation of this invention is not limited to these examples. In some embodiments, it can be based on... Figure 2 To implement the data FIFO circuit, N is equal to or greater than 4, M is equal to or greater than 2, and N is greater than M. For example, using the structure of the data FIFO circuit 1, a data FIFO circuit can be implemented with four buffers in the buffer unit and two data multiplexers.

[0081] The output multiplexer 30 is coupled to the plurality of data multiplexers (e.g., 21-24), which are used to sequentially provide corresponding outputs from the plurality of data multiplexers.

[0082] Figure 2The data FIFO circuit 1 facilitates the application of memory devices with high data rates. For example, in a practical application of the data FIFO circuit 1 in DDR4 SDRAM, the data FIFO circuit 1 can reduce circuit complexity by using a decoder in the buffer unit 10, thereby reducing the number of input control signals required to control the buffer unit 10. Furthermore, the data FIFO circuit 1 utilizes a structure of at least two stages of data multiplexers (e.g., the multiple data multiplexers as a first stage and the output multiplexer as a second stage) for data output, which reduces the load on the output multiplexer and improves the reliability of memory devices using the data FIFO circuit 1.

[0083] The following provides various embodiments of the buffer unit, the plurality of data multiplexers, and the output multiplexer.

[0084] In one embodiment, the plurality of buffers (e.g., R0-R7) can be configured to sequentially receive the input data (e.g., each 8-bit data) according to corresponding decoding signals output by the plurality of decoders (e.g., D0-D7). In some examples, the plurality of decoders (e.g., D0-D7) can be implemented by corresponding logic circuits or components. Reference Figure 2 As shown, each of the plurality of decoders D0-D3 can be implemented using AND logic gates with two inputs or equivalent logic circuits or components (e.g., ZI[0] and ZIE' for decoder D0), and the corresponding decoded signal is the result of the AND operation of the plurality of two inputs. Each of the plurality of decoders D4-D7 can be implemented using AND gates with two inputs (e.g., ZI[0] and ZIE' for decoder D4) or equivalent logic circuits or components, and the corresponding decoded signal is the result of the AND operation of the two inputs. In this way, with Figure 1 Compared to conventional data FIFO circuits, the use of multiple decoders and multiple buffers in the data FIFO circuit 1 facilitates the reduction of the number of input control signals required for data input. Furthermore, the multiple buffers can be implemented using any suitable circuit, such as flip-flops. Of course, implementations of the invention are not limited to these examples.

[0085] In one embodiment, each of the plurality of data multiplexers (e.g., 21-24) provides corresponding data to the output multiplexer 30 in response to at least an output start signal (e.g., ZOE[0:3]), and the output multiplexer 30 provides corresponding outputs from the plurality of data multiplexers (e.g., 21-24) in response to a plurality of corresponding output control signals (e.g., ZO[0:3]).

[0086] In one embodiment, Figure 2 The data FIFO circuit 1 can be used as follows: Figure 6 The diagram shows a block diagram illustrating the construction of the output FIFO unit of a DDR4 memory device. (Reference) Figure 3 As shown, an embodiment of the present invention is illustrated. Figure 2 A schematic timing diagram illustrating the operation of the data FIFO circuit 1 is provided below. The following example illustrates FIFO operation with a Column Access Strobe (CAS) delay, or a CL equal to 30 (in clock cycles). Figure 3 As shown, when the memory device processes a read command (e.g., the read command is represented by RD in the waveform of the command represented by CMD) in response to a clock signal (e.g., the clock signal is represented by CLK and multiple clock cycles are represented by T0, T1-T39, etc.), the multiple buffers R0-R7 can be controlled by using the multiple input control signals represented by ZI[0] to ZI[3] and the input start signal represented by ZIE (or ZIE'), such that each buffer stores the respective 8-bit data from the FIFO input in a sequential manner (e.g., in...). Figure 3 Each 8-bit data is represented by "ABCDEFGH". For example, when the input control signal ZI[0] and the input start signal ZIE are declared simultaneously (e.g., explicitly started), the corresponding 8-bit data can be received through the buffer R0, as indicated by the pulse of the input control signal ZI[0] represented by "0" and the high level of the input start signal ZIE. Similarly, when the input start signal ZIE and one of the plurality of input control signals ZI[1]-ZI[3] are declared, three 8-bit data can be received respectively through the plurality of buffers R1-R3.

[0087] When the input control signal ZI[0] is declared and the input start signal ZIE is dedeclared (or ZIE' is declared), the corresponding 8-bit data can be received by the buffer R4, as indicated by the pulse of the input control signal ZI[0] represented by "4" and the low level of the input start signal ZIE. Similarly, when the input start signal ZIE is dedeclared and one of the plurality of input control signals ZI[1]-ZI[3] is declared, the plurality of buffers R4-R7 can respectively receive three 8-bit data.

[0088] As in Figure 3As shown, in order to meet the requirements of CL=30 and AL=0, the multiple data multiplexers (e.g., 21-24) can be controlled sequentially by the output start signal and the multiple output control signals to ensure that data can be output after the delay time of CL of the corresponding read command. For example, when the output start signal ZOE[0] is declared and one of the multiple output control signals ZO[0]-ZO[3] is declared sequentially (as shown in the diagram), the multiple data multiplexers can be controlled sequentially by the output start signal ZOE[0]-ZO[3] (e.g., in the diagram). Figure 3 When the pulses of the plurality of output control signals ZO[0]-ZO[3] are represented by "0" and "1", the output multiplexer 30 sequentially outputs the individual data from the plurality of buffers R0-R1. When the output start signal ZOE[1] is declared and one of the plurality of output control signals ZO[0]-ZO[3] is declared sequentially (as in Figure 3 When the pulses of the multiple output control signals ZO[0]-ZO[3] are represented by "2" and "3", the corresponding data from the multiple buffers R2-R3 are sequentially output through the output multiplexer 30. Then, the operation for outputting corresponding data from the multiple buffers R4-R5, R6-R7 can be performed similarly, and will not be described in detail for the sake of brevity. When the data from the multiple buffers is sequentially output through the output multiplexer 30, the memory device (e.g., DDR4 SDRAM) using the data FIFO circuit 1 can output data according to the requirements of the memory data interface (e.g., DDR4), for example, as in Figure 3 As shown, the timing is based on the data strobe signal represented by DQS and the data signal represented by DQ (e.g., for DQ[0]). Of course, the implementation of the present invention is not limited to the above examples.

[0089] As described above, using a data multiplexing structure with at least two levels for data output can reduce the load on the output multiplexer 30 and also lead to a lower gate delay. In this regard, it should be noted that, for example, during the declaration of the output start signal ZOE[0], the plurality of data multiplexers 21-24 can output corresponding data from the plurality of buffers R0-R1, such that once the plurality of output control signals ZO[0]-ZO[3] are declared sequentially, the output multiplexer 30 can output the corresponding data with a lower gate delay. In contrast, if the plurality of data multiplexers 21-24 and the output multiplexer 30 are combined with… Figure 1The data FIFO circuit 1 replaces the 16-to-1 multiplexer in a similar structure to the data FIFO circuit described above. However, due to the multiple serial logic gates in the 16-to-1 multiplexer, the gate-based 16-to-1 multiplexer can be affected by gate delays. Therefore, the data FIFO circuit 1 can improve the reliability of memory devices using the FIFO circuit 1.

[0090] In one embodiment, the first of the plurality of data multiplexers (e.g., data multiplexer 21 or 23) is configured to receive a first portion of the corresponding output (e.g., the first 4 bits of 8-bit data) from the first buffer (e.g., buffer R0 or R1) of the plurality of corresponding M (e.g., 2 or more) buffers. (See reference) Figure 2 As shown, for example, the data multiplexer 21 is coupled to buffers R0, R2, R4, and R6 (e.g., for M=4) among the plurality of buffers R0-R1 to receive their respective first portions. The data multiplexer 23, for example, is coupled to buffers R1, R3, R5, and R7 (e.g., for M=4) among the plurality of buffers R0-R7 to receive their respective first portions.

[0091] In one embodiment, the second of the plurality of data multiplexers (e.g., data multiplexer 22 or 24) is configured to receive a second portion of the corresponding output (e.g., a second 4-bit of the 8-bit data) from the first buffer (e.g., buffer R0 or R1) of the plurality of corresponding M buffers. (See reference) Figure 2 As shown, for example, the data multiplexer 22 is coupled to buffers R0, R2, R4, and R6 (e.g., for M=4) of the plurality of buffers R0-R7 to receive their respective second portions. The data multiplexer 24, for example, is coupled to buffers R1, R3, R5, and R7 (e.g., for M=4) of the plurality of buffers R0-R7 to receive their respective second portions.

[0092] In one embodiment, in response to at least one output start signal (e.g., one of ZOE[0], ZOE[1], ZOE[2], ZOE[3] is declared), the output start signal representing the start of providing the corresponding output of the first buffer (e.g., one of buffers R0-R3; one of buffers R4-R7), the first and second of the data multiplexers (e.g., data multiplexers 21, 22; or 23, 24) respectively provide a first portion and a second portion of the corresponding output as two inputs to the output multiplexer 30. For example, refer to Figure 2 and 3As shown, when the output start signal ZOE[0] is declared, the first and second of the plurality of data multiplexers (e.g., data multiplexers 21, 22; 23, 24) respectively provide the output multiplexer 30 with the first portion (e.g., the first 4-bit data of an 8-bit data) and the second portion (e.g., the second 4-bit data of an 8-bit data) of the corresponding output from the first buffer (e.g., buffer R0 or R1) as two inputs. Where appropriate, the above embodiment can also be used similarly for the operation of other buffers, and will not be repeated for the sake of brevity.

[0093] In one embodiment, in response to a plurality of corresponding output control signals representing a selection of the first buffer, the output multiplexer 30 sequentially provides two inputs. For example, refer to Figure 2 and 3 As shown, when the plurality of output control signals ZO[0] and ZO[1] (by means of...) Figure 3 When the "0" in the input represents the selection of the buffer R0 (or R1, R2, R3), the output multiplexer 30 sequentially provides the two inputs (e.g., in...). Figure 3 In this context, the FIFO output is represented by "ABCD" and "EFGH".

[0094] In the above embodiments, when the corresponding output start signal is announced, the first and second portions can be provided simultaneously by the first and second (e.g., data multiplexers 21, 22 or 23, 24) of the plurality of data multiplexers, so that the output multiplexer 30 can output the first and second portions stepwise and sequentially in a portion, avoiding gate delays caused by serial logic gates in the 16-to-1 multiplexer. Therefore, the structure of at least two stages of data multiplexers for data output makes the data FIFO circuit suitable for high data rate memory device applications. Of course, embodiments of the present invention are not limited to these examples.

[0095] In one embodiment, M is equal to or greater than four, and each of the plurality of data multiplexers is coupled to M of the plurality of buffers.

[0096] In one embodiment, the data multiplexer 21 is configured to receive a first portion of a corresponding output from the buffers R0 (or R2, R4, R6). The data multiplexer 22 is configured to receive a second portion of the corresponding output from the buffers R0 (or R2). The data multiplexer 23 is configured to receive a first portion of a corresponding output from the buffers R1 (or R3). The data multiplexer 24 is configured to receive the second portion of the corresponding output from the buffers R1 (or R3). The output multiplexer 30 is configured to receive output from the plurality of data multiplexers 21-24, and sequentially receive output data from one of the plurality of data multiplexers 21-24.

[0097] In one embodiment, in response to at least one output start signal (e.g., when one of ZOE[0]-ZOE[3] is declared), the output start signal representing the start of providing the plurality of corresponding outputs of the first and second buffers (e.g., buffers R0, R1; R2, R3; R4, R5; R6, R7), the plurality of data multiplexers 21-24 respectively provide the first and second portions of the corresponding outputs from the first buffer (e.g., buffers R0, R2, R4 or R6), and the first and second portions of the corresponding outputs from the second buffer (e.g., buffers R1, R3, R5 or R7) as inputs to the output multiplexer 30.

[0098] In one embodiment, in response to a plurality of corresponding output control signals (e.g., ZO[0] to ZO[3]), which represent the selection of the first and second buffers (e.g., buffers R0, R1; R2, R3; R4, R5; R6, R7), the output multiplexer 30 sequentially provides the plurality of inputs.

[0099] In one embodiment, the data multiplexer 21 is further configured to receive a first portion of the corresponding output from a third buffer (e.g., R4 or R6); the data multiplexer 22 is further configured to receive a second portion of the corresponding output from the third buffer (e.g., R4 or R6); the data multiplexer 23 is further configured to receive a first portion of the corresponding output from a fourth buffer (e.g., R5 or R7); the data multiplexer 23 is further configured to receive a second portion of the corresponding output from the fourth buffer (e.g., R5 or R7), wherein the output multiplexer 30 is configured to receive output from the plurality of data multiplexers 21-24 and sequentially receive output data from one of the plurality of data multiplexers 21-24.

[0100] In one embodiment, in response to at least one output start signal (e.g., when one of ZOE[1]-ZOE[3] is declared), the output start signal representing the start of the plurality of corresponding outputs of the plurality of third and fourth buffers (e.g., buffers R2, R3; R4, R5; R6, R7), the plurality of data multiplexers 21-24 respectively provide the output multiplexer 30 with the first and second portions of the corresponding outputs from the third buffers (e.g., buffers R2, R4, or R6) and the first and second portions of the corresponding outputs from the fourth buffers (e.g., buffers R3, R5, or R7) as inputs.

[0101] In one embodiment, in response to a plurality of corresponding output control signals (e.g., ZO[0] to ZO[3]), which represent the selection of a plurality of third and fourth buffers (e.g., buffers R2, R3; R4, R5; R6, R7), the output multiplexer 30 sequentially provides the plurality of inputs.

[0102] In the above embodiments, when the corresponding output start signal is announced, the first to fourth data multiplexers (e.g., data multiplexers 21, 22, 23, 24) can simultaneously provide the first and second portions of the output from a pair of buffers (e.g., buffers R0, R1; R2, R3; R4, R5; R6, R7), allowing the output multiplexer 30 to output the first and second portions of the output from the pair of buffers incrementally and sequentially, avoiding gate delays caused by serial logic gates in the 16-to-1 multiplexer. Therefore, the structure of at least two stages of data multiplexers for data output makes the data FIFO circuit suitable for high data rate memory device applications.

[0103] In addition, examples of implementations for the plurality of data multiplexers and the output multiplexer are provided. Figure 4 It is shown in the form of a diagram. Figure 2 One embodiment of a data multiplexer. It can be based on... Figure 4 Data multiplexer implementation in Figure 2 The multiple data multiplexers 21-24 mentioned above. Figure 5 Shown in the form of a diagram Figure 2 An embodiment of the output multiplexer. It can be based on... Figure 5 The output multiplexer 30 is used to implement this, and the output multiplexer 30 uses a transmission gate. Of course, the implementation of the present invention is not limited to these examples.

[0104] In some embodiments, based on Figure 2The data FIFO circuit described above can be used as a building block for the output FIFO unit of DDR series (e.g., DDR4, DDR5, etc.) memory devices, as in... Figure 6 As shown. (As in...) Figure 6 As shown, data FIFO unit 2 includes multiple data FIFO circuits, represented by F1, F2 to FP, where P is an integer greater than 2. In practical applications of DDR series memory devices such as DDR4, the data FIFO unit 2 can be implemented to include the multiple data FIFO circuits F1 to FP, for example, where P is equal to 16. In this case, the FIFO input is 8 bits of data each time and the FIFO output is 4 bits of data each time. When the multiple FIFO circuits F1 and FP sequentially output data to the multiple caches, the memory device (e.g., DDR4 SDRAM) can output data according to the requirements of the memory data interface (e.g., DDR4), for example, according to the timing of the data strobe signal represented by DQS and the data signals represented by DQ (e.g., for DQ[0]-DQ[P-1]).

[0105] As in Figure 6 In the illustrated embodiment, the number of control signals used to control the 16 data FIFO circuits is reduced, with 5 control signals (including four input control signals ZI[0:3] and one input start signal ZIE) used for FIFO input control, and 8 control signals (including four output control signals ZO[0:3] and four output start signals ZOE[0:3]) used for FIFO output control. In this way, the number of traces for the multiple control signals and output control signals can be significantly reduced, thereby reducing the complexity of the data FIFO unit 2 and contributing to a more compact and efficient circuit layout for the memory device using the data FIFO unit. The multiple control signals can, for example, be implemented and generated through memory control of the memory device (or module).

[0106] The above embodiments illustrate the application of the data FIFO circuit to DDR4 SDRAM. However, the embodiments of the present invention are not limited thereto. The structure and operation of the data FIFO circuit 1 can be applied to other or next-generation DDR memory interface technologies or the FIFO structure of any electronic device employing a data FIFO circuit.

[0107] refer to Figure 7 As shown, a data FIFO circuit according to another embodiment of the present invention is illustrated in block diagram form. For example, based on Figure 7 The data FIFO circuit 3 can be used with Figure 6A similar approach is used as the building block for the output FIFO unit of DDR5 memory devices. For example, in Figure 7 As shown, the data FIFO circuit 3 includes a buffer unit 10A, multiple data multiplexers (e.g., represented by 21A-24A), and multiple output multiplexers 30A and 35A. The data FIFO circuit 3 in this embodiment and... Figure 2 The main difference between the data FIFO circuit 1 and the data FIFO circuit 3 is that the data FIFO circuit 3 also includes the output multiplexer 35A, coupled to the output multiplexer 30A, for selectively outputting a portion of the data output by the output multiplexer 30A. Additionally, the output multiplexer 35A can be controlled by two output control signals ZO[0:1]. In practical applications of the data FIFO circuit 3 for DDR5 SDRAM, the FIFO input is 16 bits of data at a time and the FIFO output is 4 bits of data at a time, and 10 control signals (including two output control signals ZO[0:1], four output control signals ZOE1[0:3], and four output start signals ZOE2[0:3]) can be used for FIFO output control. In contrast, based on... Figure 1 The conventional approach to the data FIFO circuit structure shown requires a 32-to-1 multiplexer to sequentially output 4 bits of data each time, starting with 8 16-bit data bits, resulting in 32 control signals for FIFO output control. This 32-to-1 multiplexer may be unsuitable for high data rate applications due to signal overload or gate delay issues.

[0108] The structure and operation of the data FIFO circuit 3 are illustrated below. The buffer unit 10A can be implemented based on the buffer unit 10 in a similar manner, except that buffers R0A-R7A of the buffer unit 10A are configured to store 16-bit data, thus ensuring that each FIFO input is 16-bit data. Buffers R0A-R7A can be implemented with... Figure 2 The data FIFO circuit 1 is implemented in a similar way.

[0109] Regarding the plurality of multiplexers, in one embodiment, the plurality of data multiplexers 21A-24A and the output multiplexer 30A can be implemented by an 8-bit 4-to-1 data multiplexer. For example, it can be based on Figure 4 This forms the 8-bit 4-to-1 data multiplexer. The output multiplexer 35A can be implemented using a 4-bit 2-to-1 data multiplexer. For example, it can be based on a similar... Figure 5 The transmission gates are used to form a 4-bit 2-to-1 data multiplexer. Of course, embodiments of the present invention are not limited to these examples.

[0110] refer to Figure 8As shown, an embodiment of the present invention is illustrated. Figure 7 A schematic timing diagram illustrating the operation of the data FIFO circuit, wherein the FIFO input consists of multiple 16-bit data represented by D[0:15]. Figure 8 and Figure 3 Compared to, used for Figure 7 The operation of the FIFO input control of the data FIFO circuit, and for... Figure 2 and Figure 3 The operation of the data FIFO circuit shown is similar, therefore, it will not be described in detail for the sake of brevity.

[0111] Regarding the plurality of data multiplexers 21A-24A and the output multiplexer 30A, as follows Figure 8 As shown, for Figure 7 The operation of the FIFO output control of the data FIFO circuit 3 can be considered as related to... Figure 2 and Figure 3 The data FIFO circuit shown is similar to that described above, therefore, it will not be described in detail for the sake of brevity.

[0112] In addition, such as in Figure 8 As shown, for Figure 7 The operation of the FIFO output control of the data FIFO circuit 3, and for Figure 2 The main difference in the operation of the FIFO output control of the data FIFO circuit 1 shown is that the data output from the output multiplexer 30A of the data FIFO circuit 3 is further input to the output multiplexer 35A, and the output multiplexer 35A responds to the plurality of control signals ZO[0] and ZO[1] to output the first portion of the data in a sequential manner (e.g., in Figure 8 The first 4-bit data of the 8-bit data represented by D[0:3]) and the second part (e.g., in Figure 8 The second 4-bit data in the 8-bit data represented by D[4:7]. For example, refer to Figure 8 As shown, when the plurality of output start signals ZOE2[0:3] are represented by binary 1000, the plurality of output control signals ZOE1[0:3] are represented by binary 1000, and the plurality of output control signals ZO[0]-ZO[1] are declared sequentially (as shown in... Figure 8 The pulses of the plurality of output control signals ZO[0]-ZO[1] mentioned above are represented by "0", and the data (e.g., 16-bit data) from the buffer R0A (e.g., in the first part) Figure 8 The middle part is represented by D[0:3] for FIFO output and the second part (e.g., in Figure 8The D[4:7] values ​​(represented by the FIFO output) are output sequentially via the output multiplexer 35A. For example, refer to Figure 8 As shown, when the plurality of output start signals ZOE2[0:3] are represented by binary 1000, the plurality of output control signals ZOE1[0:3] are represented by binary 0100, and the output control signals ZO[0]-ZO[1] are declared sequentially (as shown in... Figure 8 The pulses of the multiple output control signals ZO[0]-ZO[1] mentioned above are represented by "0", and the data (e.g., 16-bit data) from the buffer R0A in the third and fourth parts (e.g., in Figure 8 The data (represented by D[12:15] for FIFO output) is output sequentially via the output multiplexer 35. Similarly, the operation for outputting the corresponding data to the plurality of buffers R1A-R7A can then be performed in a similar manner, and will not be described in detail for the sake of brevity.

[0113] Therefore, in order to execute the use of Figure 7 The operation of the FIFO output control of the data FIFO circuit, to meet the requirements of CL=58 and AL=0, is achieved by the plurality of data multiplexers (e.g., 21A-24A) being controlled sequentially by the output start signal and the plurality of output control signals, ensuring that data can be output after a delay time of CL for the corresponding read command. Thus, the structure of at least two stages of data multiplexers for data output makes the data FIFO circuit 3 suitable for high data rate memory device applications such as DDR5.

[0114] The above embodiments illustrate the application of the data FIFO circuit in the FIFO circuit of DDR series SDRAM. However, the embodiments of the present invention are not limited thereto. Regarding the plurality of control signals for FIFO input and output control, the operation and structure of the data FIFO circuit can be applied to other or next-generation DDR memory interface technology FIFO structures or any electronic device using a data FIFO circuit.

[0115] The following provides examples of the application of control signal techniques for FIFO input and output control used in data FIFO circuits 1 or 3 for other delay counter schemes.

[0116] refer to Figure 9 The diagram shown illustrates a schematic timing diagram of FIFO operation according to an embodiment of the present invention. Figure 9 As shown, the operation of the FIFO input control for the data FIFO circuit (not shown) is designed to work in conjunction with... Figure 2 and Figure 7 The data FIFO circuit shown operates similarly, with five control signals used for FIFO input control, including four input control signals QI[0]-QI[3] and one input start signal QIE. Therefore, for the sake of brevity, it will not be elaborated further. In order to be based on Figure 9 The timing diagram shown illustrates the operation of the data FIFO circuit to perform the FIFO output control. To meet the requirements of AL=31 and CL=32, the data multiplexer used in the data FIFO circuit (not shown) can be designed and controlled sequentially using the output start signal represented by QOE and the output control signals represented by QO[0]-QO[3] to ensure that data (e.g., 10-bit data) can be output when the timing requirements of AL and CL are met. Thus, the data FIFO circuit (not shown) can be designed using a structure of at least two stages of data multiplexers for data output, making the data FIFO circuit suitable for high data rate memory device applications.

[0117] Although the invention has been described through specific embodiments, those skilled in the art can make various modifications, combinations and variations thereto without departing from the scope and spirit of this disclosure as set forth in the claims.

Claims

1. A data first-in-first-out (FIFO) circuit, characterized in that, The data FIFO circuit includes: The buffer unit contains: Multiple decoders are configured to output multiple decoded signals in response to multiple corresponding input control signals and at least one input start signal. N buffers are configured to receive input data from the plurality of corresponding decoders in response to the plurality of corresponding decoding signals; Multiple data multiplexers, each coupled to M of the multiple buffers, where N and M are positive integers, N is equal to or greater than four, M is equal to or greater than two, and M is greater than M; and An output multiplexer, coupled to the plurality of data multiplexers, is used to sequentially provide corresponding outputs from the plurality of data multiplexers.

2. The data FIFO circuit according to claim 1, characterized in that, The N+ buffers are configured to receive the input signals sequentially according to the corresponding decoding signals.

3. The data FIFO circuit according to claim 1, characterized in that, Each of the plurality of data multiplexers provides corresponding data to the output multiplexer in response to at least one output start signal, and the output multiplexer provides corresponding outputs from the plurality of data multiplexers in response to a plurality of corresponding control signals.

4. The data FIFO circuit according to claim 1, characterized in that, The first of the plurality of data multiplexers is configured to receive a first portion of the corresponding output from the first buffer of the plurality of corresponding M buffers.

5. The data FIFO circuit according to claim 4, characterized in that, The second of the plurality of data multiplexers is configured to receive a second portion of the corresponding output from the first buffer of the corresponding M buffers.

6. The data FIFO circuit according to claim 5, characterized in that, In response to at least one output start signal, which represents the start of providing the corresponding output of the first buffer, the first and second of the plurality of data multiplexers respectively take the first and second portions of the plurality of corresponding outputs as the two inputs of the output multiplexer.

7. The data FIFO circuit according to claim 6, characterized in that, In response to a plurality of corresponding output control signals, the plurality of output control signals representing the selection of the first buffer, the output multiplexer sequentially provides the two outputs.

8. The data FIFO circuit according to claim 1, characterized in that, The output multiplexer is a first output multiplexer, and the data FIFO circuit also includes: A second output multiplexer is coupled to the first output multiplexer, and the second output multiplexer is used to selectively output a portion of the data output by the first output multiplexer.

9. The data FIFO circuit according to claim 1, characterized in that, Where M is equal to or greater than 4, and each of the plurality of data multiplexers is coupled to M of the plurality of buffers.

10. The data FIFO circuit according to claim 1, characterized in that, The plurality of caches include: The first multiplexer is configured to receive a first portion of the corresponding output from the first buffer of the plurality of corresponding M buffers; The second multiplexer is configured to receive a second portion of the corresponding output from the first buffer of the plurality of corresponding M buffers; The third multiplexer is configured to receive a first portion of the corresponding output from the second buffer of the plurality of corresponding M buffers; The fourth multiplexer is configured to receive a second portion of the corresponding output from the second buffer of the plurality of corresponding M buffers; The output multiplexer is configured to receive output from the plurality of data multiplexers and sequentially receive output data from one of the plurality of data multiplexers.

11. The data FIFO circuit according to claim 10, characterized in that, In response to at least one output start signal, the output start signal representing the start of providing the plurality of corresponding outputs of the plurality of first and fourth buffers, the first to fourth buffers respectively take the first and second portions of the corresponding outputs from the first buffer and the first and second portions of the corresponding outputs from the second buffer as inputs to the output multiplexer.

12. The data FIFO circuit according to claim 11, characterized in that, In response to a plurality of corresponding output control signals, which represent the selection of the first and second buffers, the output multiplexer sequentially provides inputs.

13. The data FIFO circuit according to claim 10, characterized in that, in: The first multiplexer is further configured to receive a first portion of the corresponding output from a third buffer of the plurality of corresponding M buffers; The second multiplexer is further configured to receive a second portion of the corresponding output from the third buffer of the plurality of corresponding M buffers; The third multiplexer is further configured to receive a first portion of the corresponding output from a fourth buffer of the plurality of corresponding M buffers; The fourth multiplexer is further configured to receive a second portion of the corresponding output from the fourth buffer of the plurality of corresponding M buffers; as well as The output multiplexer is configured to receive output from the plurality of data multiplexers and sequentially receive output data from one of the plurality of data multiplexers.

14. The data FIFO circuit according to claim 13, characterized in that, In response to at least one output start signal, which represents the start of providing the plurality of corresponding outputs of the third and fourth buffers, the first to fourth multiplexers respectively take the first and second portions of the corresponding outputs from the third buffer and the first and second portions of the corresponding outputs from the fourth buffer as inputs to the output multiplexer.

15. The data FIFO circuit according to claim 14, characterized in that, In response to a plurality of corresponding output control signals, which represent the selection of the third and fourth buffers, the output multiplexer sequentially provides outputs.

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