Leakage current control of a multi-chip module

Abstract

The present invention relates to a multi-chip module including a chip, wherein the chip includes a level control circuit, a drive circuit, an output circuit, a level control circuit and an output end. The level control circuit is used to output a response signal in response to the operating mode of the chip. When the operating mode is the working mode, the response signal is a first level. When the operating mode is the power saving mode, the response signal is a second level. The drive circuit is used to output a first drive signal and a second drive signal. The output circuit has an output side, and the output side is coupled to the output end. When the chip is in the power saving mode, the output side of the output circuit is in a floating state. When the chip is in the working mode, the output circuit is used to output an output signal at the output end according to the first drive signal. When the chip is in the power saving mode, the level supply circuit is used to provide a level voltage to the output end according to the second drive signal and the response signal, so that the output end has a fixed level.

Description

Technical Field

[0001] This case relates to the field of multi-chip modules, and in particular to leakage current control of a multi-chip module (MCM). Background Art

[0002] To reduce the size of chips in electronic products, multiple chips (CHIPs) are often packaged in a single integrated circuit (IC), also known as a multi-chip module (MCM). For example, a microprocessor chip and a memory chip are integrated into a multi-chip module, which is then packaged into a single IC. If the microprocessor chip and the memory chip are not developed and designed by the same chip design company, integration problems are more likely to occur. Furthermore, because the memory chip's I / O pad circuit design is not designed for a specific microprocessor chip, and the memory chip's active mode is controlled by the microprocessor chip, when the microprocessor is in power-saving mode, the microprocessor's output pins (PADs) are in a non-output state. Therefore, if the memory chip's input pins do not receive an output signal from the microprocessor's output pins (PADs), the memory chip's output pins are in a floating state. In this scenario, the memory chip will cause leakage current, increasing the chip's overall power consumption. Furthermore, because the multi-chip module is packaged into a single IC, it is difficult or impossible to reduce or prevent leakage through external circuitry. This means that poorly controlled leakage current within the multi-chip module causes leakage throughout the entire IC, making it difficult to control.

[0003] With the rapid advancement of electronic products today, the demand for low power consumption and small size in electronic devices (such as IoT devices) is gradually increasing. Therefore, how to achieve better leakage control in multi-chip modules and thus control the leakage of the entire IC is a problem that needs to be solved. Summary of the Invention

[0004] In view of the above, this invention proposes a leakage control method for a multi-chip module.

[0005] According to some embodiments, a multi-chip module includes a first chip, and the first chip includes a level control circuit, a driving circuit, an output circuit, a level control circuit and an output end. The level control circuit is used to output a response signal in response to the operating mode of the first chip. When the operating mode is the working mode, the response signal is a first level. When the operating mode is the power saving mode, the response signal is a second level. The driving circuit is used to output a first driving signal and a second driving signal. The output circuit has an output side, and the output side is coupled to the output end. When the first chip is in the power saving mode, the output side of the output circuit is in a floating state. When the first chip is in the working mode, the output circuit is used to output an output signal at the output end according to the first driving signal. When the first chip is in the power saving mode, the level supply circuit is used to provide a level voltage to the output end according to the second driving signal and the response signal, so that the output end has a fixed level.

[0006] According to some embodiments, a multi-chip module includes a first chip and a second chip. The second chip includes an input circuit and a mode control circuit. The input circuit is coupled to an output terminal of the first chip. The input circuit is configured to receive an output signal from the first chip and output a control signal. The mode control circuit is configured to control the second chip to be in an idle mode or an active mode based on the control signal output by the input circuit.

[0007] In summary, in some embodiments of the present invention, when a first chip is in power-saving mode, an output signal of the first chip can be at a first output level, rather than in a floating state. In some embodiments, a multi-chip module includes a first chip and a second chip. When the first chip is in power-saving mode, an output signal of the first chip can be at the first output level, rather than in a floating state. The second chip can operate in an idle mode based on the output signal at the first output level, without unnecessary power consumption caused by the output signal being in a floating state. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Below, the preferred embodiments of the present invention will be further described in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 is a schematic diagram of a multi-chip module according to some embodiments of the present invention;

[0010] Figure 2 is a schematic diagram of a first chip according to some embodiments of the present invention;

[0011] Figure 3 is a circuit diagram of a first chip according to some embodiments of the present invention;

[0012] Figure 4 is a circuit diagram of a multi-chip module according to some embodiments of the present invention; and

[0013] Figure 5 FIG. 1 is a schematic diagram of a level control circuit according to some embodiments of the present invention.

[0014] 10: Multi-chip module

[0015] 100: First Chip

[0016] 110: Switching element

[0017] 120: Level control circuit

[0018] 122: First inverter

[0019] 124: Second inverter

[0020] 126: Third inverter

[0021] 130: Pre-amplifier circuit

[0022] 140: driving circuit

[0023] 160: Output circuit

[0024] 170: Temporary circuit

[0025] 180: Level supply circuit

[0026] 190: Output

[0027] 200: Second chip

[0028] 210: Input circuit

[0029] 230: Mode control circuit

[0030] P1: First input power

[0031] P2: Second input power

[0032] V0: Response signal

[0033] V1: first driving signal

[0034] V12: first output drive signal

[0035] V14: Second output drive signal

[0036] V2: second driving signal

[0037] V22: First standard drive signal

[0038] V24: Second level driving signal

[0039] V3: output signal

[0040] V4: Level voltage

[0041] V5:Logic Signal

[0042] V6: control signal

[0043] M1: first transistor

[0044] M2: Second transistor

[0045] M3: The third transistor

[0046] M4: the fourth transistor

[0047] M5: The fifth transistor

[0048] M6: the sixth transistor

[0049] M8: The eighth transistor

[0050] M9: Ninth transistor

[0051] N1: first node

[0052] N2: Second node DETAILED DESCRIPTION

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0054] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0055] In this case, the "first level" and "first output level" are described as high levels, and the "second level" and "second output level" are described as low levels. However, this is not limiting. In other words, when the circuit configuration is adjusted accordingly, this case can be implemented with the "first level" and "first output level" as low levels, and the "second level" and "second output level" as high levels.

[0056] Figure 1 FIG. 1 is a schematic diagram of a multi-chip module 10 according to some embodiments of the present invention. Figure 1 In some embodiments, the multi-chip module 10 includes a first chip 100, wherein the first chip 100 includes a level control circuit 120, a driver circuit 140, an output circuit 160, a level supply circuit 180, and an output terminal 190. The level control circuit 120 is coupled to the driver circuit 140 and the level supply circuit 180. The input side of the output circuit 160 and the input side of the level supply circuit 180 are respectively coupled to the driver circuit 140. The output side of the output circuit and the output side of the level supply circuit 180 are commonly coupled to the output terminal 190. The level control circuit 120 is configured to output a response signal V0 in response to the operating mode of the first chip 100. When the first chip 100 is in working mode (e.g., when the driver circuit 140 is enabled), the response signal V0 generated by the level control circuit 120 is at a first level. When the first chip 100 is in power saving mode (e.g., when the driver circuit 140 is disabled), the response signal V0 generated by the level control circuit 120 is at a second level. The driver circuit 140 is configured to output a first driving signal V1 and a second driving signal V2. When the first chip 100 is in working mode, the output circuit 160 is configured to output an output signal V3 at the output terminal 190 of the first chip 100 based on the first driving signal V1. When the first chip 100 is in power-saving mode, the output side of the output circuit 160 is in a floating state. However, because the level supply circuit 180 is used to provide a level voltage V4 to the output terminal 190 of the first chip 100 based on the second drive signal V2 and the response signal V0, the output terminal 190 of the first chip 100 has a fixed level rather than being floating. The level supply circuit 180 can be implemented as a pull-up circuit, a pull-down circuit, or a pull-up and pull-down circuit. It should be noted that the power-saving mode is provided for illustrative purposes only and is not intended to be limiting. The power-saving mode can be replaced with a sleep mode or other non-operating mode.

[0057] In some embodiments, when the first chip 100 is in the operating mode, the driver circuit 140 is in an on state (hereinafter referred to as "on"). When the first chip 100 is in the power saving mode, the driver circuit 140 is in an off state (hereinafter referred to as "off"). In some embodiments, when the driver circuit 140 is in the on state, the output circuit 160 is electrically connected to the output terminal 190 in response to the first driving signal V1 (the first driving signal V1 output corresponding to the driver circuit 140 being in the on state), and the level supply circuit 180 is electrically disconnected from the output terminal 190 in response to the second driving signal V2 and the response signal V0 at the first level. In some embodiments, when the driving circuit 140 is in the off state, the output circuit 160 disconnects the electrical connection with the output terminal 190 according to the first driving signal V1 (the first driving signal V1 output corresponding to the driving circuit 140 being in the off state), and the level supply circuit 180 connects the electrical connection with the output terminal 190 according to the second driving signal V2 and the response signal V0 at the second level.

[0058] Figure 2 FIG1 is a schematic diagram of a first chip 100 according to some embodiments of the present invention. Figure 2 In some embodiments, the first chip 100 further includes a front-end circuit 130 (e.g., a processor, a microprocessor, a controller, etc.), and the driving circuit 140 is configured to output a first driving signal V1 and a second driving signal V2 in response to the output of the front-end circuit 130. Specifically, in addition to being affected by the front-end circuit 130, the first driving signal V1 is also affected by whether the first chip 100 is in an operating mode or a power saving mode. That is, the first driving signal V1 when the first chip 100 is in an operating mode is different from the first driving signal V1 when the first chip 100 is in a power saving mode. Conversely, the second driving signal V2 is not affected by whether the first chip 100 is in an operating mode or a power saving mode. In other words, the second driving signal V2 is a signal with a specific fixed potential and can be output by any circuit that can generate the specific fixed potential.

[0059] In some embodiments, when the driver circuit 140 is on, the voltage at the output of the output circuit 160 (i.e., the output signal V3) can correspond to a first output level or a second output level depending on the output level of the preceding circuit 130. That is, when the first chip 100 is in operating mode, the output circuit 160 can adjust the output signal V3 based on different first driver signals V1. However, when the first chip 100 is in power-saving mode, the driver circuit 140 is off, and the output of the output circuit 160 is simply floating (without regard to the level supply circuit 180). The response signal V0 corresponds to different operating modes, because the level supply circuit 180 provides a level voltage V4 based on the response signal V0. Therefore, when the first chip 100 is in power-saving mode, even though the output of the output circuit 160 is floating, the level supply circuit 180 can provide the level voltage V4 to maintain a fixed level (e.g., the first output level) at the output of the output circuit 160. In other words, when the first chip 100 is in power-saving mode, the output terminal 190 of the first chip 100 can still be at a fixed level, rather than being in an uncontrolled floating state. Thus, in some embodiments, the multi-chip module 10 further includes a second chip 200, with the input terminal of the second chip 200 coupled to the output terminal 190 of the first chip 100. The fixed level of the output terminal 190 can prevent unnecessary leakage current from the input terminal of the second chip 200.

[0060] Continued reference Figure 2 In some embodiments, the first chip 100 further includes a switch element 110 having a first terminal and a second terminal. The first terminal of the switch element 110 is coupled to the first input power P1, and the second terminal of the switch element 110 is coupled to the level control circuit 120 and the driver circuit 140. That is, when the first chip 100 is in the operating mode, the switch element 110 is turned on, and the driver circuit 140 is in the on state. Conversely, when the first chip 100 is in the power saving mode, the switch element 110 is turned off, and the driver circuit 140 is in the off state.

[0061] Figure 3 FIG1 is a circuit diagram of the first chip 100 according to some other embodiments of the present invention. Figure 3In some embodiments, the first chip 100 receives multiple input powers (e.g., a first input power P1 and a second input power P2), wherein the first input power P1 is core power and the second input power P2 is input / output power (I / O power). The driver circuit 140 receives the first input power P1 (e.g., 1.2 or 1.8 volts), while the level control circuit 120, the pre-stage circuit 130, the driver circuit 140, the output circuit 160, and the level supply circuit 180 receive the second input power P2 (e.g., 3.3 or 5.0 volts), but the present invention is not limited thereto. Figure 2 In the embodiment of FIG. 5 , the level control circuit 120 generates the response signal V0 according to the actuation of the switch element 110 .

[0062] In some embodiments, a resistor R0 is further provided between the output side of the level supply circuit 180 and the output terminal 190 of the first chip 100 .

[0063] In some embodiments, the first drive signal V1 includes a first output drive signal V12 and a second output drive signal V14. The output circuit 160 includes a first transistor M1 and a second transistor M2. The first transistor M1 is controlled by the first output drive signal V12, and the second transistor M2 is controlled by the second output drive signal V14. When the first chip 100 is in operating mode, if the first transistor M1 is on and the second transistor M2 is off, the first transistor M1 outputs an output signal V3 at a first output level. Conversely, if the first transistor M1 is off and the second transistor M2 is on, the second transistor M2 outputs an output signal V3 at a second output level. When the first chip is in power saving mode, the first transistor M1 and the second transistor M2 are off, meaning that the output circuit 160 does not output the output signal V3. Therefore, ignoring the effectiveness of the level supply circuit 180, the connection point between the first transistor M1 and the second transistor M2 is at a floating level (i.e., the output side of the output circuit 160 is in a floating state).

[0064] Specifically, in some embodiments, when the first transistor M1 is on and the second transistor M2 is off, the output signal V3 is controlled by the first transistor M1. When the first transistor M1 is off and the second transistor M2 is on, the output signal V3 is controlled by the second transistor M2. When the first transistor M1 and the second transistor M2 are off, neither the first transistor M1 nor the second transistor M2 can control the output signal V3, and thus the output signal V3 is at a floating level.

[0065] In some embodiments, the first transistor M1 is a P-type transistor, and the second transistor M2 is an N-type transistor.

[0066] It should be noted that when the driving circuit 140 is turned on and the first transistor M1 is turned on and the second transistor M2 is turned off, the first transistor M1 can pull the output signal V3 up to the second input power P2 according to the second input power P2, that is, pull it up to the first level. Conversely, when the driving circuit 140 is turned on and the first transistor M1 is turned off and the second transistor M2 is turned on, the second transistor M2 can pull the output signal V3 down to the ground level according to the ground level of the ground terminal, that is, pull it down to the second level.

[0067] In some embodiments, the second driving signal V2 includes a first level driving signal V22 and a second level driving signal V24. The level supply circuit 180 includes a logic element 182, a third transistor M3, and a fourth transistor M4. The logic element 182 is coupled between the driving circuit 140 and the third transistor M3, and the logic element 182 is used to generate a logic signal V5 based on the first level driving signal V22 and the response signal V0. The third transistor M3 is controlled by the logic signal V5, and the fourth transistor M4 is controlled by the second level driving signal V24. When the first chip 100 is in the working state, the third transistor M3 and the fourth transistor M4 are turned off, and the level supply circuit 180 does not provide the level voltage V4. When the first chip 100 is in the power saving mode, the fourth transistor M4 is turned off, and the third transistor M3 is turned on through the operation of the logic element 182 to provide the clamping signal V4.

[0068] Specifically, in some embodiments, when the first chip 100 is in an operating state, the third transistor M3 and the fourth transistor M4 are both off, and the level supply circuit 180 does not provide the level voltage V4. Therefore, the output signal V3 output by the output circuit 160 is not affected by the level supply circuit 180. In contrast, when the first chip 100 is in a power-saving mode, the third transistor M3 is on and the fourth transistor M4 is off, and the output circuit 160 has no output. However, the level supply circuit 180 provides the level voltage V4. Therefore, the output terminal 190 of the first chip 100 has a fixed level corresponding to the level voltage V4.

[0069] In some embodiments, the logic element 182 is an AND gate. When the first chip 100 is in an operating state (when the driver circuit 140 is on and the switch element 110 is conductive), the first level-driving signal V22 is at a first level, the response signal V0 is at a second level, and the logic signal V5 is at the second level. When the first chip 100 is in a power-saving state (when the driver circuit 140 is off and the switch element 110 is disconnected), the first level-driving signal V22 is at a first level, the response signal V0 is at a first level, and the logic signal V5 is at the first level. Therefore, when the first chip 100 is in an operating state, the third transistor M3 and the fourth transistor M4 are disconnected. When the first chip 100 is in a power-saving state, the third transistor M3 is on and the fourth transistor M4 is disconnected.

[0070] In some embodiments, the third transistor M3 is a P-type transistor, and the fourth transistor M4 is an N-type transistor.

[0071] Specifically, in some embodiments, logic element 182 is an AND gate. When first chip 100 is in operation, response signal V0 is at the second level, and driver circuit 140 outputs first-level drive signal V22 at the first level and second-level drive signal V24 at the second level. Therefore, logic signal V5 is at the second level. Therefore, third transistor M3 is turned on, and fourth transistor M4 is turned off. Third transistor M3 can pull voltage level V4 up to approximately the second input power P2, i.e., to the first output level, based on second input power P2. Therefore, third transistor M3 can also pull output terminal 190 of first chip 100 up to approximately the first output level.

[0072] In some embodiments, if the first chip 100 is in a power-saving state (when the driver circuit 140 is off and the switch element 110 is disconnected), the response signal V0 is at the first level. The logic element 182 can be designed to be coupled between the driver circuit 140 and the fourth transistor M4, and the logic element 182 can be designed as an OR gate. Therefore, the third transistor M3 is off and the fourth transistor M4 is on. The fourth transistor M4 can then pull the voltage V4 down to the ground potential, i.e., to the second output potential, based on the ground potential of the ground terminal. Therefore, the fourth transistor M4 can also pull the output terminal 190 of the first chip 100 down to the second output potential.

[0073] Also refer to Figure 2 and Figure 3In some embodiments, the first chip 100 further includes a temporary storage circuit 170. The temporary storage circuit 170 is used to store a temporary value and adjust the level voltage V4 provided by the level supply circuit 180 to a high level or a low level. In other words, the level supply circuit 180 determines whether the level voltage V4 provided to the output terminal 190 of the first chip 100 is a high level or a low level based on the temporary storage value of the temporary storage circuit 170. In addition, in some embodiments, the second chip 200 includes an input circuit 210. Due to the circuit characteristics of the input circuit 210 of the second chip 200, the level V4 provided by the level supply circuit 180 may be a high level (the second input power P2) or a low level (the ground potential of the ground terminal). Considering that the input circuit 210 of the second chip 200 already has a pull-up resistor or a pull-down resistor, the level supply circuit 180 can also set the third transistor M3 and the fourth transistor M4 to be disconnected based on the temporary value of the temporary register circuit 170, so that the connection point between the third transistor M3 and the fourth transistor M4 (the output side of the level supply circuit 180) is in a floating state. The pull-up resistor or the pull-down resistor of the input circuit 210 of the second chip 200 is directly utilized to prevent leakage current of the entire multi-chip module 10.

[0074] Figure 4 FIG. 1 is a circuit diagram of a multi-chip module 10 according to some embodiments of the present invention. Figure 4 In some embodiments, a multi-chip module 10 includes a first chip 100 and a second chip 200. The first chip 100 is coupled to the second chip 200 and controls and accesses the second chip 200. Specifically, an output pad of the first chip 100 is coupled to an input pad of the second chip 200. In one embodiment, the second chip 200 is a memory chip, and the input pad of the second chip 200 is a chip select pin or a chip enable pin of the memory chip.

[0075] In some embodiments, the second chip 200 includes an input circuit 210 and a mode control circuit 230. The input circuit 210 is coupled to the output terminal 190 of the first chip 100. The input circuit 210 is also coupled to the mode control circuit 230. The input circuit 210 of the second chip 200 is configured to receive the output signal V3 from the output terminal 190 of the first chip 100 and output a control signal V6 based on the output signal V3. The mode control circuit 230 receives the control signal V6 output by the input circuit 210 and controls the second chip 200 to operate in either an idle mode or an active mode based on the control signal V6.

[0076] It should be noted that in some embodiments, when the multi-chip module 10 operates in power-saving mode, the first chip 100 also operates in power-saving mode, while the second chip 200 is in idle mode. When the multi-chip module 10 operates in active mode, the first chip 100 operates in active mode, while the second chip 200 can be controlled by output signal V3 to operate in either active mode or idle mode. In other words, when the chip module 10 operates in power-saving mode (i.e., the first chip 100 operates in power-saving mode), the voltage level V4 adjusts the output terminal 190 of the first chip 100 from a floating state to a first output level. Therefore, when the first chip 100 operates in power-saving mode, the second chip 200 is guaranteed to be in idle mode. If the output terminal 190 of the first chip 100 is floating, the second chip 200 may enter active mode, resulting in unnecessary power consumption.

[0077] In some embodiments, the input circuit 210 includes a fifth transistor M5 and a sixth transistor M6. The fifth transistor M5 is a P-type transistor, and the sixth transistor M6 is an N-type transistor.

[0078] In some embodiments, the first chip 100 further includes two diodes. These two diodes are ESD protection circuits and are disposed at the output terminal 190 of the first chip 100. In some embodiments, the second chip 200 further includes two diodes. These two diodes are ESD protection circuits and are disposed at the input terminal of the second chip 200.

[0079] Figure 5 FIG. 1 is a schematic diagram of a level control circuit 120 according to some embodiments of the present invention. Figure 5In some embodiments, the level control circuit 120 includes an eighth transistor M8, a ninth transistor M9, a first inverter 122, a second inverter 124, a third inverter 126, a first node N1, and a second node N2. The ninth transistor M9 is a P-type transistor, and the eighth transistor M8 is an N-type transistor. The first inverter 122, the second inverter 124, and the third inverter 126 have a threshold voltage. The eighth transistor M8 includes an eighth gate terminal, an eighth source terminal, and an eighth drain terminal. The ninth transistor M9 includes a ninth gate terminal, a ninth source terminal, and a ninth drain terminal. The first inverter 122 includes a first input terminal and a first output terminal. The second inverter 124 includes a second input terminal and a second output terminal. The third inverter 126 includes a third input terminal and a third output terminal. The eighth drain terminal and the ninth source terminal receive the second input power P2. The eighth gate terminal receives the first input power P1. The eighth drain terminal, the ninth drain terminal, and the first input terminal are coupled to the first node N1. The eighth source terminal is coupled to the ground terminal. The ninth gate terminal, the first output terminal, and the second input terminal are coupled to the second node N2. The second output terminal is coupled to the third input terminal. The third output terminal is configured to output a response signal V0. Specifically, the level control circuit 120 outputs a corresponding response signal V0 from the third output terminal based on the signal received at the eighth gate terminal indicating whether the driving circuit 140 is on or off.

[0080] Specifically, in some embodiments, when the driver circuit 140 is off, for example, the signal received by the eighth gate terminal indicating that the driver circuit 140 is off is at a second level. The first node voltage of the first node N1 will be greater than the threshold voltage of the first inverter 122, and thus the second node voltage of the second node N2 will be at a second level. Feedback is then provided through the ninth transistor M9, pulling the first node voltage of the first node N1 up to the second input power P2. In other words, the ninth gate terminal is turned on in response to the second node voltage being at the second level, and thus the first node voltage of the first node N1 is pulled up to the second input power P2 by the turned-on ninth transistor M9.

[0081] In some embodiments, the first chip 100 and the multi-chip module 10 are applied in, for example but not limited to, an Internet of Things device, a mobile device, or other electronic devices.

[0082] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0083] The above embodiments are only used to illustrate the present invention, and are not intended to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims

1. A multi-chip module, comprising a chip, the chip comprising: a level control circuit for outputting a response signal in response to an operating mode of the chip, wherein the response signal is at a first level when the operating mode is a working mode and at a second level when the operating mode is a power saving mode; a driving circuit for outputting a first driving signal and a second driving signal; an output terminal; an output circuit having an output side coupled to the output terminal, wherein when the chip is in the power saving mode, the output side of the output circuit is in a floating state, and when the chip is in the working mode, the output circuit is configured to output an output signal at the output terminal according to the first driving signal; and a level supply circuit, which is used to provide a level voltage to the output terminal according to the second driving signal and the response signal when the chip is in the power saving mode, so that the output terminal has a fixed level; The multi-chip module further includes another chip for controlling and accessing the other chip. The input end of the other chip is coupled to the output end of the chip. The output end of the chip is at a fixed level for reducing leakage current generated by the other chip.

2. The multi-chip module according to claim 1, wherein the chip further comprises: A switching element having: a first terminal coupled to an input power; and a second terminal coupled to the level control circuit and the driving circuit; When the chip is in this working mode, the switch element is turned on and the drive circuit is in an on state; When the chip is in the power saving mode, the switch element is disconnected and the driving circuit is in a closed state.

3. The multi-chip module as claimed in claim 1, wherein the chip further comprises a front-end circuit, and the driving circuit is configured to output the first driving signal and the second driving signal in response to an output of the front-end circuit.

4. The multi-chip module of claim 1 , wherein when the chip is in the operating mode, the driving circuit is in an on-state, the output circuit is electrically connected to the output terminal in response to the first driving signal corresponding to the on-state, and the level supply circuit is electrically disconnected from the output terminal in response to the second driving signal and the response signal at the first level.

5. The multi-chip module of claim 1 , wherein when the chip is in the power saving mode, the driving circuit is in a shutdown state, the output circuit is electrically disconnected from the output terminal in response to the first driving signal corresponding to the shutdown state, and the level supply circuit is electrically connected to the output terminal in response to the second driving signal and the response signal at the second level.

6. The multi-chip module according to claim 1 , wherein the first driving signal comprises a first output driving signal and a second output driving signal, and the output circuit comprises: a first transistor controlled by the first output drive signal; and a second transistor controlled by the second output drive signal; Wherein, when the chip is in the working mode, the first transistor is turned on and the second transistor is turned off, the first transistor outputs the output signal at the first output level; Wherein, when the chip is in the working mode, the first transistor is turned off and the second transistor is turned on, the second transistor outputs the output signal at a second output level; and When the chip is in the power saving mode, the first transistor and the second transistor are disconnected, and the output circuit does not output the output signal.

7. The multi-chip module according to claim 1 , wherein the second driving signal comprises a first-level driving signal and a second-level driving signal, and the level supply circuit comprises: a logic element for generating a logic signal according to the first-level driving signal and the response signal; a third transistor controlled by the logic signal; and a fourth transistor controlled by the second-level driving signal; When the chip is in the working mode, the third transistor and the fourth transistor are disconnected, and the level supply circuit does not output the level voltage; and When the chip is in the power saving mode, the third transistor is turned on and outputs the level voltage, and the fourth transistor is turned off.

8. The multi-chip module according to claim 7, wherein the logic element is an AND gate; in, When the chip is in the working mode, the first-level driving signal is at the first level, the response signal is at the second level, and the logic signal is at the second level; and When the chip is in the power saving mode, the first level driving signal is at the first level, the response signal is at the first level, and the logic signal is at the first level.

9. The multi-chip module according to claim 1, wherein the chip further comprises: a temporary storage circuit for storing a temporary value; The level supply circuit determines whether the output level voltage is a high level or a low level according to the temporary value.

10. The multi-chip module according to claim 1, wherein the other chip comprises: an input circuit coupled to the output terminal of the chip through the input terminal of the other chip, for receiving the output signal from the chip and outputting a control signal; and A mode control circuit is used to control the other chip to be in an idle mode or an active mode according to the control signal output by the input circuit.

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