Uninstall card namespace management, input and output request processing system and method

Abstract

The disclosed embodiment discloses an offload card namespace management, input / output request processing system and method. The offload card namespace management system includes a host and an offload card connected to the host, wherein multiple applications that issue input / output requests are running on the host, and the host sends a namespace creation request to the offload card, and the offload card creates multiple namespaces corresponding to the multiple applications according to the namespace creation request, and the offload card allocates multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binds the allocated multiple hardware queues to the corresponding namespaces respectively, so that multiple namespaces can be created, and exclusive hardware queues are dynamically allocated to each namespace, realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to an uninstall card namespace management, input / output request processing system and method. Background Art

[0002] NVMe (Non-Volatile Memory express) memory is a common solid-state memory in the field of server technology, for example, NVMe SSD (Solid State Drive). With the complexity of product application scenarios, direct-connected NVMe devices require a large amount of computing space on the central processing unit (CPU), thus affecting the performance of the CPU.

[0003] Currently, namespace technology has been used to divide / manage NVME storage space, mainly for dividing disk logical space for different applications and establishing a security isolation mechanism. Different namespaces are isolated using software technology and share some hardware resources, such as hardware queues.

[0004] The advantages of the namespace technology known in the related technology: it is implemented through software, provides flexible space management capabilities, and meets the requirements of software-defined storage.

[0005] Disadvantages of the known namespace technology in the related art: Different applications in the namespace will share the hardware resources of the NVMe device, such as the hardware queue, which will cause performance interference problems and the fault isolation capability is relatively poor. Summary of the invention

[0006] In order to solve the problems in the related art, the embodiments of the present disclosure provide an offload card namespace management and input / output request processing system and method.

[0007] In a first aspect, an embodiment of the present disclosure provides an offload card namespace management system, including a host and an offload card connected to the host, wherein:

[0008] A plurality of applications issuing input and output requests are running on the host, and the host sends a create namespace request to the offload card,

[0009] The offloading card creates a plurality of corresponding namespaces for the plurality of applications according to the namespace creation request,

[0010] The offload card allocates a plurality of hardware queues corresponding to the created plurality of namespaces according to the namespace creation request and binds the allocated plurality of hardware queues to the corresponding namespaces respectively.

[0011] In combination with the first aspect, in a first implementation of the first aspect of the present disclosure, a virtual machine is running on the host, the multiple applications are running in the virtual machine, and the virtual machine includes:

[0012] A driver is used to manage the multiple hardware queues, and the virtual machine sends the namespace creation request to the offload card through the driver.

[0013] In combination with the first implementation of the first aspect, in a second implementation of the first aspect of the present disclosure, the offload card includes a controller and a hardware accelerator, wherein:

[0014] The controller creates respective namespaces for the multiple applications according to the namespace creation request, allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator, and binds the allocated multiple hardware queues to the corresponding namespaces respectively.

[0015] In combination with the second implementation of the first aspect, in a third implementation of the first aspect of the present disclosure, the host includes a multi-core central processing unit, the virtual machine includes a user space and a kernel space,

[0016] The plurality of applications are run in the user space, and the applications are executed by corresponding cores.

[0017] The kernel space includes a common block layer and the driver, the common block layer includes a plurality of software queues corresponding to the plurality of cores, and a one-to-one correspondence is established from the plurality of software queues to the plurality of hardware queues.

[0018] In combination with the third implementation of the first aspect, in a fourth implementation of the first aspect of the present disclosure, the drive is an NVMe drive, the controller is an NVMe controller,

[0019] Wherein, the host is connected to the NVMe device through the offload card,

[0020] The NVMe device is mounted inside the virtual machine.

[0021] The application running in the user space sends an input / output request to the general block layer.

[0022] The input / output request is converted into an input / output request that complies with the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller.

[0023] The NVMe controller transfers the input and output requests that comply with the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace.

[0024] The offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

[0025] In a second aspect, an embodiment of the present disclosure provides an offload card namespace management method, the method running in an offload card namespace management system, the offload card namespace management system including a host and an offload card connected to the host, wherein the method includes:

[0026] Based on a plurality of applications running on the host issuing input and output requests, the host sends a create namespace request to the offload card;

[0027] The offload card creates a plurality of corresponding namespaces for the plurality of applications according to the namespace creation request;

[0028] The offload card allocates a plurality of hardware queues corresponding to the created plurality of namespaces according to the namespace creation request and binds the allocated plurality of hardware queues to the corresponding namespaces respectively.

[0029] In combination with the second aspect, in a first implementation of the second aspect of the present disclosure, a virtual machine is running on the host, the multiple applications are running in the virtual machine, the virtual machine includes a driver for managing the multiple hardware queues, wherein the host sends a namespace creation request to the offload card, including:

[0030] The virtual machine sends the namespace creation request to the offload card through the driver.

[0031] In combination with the first implementation manner of the second aspect, in a second implementation manner of the second aspect of the present disclosure, the offload card includes a controller and a hardware accelerator, wherein the offload card creates a plurality of corresponding namespaces for the plurality of applications according to the namespace creation request, including:

[0032] The controller creates respective namespaces for the multiple applications according to the namespace creation request,

[0033] The offload card allocates a plurality of hardware queues corresponding to the created plurality of namespaces according to the namespace creation request and binds the allocated plurality of hardware queues to the corresponding namespaces respectively, including:

[0034] The controller allocates a plurality of hardware queues corresponding to the created plurality of namespaces from the hardware accelerator and binds the allocated plurality of hardware queues to the corresponding namespaces respectively.

[0035] In combination with the second implementation of the second aspect, in a third implementation of the second aspect of the present disclosure, the host includes a multi-core central processing unit, the virtual machine includes a user space and a kernel space,

[0036] The plurality of applications are run in the user space, and the applications are executed by corresponding cores.

[0037] The kernel space includes a common block layer and the driver, the common block layer includes a plurality of software queues corresponding to the plurality of cores, and a one-to-one correspondence is established from the plurality of software queues to the plurality of hardware queues.

[0038] In combination with the third implementation manner of the second aspect, in a fourth implementation manner of the second aspect of the present disclosure, the drive is an NVMe drive, the controller is an NVMe controller,

[0039] Wherein, the host is connected to the NVMe device through the offload card,

[0040] Wherein, the method further comprises:

[0041] Mounting the NVMe device into the virtual machine;

[0042] The application running in the user space sends an input and output request to the common block layer;

[0043] The input / output request is converted into an input / output request conforming to the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller;

[0044] The NVMe controller transfers the input and output requests that comply with the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace.

[0045] The offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

[0046] In a third aspect, an input / output request processing system is provided in an embodiment of the present disclosure, comprising a host, an offload card, and an NVMe device connected to the host via the offload card.

[0047] A virtual machine is running on the host, the host includes a multi-core central processing unit, the virtual machine includes a user space and a kernel space, a plurality of applications issuing input and output requests are running in the user space, the applications are executed by corresponding cores, the kernel space includes a common block layer and an NVMe driver, the common block layer includes a plurality of software queues corresponding to the plurality of cores, the virtual machine sends a namespace creation request to the offload card through the NVMe driver,

[0048] The offload card includes an NVMe controller and a hardware accelerator, wherein the NVMe controller creates respective namespaces for the multiple applications according to the namespace creation request, and allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively.

[0049] The NVMe driver is used to manage the multiple hardware queues, and the general block layer establishes a one-to-one correspondence between the multiple software queues and the multiple hardware queues.

[0050] The application running in the user space sends an input / output request to the general block layer.

[0051] The input / output request is converted into an input / output request that complies with the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller.

[0052] The NVMe controller transfers the input and output requests that comply with the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace.

[0053] The offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

[0054] In a fourth aspect, an input / output request processing method is provided in an embodiment of the present disclosure, wherein the method is run in an input / output request processing system, wherein the input / output request processing system includes a host, an offload card, and an NVMe device connected to the host via the offload card.

[0055] A virtual machine is running on the host, the host includes a multi-core central processing unit, the virtual machine includes a user space and a kernel space, a plurality of applications issuing input and output requests are running in the user space, the applications are executed by corresponding cores, the kernel space includes a common block layer and an NVMe driver, the common block layer includes a plurality of software queues corresponding to the plurality of cores, the virtual machine sends a namespace creation request to the offload card through the NVMe driver,

[0056] The offload card includes an NVMe controller and a hardware accelerator, wherein the NVMe controller creates respective namespaces for the multiple applications according to the namespace creation request, and allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively.

[0057] The NVMe driver is used to manage the multiple hardware queues, and the general block layer establishes a one-to-one correspondence between the multiple software queues and the multiple hardware queues.

[0058] Wherein, the method comprises:

[0059] The application running in the user space sends an input and output request to the common block layer;

[0060] The input / output request is converted into an input / output request conforming to the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller;

[0061] The NVMe controller carries the input and output requests conforming to the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace;

[0062] The offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

[0063] According to the technical solution provided by the embodiment of the present disclosure, through the unloading card namespace management system, including a host and an unloading card connected to the host, wherein multiple applications that issue input and output requests are running on the host, and the host sends a namespace creation request to the unloading card, the unloading card creates multiple namespaces corresponding to the multiple applications according to the namespace creation request, the unloading card allocates multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binds the allocated multiple hardware queues to the corresponding namespaces respectively, multiple namespaces can be created, and exclusive hardware queues are dynamically allocated to each namespace, hardware-level namespace resources are realized, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace. Moreover, compared with the solution that all application processes share multiple hardware queues uniformly managed by one namespace, the solution of the embodiment of the present disclosure does not affect the applications of other hardware queues when a single hardware queue fails, and has a great improvement in performance isolation capability and fault isolation capability.

[0064] According to the technical solution provided by the embodiment of the present disclosure, a virtual machine is run on the host, and the multiple applications are run in the virtual machine. The virtual machine includes: a driver, which is used to manage the multiple hardware queues. The virtual machine sends the namespace creation request to the offload card through the driver, and can create multiple namespaces. An exclusive hardware queue is dynamically allocated to each namespace, thereby realizing hardware-level namespace resources. The application can use its own corresponding hardware queue, which greatly improves the performance isolation capability and reliability of the namespace.

[0065] According to the technical solution provided by the embodiment of the present disclosure, the offload card includes a controller and a hardware accelerator, wherein the controller creates respective namespaces for the multiple applications according to the namespace creation request, and allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces, respectively. Multiple namespaces can be created, and exclusive hardware queues can be dynamically allocated to each namespace, thereby realizing hardware-level namespace resources. Applications can use their own corresponding hardware queues, greatly improving the performance isolation capability and reliability of the namespace.

[0066] According to the technical solution provided by the embodiment of the present disclosure, the host includes a multi-core central processing unit, and the virtual machine includes a user space and a kernel space, wherein the multiple applications are running in the user space, and the applications are executed by corresponding cores, wherein the kernel space includes a common block layer and the driver, and the common block layer includes a plurality of software queues corresponding to the plurality of cores, and a one-to-one correspondence is established from the plurality of software queues to the plurality of hardware queues, multiple namespaces can be created, and exclusive hardware queues can be dynamically allocated to each namespace, thereby realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace.

[0067] According to the technical solution provided by the embodiment of the present disclosure, the driver is an NVMe driver, the controller is an NVMe controller, wherein the host is connected to the NVMe device through the offload card, wherein the NVMe device is mounted inside the virtual machine, wherein the application running in the user space sends an input and output request to the general block layer, wherein the input and output request is converted into an input and output request that complies with the NVMe protocol through the processing of the general block layer and the NVMe driver, and sent to the NVMe controller, wherein the NVMe controller carries the input and output request that complies with the NVMe protocol to the offload card through the hardware queue corresponding to the created namespace, wherein the offload card sends the input and output request that complies with the NVMe protocol to the NVMe device, multiple namespaces can be created, and exclusive hardware queues are dynamically allocated to each namespace, hardware-level namespace resources are realized, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace. Moreover, the existing NVMe namespace capabilities are strengthened and expanded, and combined with the technical architecture of hardware and software integration, the performance isolation capability and fault isolation capability are greatly improved, and the software ecology of the upper-layer application is fully compatible.

[0068] According to the technical solution provided by the embodiment of the present disclosure, through the unloading card namespace management method, the method runs on the unloading card namespace management system, the unloading card namespace management system includes a host and an unloading card connected to the host, wherein the method includes: based on multiple applications running on the host that issue input and output requests, the host sends a namespace creation request to the unloading card; the unloading card creates multiple namespaces corresponding to the multiple applications according to the namespace creation request; the unloading card allocates multiple hardware queues corresponding to the multiple namespaces created according to the namespace creation request and binds the allocated multiple hardware queues to the corresponding namespaces respectively, multiple namespaces can be created, and exclusive hardware queues are dynamically allocated to each namespace, hardware-level namespace resources are realized, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace. Moreover, compared with the solution that all application processes share multiple hardware queues uniformly managed by one namespace, the solution of the embodiment of the present disclosure does not affect the applications of other hardware queues when a single hardware queue fails, and has a great improvement in performance isolation capability and fault isolation capability.

[0069] According to the technical solution provided by the embodiment of the present disclosure, a virtual machine is run on the host, and the multiple applications are run in the virtual machine, and the virtual machine includes a driver for managing the multiple hardware queues, wherein the host sends a namespace creation request to the offload card, including: the virtual machine sends the namespace creation request to the offload card through the driver, multiple namespaces can be created, and exclusive hardware queues are dynamically allocated to each namespace, thereby realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace.

[0070] According to the technical solution provided by the embodiment of the present disclosure, the offload card includes a controller and a hardware accelerator, wherein the offload card creates corresponding multiple namespaces for the multiple applications according to the namespace creation request, including: the controller creates respective namespaces for the multiple applications according to the namespace creation request, wherein the offload card allocates multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binds the allocated multiple hardware queues to the corresponding namespaces respectively, including: the controller allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively, multiple namespaces can be created, and exclusive hardware queues can be dynamically allocated to each namespace, thereby realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace.

[0071] According to the technical solution provided by the embodiment of the present disclosure, the host includes a multi-core central processing unit, and the virtual machine includes a user space and a kernel space, wherein the multiple applications are running in the user space, and the applications are executed by corresponding cores, wherein the kernel space includes a common block layer and the driver, and the common block layer includes a plurality of software queues corresponding to the plurality of cores, and a one-to-one correspondence is established from the plurality of software queues to the plurality of hardware queues, multiple namespaces can be created, and exclusive hardware queues can be dynamically allocated to each namespace, thereby realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace.

[0072] According to the technical solution provided by the embodiment of the present disclosure, the driver is an NVMe driver, the controller is an NVMe controller, wherein the host is connected to the NVMe device through the offload card, wherein the method further includes: mounting the NVMe device inside the virtual machine; the application running in the user space sends an input and output request to the general block layer; the input and output request is converted into an input and output request that complies with the NVMe protocol through the processing of the general block layer and the NVMe driver, and sent to the NVMe controller; the NVMe controller transports the input and output request that complies with the NVMe protocol to the offload card through the hardware queue corresponding to the created namespace, and the offload card sends the input and output request that complies with the NVMe protocol to the NVMe device, multiple namespaces can be created, and a dedicated hardware queue is dynamically allocated to each namespace, realizing hardware-level namespace resources, and the application can use its own corresponding hardware queue, which greatly improves the performance isolation capability and reliability of the namespace. Moreover, the existing NVMe namespace capabilities are strengthened and expanded, and combined with the technical architecture of software and hardware integration, the performance isolation capability and fault isolation capability are greatly improved, and the software ecology of the upper-layer application is fully compatible.

[0073] According to the technical solution provided by the embodiment of the present disclosure, by using the aforementioned unloading card namespace management solution to process input and output requests, multiple namespaces can be created, and a dedicated hardware queue is dynamically allocated to each namespace, realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues to avoid interference between input and output requests of different applications, and improve fault isolation capabilities. The performance isolation capability and reliability of the namespace are greatly improved. In addition, the existing NVMe namespace capabilities are strengthened and expanded, and combined with the technical architecture of hardware and software integration, the performance isolation capability and fault isolation capability are greatly improved, and the software ecology of the upper-level applications is fully compatible.

[0074] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0076] Figure 1 An exemplary schematic diagram showing an implementation scenario of an uninstall card namespace management system according to the related art;

[0077] Figure 2An exemplary schematic diagram showing an implementation scenario of an uninstall card namespace management system according to an embodiment of the present disclosure;

[0078] Figure 3 A structural block diagram of an offload card namespace management system according to an embodiment of the present disclosure is shown;

[0079] Figure 4 A flowchart showing a method for managing an uninstall card namespace according to an embodiment of the present disclosure is shown;

[0080] Figure 5 A structural block diagram of an input and output request processing system according to an embodiment of the present disclosure is shown;

[0081] Figure 6 A flowchart showing an input and output request processing method according to an embodiment of the present disclosure;

[0082] Figure 7 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0083] Figure 8 It is a schematic diagram of the structure of a computer system suitable for implementing the methods according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0084] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0085] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0086] In the present disclosure, the acquisition of user information or user data is an operation authorized and confirmed by the user, or actively selected by the user.

[0087] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0088] The following is a brief description of terms that may be involved in the embodiments of the present disclosure.

[0089] DMA (Direct Memory Access): Direct memory access is a memory access technology in computer science. It allows certain computer hardware subsystems (computer peripherals) to read and write system memory independently without the intervention of the central processing unit (CPU). Under the same processor load, DMA is a fast data transfer method. Many hardware systems use DMA, including hard disk controllers, graphics cards, network cards, and sound cards.

[0090] Offloading card: It implements the functions originally implemented by software through hardware, so that some data processing originally performed on the operating system can be moved to hardware, reducing system CPU consumption while improving processing performance.

[0091] PCIe (Peripheral Component Interconnect express): is a high-speed serial computer expansion bus standard that uses the existing PCI programming concepts and signal standards and builds a higher-speed serial communication system standard.

[0092] FPGA (Field-Programmable Gate Array): Field-programmable logic gate array, which is developed based on the technology of programmable logic devices such as PAL, GAL, CPLD, etc. As a semi-customized circuit in ASIC, it not only makes up for the shortcomings of ASIC circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable logic devices.

[0093] ASIC (Application Specific Integrated Circuit): refers to a special specification integrated circuit that is fully customized according to different product requirements. It is an integrated circuit product that is different from standard industrial IC.

[0094] ioctl (input / output control): input / output control is a system call function dedicated to device input and output operations. It passes in a request code related to the device. The function of the system call depends entirely on the request code. ioctl is a function in the device driver that manages the I / O channel of the device.

[0095] As mentioned above, namespace technology is currently used to divide / manage NVME storage space, mainly for dividing disk logical space for different applications and establishing a security isolation mechanism. Different namespaces are isolated using software technology and share some hardware resources, such as hardware queues, which will cause performance interference problems and have poor fault isolation capabilities. In addition to providing space division functions, namespace technology can also provide independent formatting and encryption capabilities for each namespace, which is equivalent to independent configuration functions.

[0096] The following reference Figure 1 The present invention describes an offload card namespace management system in the related art. Figure 1 An exemplary schematic diagram showing an implementation scenario of an offload card namespace management system according to the related art.

[0097] like Figure 1 As shown, the offload card namespace management system of the related art can adopt a hardware offloading architecture, and the system can include a host 1100 and an offload card 1200. The host 1100 can access the NVMe device 1300 through the offload card 1200. The offload card 1200 and the NVMe device 1300 can be used together as a storage system. The offload card 1200 and the NVMe device 1300 can be connected through a PCIe interface. The specific PCIe interface specification can be obtained from the related art, and this disclosure will not go into details.

[0098] like Figure 1As shown, a virtual machine 1110 is running on the host 1100, and the virtual machine 1110 may include a user space 1111 and a kernel space 1115. In one embodiment of the present disclosure, the virtual machine 1110 may be a Linux virtual machine. In one embodiment of the present disclosure, an application 1112 (or a thread of an application) is running in the user space 1111, and the application 1112 sends data through a central processing unit (CPU) core 1113. The kernel space 1115 of the virtual machine 1110 has a general block layer (Blk-mq in the Linux kernel) 1116. The general block layer 1116 provides a software queue for the upper layer application 1112, and each CPU core 1113 corresponds to a software queue 11161. The kernel space 1115 of the virtual machine 1110 also has a driver (e.g., an NVMe driver) 1117 for maintaining and managing a hardware queue 11171, and can send input and output (IO) requests to specific physical hardware (e.g., an offload card) for processing by, for example, setting hardware registers. The general block layer 1116 can maintain a mapping relationship from the software queue 11161 to the hardware queue 11171. The software queue 11161 can be used to forward data sent by the CPU core 1113. The hardware queue 11171 is used to forward data that needs to be sent to the NVMe device.

[0099] In the offload card namespace management system of the related art, because the general block layer 1116 needs to interact with the hardware through the NVMe driver 1117, the hardware also needs to support multiple queues. The ideal situation is that the hardware supports enough queues, and each software queue 11161 of the general block layer 1116 has a hardware queue 11171 associated with it. However, the hardware queues supported by the hardware in the related art are limited, so the following is formed: Figure 1 The relationship shown. Figure 1 There are 4 hardware queues 11171 in the general block layer 1116, but the general block layer 1116 forms a total of 8 software queues 11161. Therefore, the general block layer 1116 associates 2 software queues 11161 with 1 hardware queue 11171, that is, establishes a mapping relationship from 2 software queues 11161 to 1 hardware queue 11171.

[0100] In the offload card namespace management system of the related art, the offload card 1200 includes an NVMe controller 1210 and an accelerator 1220. The offload card 1200 can simulate the standard NVMe controller 1210 through software and hardware technology, and is responsible for processing the configuration request of the NVMe driver 1117 in the kernel space 1115 in the virtual machine 1110, and completing the management tasks such as initialization, mounting / unmounting of the NVMe device 1300. The accelerator 1220 is, for example, an accelerator based on FPGA hardware or ASIC hardware, which is responsible for transferring the IO request in the virtual machine 1110 to the offload card 1200 in a DMA manner and sending it to the NVMe device 1300 through a connection method such as a network card or PCI. For example, in the offload card 1200, the 4 hardware queues 11171 contained in the NVMe controller 1210 are pre-allocated in the accelerator 1220 corresponding to the hardware part 1221, and are managed by a namespace 1211.

[0101] In the offload card namespace management system of the related art, the NVMe controller 1210 manages the disk space of the device 1300 and the block device-related attributes, such as sector size, capacity, etc., through a namespace. In the offload card 1200, an NVMe controller 1210 can include 4 hardware queues, which are uniformly managed by a namespace 1211. The NVMe controller 1210 of the related art may actually include more hardware queues, but the core problem is that even if the number of hardware queues can match the number of applications, it is impossible to allocate independent hardware queues to each application by dividing the namespace. All application processes share the hardware queues of the NVMe controller 1210, and different applications on the namespace 1211 of the NVMe controller 1210 will share the hardware resources of the NVMe device 1300. Therefore, there are certain performance resource contention problems and weak fault isolation capabilities.

[0102] In the case of processing IO requests using the offload card namespace management system of the related technology, the application 1112 in the virtual machine 1110 can send IO requests to the general block layer 1116 in the kernel space 1115 through the system call interface. The general block layer 1116 in the kernel space 1115 receives the IO request and encapsulates it into a bio request (a request of the general block layer). The NVMe driver 1117 is responsible for converting the bio request into an IO request that complies with the NVMe protocol, and can send IO requests that comply with the NVMe protocol through the device hardware register. The NVMe driver 1117 can notify the NVMe controller 1210 on the offload card 1200 to process IO requests that comply with the NVMe protocol by setting the hardware register. The accelerator 1220 transfers the IO request of the virtual machine 1110 to the offload card 1200 by DMA and sends it to the NVMe device 1300 through an interface such as a network card or PCI.

[0103] In the process of processing IO requests using the unload card namespace management system of the related technology, the hardware queues of the NVMe device 1300 are uniformly managed by one namespace, and different applications share hardware queue resources, which results in performance interference problems and poor fault isolation capabilities. For example, if application A is a low-latency IO model and application B is a high-throughput IO model, if they share a hardware queue, the IO request of application A will be slowed down by application B. Under certain circumstances, a single hardware queue failure will cause all the above application IOs to suspend, with a wide impact range and poor fault isolation capabilities.

[0104] In order to solve the above problems, the present disclosure proposes an offload card namespace management and input / output request processing system and method.

[0105] According to the technical solution provided by the embodiment of the present disclosure, through the unloading card namespace management system, including a host and an unloading card connected to the host, wherein multiple applications that issue input and output requests are running on the host, and the host sends a namespace creation request to the unloading card, the unloading card creates multiple namespaces corresponding to the multiple applications according to the namespace creation request, the unloading card allocates multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binds the allocated multiple hardware queues to the corresponding namespaces respectively, multiple namespaces can be created, and exclusive hardware queues are dynamically allocated to each namespace, hardware-level namespace resources are realized, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace. Moreover, compared with the solution of the related technology that cannot allocate independent hardware queues to each application, the solution of the embodiment of the present disclosure does not affect the applications of other hardware queues when a single hardware queue fails, and has a great improvement in performance isolation capability and fault isolation capability.

[0106] The following reference Figure 2 The implementation scenario of the offload card namespace management system according to the embodiment of the present disclosure is described. Figure 2 An exemplary schematic diagram is shown of an implementation scenario of an uninstall card namespace management system according to an embodiment of the present disclosure.

[0107] like Figure 2As shown, the offload card namespace management system according to the embodiment of the present disclosure is similar to the offload card namespace management system in the related art, and a hardware offloading architecture can be adopted, and the system may include a host 2100 and an offload card 2200. The host 2100 can access the NVMe device 2300 through the offload card 2200. The offload card 2200 and the NVMe device 2300 can be used together as a storage system. The offload card 2200 and the NVMe device 2300 can be connected via a PCIe interface. The specific PCIe interface specification can be obtained from the related art, and the present disclosure will not go into details about this.

[0108] like Figure 2 As shown, a virtual machine 2110 is running on the host 2100, and the virtual machine 2110 may include a user space (userspace) 2111 and a kernel space (kernel space) 2115. In one embodiment of the present disclosure, the virtual machine 2110 may be a Linux virtual machine. In one embodiment of the present disclosure, an application 2112 (or a thread of an application) is running in the user space 2111, and the application 2112 sends data through a central processing unit (CPU) core 2113. The kernel space 2115 of the virtual machine 2110 has a general block layer (Blk-mq in the Linux kernel) 2116. The general block layer 2116 provides a software queue for the upper layer application 2112, and each CPU core 2113 corresponds to a software queue 21161. The kernel space 2115 of the virtual machine 2110 also has a driver (e.g., an NVMe driver) 2117 for maintaining and managing the hardware queue 21171, and can send input and output (IO) requests to specific physical hardware (e.g., an offload card) for processing by, for example, setting hardware registers. The general block layer 2116 can maintain a mapping relationship from the software queue 21161 to the hardware queue 21171. The software queue 21161 can be used to forward data sent by the CPU core 2113. The hardware queue 21171 is used to forward data that needs to be sent to the NVMe device.

[0109] In the offload card namespace management system according to the embodiment of the present disclosure, since the general block layer 2116 needs to interact with the hardware through the NVMe driver 2117, the hardware needs to support multiple queues. The most ideal situation is that the hardware supports enough queues, and each software queue 11161 of the general block layer 2116 has a hardware queue 21171 associated with it. Figure 2There are 8 hardware queues 21171 in the general block layer 2116, and a total of 8 software queues 11161 are formed by the general block layer 2116. Therefore, the general block layer 2116 associates 1 software queue 21161 with 1 hardware queue 21171, that is, a one-to-one mapping relationship between software queue 11161 and hardware queue 11171 is established. The following describes a specific method of using an offload card to create multiple namespaces to allocate hardware queues in an embodiment of the present disclosure.

[0110] In the offload card namespace management system according to the embodiment of the present disclosure, the offload card 2200 includes an NVMe controller 2210 and an accelerator 2220. The offload card 2200 can simulate the standard NVMe controller 2210 through software and hardware technology, and is responsible for processing the configuration request of the NVMe driver 2117 in the kernel space 2115 in the virtual machine 2110, and completing the management tasks such as initialization, mounting / unmounting of the NVMe device 2300. The accelerator 2220 is, for example, an accelerator based on FPGA hardware or ASIC hardware, and is responsible for transferring the IO request in the virtual machine 2110 to the offload card 2200 in a DMA manner and sending it to the NVMe device 2300 through a connection method such as a network card or PCI.

[0111] In the offload card namespace management system according to the embodiment of the present disclosure, the NVMe device 2300 can be mounted inside the virtual machine 2110. An independent namespace can be created for each application 2112 inside the virtual machine 2110 through tools such as nvme-cli (a command line tool for Linux for monitoring and configuring NVMe devices). Specifically, the virtual machine 2110 can issue an NVMe Admin Command command to the NVMe driver 2117 through the ioctl system call, specifically, a namespace creation request (also referred to as a namespace creation request). After the NVMe driver 2117 receives the namespace creation request, it can send a namespace creation request to the offload card 2200. For example, the NVMe driver 2117 can send a namespace creation request to the offload card 2200 by setting a hardware register to send a configuration information request to the offload card 2200. After receiving the namespace creation request, the NVMe controller 2210 on the offload card 2200 creates corresponding namespaces NS1, NS2, NS3, NS4, NS5, NS6, NS7, and NS8 for each application 2112, and allocates hardware queues 21171 from the corresponding hardware part 2221 in the accelerator 2220, and binds them to the created namespaces NS1, NS2, NS3, NS4, NS5, NS6, NS7, and NS8 respectively. For example, in the offload card 2200, the NVMe controller 2210 allocates 8 hardware queues 21171 from the corresponding hardware part 2221 of the accelerator 2220 according to the namespace creation request, which are managed by eight namespaces NS1, NS2, NS3, NS4, NS5, NS6, NS7, and NS8 respectively. Other hardware parts 2222 than the hardware part 2221 in the accelerator 2220 are not allocated for management by the namespaces NS1, NS2, NS3, NS4, NS5, NS6, NS7, NS8.

[0112] from Figure 2It can be seen that an application 2112 corresponds to a software queue 21161, which corresponds to a hardware queue 21171, and a hardware queue 21171 is managed by a namespace bound to it. Therefore, in the offload card namespace management system according to the embodiment of the present disclosure, the hardware-level namespace resources can be realized by dynamically allocating exclusive hardware queues to each NVMe namespace, which greatly improves the performance isolation capability and reliability of the namespace. Compared with the offload card namespace management system of the related art, there is a great improvement in performance isolation capability and performance isolation capability. Moreover, with the development of hardware offload technology, existing offload cards can already support one thousand or thousands of hardware queues. The offload card namespace management system according to the embodiment of the present disclosure adopts a technical architecture that combines software and hardware, supports the device form of multiple namespaces, and allocates independent hardware queues to each namespace, avoiding the problem of mutual interference between IO requests of different applications, and improving the fault isolation capability.

[0113] In the case of processing IO requests using the offload card namespace management system according to an embodiment of the present disclosure, the application 2112 in the virtual machine 2110 can send IO requests to the general block layer 2116 in the kernel space 2115 through the system call interface. The general block layer 1116 in the kernel space 2115 receives the IO request and encapsulates it into a bio request (a request of the general block layer). The NVMe driver 2117 is responsible for converting the bio request into an IO request that complies with the NVMe protocol, and can send IO requests that comply with the NVMe protocol through the device hardware register. The NVMe driver 2117 can notify the NVMe controller 2210 on the offload card 2200 to process IO requests that comply with the NVMe protocol by setting the hardware register. The accelerator 2220 transfers the IO request of the virtual machine 2110 to the offload card 2200 through an independent hardware queue (i.e., a hardware queue corresponding to each namespace) 21171 through DMA and sends it to the NVMe device 2300 through an interface such as a network card or PCI.

[0114] In the offload card namespace management system according to the embodiment of the present disclosure, as in the offload card namespace management system of the related art, each CPU core 2113 corresponds to a software queue 21161, but in the general block layer 2116, unlike the offload card namespace management system of the related art, the driver 2117 manages and maintains not the preset hardware queues, but the hardware queues allocated from the accelerator 2220 after the NVMe controller 2210 of the offload card 2200 creates multiple namespaces with the same number of software queues according to the namespace creation request. The number of hardware queues 21171 can be the same as that of software queues 21161, and the two can correspond one to one, so that the hardware queues of the NVMe device 2300 are managed by independent namespaces, and different applications use their own hardware queue resources, so there is no performance interference, and the fault isolation capability is very good.

[0115] The following reference Figure 3 An offload card namespace management system according to an embodiment of the present disclosure is described. Figure 3 A structural block diagram of an offload card namespace management system 300 according to an embodiment of the present disclosure is shown.

[0116] Figure 3 The offload card namespace management system 300 shown includes a host 301 and an offload card 302. The host 301 runs multiple applications that issue input and output requests, and the host 301 sends a create namespace request to the offload card 302. The offload card 302 creates multiple namespaces corresponding to the multiple applications according to the create namespace request. The offload card 302 allocates multiple hardware queues corresponding to the created multiple namespaces according to the create namespace request and binds the allocated multiple hardware queues to the corresponding namespaces respectively.

[0117] According to the technical solution provided by the embodiment of the present disclosure, through the unloading card namespace management system, including a host and an unloading card connected to the host, wherein multiple applications that issue input and output requests are running on the host, and the host sends a namespace creation request to the unloading card, the unloading card creates multiple namespaces corresponding to the multiple applications according to the namespace creation request, the unloading card allocates multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binds the allocated multiple hardware queues to the corresponding namespaces respectively, multiple namespaces can be created, and exclusive hardware queues are dynamically allocated to each namespace, hardware-level namespace resources are realized, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace. Moreover, compared with the solution that all application processes share multiple hardware queues uniformly managed by one namespace, the solution of the embodiment of the present disclosure does not affect the applications of other hardware queues when a single hardware queue fails, and has a great improvement in performance isolation capability and fault isolation capability.

[0118] In one embodiment of the present disclosure, a virtual machine is running on the host 301, and the multiple applications are running in the virtual machine. The virtual machine includes: a driver, which is used to manage the multiple hardware queues, and the virtual machine sends the create namespace request to the offload card 302 through the driver.

[0119] According to the technical solution provided by the embodiment of the present disclosure, a virtual machine is run on the host, and the multiple applications are run in the virtual machine. The virtual machine includes: a driver, which is used to manage the multiple hardware queues. The virtual machine sends the namespace creation request to the offload card through the driver, and can create multiple namespaces. An exclusive hardware queue is dynamically allocated to each namespace, thereby realizing hardware-level namespace resources. The application can use its own corresponding hardware queue, which greatly improves the performance isolation capability and reliability of the namespace.

[0120] In one embodiment of the present disclosure, the offload card 302 includes a controller and a hardware accelerator, wherein the controller creates respective namespaces for the multiple applications according to the namespace creation request, and allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively.

[0121] According to the technical solution provided by the embodiment of the present disclosure, the offload card includes a controller and a hardware accelerator, wherein the controller creates respective namespaces for the multiple applications according to the namespace creation request, and allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces, respectively. Multiple namespaces can be created, and exclusive hardware queues can be dynamically allocated to each namespace, thereby realizing hardware-level namespace resources. Applications can use their own corresponding hardware queues, greatly improving the performance isolation capability and reliability of the namespace.

[0122] In one embodiment of the present disclosure, the host 301 includes a multi-core central processing unit, and the virtual machine includes a user space and a kernel space, wherein the multiple applications are running in the user space, and the applications are executed by corresponding cores, wherein the kernel space includes a common block layer and the driver, and the common block layer includes multiple software queues corresponding to the multiple cores, and a one-to-one correspondence is established from the multiple software queues to the multiple hardware queues.

[0123] According to the technical solution provided by the embodiment of the present disclosure, the host includes a multi-core central processing unit, and the virtual machine includes a user space and a kernel space, wherein the multiple applications are running in the user space, and the applications are executed by corresponding cores, wherein the kernel space includes a common block layer and the driver, and the common block layer includes a plurality of software queues corresponding to the plurality of cores, and a one-to-one correspondence is established from the plurality of software queues to the plurality of hardware queues, multiple namespaces can be created, and exclusive hardware queues can be dynamically allocated to each namespace, thereby realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace.

[0124] In one embodiment of the present disclosure, the driver is an NVMe driver, and the controller is an NVMe controller, wherein the host 301 is connected to the NVMe device 303 through the offload card 302, wherein the NVMe device 303 is mounted inside the virtual machine, wherein the application running in the user space issues an input / output request to the common block layer, wherein the input / output request is converted into an input / output request compliant with the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller, wherein the NVMe controller carries the input / output request compliant with the NVMe protocol to the offload card 302 through a hardware queue corresponding to the created namespace, and wherein the offload card 302 sends the input / output request compliant with the NVMe protocol to the NVMe device 303.

[0125] In one embodiment of the present disclosure, the input / output request is converted into an input / output request that complies with the NVMe protocol through processing by the common block layer and the NVMe driver, and a specific manner of sending the request to the NVMe controller may include: the common block layer converts the input / output request request issued by the application into an input / output request request that complies with the common block device protocol (for example, a bio structure), and the NVMe driver converts the input / output request request that complies with the common block device protocol into an input / output request that complies with the NVMe protocol, and issues the input / output request through the device hardware register.

[0126] According to the technical solution provided by the embodiment of the present disclosure, the driver is an NVMe driver, the controller is an NVMe controller, wherein the host is connected to the NVMe device through the offload card, wherein the NVMe device is mounted inside the virtual machine, wherein the application running in the user space sends an input and output request to the general block layer, wherein the input and output request is converted into an input and output request that complies with the NVMe protocol through the processing of the general block layer and the NVMe driver, and sent to the NVMe controller, wherein the NVMe controller carries the input and output request that complies with the NVMe protocol to the offload card through the hardware queue corresponding to the created namespace, wherein the offload card sends the input and output request that complies with the NVMe protocol to the NVMe device, multiple namespaces can be created, and exclusive hardware queues are dynamically allocated to each namespace, hardware-level namespace resources are realized, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace. Moreover, the existing NVMe namespace capabilities are strengthened and expanded, and combined with the technical architecture of hardware and software integration, the performance isolation capability and fault isolation capability are greatly improved, and the software ecology of the upper-layer application is fully compatible.

[0127] Those skilled in the art will understand that referring to Figure 3 The technical solutions described can be compared with Figure 1 and Figure 2 The implementation scenarios described are combined to provide a reference Figure 1 and Figure 2 The technical effects achieved by the described implementation scenarios. For details, please refer to the above Figure 1 and Figure 2 The specific content of the description will not be repeated here.

[0128] The following reference Figure 4 A method for managing an uninstall card namespace according to an embodiment of the present disclosure is described.

[0129] Figure 4 A flowchart of an uninstall card namespace management method according to an embodiment of the present disclosure is shown.

[0130] Figure 4 The offload card namespace management method according to the embodiment of the present disclosure is shown to be run on an offload card namespace management system, wherein the offload card namespace management system includes a host and an offload card connected to the host. Figure 3 The uninstall card namespace management system.

[0131] like Figure 4 As shown, the uninstall card namespace management method according to the embodiment of the present disclosure includes steps S401, S402, and S403.

[0132] In step S401, based on a plurality of applications running on the host and issuing input and output requests, the host sends a create namespace request to the offload card.

[0133] In step S402, the offload card creates a plurality of corresponding namespaces for the plurality of applications according to the namespace creation request.

[0134] In step S403, the offload card allocates a plurality of hardware queues corresponding to the created plurality of namespaces according to the namespace creation request and binds the allocated plurality of hardware queues to the corresponding namespaces respectively.

[0135] In one embodiment of the present disclosure, a virtual machine is running on the host, the multiple applications are running in the virtual machine, and the virtual machine includes a driver for managing the multiple hardware queues, wherein the host sends a create namespace request to the offload card, including: the virtual machine sends the create namespace request to the offload card through the driver.

[0136] According to the technical solution provided by the embodiment of the present disclosure, a virtual machine is run on the host, and the multiple applications are run in the virtual machine, and the virtual machine includes a driver for managing the multiple hardware queues, wherein the host sends a namespace creation request to the offload card, including: the virtual machine sends the namespace creation request to the offload card through the driver, multiple namespaces can be created, and exclusive hardware queues are dynamically allocated to each namespace, thereby realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace.

[0137] In one embodiment of the present disclosure, the offload card includes a controller and a hardware accelerator, wherein step S402 includes: the controller creates respective namespaces for the multiple applications according to the namespace creation request, wherein the offload card allocates multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binds the allocated multiple hardware queues to the corresponding namespaces respectively, including: the controller allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively.

[0138] According to the technical solution provided by the embodiment of the present disclosure, the offload card includes a controller and a hardware accelerator, wherein the offload card creates corresponding multiple namespaces for the multiple applications according to the namespace creation request, including: the controller creates respective namespaces for the multiple applications according to the namespace creation request, wherein the offload card allocates multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binds the allocated multiple hardware queues to the corresponding namespaces respectively, including: the controller allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively, multiple namespaces can be created, and exclusive hardware queues can be dynamically allocated to each namespace, thereby realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace.

[0139] In one embodiment of the present disclosure, the host includes a multi-core central processing unit, and the virtual machine includes a user space and a kernel space, wherein the multiple applications are running in the user space and the applications are executed by corresponding cores, wherein the kernel space includes a common block layer and the driver, the common block layer includes a plurality of software queues corresponding to the plurality of cores, and a one-to-one correspondence is established from the plurality of software queues to the plurality of hardware queues.

[0140] According to the technical solution provided by the embodiment of the present disclosure, the host includes a multi-core central processing unit, and the virtual machine includes a user space and a kernel space, wherein the multiple applications are running in the user space, and the applications are executed by corresponding cores, wherein the kernel space includes a common block layer and the driver, and the common block layer includes a plurality of software queues corresponding to the plurality of cores, and a one-to-one correspondence is established from the plurality of software queues to the plurality of hardware queues, multiple namespaces can be created, and exclusive hardware queues can be dynamically allocated to each namespace, thereby realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues, which greatly improves the performance isolation capability and reliability of the namespace.

[0141] In one embodiment of the present disclosure, the driver is an NVMe driver, the controller is an NVMe controller, wherein the host is connected to the NVMe device via the offload card, wherein the method further comprises: mounting the NVMe device inside the virtual machine;

[0142] The application running in the user space sends an input / output request to the common block layer; the input / output request is converted into an input / output request that complies with the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller; the NVMe controller carries the input / output request that complies with the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace, and the offload card sends the input / output request that complies with the NVMe protocol to the NVMe device.

[0143] According to the technical solution provided by the embodiment of the present disclosure, the driver is an NVMe driver, the controller is an NVMe controller, wherein the host is connected to the NVMe device through the offload card, wherein the method further includes: mounting the NVMe device inside the virtual machine; the application running in the user space sends an input and output request to the general block layer; the input and output request is converted into an input and output request that complies with the NVMe protocol through the processing of the general block layer and the NVMe driver, and sent to the NVMe controller; the NVMe controller transports the input and output request that complies with the NVMe protocol to the offload card through the hardware queue corresponding to the created namespace, and the offload card sends the input and output request that complies with the NVMe protocol to the NVMe device, multiple namespaces can be created, and a dedicated hardware queue is dynamically allocated to each namespace, realizing hardware-level namespace resources, and the application can use its own corresponding hardware queue, which greatly improves the performance isolation capability and reliability of the namespace. Moreover, the existing NVMe namespace capabilities are strengthened and expanded, and combined with the technical architecture of software and hardware integration, the performance isolation capability and fault isolation capability are greatly improved, and the software ecology of the upper-layer application is fully compatible.

[0144] Those skilled in the art will understand that referring to Figure 4 The technical solutions described can be compared with Figures 1 to 3 The implementation scenarios described are combined to provide a reference Figures 1 to 3 The technical effects achieved by the described implementation scenarios. For details, please refer to the above Figures 1 to 3 The specific content of the description will not be repeated here.

[0145] The following reference Figure 5 An input / output request processing system according to an embodiment of the present disclosure is described.

[0146] Figure 5 The structure block diagram of the input / output request processing system 500 according to the embodiment of the present disclosure is shown. The input / output request processing system 500 is a system that utilizes Figure 3 The offload card namespace management system 300 shown is implemented.

[0147] like Figure 5 As shown, the input / output request processing system 500 includes a host 501, an offload card 502, and an NVMe device 503 connected to the host 501 via the offload card 502.

[0148] A virtual machine is running on the host 501, the host 501 includes a multi-core central processing unit, the virtual machine includes a user space and a kernel space, wherein multiple applications that issue input and output requests are running in the user space, and the applications are executed by corresponding cores, wherein the kernel space includes a common block layer and an NVMe driver, the common block layer includes multiple software queues corresponding to the multiple cores, wherein the virtual machine sends a namespace creation request to the offload card 502 through the NVMe driver.

[0149] The offload card 502 includes an NVMe controller and a hardware accelerator, wherein the NVMe controller creates respective namespaces for the multiple applications according to the namespace creation request, and allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively.

[0150] The NVMe driver is used to manage the multiple hardware queues, and the general block layer establishes a one-to-one correspondence between the multiple software queues and the multiple hardware queues.

[0151] The application running in the user space sends an input / output request to the general block layer.

[0152] The input / output request is converted into an input / output request that complies with the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller.

[0153] The NVMe controller transfers the input and output requests that comply with the NVMe protocol to the offload card 502 through a hardware queue corresponding to the created namespace.

[0154] The offload card 502 sends an input / output request that complies with the NVMe protocol to the NVMe device 503 .

[0155] According to the technical solution provided by the embodiment of the present disclosure, by using the aforementioned unloading card namespace management solution to process input and output requests, multiple namespaces can be created, and a dedicated hardware queue is dynamically allocated to each namespace, realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues to avoid interference between input and output requests of different applications, and improve fault isolation capabilities. The performance isolation capability and reliability of the namespace are greatly improved. In addition, the existing NVMe namespace capabilities are strengthened and expanded, and combined with the technical architecture of hardware and software integration, the performance isolation capability and fault isolation capability are greatly improved, and the software ecology of the upper-level applications is fully compatible.

[0156] The following reference Figure 6 The present invention describes an input / output request processing method according to an embodiment of the present disclosure.

[0157] Figure 6 A flowchart of an input / output request processing method according to an embodiment of the present disclosure is shown. Figure 6 The input and output request processing method shown is to use Figure 5 The input and output request processing system 500 shown is implemented. Figure 5 The input / output request processing system 500 shown is a system that utilizes Figure 3 The offload card namespace management system 300 shown is implemented.

[0158] An input / output request processing system running an input / output request processing method includes a host, an offload card, and an NVMe device connected to the host via the offload card.

[0159] A virtual machine is running on the host, the host includes a multi-core central processing unit, the virtual machine includes a user space and a kernel space, a plurality of applications issuing input and output requests are running in the user space, the applications are executed by corresponding cores, the kernel space includes a common block layer and an NVMe driver, the common block layer includes a plurality of software queues corresponding to the plurality of cores, the virtual machine sends a namespace creation request to the offload card through the NVMe driver,

[0160] The offload card includes an NVMe controller and a hardware accelerator, wherein the NVMe controller creates respective namespaces for the multiple applications according to the namespace creation request, and allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively.

[0161] The NVMe driver is used to manage the multiple hardware queues, and the general block layer establishes a one-to-one correspondence between the multiple software queues and the multiple hardware queues.

[0162] The method includes steps S601, S602, S603 and S604.

[0163] In step S601, the application running in the user space sends an input / output request to the general block layer;

[0164] In step S602, the input / output request is converted into an input / output request that complies with the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller;

[0165] In step S603, the NVMe controller transfers the input and output request conforming to the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace;

[0166] In step S604, the offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

[0167] According to the technical solution provided by the embodiment of the present disclosure, by using the aforementioned unloading card namespace management solution to process input and output requests, multiple namespaces can be created, and a dedicated hardware queue is dynamically allocated to each namespace, realizing hardware-level namespace resources, and applications can use their own corresponding hardware queues to avoid interference between input and output requests of different applications, and improve fault isolation capabilities. The performance isolation capability and reliability of the namespace are greatly improved. In addition, the existing NVMe namespace capabilities are strengthened and expanded, and combined with the technical architecture of hardware and software integration, the performance isolation capability and fault isolation capability are greatly improved, and the software ecology of the upper-level applications is fully compatible.

[0168] Figure 7 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0169] The present disclosure also provides an electronic device, such as Figure 7 As shown, it includes at least one processor 701; and a memory 702 that is communicatively connected to the at least one processor 701; wherein the memory 702 stores instructions that can be executed by the at least one processor 701, and the instructions run in the offload card namespace management system, and the offload card namespace management system includes a host and an offload card connected to the host, and the instructions are executed by the at least one processor 701 to implement the following steps:

[0170] Based on a plurality of applications running on the host issuing input and output requests, the host sends a create namespace request to the offload card;

[0171] The offload card creates a plurality of corresponding namespaces for the plurality of applications according to the namespace creation request;

[0172] The offload card allocates a plurality of hardware queues corresponding to the created plurality of namespaces according to the namespace creation request and binds the allocated plurality of hardware queues to the corresponding namespaces respectively.

[0173] In one embodiment of the present disclosure, a virtual machine is running on the host, the multiple applications are running in the virtual machine, the virtual machine includes a driver for managing the multiple hardware queues, wherein the host sends a create namespace request to the offload card, including:

[0174] The virtual machine sends the namespace creation request to the offload card through the driver.

[0175] In one embodiment of the present disclosure, the offload card includes a controller and a hardware accelerator, wherein the offload card creates a plurality of corresponding namespaces for the plurality of applications according to the namespace creation request, including:

[0176] The controller creates respective namespaces for the multiple applications according to the namespace creation request,

[0177] The offload card allocates a plurality of hardware queues corresponding to the created plurality of namespaces according to the namespace creation request and binds the allocated plurality of hardware queues to the corresponding namespaces respectively, including:

[0178] The controller allocates a plurality of hardware queues corresponding to the created plurality of namespaces from the hardware accelerator and binds the allocated plurality of hardware queues to the corresponding namespaces respectively.

[0179] In one embodiment of the present disclosure, the host includes a multi-core central processing unit, and the virtual machine includes a user space and a kernel space.

[0180] The plurality of applications are run in the user space, and the applications are executed by corresponding cores.

[0181] The kernel space includes a common block layer and the driver, the common block layer includes a plurality of software queues corresponding to the plurality of cores, and a one-to-one correspondence is established from the plurality of software queues to the plurality of hardware queues.

[0182] In one embodiment of the present disclosure, the drive is an NVMe drive, the controller is an NVMe controller,

[0183] Wherein, the host is connected to the NVMe device through the offload card,

[0184] Wherein, the method further comprises:

[0185] Mounting the NVMe device into the virtual machine;

[0186] The application running in the user space sends an input and output request to the common block layer;

[0187] The input / output request is converted into an input / output request conforming to the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller;

[0188] The NVMe controller transfers the input and output requests that comply with the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace.

[0189] The offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

[0190] The present disclosure also provides an electronic device, such as Figure 7 As shown, it includes at least one processor 701; and a memory 702 that is communicatively connected to the at least one processor 701; wherein the memory 702 stores instructions that can be executed by the at least one processor 701, and the instructions run on an input / output request processing system, wherein the input / output request processing system includes a host, an offload card, and an NVMe device connected to the host through the offload card,

[0191] A virtual machine is running on the host, the host includes a multi-core central processing unit, the virtual machine includes a user space and a kernel space, a plurality of applications issuing input and output requests are running in the user space, the applications are executed by corresponding cores, the kernel space includes a common block layer and an NVMe driver, the common block layer includes a plurality of software queues corresponding to the plurality of cores, the virtual machine sends a namespace creation request to the offload card through the NVMe driver,

[0192] The offload card includes an NVMe controller and a hardware accelerator, wherein the NVMe controller creates respective namespaces for the multiple applications according to the namespace creation request, and allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively.

[0193] The NVMe driver is used to manage the multiple hardware queues, and the general block layer establishes a one-to-one correspondence between the multiple software queues and the multiple hardware queues.

[0194] Wherein, the method comprises:

[0195] The application running in the user space sends an input and output request to the common block layer;

[0196] The input / output request is converted into an input / output request conforming to the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller;

[0197] The NVMe controller carries the input and output requests conforming to the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace;

[0198] The offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

[0199] Figure 8 Schematic diagram of the structure of a computer system suitable for implementing the method according to each embodiment of the present disclosure. Figure 8 As shown, the computer system 800 includes a processing unit 801, which can perform various processes in the embodiments shown in the above figures according to the program stored in the read-only memory (ROM) 802 or the program loaded from the storage part 808 to the random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the system 800 are also stored. The CPU 801, the ROM 802, and the RAM 803 are connected to each other through a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0200] The following components are connected to the I / O interface 805: an input section 806 including a keyboard, a mouse, etc.; an output section 807 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN card, a modem, etc. The communication section 809 performs communication processing via a network such as the Internet. The drive 810 is also connected to the I / O interface 805 as needed. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 810 as needed, so that the computer program read therefrom is installed into the storage section 808 as needed. Among them, the processing unit 801 can be implemented as a processing unit such as a CPU, a GPU, a TPU, an FPGA, an NPU, etc.

[0201] In particular, according to an embodiment of the present disclosure, the method described above with reference to the accompanying drawings can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program tangibly contained on a readable medium thereof, and the computer program includes a program code for executing the method in the accompanying drawings. In such an embodiment, the computer program can be downloaded and installed from a network through a communication portion 809, and / or installed from a removable medium 811. For example, an embodiment of the present disclosure includes a readable storage medium on which computer instructions are stored, and when the computer instructions are executed by a processor, the program code for executing the method in the accompanying drawings is implemented.

[0202] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the road map or block diagram can represent a part of a module, program segment or code, and the part of the module, program segment or code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a different order from the order marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0203] The units or modules involved in the embodiments described in the present disclosure may be implemented by software or hardware. The units or modules described may also be set in a processor, and the names of these units or modules do not constitute limitations on the units or modules themselves in some cases.

[0204] As another aspect, the present disclosure further provides a computer-readable storage medium, which may be a computer-readable storage medium included in the node described in the above embodiment; or a computer-readable storage medium that exists independently and is not installed in a device. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the method described in the present disclosure.

[0205] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. An offload card namespace management system, comprising a host and an offload card connected to the host, wherein the host comprises a multi-core central processing unit, and the host is connected to an NVMe device through the offload card; wherein: A virtual machine is running on the host, the virtual machine includes a user space and a kernel space, a plurality of applications that issue input and output requests are running in the user space, the applications are executed by corresponding cores, the kernel space includes a common block layer and a driver, the common block layer includes a plurality of software queues corresponding to a plurality of cores and a one-to-one correspondence is established from the plurality of software queues to a plurality of hardware queues, the driver is used to manage a plurality of hardware queues, and the hardware queue is used to forward data to be sent to the NVMe device; the virtual machine sends a namespace creation request to the offload card through the driver; The offload card includes a controller and a hardware accelerator, wherein the controller is used to create respective namespaces for the multiple applications according to the namespace creation request, and allocate multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and bind the allocated multiple hardware queues to the corresponding namespaces respectively.

2. The system according to claim 1, wherein: The drive is an NVMe drive, the controller is an NVMe controller, The NVMe device is mounted inside the virtual machine. The application running in the user space sends an input / output request to the general block layer. The input / output request is converted into an input / output request that complies with the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller. The NVMe controller transfers the input and output requests that comply with the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace. The offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

3. A method for managing an offload card namespace, the method running on an offload card namespace management system, the offload card namespace management system comprising a host and an offload card connected to the host, the host comprising a multi-core central processing unit, the host being connected to an NVMe device via the offload card; a virtual machine running on the host, the virtual machine comprising a user space and a kernel space, a plurality of applications issuing input and output requests running in the user space, the applications being executed by corresponding cores, the kernel space comprising a general block layer and a driver, the general block layer comprising a plurality of software queues corresponding to a plurality of cores and establishing a one-to-one correspondence from the plurality of software queues to a plurality of hardware queues, the driver being used to manage the plurality of hardware queues, the hardware queue being used to forward data to be sent to the NVMe device; The offload card includes a controller and a hardware accelerator, wherein: The method comprises: Based on the multiple applications running in the virtual machine, the virtual machine sends a namespace creation request to the offload card through the driver; The controller creates respective namespaces for the multiple applications according to the namespace creation request; The controller allocates a plurality of hardware queues corresponding to the created plurality of namespaces from the hardware accelerator and binds the allocated plurality of hardware queues to the corresponding namespaces respectively.

4. The method according to claim 3, wherein: The drive is an NVMe drive, the controller is an NVMe controller, Wherein, the method further comprises: Mounting the NVMe device into the virtual machine; The application running in the user space sends an input and output request to the common block layer; The input / output request is converted into an input / output request conforming to the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller; The NVMe controller transfers the input and output requests that comply with the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace. The offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

5. An input / output request processing system, comprising a host, an offload card, and an NVMe device connected to the host via the offload card, in, A virtual machine is running on the host, the host includes a multi-core central processing unit, the virtual machine includes a user space and a kernel space, wherein a plurality of applications issuing input and output requests are running in the user space, the applications are executed by corresponding cores, wherein the kernel space includes a common block layer and an NVMe driver, the common block layer includes a plurality of software queues corresponding to the plurality of cores, wherein the virtual machine sends a namespace creation request to the offload card through the NVMe driver, The offload card includes an NVMe controller and a hardware accelerator, wherein the NVMe controller creates respective namespaces for the multiple applications according to the namespace creation request, and allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively. The NVMe driver is used to manage the multiple hardware queues, the general block layer establishes a one-to-one correspondence from the multiple software queues to the multiple hardware queues, and the hardware queues are used to forward data to be sent to the NVMe device; The application running in the user space sends an input / output request to the general block layer. The input / output request is converted into an input / output request that complies with the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller. The NVMe controller transfers the input and output requests that comply with the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace. The offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

6. An input / output request processing method, the method running in an input / output request processing system, the input / output request processing system comprising a host, an offload card, and an NVMe device connected to the host via the offload card, in, A virtual machine is running on the host, the host includes a multi-core central processing unit, the virtual machine includes a user space and a kernel space, wherein a plurality of applications issuing input and output requests are running in the user space, the applications are executed by corresponding cores, wherein the kernel space includes a common block layer and an NVMe driver, the common block layer includes a plurality of software queues corresponding to the plurality of cores, wherein the virtual machine sends a namespace creation request to the offload card through the NVMe driver, The offload card includes an NVMe controller and a hardware accelerator, wherein the NVMe controller creates respective namespaces for the multiple applications according to the namespace creation request, and allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues to the corresponding namespaces respectively. The NVMe driver is used to manage the multiple hardware queues, the general block layer establishes a one-to-one correspondence from the multiple software queues to the multiple hardware queues, and the hardware queues are used to forward data to be sent to the NVMe device; Wherein, the method comprises: The application running in the user space sends an input and output request to the common block layer; The input / output request is converted into an input / output request conforming to the NVMe protocol through processing by the common block layer and the NVMe driver, and sent to the NVMe controller; The NVMe controller carries the input and output requests conforming to the NVMe protocol to the offload card through a hardware queue corresponding to the created namespace; The offload card sends an input / output request that complies with the NVMe protocol to the NVMe device.

7. An electronic device comprising a memory and a processor; wherein: The memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method steps described in any one of claims 3-4 and 6.

8. A readable storage medium having computer instructions stored thereon, wherein the computer instructions, when executed by a processor, implement the method steps described in any one of claims 3-4 and 6.

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