A method for identifying hot spots in photolithography active areas and transistors therein

Abstract

The present invention provides a method for identifying hot spots in a photolithography active area, comprising: obtaining layout information; defining an initial edge; identifying a rectangular area remaining in an active area pattern after removing an area overlapping with a gate pattern as a first rectangle, and identifying the first rectangle in contact with the first short side as an L-shaped irregular active area, i.e., a hot spot in the photolithography active area. The present invention also provides a method for identifying transistors in a photolithography active area. The hot spots in the photolithography active area identified by the method of the present invention can identify and obtain attribute information of transistors in the photolithography active area. The process is simple, the result is intuitive, and it is conducive to the improvement of production technology and efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor design and production, and in particular to a method for identifying irregular active areas in a layout and transistors therein. Background Art

[0002] As the technology nodes of integrated circuit production process continue to advance, the design of integrated circuits has become more and more complex. The wavelength of the mainstream photolithography process used in integrated circuit production today has been maintained at 193nm. When the wavelength of the exposure machine is not updated, the size of the exposure pattern continues to shrink, which will produce many photolithography patterns that meet the design rules but have poor actual process windows. These are called photolithography defect hotspot patterns, which generally refer to patterns or combinations of patterns in the layout that have certain geometric features and feature sizes within a certain range that are prone to photolithography defects.

[0003] In the FinFET process, irregular active areas are also a type of lithography defect hotspot pattern. Figure 1 The L-shaped irregular active area shown is formed by deleting the fin layer. However, due to the optical proximity effect in the photolithography process, the ideal rectangle shown in Figure 2(a) will be deformed at the corners of the deleted layer, such as the potential victim in Figure 2(b). As a result, the actual deleted active area will have fin extensions at the corners of the deleted layer. The extended fins will have the risk of short-circuiting with the nearby metal layer, thereby affecting the source / drain terminals of the corners and the adjacent devices below the corners.

[0004] In actual manufacturing production, due to the differences in specific processes or processing methods of different manufacturers, the lithography defect hotspot patterns may not actually cause lithography defects, that is, for different manufacturers, the lithography defect hotspot patterns that actually cause lithography defects may be different. The processing method for the lithography defect hotspot pattern includes optimizing the original layout design before tape-out and performing special process processing on the detected lithography process hotspots.

[0005] Therefore, if the hot spots of the photolithography active area can be quickly and accurately located in a large amount of layout data in advance, and the relevant environmental properties of transistors that are completely in these photolithography active areas or partially in contact with them can be determined to quantify the risks, it will have great practical significance for guiding manufacturers in design and production. In the prior art, there is no particularly effective method specifically for identifying hot spots of the photolithography active area or transistors in these photolithography active areas, which is not conducive to the further improvement of the photolithography process and design. Summary of the invention

[0006] The present invention is based on all or part of the above-mentioned problems of the prior art, and aims to provide a method for identifying hot spots in a photolithography active area and transistors in the photolithography active area, which is used to search and locate the photolithography active area and the transistors therein in a large amount of layout data. All explanations or definitions of the terms and related technical principles involved in the following description of this application are only exemplary and not restrictive.

[0007] On one hand, the present invention provides a method for identifying hot spots in photolithography active areas, comprising: step S1. acquiring layout information, including active area graphics and gate graphics; step S2. the contour edges connected in all or part of the active area graphics are perpendicular to each other, forming a first corner with an internal angle of 90° and a second corner with an internal angle of 270°, and defining the edge between the vertex of the first corner and the vertex of the second corner as the initial edge; step S3. identifying a rectangular area in the active area graphics that overlaps with the gate graphics as a transistor graphics, identifying the contour edge in the transistor graphics that overlaps with the initial edge as the first long edge, and the portion of the first long edge that does not overlap with the initial edge as the first short edge; step S4. identifying the rectangular area remaining in the active area graphics after removing the overlapping area with the gate graphics as the first rectangle, identifying the first rectangle in contact with the first short edge as an L-shaped irregular active area, which is used to locate the hot spot in the photolithography active area.

[0008] In some cases, the layout information obtained in step S1 includes an active area pattern, a gate pattern and M0; the M0 is a connection layer for connecting the active area. M0 can be metal or non-metal, and is not limited. Since each layout layer has its own characteristics and the role it plays in the device, the patterns in each layout layer will be different. In a specific embodiment, the M0 is preferably a metal layer.

[0009] Also for the convenience of description, in this application, the gate extension direction is taken as the vertical direction, and the direction perpendicular to the gate extension direction is taken as the horizontal direction; after the step S1 obtains the layout information, for the vertical contour edge of the active area graphic in the overlapping area between the active area graphic and the gate graphic, it is determined whether the vertical contour edge overlaps with the vertical contour edge of the gate graphic: when the vertical contour edge overlaps with the vertical contour edge of the gate graphic, step S2 is directly performed; when the vertical contour edge does not overlap with the vertical contour edge of the gate graphic, layout processing is performed: the vertical contour edge is moved along the horizontal direction toward the outside of the active area graphic until it overlaps with the vertical contour edge of the gate graphic; then step S2 is performed.

[0010] In step S4, information of the L-shaped irregular active region is also recorded, including the length of the first short side in contact with the L-shaped irregular active region, the length of the first long side, and the ratio of the length of the first short side to the length of the first long side.

[0011] Included in the step S4 or after the step S4, a region formed by two adjacent opposite L-shaped irregular active regions is identified as a U-shaped irregular active region for locating a hot spot of a photolithography active region.

[0012] The specific process of identifying the U-shaped irregular active area includes: connecting the first corner vertices on two adjacent initial edges in the same active area, connecting the second corner vertices on two adjacent initial edges, then the line connecting the two vertices and the two adjacent initial edges form a polygonal area, and the polygons in the enclosed polygonal area that do not overlap with the active area graphic are identified as U-shaped irregular active areas.

[0013] Furthermore, the specific process of identifying the U-shaped irregular active area also includes: recording information of the U-shaped irregular active area, including: the lengths of two sides overlapping with the initial sides are recorded as Ushape_h1 and Ushape_h2; the length of the side in contact with the active area pattern in the horizontal direction is recorded as Ushape_innerspace.

[0014] Another aspect of the present invention provides a method for identifying transistors in a photolithography active area, comprising: using the above method for identifying hot spots in photolithography active areas to identify L-shaped irregular active areas; identifying transistors in contact with the L-shaped irregular active areas.

[0015] Among the transistors identified as being in contact with the L-shaped irregular active area, the transistor graphic containing the initial edge is recorded as the first transistor, and the transistor graphic not containing the initial edge is recorded as the second transistor; the first transistor has only one side in contact with the L-shaped irregular active area, and the information of the L-shaped irregular active area in contact with it is recorded as the information of the first transistor, including: the length of the first short side in contact with the L-shaped irregular active area, the length of the first long side, and the ratio of the length of the first short side to the length of the first long side, which is used to characterize the environmental properties of the first transistor; the second transistor has at least one side in contact with the L-shaped irregular active area, and the information of the L-shaped irregular active area in contact with it is recorded as the information of the second transistor, including the length of the first short side in contact with the L-shaped irregular active area, the length of the first long side, and the ratio of the length of the first short side to the length of the first long side; which is used to characterize the environmental properties of the second transistor.

[0016] In a preferred embodiment, it also includes identifying the positional relationship between the first transistor and / or the second transistor and the L-shaped irregular active area in contact with them (for example, the left side of the transistor contacts the L-shaped irregular active area, and the right side of the transistor contacts the L-shaped irregular active area).

[0017] In a specific implementation, an L-shaped irregular active area and a U-shaped irregular active area are identified; among the identified first transistors and second transistors, a transistor in the U-shaped irregular active area or in contact with the U-shaped irregular active area is identified.

[0018] In the information of the first transistor and the second transistor, the information of the U-shaped irregular active area is added, including: for the first transistor or the second transistor in the U-shaped irregular active area or in contact with the U-shaped irregular active area, the information of the U-shaped irregular active area, including: Ushape_h1, Ushape_h2 and Ushape_innerspace, is recorded in the information of the transistor; for the first transistor or the second transistor not in contact with the U-shaped irregular active area, the value of the relevant information of the U-shaped irregular active area of ​​the transistor is recorded as 0, that is, the values ​​of Ushape_h1, Ushape_h2 and Ushape_innerspace are all 0. The information of the U-shaped irregular active area is used to quantify the risk degree of the transistor formed by the active area lithography.

[0019] The present invention has the following beneficial effects: (1) According to a method for identifying hot spots in photolithography active areas involved in the present invention, irregular active areas can be accurately and intuitively identified through the initial edge, the first long edge and the first short edge, so as to conveniently and quickly identify irregular active areas with risks of photolithography defects in the published drawings; by recording various attribute data of irregular active areas, the number and distribution of such risks in the layout can be counted, providing favorable guidance for the location and analysis of layout hot spots and the design of test structures. (2) In addition, according to a method for identifying transistors in photolithography active areas according to the present invention, the attribute information of transistors in irregular active areas can be identified and obtained, and then the risk level of transistors formed by active area photolithography can be effectively evaluated, which is beneficial to the improvement of production processes, the improvement of efficiency and the saving of manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the influence of the optical proximity effect on the active area during the photolithography process in the prior art.

[0021] FIG2( a ) is a schematic diagram of an ideal active area in a layout.

[0022] FIG2( b ) is a schematic diagram of the actual active area in the layout.

[0023] Figure 3 It is a schematic diagram of the method process for identifying hot spots in the photolithography active area in the first embodiment of the present invention.

[0024] Figure 4 It is a schematic diagram of the first corner, the second corner and the initial edge in the first embodiment of the present invention.

[0025] Figure 5 It is a schematic diagram of the first long side and the first short side in the first embodiment of the present invention.

[0026] Figure 6 It is a schematic diagram of the method process for identifying hot spots in the photolithography active area in the second embodiment of the present invention.

[0027] Figure 7 It is a schematic diagram of a U-shaped irregular active area in the third embodiment of the present invention.

[0028] Figure 8 Schematic diagram of the first transistor and the second transistor in the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0029] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings. In the following embodiments, the operation of the embodiments is described in a specific order, and the description of these orders is for better understanding of the details in the embodiments to fully understand the present invention, but the description of these orders does not necessarily correspond to a method for identifying a hot spot in a photolithography active area and a transistor therein of the present invention, nor can it be used to limit the scope of the present invention.

[0030] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the operation process that may be implemented according to the method of the embodiment of the present invention. It should also be noted that in some alternative implementations, the functions marked in the blocks may also occur in a different order than the order marked in the accompanying drawings. For example, two blocks shown in succession may actually be executed substantially in parallel, and they may sometimes be executed alternately, depending on the purpose to be achieved by the steps involved.

[0031] Embodiment 1

[0032] like Figure 3 As shown and combined with reference Figure 4 , Figure 5, the method for identifying hot spots in photolithography active areas in the first embodiment of the present invention includes: step S1. obtaining layout information, including active area graphics, gate graphics and M0; the M0 is used to connect the active area. Since each layout layer has its own characteristics and the role it plays in the device, the graphics in each layout layer will be different. In this embodiment, the M0 is preferably a metal layer, and in this embodiment it is the metal layer M0, but in some embodiments M0 is not a metal, which is not limited here. Step S2. The contour edges connected in all or part of the active area graphics are perpendicular to each other, forming a first corner with an internal angle of 90° and a second corner with an internal angle of 270°, and the edge between the vertex of the first corner and the vertex of the second corner is defined as the initial edge. For the convenience of description in this embodiment, the first corner and the second corner are defined as a corner group M; the edge between the two vertices in the corner group M is the initial edge, recorded as edge_ori; step S3. The rectangular area overlapping with the gate pattern in the active area pattern is identified as a transistor pattern, and the contour edge of the transistor pattern that overlaps with the initial edge edge_ori is identified as the first long side, recorded as edge_long; the part of the first long side that does not overlap with the initial side is the first short side, that is, the remaining line segment after edge_long is subtracted from edge_ori is recorded as edge_short; step S4. The rectangular area remaining after removing the gate from the active area pattern is identified as the first rectangle, recorded as S / Darea in this embodiment; S / Darea in contact with edge_short is identified as Lshape_S / Darea, that is, an L-shaped irregular active area, which is used to locate the hotspot of the lithography active area.

[0033] Embodiment 2

[0034] For the convenience of description, in this embodiment, the gate extension direction is taken as the vertical direction, and the direction perpendicular to the gate extension direction is taken as the horizontal direction. Figure 6 As shown, the main difference between Example 2 and Example 1 is that in step S1, after obtaining the layout information, it is also determined whether the vertical contour edge of the active area graphic in the overlapping area of ​​the active area graphic and the gate graphic overlaps with the vertical contour edge of the gate graphic, and subsequent processing is determined based on the judgment result.

[0035] In the layout of this embodiment, if the vertical contour edge overlaps with the vertical contour edge of the gate pattern, step S2 is directly performed; however, when the vertical contour edge does not overlap with the vertical contour edge of the gate pattern, layout processing is performed: the vertical contour edge is moved horizontally toward the outside of the active area pattern until it overlaps with the vertical contour edge of the gate pattern; then step S2 is performed.

[0036] This embodiment is different from the first embodiment in that step S4 also records information of the L-shaped irregular active area Lshape_S / Darea, including the length Lshape_short of the edge_short in contact with it, the length Lshape_long of the edge_long, and the value Lshape_ratio of Lshape_short divided by Lshape_long.

[0037] Embodiment 3

[0038] The difference between the third embodiment of the present invention and the first embodiment is that the step S4 or thereafter identifies the non-active area formed by two adjacent opposite L-shaped irregular active areas as a U-shaped irregular active area, which is recorded as Ushape_space and is used to locate the hot spot of the photolithography active area. Figure 7 shown.

[0039] The specific process of identifying the U-shaped irregular active area includes: connecting the two first corner vertices in the adjacent corner group, connecting the two second corner vertices, and identifying the polygon that does not overlap with the active area pattern in the area surrounded by the two opposite initial edges edge_ori as Ushape_space. In this embodiment, the information of Ushape_space is also recorded, including: the lengths of the two sides overlapping with edge_ori are recorded as Ushape_h1 and Ushape_h2; the length of the side contacting the active area pattern in the horizontal direction is recorded as Ushape_innerspace.

[0040] Embodiment 4

[0041] In this embodiment, based on the third embodiment, the transistors in the L-shaped irregular active region are identified, such as Figure 8 As shown, the transistors in contact with the L-shaped irregular active area are identified. Among these identified transistors: the transistor graph containing the initial edge is recorded as the first transistor, recorded as Lshape_deviceA, and each Lshape_deviceA must have only one side in contact with Lshape_S / Darea; the transistor graph not containing the initial edge is recorded as the second transistor, recorded as Lshape_deviceB, and each Lshape_deviceB must have one side in contact with Lshape_S / Darea.

[0042] In this embodiment, information of the L-shaped irregular active area Lshape_S / Darea in contact with the first transistor Lshape_deviceA is also recorded as information of the first transistor, including the length Lshape_short of edge_short and the length Lshape_long of edge_long in contact with the Lshape_S / Darea, and the value Lshape_ratio of Lshape_short divided by Lshape_long.

[0043] The information of the L-shaped irregular active area Lshape_S / Darea in contact with the second transistor Lshape_deviceB is also recorded as the information of the second transistor, including the length Lshape_short of edge_short and the length Lshape_long of edge_long in contact with the Lshape_S / Darea, and the value Lshape_ratio of Lshape_short divided by Lshape_long. The recorded information of the first transistor and the second transistor represents the environmental attributes of the transistor, so as to quantify the risk degree of the transistor formed by the active area lithography.

[0044] In this embodiment, it is also identified whether the left side or the right side of the Lshape_deviceA contacts the Lshape_S / Darea. If it contacts the left side, it is recorded as Lshape_short_l, Lshape_long_l and Lshape_ratio_l respectively. If it contacts the right side, it is recorded as Lshape_short_r, Lshape_long_r and Lshape_ratio_r. It is also identified whether the left side or the right side of the Lshape_deviceB contacts the Lshape_S / Darea: if it contacts the left side, it is recorded as Lshape_short_l, Lshape_long_l and Lshape_ratio_l respectively. If it contacts the right side, it is recorded as Lshape_short_r, Lshape_long_r and Lshape_ratio_r.

[0045] In this embodiment, transistors in or in contact with the U-shaped irregular active area are also identified. Specifically: all Lshape_deviceA or Lshape_deviceB in contact with Ushape_space are identified; Ushape_h1, Ushape_h2 and Ushape_innerspace of Ushape_space are recorded as information of transistors in the U-shaped irregular active area, indicating the environmental properties of the transistor, so as to quantify the risk level of the transistor due to active area lithography. In one case in this embodiment, for Lshape_deviceA or Lshape_deviceB that does not contact the Ushape_space, the values ​​of Ushape_h1, Ushape_h2 and Ushape_innerspace of the transistor are defaulted to 0.

[0046] The above-mentioned embodiments are preferred cases of the present invention and are not intended to limit the protection scope of the present invention. It should be understood that the details of these implementations should not be used to limit the present invention. In addition, in order to simplify the drawings, some structures and components will be illustrated in the drawings in a simple schematic manner, which is only for illustration and does not limit specific actual possible design situations.

[0047] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and do not specifically refer to the order or sequence, nor are they used to limit the present invention. They are only used to distinguish components or operations described with the same technical terms, and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features.

[0048] The technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that they can be implemented by ordinary technicians in the field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

Claims

1. A method for identifying hot spots in a photolithography active area, characterized in that: include: Step S1. Obtaining layout information, including active area graphics and gate graphics; Step S2. The contour edges connected in all or part of the active area pattern are perpendicular to each other, forming a first corner with an internal angle of 90° and a second corner with an internal angle of 270°, and defining the contour edge between the vertex of the first corner and the vertex of the second corner as the initial edge; Step S3. Identify the rectangular area in the active area pattern that overlaps with the gate pattern as a transistor pattern, identify the contour edge in the transistor pattern that overlaps with the initial edge as the first long edge, and the portion of the first long edge that does not overlap with the initial edge as the first short edge; Step S4. Identify the rectangular area remaining in the active area pattern after removing the overlapping area with the gate pattern as the first rectangle, and identify the first rectangle in contact with the first short side as the L-shaped irregular active area for locating the hot spot of the lithography active area.

2. A method for identifying hot spots in photolithography active areas according to claim 1, characterized in that: The gate extension direction is the vertical direction, and the direction perpendicular to the gate extension direction is the horizontal direction; after the layout information is acquired in step S1, for the vertical contour edge of the active area pattern in the overlapping area of ​​the active area pattern and the gate pattern, it is determined whether the vertical contour edge overlaps with the vertical contour edge of the gate pattern: When the vertical contour edge overlaps with the vertical contour edge of the gate pattern, directly proceed to step S2; When the vertical contour edge does not overlap with the vertical contour edge of the gate pattern, layout processing is performed: the vertical contour edge is moved horizontally toward the outside of the active area pattern until it overlaps with the vertical contour edge of the gate pattern; then step S2 is performed.

3. The method for identifying hot spots in photolithography active areas according to claim 1, characterized in that: In step S4, information of the L-shaped irregular active region is also recorded, including the length of the first short side in contact with the L-shaped irregular active region, the length of the first long side, and the ratio of the length of the first short side to the length of the first long side.

4. A method for identifying hot spots in a photolithography active area according to any one of claims 1 to 3, characterized in that: Included in the step S4 or after the step S4, a region formed by two adjacent opposite L-shaped irregular active regions is identified as a U-shaped irregular active region for locating a hot spot of a photolithography active region.

5. The method for identifying hot spots in photolithography active areas according to claim 4, characterized in that: The specific process of identifying the U-shaped irregular active area includes: connecting the first corner vertices on two adjacent initial edges in the same active area, connecting the second corner vertices on two adjacent initial edges, then the line connecting the two vertices and the two adjacent initial edges form a polygonal area, and the polygons in the enclosed polygonal area that do not overlap with the active area graphic are identified as U-shaped irregular active areas.

6. A method for identifying hot spots in photolithography active areas according to claim 5, characterized in that: The specific process of identifying the U-shaped irregular active area also includes: recording the information of the U-shaped irregular active area, including: the lengths of the two sides overlapping the initial sides are recorded as Ushape_h1 and Ushape_h2; the length of the side contacting the active area pattern in the horizontal direction is recorded as Ushape_innerspace.

7. A method for identifying transistors in a photolithographic active region, characterized in that: include: Using the method for identifying hot spots in photolithography active areas as described in any one of claims 1 to 6 to identify L-shaped irregular active areas; Identify transistors that are in contact with the L-shaped irregular active region.

8. A method for identifying transistors in a photolithography active region according to claim 7, characterized in that: Among the identified transistors that are in contact with the L-shaped irregular active region, a transistor pattern including an initial edge is recorded as a first transistor, and a transistor pattern not including the initial edge is recorded as a second transistor; Only one side of the first transistor is in contact with the L-shaped irregular active region, and information of the L-shaped irregular active region in contact with the first transistor is recorded as information of the first transistor, including the length of a first short side in contact with the L-shaped irregular active region, the length of a first long side, and the ratio of the length of the first short side to the length of the first long side; used to characterize the environmental properties of the first transistor; At least one side of the second transistor is in contact with the L-shaped irregular active area, and information of the L-shaped irregular active area in contact with the second transistor is recorded as information of the second transistor, including the length of the first short side in contact with the L-shaped irregular active area, the length of the first long side, and the ratio of the length of the first short side to the length of the first long side, which is used to characterize the environmental properties of the second transistor.

9. A method for identifying transistors in a photolithography active region according to claim 8, characterized in that: The method also includes identifying a positional relationship between the first transistor and / or the second transistor and an L-shaped irregular active region in contact with the first transistor and / or the second transistor.

10. The method for identifying transistors in a photolithography active region according to claim 7, characterized in that: A method for identifying hot spots in photolithography active areas as described in claim 6 is used to identify L-shaped irregular active areas and U-shaped irregular active areas; among the identified first transistors and second transistors, transistors that are within the U-shaped irregular active area or in contact with the U-shaped irregular active area are identified.

11. A method for identifying transistors in a photolithography active region according to claim 10, characterized in that: In the information of the first transistor and the second transistor, information recording the U-shaped irregular active area is added, including: For a first transistor or a second transistor in or in contact with the U-shaped irregular active region, information of the U-shaped irregular active region, including: Ushape_h1, Ushape_h2 and Ushape_innerspace, is recorded in the information of the transistor; For the first transistor or the second transistor that does not contact the U-shaped irregular active area, the value of the related information of the U-shaped irregular active area of ​​the transistor is recorded as 0, that is, the values ​​of Ushape_h1, Ushape_h2 and Ushape_innerspace are all 0.

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