Methods to improve wafer edge product yield

Abstract

The present invention provides a method for improving the yield of wafer edge products, providing a substrate, on which a shallow groove is formed, and then forming a first oxide layer covering the shallow groove on the substrate; forming a second oxide layer on the first oxide layer; grinding the second oxide layer and the first oxide layer below it, so that the thickness of the first oxide layer at the edge of the substrate is the first thickness; etching the remaining first oxide layer, so that the thickness of the first oxide layer at the edge of the substrate is the second thickness; depositing a gate layer covering the shallow groove and the first oxide layer on the substrate; forming a third oxide layer on the gate layer, grinding the third oxide layer to above the gate layer; etching back the third oxide layer, grinding the gate layer, so that the top of the gate layer is flattened. The present invention cleans wafer edge defects and improves wafer edge yield; retains part of the oxide on the wafer, and reduces wafer film stress.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving the yield rate of wafer edge products. Background Art

[0002] It is difficult to control the polishing rate of the wafer edge during CMP (chemical mechanical planarization), especially for FINFET (fin field effect transistor), where the polishing rate at the edge is about 10 times faster than that at the center of the wafer.

[0003] The raw material silicon at the edge of the wafer will be damaged during the gate etching process, and the subsequent photolithography process will cause spin-coated carbon mask or photoresist residue or cause film peeling, which will affect the chip yield at the edge of the wafer.

[0004] To this end, a method is needed to improve the yield of wafer edge products. In order to increase the final polysilicon height at the wafer edge, the gate material will land smoothly on the STI (shallow trench isolation). After that, the etching of the gate will not damage the raw silicon, so that the overall wafer edge defects will be improved and the wafer edge yield will increase. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a method for improving the yield of wafer edge products, which is used to solve the problem in the prior art that the raw material silicon at the edge of the wafer will be damaged during the gate etching process, and the subsequent photolithography process will cause spin-coated carbon mask or photoresist residue or cause film peeling, thereby affecting the yield of the chip at the edge of the wafer.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for improving the yield of wafer edge products, comprising:

[0007] Step 1, providing a substrate, wherein a shallow trench is formed on the substrate, and then forming a first oxide layer covering the shallow trench on the substrate;

[0008] Step 2: forming a second oxide layer on the first oxide layer;

[0009] Step 3: grinding the second oxide layer and the first oxide layer thereunder by using a chemical mechanical planarization process, so that the thickness of the first oxide layer at the edge of the substrate is a first thickness;

[0010] Step 4: etching the remaining first oxide layer so that the thickness of the first oxide layer at the edge of the substrate is the second thickness;

[0011] Step 5: depositing a gate layer covering the shallow trench and the first oxide layer on the substrate;

[0012] Step 6, forming a third oxide layer on the gate layer, and then grinding the third oxide layer to above the gate layer using a chemical mechanical planarization process;

[0013] Step seven, etching back the third oxide layer, and then grinding the gate layer to planarize the upper surface of the gate layer.

[0014] Preferably, the substrate in step one is a silicon substrate.

[0015] Preferably, the material of the first oxide layer in step 1 is silicon dioxide.

[0016] Preferably, the materials of the second oxide layer in step two and the third oxide layer in step six are both silicon dioxide.

[0017] Preferably, the thickness of the second oxide layer in step 2 is 500 angstroms to 700 angstroms.

[0018] Preferably, the first thickness in step three is 500 angstroms to 600 angstroms.

[0019] Preferably, the etching in step 4 is dry etching.

[0020] Preferably, the second thickness in step four is 100 angstroms to 200 angstroms.

[0021] Preferably, the material of the gate layer in step five is polysilicon.

[0022] Preferably, the thickness of the third oxide layer in step six is ​​500 angstroms to 700 angstroms.

[0023] Preferably, the substrate in step 1 is used to form a fin field effect transistor.

[0024] Preferably, the grinding in step three, step six and step seven all adopts a chemical mechanical planarization process.

[0025] As described above, the method for improving the yield of wafer edge products of the present invention has the following beneficial effects:

[0026] After the wafer is chemically and mechanically planarized, the edge of the wafer will retain part of the oxide; the gate material will land smoothly on the STI (shallow trench isolation), and the etching of the gate will not damage the raw material silicon; the photolithography process will remove the residues of the spin-coated carbon mask or photoresist, instead of leaving them in the silicon area with damaged bevels, the wafer edge defects are cleaned and the wafer edge yield is improved; part of the oxide is retained on the wafer, and the wafer film stress is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0028] Figure 2 Shown is a schematic structural diagram of a substrate of the present invention;

[0029] Figure 3 It is a schematic diagram showing the present invention after forming a first oxide layer;

[0030] Figure 4 It is a schematic diagram showing the chemical mechanical planarization of the first oxide layer according to the present invention;

[0031] Figure 5 It is a schematic diagram showing the etching of the first oxide layer according to the present invention;

[0032] Figure 6 It is a schematic diagram showing the formation of a gate layer according to the present invention;

[0033] Figure 7 It is a schematic diagram showing the formation of a third oxide layer according to the present invention;

[0034] Figure 8 It is a schematic diagram showing the chemical mechanical planarization of the third oxide layer according to the present invention;

[0035] Fig. 9 Shown is a schematic diagram of the chemical mechanical planarization of the gate layer of the present invention. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] See also Figure 1 The present invention provides a method for improving the yield of wafer edge products, comprising:

[0038] Step 1, see Figure 2 , providing a substrate 10, on which a shallow trench is formed, and then forming a first oxide layer 11 covering the shallow trench on the substrate 10 to generate a shallow trench isolation (STI). The formation of the STI structure is usually to first deposit a silicon nitride layer on the semiconductor substrate 10, and then pattern the silicon nitride layer to form a hard mask. Then, the substrate 10 is etched to form a steep shallow trench between adjacent components. Finally, oxide is filled in the shallow trench to form a component isolation structure;

[0039] In an optional implementation, the substrate 10 in step one is a silicon substrate 10 .

[0040] In an optional embodiment, the material of the first oxide layer 11 in step 1 is silicon dioxide, which can usually be formed by a chemical vapor deposition process.

[0041] In an optional implementation, the substrate in step one is used to form a fin field effect transistor.

[0042] Step 2, see Figure 3 , forming a second oxide layer 12 on the first oxide layer 11, which can usually be formed by a chemical vapor deposition process;

[0043] In an optional embodiment, the materials of the second oxide layer 12 in step two and the third oxide layer 14 in step six are both silicon dioxide.

[0044] In an optional embodiment, the thickness of the second oxide layer 12 in step 2 is 500 angstroms to 700 angstroms.

[0045] Step 3, see Figure 4 , grinding the second oxide layer 12 and the first oxide layer 11 thereunder by a chemical mechanical planarization process, so that the thickness of the first oxide layer 11 at the edge of the substrate 10 is the first thickness, because a second oxide layer 12 is added on the first oxide layer 11, the oxide layer at the edge of the substrate 10 is prevented from being completely removed during grinding, and due to the difference in polishing rate during grinding, the first oxide layer 11 at the edge of the substrate 10 is lost faster and is in a slope shape;

[0046] In an optional embodiment, the first thickness in step three is 500 angstroms to 600 angstroms.

[0047] Step 4, see Figure 5 , etching the remaining first oxide layer 11 so that the thickness of the first oxide layer 11 at the edge of the substrate 10 is a second thickness;

[0048] In an optional implementation, the etching in step four is dry etching.

[0049] In an optional embodiment, the second thickness in step four is 100 angstroms to 200 angstroms.

[0050] Step 5, see Figure 6 , depositing a gate layer 13 covering the shallow trench and the first oxide layer 11 on the substrate 10 for subsequent etching to form a gate;

[0051] In an optional implementation, the material of the gate layer 13 in step five is polysilicon.

[0052] Step 6, see Figure 7, a third oxide layer 14 is formed on the gate layer 13, and then the third oxide layer 14 is polished to above the gate layer 13 by a chemical mechanical planarization process. Due to the blocking effect of the third oxide layer 14, the damage to the lower gate layer 13 is reduced during polishing, thereby forming a Figure 8 The structure shown;

[0053] In an optional embodiment, the thickness of the third oxide layer 14 in step six is ​​500 angstroms to 700 angstroms.

[0054] Step 7, see Fig. 9 , the third oxide layer 14 is etched back, and after the third oxide layer 14 is completely removed, the gate layer 13 is polished by a chemical mechanical planarization process, so that the upper surface of the gate layer 13 is planarized.

[0055] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0056] In summary, after the wafer is chemically and mechanically planarized, the edge of the wafer will retain part of the oxide; the gate material will land smoothly on the STI (shallow trench isolation), and the etching of the gate will not damage the raw material silicon; the residue of the spin-coated carbon mask or photoresist brought about by the photolithography process will be removed instead of being left in the silicon area with damaged bevels, the wafer edge defects are cleaned and the wafer edge yield is improved; and part of the oxide is retained on the wafer, and the wafer film stress is reduced. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0057] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving the yield of wafer edge products, characterized in that: At least: Step 1, providing a substrate, wherein a shallow trench is formed on the substrate, and then forming a first oxide layer covering the shallow trench on the substrate; Step 2: forming a second oxide layer on the first oxide layer; Step 3: grinding the second oxide layer and the first oxide layer thereunder so that the thickness of the first oxide layer at the edge of the substrate is the first thickness; Step 4: etching the remaining first oxide layer so that the thickness of the first oxide layer at the edge of the substrate is the second thickness; Step 5: depositing a gate layer covering the shallow trench and the first oxide layer on the substrate; Step 6, forming a third oxide layer on the gate layer, and then grinding the third oxide layer to above the gate layer; Step seven, etching back the third oxide layer, and then grinding the gate layer to planarize the upper surface of the gate layer.

2. The method for improving wafer edge product yield according to claim 1, characterized in that: The substrate in step one is a silicon substrate.

3. The method for improving wafer edge product yield according to claim 1, characterized in that: The material of the first oxide layer in step 1 is silicon dioxide.

4. The method for improving wafer edge product yield according to claim 1, characterized in that: The materials of the second oxide layer in step two and the third oxide layer in step six are both silicon dioxide.

5. The method for improving wafer edge product yield according to claim 1, characterized in that: The thickness of the second oxide layer in step 2 is 500 angstroms to 700 angstroms.

6. The method for improving wafer edge product yield according to claim 1, characterized in that: The first thickness in step three is 500 angstroms to 600 angstroms.

7. The method for improving wafer edge product yield according to claim 1, characterized in that: The etching in step 4 is dry etching.

8. The method for improving wafer edge product yield according to claim 1, characterized in that: The second thickness in step 4 is 100 angstroms to 200 angstroms.

9. The method for improving wafer edge product yield according to claim 1, characterized in that: The material of the gate layer in step five is polysilicon.

10. The method for improving wafer edge product yield according to claim 1, characterized in that: The thickness of the third oxide layer in step six is ​​500 angstroms to 700 angstroms.

11. The method for improving wafer edge product yield according to claim 1, characterized in that: The substrate in step 1 is used to form a fin field effect transistor.

12. The method for improving wafer edge product yield according to claim 1, characterized in that: The grinding in step 3, step 6 and step 7 all adopts chemical mechanical planarization process.

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