A linear voltage regulator circuit based on NMOS adjusting tube

Abstract

The application discloses a linear voltage stabilizing circuit based on NMOS regulating tube, comprising a bias voltage generating circuit, a voltage division feedback circuit, an oscillator circuit, a charge pump circuit and a pre-voltage stabilizing circuit, wherein the bias voltage is generated through the bias voltage generating circuit; the output voltage is divided to obtain a feedback voltage through the voltage division feedback circuit; the feedback voltage is amplified and then input to the oscillator circuit to generate an oscillation signal; the generated oscillation signal is input to the charge pump circuit; the gate voltage of the NMOS regulating tube is adjusted through the charge pump circuit, so as to obtain the output voltage; the pre-voltage stabilizing circuit widens the input voltage range, so that the linear voltage stabilizing circuit can work in a high input voltage environment; the linear voltage stabilizing circuit based on the NMOS regulating tube has the characteristics of wide input range and low voltage difference, fast transient response speed, and is fully compatible with the thin gate oxide process.

Description

Technical Field

[0001] This invention relates to the field of power management integrated circuit technology, specifically to a linear voltage regulator circuit based on an NMOS regulator. Background Technology

[0002] Linear regulated power supplies have been widely used in the power supply field due to their advantages of small size, low noise, and low cost. The regulating transistors of linear regulated power supply circuits are usually of two types: P-type MOSFETs and N-type MOSFETs. Chinese patents CN101122804 (published on February 13, 2008), CN101957625A (published on January 26, 2011), and CN102279612A (published on December 14, 2011) disclose linear regulated circuits using P-type MOSFETs. However, under the same conditions, linear regulated circuits using N-type MOSFETs are lower in cost, have faster transient response, better power supply noise suppression, and more flexible compensation than linear regulated circuits using P-type MOSFETs.

[0003] In the prior art, for example, Chinese patent CN108153364A (published on June 12, 2018) discloses a linear voltage regulator circuit using an N-type MOS regulator. However, the gate voltage of the regulator can only reach the input voltage, which means the output voltage can only be lower than the input voltage by the turn-on voltage of the N-type MOS regulator. This means it does not meet the low-dropout operating conditions and its application is limited. For example, US patents US6600299 and US8760131 disclose a linear voltage regulator circuit using an N-type MOS regulator. By utilizing a charge pump, it can operate at low voltage drops, but it has certain drawbacks: First, some circuits (such as the driver) need to operate in the charge pump voltage domain, which increases the requirements for the charge pump's driving capability and complicates the circuit structure. Second, since the charge pump increases the gate voltage of the N-type regulator, this voltage is usually higher than the gate oxide withstand voltage under thin gate oxide technology, which may cause process compatibility issues.

[0004] Therefore, linear voltage regulator circuits based on N-type MOS regulators still have problems such as complex circuit structure, lack of low dropout operating conditions, and incompatibility with thin gate oxide processes.

[0005] Therefore, a linear voltage regulator circuit based on an NMOS regulator is needed to solve the above problems. Summary of the Invention

[0006] The purpose of this invention is to provide a linear voltage regulator circuit based on an NMOS regulator to solve the problems mentioned in the background art.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a linear voltage regulator circuit based on an NMOS regulating transistor, the circuit comprising: a bias voltage generation circuit, a voltage divider feedback circuit, an oscillator circuit, and a charge pump circuit;

[0008] The bias voltage generating circuit is used to generate a bias voltage. The voltage divider feedback circuit is used to divide the output voltage to obtain a feedback voltage, and amplify the feedback voltage before inputting it to the oscillator circuit. The oscillator circuit is used to generate an oscillation signal, and input the generated oscillation signal to the charge pump circuit. The charge pump circuit is used to adjust the gate voltage of the NMOS regulating transistor to obtain the output voltage.

[0009] The voltage divider feedback circuit includes resistor R3, capacitor C1, resistor R1, resistor R2, amplifier A1, voltage source V1, and NMOS transistor MN2. One end of resistor R3 is connected to output VOUT, and the other end is connected to ground GND. The upper plate of capacitor C1 is connected to output VOUT, and the lower plate is connected to ground GND. One end of resistor R1 is connected to output VOUT, and the other end is connected to one end VFB of resistor R2. The other end of resistor R2 is connected to ground GND. The positive terminal of amplifier A1 is connected to VFB, and the negative terminal is connected to the positive terminal VREF of voltage source V1. The output terminal of amplifier A1 is connected to the gate terminal VEA of NMOS transistor MN2. The source terminal of NMOS transistor MN2 is connected to ground GND. The negative terminal of voltage source V1 is connected to ground GND.

[0010] Furthermore, the bias voltage generation circuit includes a current source I1, a PMOS transistor, and an NMOS transistor MN3. One end of the current source I1 is connected to the drain terminal VPG of the PMOS transistor MP1, and the other end is connected to ground GND. The gate terminal of the PMOS transistor MP1 is connected to one end VPG of the current source I1, and the drain terminal is connected to VPG. The source terminals of the PMOS transistors MP1, MP2, MP3, and MP4 are connected to the input VIN. The gate of PMOS transistor MP4 is connected to VPG, the drain of PMOS transistor MP2 is connected to VNG, the drain of PMOS transistor MP3 is connected to VCN, the drain of PMOS transistor MP4 is connected to VRAMP, the source of PMOS transistor MP5 is connected to VCN, the gate of PMOS transistor MP5 is connected to VNG, the drain of PMOS transistor MP5 is connected to ground GND, the source of NMOS transistor MN3 is connected to ground GND, the gate of NMOS transistor MN3 is connected to VNG, and the drain of NMOS transistor MN3 is connected to VNG.

[0011] Furthermore, the oscillator circuit includes a capacitor C2 and an OSC module. The upper plate of the capacitor C2 is connected to the VRAMP, and the lower plate is connected to ground (GND). One end of the OSC module is connected to the VRAMP, and the other end is connected to the input of the charge pump circuit through the VOSC output.

[0012] The charge pump circuit includes a charge pump, capacitor C3, and NMOS transistor MN1. One input terminal of the charge pump is connected to input VIN, the other input terminal is connected to VOSC, and the output terminal is connected to VGT. The source terminal of the NMOS transistor MN1 is connected to output VOUT, the gate terminal is connected to VGT, and the drain terminal is connected to input VIN. The upper plate of capacitor C3 is connected to VGT, and the lower plate is connected to VCN. By using VGT as a signal controlled by a negative feedback loop and boosted by the charge pump, it can be higher than VIN. Therefore, VOUT can be very close to VIN, solving the problem of low voltage difference operation. Moreover, the circuit structure is simple and the overhead is low.

[0013] Furthermore, the drain terminal of the NMOS transistor MN2 is connected to the input terminal VRAMP of the oscillator circuit.

[0014] Furthermore, the linear regulator circuit also includes a pre-regulator circuit, which includes NMOS transistors MN4, MN5, MN6, and MN7, and resistor R4. The source of NMOS transistor MN7 is connected to the charge pump circuit, its gate is connected to VGT2, and its drain is connected to the input VIN. One end of resistor R4 is connected to the input VIN, and the other end is connected to the drain of NMOS transistor MN6 through VGT2. The source of NMOS transistor MN6 is connected to VMID1, and its gate is connected to VGT2. The source of NMOS transistor MN5 is connected to VMID2, and its gate and drain are connected to VMID1. The source of NMOS transistor MN4 is connected to ground GND, and its gate and drain are connected to VMID2. The addition of the pre-regulator circuit generates a voltage VPRE, enabling the linear regulator circuit to operate even at high VIN voltages, ensuring the safe operation of small-sized devices.

[0015] Furthermore, the bias voltage generating circuit includes a current source I1, a PMOS transistor, and an NMOS transistor MN3. One end of the current source I1 is connected to the drain terminal VPG of the PMOS transistor MP1, and the other end is connected to ground GND. The gate terminal of the PMOS transistor MP1 is connected to one end VPG of the current source I1, and the drain terminal is connected to VPG. The sources of the PMOS transistors MP1, MP2, and MP3 are connected to the pre-regulator circuit through VPRE. The gate terminals of the PMOS transistors MP2 and MP3 are connected to VPG. The drain terminal of the PMOS transistor MP2 is connected to VNG. The drain terminal of the PMOS transistor MP3 is connected to VCN. The source terminal of the PMOS transistor MP5 is connected to VCN. The gate terminal of the PMOS transistor MP5 is connected to VNG. The drain terminal of the PMOS transistor MP5 is connected to ground GND. The source terminal of the NMOS transistor MN3 is connected to ground GND. The gate terminal of the NMOS transistor MN3 is connected to VNG. The drain terminal of the NMOS transistor MN3 is connected to VNG.

[0016] Furthermore, the oscillator circuit includes an OSC module, the output VOSC of which is connected to the input of the charge pump circuit;

[0017] The charge pump circuit includes a charge pump, capacitor C3, resistor R5, and NMOS transistor MN1. One input terminal of the charge pump is connected to the pre-regulator circuit via VPRE, and the other input terminal is connected to a fixed clock VOSC. The output terminal is connected to VCP. One end of resistor R5 is connected to the output terminal VCP of the charge pump, and the other end is connected to VGT. The source terminal of the NMOS transistor MN1 is connected to the output VOUT, the gate terminal is connected to VGT, and the drain terminal is connected to the input VIN. The upper plate of capacitor C3 is connected to VGT, and the lower plate is connected to VCN. The voltage of VGT is directly controlled by the control voltage VEA, which drives the rise and fall of VOUT, thereby improving the transient response capability of the linear regulator circuit.

[0018] Furthermore, the drain terminal of the NMOS transistor MN2 is connected to VGT.

[0019] Furthermore, the capacitor C3 is a thin-gate oxide MOSFET capacitor, and the upper plate of the capacitor C3 is the gate of the MOSFET. Charge pumps all need pump capacitors to store charge, and pump capacitors generally have a large capacitance value. Using a MOSFET capacitor reduces costs.

[0020] The bias voltage generating circuit generates a bias voltage VCN, which is connected to a capacitor C3. The lower plate of the capacitor C3 is connected to the bias voltage VCN. The capacitor C3 is used to store charge. The bias voltage VCN raises the lower plate of the capacitor C3, controlling the voltage difference across the capacitor C3 to be within the withstand voltage range of the thin gate oxide process. This avoids the charge pump output VCP voltage being too high, which could damage the device and ensures full compatibility with the thin gate oxide process.

[0021] Furthermore, capacitor C1 is an output capacitor, and resistor R3 is an output load. Resistors R1 and R2 form a voltage divider circuit, which inputs the voltage-divided signal VOUT to amplifier A1. Amplifier A1 subtracts the input voltage-divided signal from the reference voltage signal generated by voltage source V1 and amplifies it to obtain control voltage VEA. VEA controls the current flowing through NMOS transistor MN2.

[0022] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0023] This invention proposes a linear voltage regulator circuit based on an NMOS regulator, which, compared to a PMOS regulator, offers advantages such as lower cost, faster transient response, better power supply noise suppression, and more flexible compensation. Compared to existing technologies, the addition of a pre-regulator circuit enables the linear regulator to operate even at high VIN voltages, ensuring the safe operation of thin-gate oxide devices. The bias voltage VCN generated by the bias voltage generation circuit raises the lower plate of the pump capacitor, protecting the voltage difference across the pump capacitor within the withstand voltage range of the thin-gate oxide process, preventing excessively high VCP output voltage from the charge pump and thus ensuring full compatibility with the thin-gate oxide process. The control voltage VEA directly controls the voltage of VGT, driving the rise and fall of VOUT, improving the transient response capability of the linear regulator circuit. The charge pump boost control of the NMOS regulator's gate voltage allows it to exceed VIN, solving the problem of low voltage difference operation. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0025] Figure 1 This is a schematic diagram of a linear voltage regulator circuit based on an NMOS regulator provided in an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of another linear voltage regulator circuit based on an NMOS regulating transistor provided in an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of another linear voltage regulator circuit based on an NMOS regulating transistor provided in an embodiment of the present invention;

[0028] Figure 4 This is a first simulation waveform diagram of a linear voltage regulator circuit based on an NMOS regulating transistor provided in an embodiment of the present invention;

[0029] Figure 5 This is a second simulation waveform diagram of a linear voltage regulator circuit based on an NMOS regulating transistor provided in an embodiment of the present invention. Detailed Implementation

[0030] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0031] The following is combined with Figures 1-5 The present invention will be further described with reference to specific embodiments.

[0032] Example 1:

[0033] like Figure 1 As shown, a linear voltage regulator circuit based on an NMOS regulator includes: a bias voltage generation circuit, a voltage divider feedback circuit, an oscillator circuit, and a charge pump circuit.

[0034] The bias voltage generation circuit is used to generate the bias voltage. The voltage divider feedback circuit is used to divide the output voltage to obtain the feedback voltage, and then amplifies the feedback voltage and inputs it to the oscillator circuit. The oscillator circuit is used to generate the oscillation signal, and then inputs the generated oscillation signal to the charge pump circuit. The charge pump circuit is used to adjust the gate voltage of the NMOS regulator to obtain the output voltage.

[0035] The bias voltage generation circuit includes a current source I1, a PMOS transistor, and an NMOS transistor MN3. One end of the current source I1 is connected to the drain terminal VPG of the PMOS transistor MP1, and the other end is connected to ground GND. The gate terminal of the PMOS transistor MP1 is connected to one end VPG of the current source I1, and the drain terminal is connected to VPG. The sources of PMOS transistors MP1, MP2, MP3, and MP4 are connected to the input VIN. The gate terminals of PMOS transistors MP2, MP3, and MP4 are connected to VPG, and the drain terminal of PMOS transistor MP2 is connected to VN. G, the drain of PMOS transistor MP3 is connected to VCN, the drain of PMOS transistor MP4 is connected to VRAMP, the source of PMOS transistor MP5 is connected to VCN, the gate of PMOS transistor MP5 is connected to VNG, the drain of PMOS transistor MP5 is connected to ground GND, the source of NMOS transistor MN3 is connected to ground GND, the gate of NMOS transistor MN3 is connected to VNG, the drain of NMOS transistor MN3 is connected to VNG, and the current source I1 provides bias current, which together with PMOS transistors MP1, MP2, MP3, MP4, MP5 and NMOS transistor MN3 forms a current mirror;

[0036] The oscillator circuit includes capacitor C2 and OSC module. The upper plate of capacitor C2 is connected to VRAMP, and the lower plate is connected to ground GND. One end of the OSC module is connected to VRAMP, and the other end is connected to the input of the charge pump circuit through VOSC output.

[0037] The charge pump circuit includes a charge pump, capacitor C3, and NMOS transistor MN1. One input terminal of the charge pump is connected to input VIN, the other input terminal is connected to VOSC, and the output terminal is connected to VGT. The source terminal of NMOS transistor MN1 is connected to output VOUT, the gate terminal is connected to VGT, and the drain terminal is connected to input VIN. The upper plate of capacitor C3 is connected to VGT, and the lower plate is connected to VCN.

[0038] The charge pump requires capacitor C3 to store charge and stabilize the output of the charge pump. This capacitor usually has a large capacitance value. To reduce costs, C3 is usually implemented using a thin gate oxide MOSFET capacitor. Since the upper plate of this capacitor is the gate of the MOSFET, it is connected to VGT in the circuit. This voltage usually exceeds the gate oxide withstand voltage of the thin gate oxide process. A bias voltage VCN is generated by the bias voltage generation circuit. The lower plate of capacitor C3 is connected to the bias voltage VCN. The bias voltage VCN raises the lower plate of capacitor C3, controlling the voltage difference across capacitor C3 to be within the withstand voltage range of the thin gate oxide process.

[0039] The voltage divider feedback circuit includes resistor R3, capacitor C1, resistor R2, amplifier A1, voltage source V1, and NMOS transistor MN2. One end of resistor R3 is connected to the output VOUT, and the other end is connected to ground GND. The upper plate of capacitor C1 is connected to the output VOUT, and the lower plate is connected to ground GND. One end of resistor R1 is connected to the output VOUT, and the other end is connected to one end of resistor R2, VFB. The other end of resistor R2 is connected to ground GND. The positive terminal of amplifier A1 is connected to VFB, and the negative terminal is connected to the positive terminal VREF of voltage source V1. The output of amplifier A1... The gate terminal VEA of NMOS transistor MN2 is connected, the source terminal of NMOS transistor MN2 is connected to ground GND, the drain terminal is connected to the input terminal VRAMP of the oscillator circuit, and the negative terminal of voltage source V1 is connected to ground GND. The basic principle of the linear voltage regulator circuit based on NMOS transistor proposed in this invention is as follows: This voltage regulator circuit is based on the negative feedback principle: First, the output voltage VOUT is divided to obtain the feedback voltage VFB, and the feedback voltage VFB is subtracted from a reference voltage signal V1 and then amplified to obtain a control voltage VEA. The control voltage VEA is then compared with the output voltage VO. UT is an in-phase signal. The lower the output voltage VOUT, the lower the control voltage VEA; the higher the output voltage VOUT, the higher the control voltage VEA. Secondly, this voltage regulator circuit controls the current through MN2 via the control voltage VEA. VEA is in phase with the current flowing through MN2; the higher the VEA, the larger the current flowing through MN2. This current, subtracted from the current flowing through the MP4 transistor, charges and discharges capacitor C2 through the OSC module, generating a one-cycle signal VOSC. The frequency of VOSC increases with the increase of the current flowing through C2. Therefore, the frequency of VOSC is related to the control voltage VOUT. The voltage VEA has opposite polarities; the higher the control voltage VEA, the slower the frequency of VOSC, and vice versa. Furthermore, under the control of VOSC, the charge pump module raises the VIN voltage to the output VGT. The voltage VGT is directly proportional to the frequency of VOSC; the faster the VOSC frequency, the higher VGT, and vice versa. Finally, VGT serves as the gate voltage of the NMOS regulator MN1. Lowering VGT by one gate-source turn-on voltage of MN1 yields the output voltage VOUT. Therefore, when the VOUT voltage decreases, this negative feedback loop lowers the control voltage VEA, increases the frequency of the periodic signal VOSC, and raises the voltage VGT to ultimately offset the decrease in VOUT voltage. Conversely, when the VOUT voltage decreases, this negative feedback loop also lowers the control voltage VEA, slows down the frequency of the periodic signal VOSC, and lowers the voltage VCP to ultimately offset the increase in VOUT voltage. As mentioned in the background, many voltage regulator circuits using N-type MOS transistors cannot function properly when the voltage difference between VIN and VOUT is low. This is because the gate voltage of their N-type MOS transistors can only be VIN at most, so VOUT can only be equal to VIN minus a turn-on voltage.However, this invention uses VGT as a signal controlled by a negative feedback loop, boosted by a charge pump, which can be higher than VIN. Therefore, VOUT can be very close to VIN, effectively solving the problem of low voltage drop operation. Furthermore, the circuit structure is simple and has low overhead.

[0040] Example 2: Figure 2 As shown, a linear voltage regulator circuit based on an NMOS regulator includes: a bias voltage generation circuit, a voltage divider feedback circuit, an oscillator circuit, a charge pump circuit, and a pre-regulator circuit.

[0041] The bias voltage generation circuit is used to generate the bias voltage. The voltage divider feedback circuit is used to divide the output voltage to obtain the feedback voltage, and then amplifies the feedback voltage and inputs it to the oscillator circuit. The oscillator circuit is used to generate the oscillation signal, and then inputs the generated oscillation signal to the charge pump circuit. The charge pump circuit is used to adjust the gate voltage of the NMOS regulator to obtain the output voltage.

[0042] exist Figure 1 The linear regulator circuit shown is supplemented with a pre-regulator circuit. The pre-regulator circuit includes NMOS transistors MN4, MN5, MN6, and MN7, and resistor R4. The source of NMOS transistor MN7 is connected to the charge pump circuit, its gate is connected to VGT2, and its drain is connected to the input VIN. One end of resistor R4 is connected to the input VIN, and the other end is connected to the drain of NMOS transistor MN6 through VGT2. The source of NMOS transistor MN6 is connected to VMID1, and its gate is connected to VGT2. The source of NMOS transistor MN5 is connected to VMID2, and its gate and drain are connected to VMID1. The source of NMOS transistor MN4 is connected to ground GND, and its gate and drain are connected to VMID2. Under thin gate oxide process conditions, many small-sized devices cannot withstand high voltages. The pre-regulator circuit ensures the safe operation of small-sized devices by generating voltage VPRE, enabling the regulator circuit to operate in situations where the VIN voltage is very high. This embodiment has all the advantages of embodiment one, while also having the additional advantage of a wide input voltage range.

[0043] Example 3: Figures 3-5 As shown, a linear voltage regulator circuit based on an NMOS regulator includes: a bias voltage generation circuit, a voltage divider feedback circuit, an oscillator circuit, a charge pump circuit, and a pre-regulator circuit.

[0044] The bias voltage generation circuit is used to generate the bias voltage. The voltage divider feedback circuit is used to divide the output voltage to obtain the feedback voltage, and then amplifies the feedback voltage and inputs it to the oscillator circuit. The oscillator circuit is used to generate the oscillation signal, and then inputs the generated oscillation signal to the charge pump circuit. The charge pump circuit is used to adjust the gate voltage of the NMOS regulator to obtain the output voltage.

[0045] The linear regulator circuit also includes a pre-regulator circuit, which includes NMOS transistors MN4, MN5, MN6, and MN7, and resistor R4. The source of NMOS transistor MN7 is connected to the charge pump circuit, its gate is connected to VGT2, and its drain is connected to the input VIN. One end of resistor R4 is connected to the input VIN, and the other end is connected to the drain of NMOS transistor MN6 through VGT2. The source of NMOS transistor MN6 is connected to VMID1, and its gate is connected to VGT2. The source of NMOS transistor MN5 is connected to VMID2, and its gate and drain are connected to VMID1. The source of NMOS transistor MN4 is connected to ground GND, and its gate and drain are connected to VMID2.

[0046] The bias voltage generation circuit includes a current source I1, a PMOS transistor, and an NMOS transistor MN3. One end of the current source I1 is connected to the drain terminal VPG of the PMOS transistor MP1, and the other end is connected to ground GND. The gate terminal of the PMOS transistor MP1 is connected to one end VPG of the current source I1, and the drain terminal is connected to VPG. The sources of PMOS transistors MP1, MP2, and MP3 are connected to the pre-regulator circuit through VPRE. The gate terminals of PMOS transistors MP2 and MP3 are connected to VPG. The drain terminal of PMOS transistor MP2 is connected to VNG. The drain terminal of PMOS transistor MP3 is connected to VCN. The source terminal of PMOS transistor MP5 is connected to VCN. The gate terminal of PMOS transistor MP5 is connected to VNG. The drain terminal of PMOS transistor MP5 is connected to ground GND. The source terminal of NMOS transistor MN3 is connected to ground GND. The gate terminal of NMOS transistor MN3 is connected to VNG. The drain terminal of NMOS transistor MN3 is connected to VNG.

[0047] The oscillator circuit includes an OSC module, whose output VOSC is connected to the input of the charge pump circuit.

[0048] The charge pump circuit includes a charge pump, capacitor C3, resistor R5, and NMOS transistor MN1. One input terminal of the charge pump is connected to the pre-regulator circuit through VPRE, and the other input terminal is connected to the fixed clock VOSC. The output terminal is connected to VCP. One end of resistor R5 is connected to the output terminal VCP of the charge pump, and the other end is connected to VGT. The source terminal of NMOS transistor MN1 is connected to the output VOUT, the gate terminal is connected to VGT, and the drain terminal is connected to the input VIN. The upper plate of capacitor C3 is connected to VGT, and the lower plate is connected to VCN. Compared with embodiment 2, PMOS transistor MP4 and capacitor C2 are deleted, and the variable frequency VOSC is changed to a fixed frequency VOSC signal, so that the output of the charge pump changes from an adjustable voltage VGT controlled by the loop to a fixed voltage VCP. VGT is obtained by subtracting the voltage on R5 from VCP.

[0049] The voltage divider feedback circuit includes resistor R3, capacitor C1, resistor R1, resistor R2, amplifier A1, voltage source V1, and NMOS transistor MN2. One end of resistor R3 is connected to the output VOUT, and the other end is connected to ground GND. The upper plate of capacitor C1 is connected to the output VOUT, and the lower plate is connected to ground GND. One end of resistor R1 is connected to the output VOUT, and the other end is connected to one end of resistor R2, VFB. The other end of resistor R2 is connected to ground GND. The positive terminal of amplifier A1 is connected to VFB, and the negative terminal is connected to the positive terminal VREF of voltage source V1. The output terminal of amplifier A1 is connected to the gate terminal VEA of NMOS transistor MN2. The source terminal of NMOS transistor MN2 is connected to ground GND, and the drain terminal is connected to VGT. The negative terminal of voltage source V1 is connected to ground GND.

[0050] First, the output voltage VOUT is divided to obtain the feedback voltage VFB. The feedback voltage VFB is subtracted from the reference voltage signal V1 and then amplified to obtain the control voltage VEA. The control voltage and the output voltage VOUT are in phase; the lower the output voltage VOUT, the lower the control voltage VEA. Second, the current flowing through MN2 is controlled by the control voltage VEA, which directly controls the voltage VGT. Since the output VCP of the charge pump circuit is a fixed voltage, when the control voltage VEA decreases, the current flowing through MN2 decreases, the voltage drop across resistor R5 decreases, and the voltage VGT increases, causing VOUT to rise. When the control voltage VEA increases, the current flowing through MN2 increases, the voltage drop across resistor R5 increases, and the voltage VGT decreases, causing VOUT to decrease, thus improving the transient response capability of the linear regulator circuit.

[0051] Figure 4 and Figure 5 This is a simulation waveform diagram of the linear voltage regulator circuit in Example 3, from... Figure 4 It can be seen that, under the condition of input VIN = 5.1V, the gate voltage VGT of MN1 is raised to 6.14V by the charge pump, and the output VOUT of the linear regulator circuit is 4.95V; from Figure 5 It can be seen that under the condition of input VIN = 20V, VGT is raised to 5.98V by the charge pump, and the output VOUT of the linear regulator circuit is 4.96V, realizing the function of wide input range and low voltage drop of the linear regulator circuit, thus verifying the correctness and effectiveness of the present invention.

[0052] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A linear voltage regulator circuit based on an NMOS regulator, characterized in that: The circuit includes: a bias voltage generation circuit, a voltage divider feedback circuit, an oscillator circuit, and a charge pump circuit; The bias voltage generating circuit is used to generate a bias voltage. The voltage divider feedback circuit is used to divide the output voltage to obtain a feedback voltage, and amplify the feedback voltage before inputting it to the oscillator circuit. The oscillator circuit is used to generate an oscillation signal, and input the generated oscillation signal to the charge pump circuit. The charge pump circuit is used to adjust the gate voltage of the NMOS regulating transistor to obtain the output voltage. The voltage divider feedback circuit includes resistor R3, capacitor C1, resistor R1, resistor R2, amplifier A1, voltage source V1, and NMOS transistor MN2. One end of resistor R3 is connected to output VOUT, and the other end is connected to ground GND. The upper plate of capacitor C1 is connected to output VOUT, and the lower plate is connected to ground GND. One end of resistor R1 is connected to output VOUT, and the other end is connected to one end VFB of resistor R2. The other end of resistor R2 is connected to ground GND. The positive terminal of amplifier A1 is connected to VFB, and the negative terminal is connected to the positive terminal VREF of voltage source V1. The output terminal of amplifier A1 is connected to the gate terminal VEA of NMOS transistor MN2. The source terminal of NMOS transistor MN2 is connected to ground GND. The negative terminal of voltage source V1 is connected to ground GND. The bias voltage generation circuit includes a current source I1, a PMOS transistor, and an NMOS transistor MN3. One end of the current source I1 is connected to the drain terminal VPG of the PMOS transistor MP1, and the other end is connected to ground GND. The gate terminal of the PMOS transistor MP1 is connected to one end VPG of the current source I1, and the drain terminal is connected to VPG. The source terminals of the PMOS transistors MP1, MP2, MP3, and MP4 are connected to the input VIN. The gate of PMOS transistor MP4 is connected to VPG, the drain of PMOS transistor MP2 is connected to VNG, the drain of PMOS transistor MP3 is connected to VCN, the drain of PMOS transistor MP4 is connected to VRAMP, the source of PMOS transistor MP5 is connected to VCN, the gate of PMOS transistor MP5 is connected to VNG, the drain of PMOS transistor MP5 is connected to ground GND, the source of NMOS transistor MN3 is connected to ground GND, the gate of NMOS transistor MN3 is connected to VNG, and the drain of NMOS transistor MN3 is connected to VNG. The oscillator circuit includes a capacitor C2 and an OSC module. The upper plate of the capacitor C2 is connected to the VRAMP, and the lower plate is connected to ground (GND). One end of the OSC module is connected to the VRAMP, and the other end is connected to the input of the charge pump circuit through the VOSC output. The charge pump circuit includes a charge pump, a capacitor C3, and an NMOS transistor MN1. One input terminal of the charge pump is connected to the input VIN, the other input terminal is connected to VOSC, and the output terminal is connected to VGT. The source terminal of the NMOS transistor MN1 is connected to the output VOUT, the gate terminal is connected to VGT, and the drain terminal is connected to the input VIN. The upper plate of the capacitor C3 is connected to VGT, and the lower plate is connected to VCN.

2. The linear voltage regulator circuit based on an NMOS regulating transistor according to claim 1, characterized in that: The drain terminal of the NMOS transistor MN2 is connected to the input terminal VRAMP of the oscillator circuit.

3. The linear voltage regulator circuit based on an NMOS regulating transistor according to claim 1, characterized in that: A bias voltage VCN is generated by the bias voltage generation circuit. The bias voltage VCN is connected to a capacitor C3. The lower plate of the capacitor C3 is connected to the bias voltage VCN. The capacitor C3 is used to store charge. The bias voltage VCN raises the lower plate of the capacitor C3, controlling the voltage difference across the capacitor C3 to be within the withstand voltage range of the thin gate oxide process. The capacitor C3 is a thin gate oxide MOS transistor capacitor, and the upper plate of the capacitor C3 is the gate of the MOS transistor.

4. The linear voltage regulator circuit based on an NMOS regulating transistor according to claim 1, characterized in that: The capacitor C1 is the output capacitor, and the resistor R3 is the output load. The resistors R1 and R2 form a voltage divider circuit, which inputs the voltage-divided signal VOUT to the amplifier A1. The amplifier A1 subtracts the input voltage-divided signal from the reference voltage signal generated by the voltage source V1 and amplifies it to obtain the control voltage VEA. The current flowing through the NMOS transistor MN2 is controlled by VEA.

Images