Chip packaging method, chip electrostatic clamping device and chip

Abstract

The present invention discloses a chip packaging method, a chip electrostatic clamping device, and a chip. The chip packaging method includes: identifying redundant IO ports on a chip; and performing wire bonding on the pads of at least some of the redundant IO ports, so that the driver transistors corresponding to at least some of the IO ports and the discharge switch transistors in the electrostatic clamping circuit are connected in parallel between the power pin and the ground pin of the chip. Thus, the chip packaging method optimizes the wire bonding method, utilizes the redundant IO port circuits on the chip, and optimizes the packaging by bonding the pads of the IO ports to the power supply or ground, thereby enhancing surge and overvoltage resistance testing. This method improves surge performance without requiring additional area or circuit processing, reaching the highest industry standards, significantly extending the chip's service life, and reducing chip protection costs.

Description

Technical Field

[0001] The present invention relates to the technical field of surge testing, and in particular to a chip packaging method, a chip electrostatic clamping device, and a chip. Background Art

[0002] In recent years, with the continuous advancement of chip technology, EMC (electromagnetic compatibility) testing has become increasingly important for large appliances and machinery, such as home appliances, automotive components, and industrial control systems, to ensure proper operation. Surge testing, a key parameter within EMC testing, is also crucial. Surge refers to the powerful pulse generated at the moment the power is turned on. This pulse can be higher than the power supply's own pulse due to inherent circuit nonlinearity, or can be caused by internal or external spikes in the power supply or other circuit components. This surge can easily cause circuit failure.

[0003] Ordinary MCU (Microcontroller Unit) processes can only guarantee that overvoltages below 10 volts will not cause damage. However, if the high-speed overvoltage ripple exceeds 10 volts, the wafer fab cannot guarantee performance.

[0004] In related technologies, if the overvoltage exceeds 10 volts, additional circuit design is generally required to protect the circuit to prevent a short circuit between the power supply and the ground, which would affect the normal operation of the equipment. However, this method requires secondary design of the chip and the setting of additional modules to protect the chip, which greatly increases the control cost of the chip. Summary of the Invention

[0005] The present invention aims to at least partially address one of the technical problems in the related art. To this end, one object of the present invention is to provide a chip packaging method that optimizes the chip packaging by optimizing the wiring method and utilizing redundant IO (Input / Output) port circuits on the chip. This method optimizes the packaging by wiring the IO port pads to a power source or ground, thereby enhancing surge overvoltage resistance testing. This method improves surge performance without requiring additional area or circuit processing, achieving the highest industry standards, significantly extending the chip's service life, and reducing chip protection costs.

[0006] The second object of the present invention is to provide a chip.

[0007] A third objective of the present invention is to provide an electrostatic clamping device for a chip.

[0008] The fourth object of the present invention is to provide another chip.

[0009] To achieve the above-mentioned objectives, a first embodiment of the present invention proposes a chip packaging method, wherein the chip includes an electrostatic clamping circuit. The chip packaging method includes: determining redundant IO ports on the chip; and performing wire bonding packaging on the pads of at least some of the redundant IO ports so that the driving tubes corresponding to at least some of the IO ports and the discharge switching tubes in the electrostatic clamping circuit are connected in parallel between the power pin and the ground pin of the chip.

[0010] The chip packaging method of an embodiment of the present invention identifies redundant IO ports on a chip and performs wire bonding on the pads of at least some of the redundant IO ports, so that the driver transistors corresponding to at least some of the IO ports and the discharge switch transistors in the electrostatic clamp circuit are connected in parallel between the chip's power and ground pins. Thus, by optimizing the wire bonding method and utilizing the redundant IO ports on the chip, the chip packaging method optimizes the packaging by bonding the pads of these IO ports to the power supply or ground, thereby enhancing surge and overvoltage resistance testing. This improves surge performance without requiring additional area or circuit processing, reaching the highest industry standards, significantly extending the chip's service life, and reducing chip protection costs.

[0011] In some embodiments of the present invention, the driving tube corresponding to each IO port of the at least part of the IO ports includes an upper bridge driving tube and a lower bridge driving tube, and the upper bridge driving tube is connected to the lower bridge driving tube and then connected between the power pin and the ground pin, and the node between the upper bridge driving tube and the lower bridge driving tube is connected to the pad of the corresponding IO port, wherein the pads of at least part of the redundant IO ports are wired and packaged, including: wiring the pads of the at least part of the IO ports to the power pin; or wiring the pads of the at least part of the IO ports to the ground pin; or wiring the pads of some of the IO ports of the at least part of the IO ports to the power pin, and wiring the pads of other IO ports of the at least part of the IO ports to the ground pin.

[0012] In some embodiments of the present invention, the upper bridge driver transistor is a PMOS (Positive channel Metal Oxide Semiconductor) transistor, and the lower bridge driver transistor is an NMOS (Negative channel Metal Oxide Semiconductor) transistor.

[0013] To achieve the above-mentioned object, a second embodiment of the present invention provides a chip, which is formed by executing the chip packaging method of the above-mentioned embodiment.

[0014] The chip of the embodiment of the present invention can enhance the chip's surge overvoltage resistance test through the chip packaging method of the above embodiment. The surge performance can be improved without additional area or circuit processing, reaching the highest industry standards, greatly improving the chip's service life, and reducing the chip protection cost.

[0015] To achieve the above-mentioned purpose, an embodiment of the third aspect of the present invention proposes an electrostatic clamping device for a chip, wherein the chip includes at least one redundant IO port, and the device includes: an electrostatic clamping circuit, wherein the electrostatic clamping circuit includes a discharge switch tube and a trigger unit, wherein the discharge switch tube is connected between the power pin and the ground pin of the chip, and the trigger unit is used to trigger the discharge switch tube to turn on to release electrostatic electricity; an interface circuit corresponding to at least one redundant IO port, wherein the interface circuit includes an upper bridge driver tube and a lower bridge driver tube, wherein the upper bridge driver tube is connected to the lower bridge driver tube and then connected between the power pin and the ground pin of the chip, and the node between the upper bridge driver tube and the lower bridge driver tube is connected to the pad of the redundant IO port, and the pad is connected to the power pin or the ground pin, so that one of the upper bridge driver tube and the lower bridge driver tube is connected in parallel with the discharge switch tube.

[0016] The electrostatic clamping device of a chip according to an embodiment of the present invention includes an electrostatic clamping circuit and an interface circuit corresponding to at least one redundant IO port. The electrostatic clamping circuit includes a discharge switch and a trigger unit, the trigger unit being used to trigger the discharge switch to turn on for electrostatic discharge. The interface circuit corresponding to the redundant IO port includes an upper bridge driver and a lower bridge driver. The node between the upper bridge driver and the lower bridge driver is connected to a pad of the redundant IO port. The pad can be connected to a power pin or a ground pin to connect one of the upper bridge driver and the lower bridge driver in parallel with the discharge switch in the electrostatic clamping circuit. Thus, the chip packaging device connects the pad of the redundant IO port to a power source or ground to connect the discharge switch in the electrostatic clamping circuit in parallel with the driver in the IO port circuit, thereby enhancing surge overvoltage resistance testing. This improves surge performance without requiring additional area or circuit processing, meeting the highest industry standards, significantly extending the chip's service life, and reducing chip protection costs.

[0017] In some embodiments of the present invention, when there are multiple redundant IO ports, pads of at least some of the redundant IO ports are connected to power pins.

[0018] In some embodiments of the present invention, when there are multiple redundant IO ports, pads of at least some of the redundant IO ports are connected to ground pins.

[0019] In some embodiments of the present invention, when there are multiple redundant IO ports, the pads of some of the redundant IO ports are connected to ground pins, and the pads of another part of the redundant IO ports are connected to power pins.

[0020] In some embodiments of the present invention, the upper bridge driving transistor is a PMOS transistor, and the lower bridge driving transistor is an NMOS transistor.

[0021] To achieve the above-mentioned purpose, a fourth embodiment of the present invention provides another chip, which includes the electrostatic clamping device described in the above-mentioned embodiment.

[0022] The chip of this embodiment can enhance the chip's surge overvoltage resistance test through the electrostatic clamping device in the above embodiment. It can improve the surge performance without the need for additional area or circuit processing, reaching the highest industry standards, greatly improving the chip's service life, and reducing the chip protection cost.

[0023] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a flow chart of a chip packaging method according to an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of an electrostatic clamping circuit according to one embodiment of the present invention;

[0026] Figure 3 1 is a schematic diagram of the connection between an IO port circuit and an electrostatic clamping circuit according to an embodiment of the present invention;

[0027] Figure 4 is a schematic diagram of the connection between an IO port circuit and an electrostatic clamping circuit according to a specific embodiment of the present invention;

[0028] Figure 5 is a schematic diagram of the connection between an IO port circuit and an electrostatic clamping circuit according to another specific embodiment of the present invention;

[0029] Figure 6 1 is a schematic diagram of a chip external VDD signal and a chip internal VDD signal during surge detection according to one embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the chip's external VDD signal and the chip's internal VDD signal during surge detection in the related art;

[0031] Figure 8 is a structural block diagram of an electrostatic clamping device according to an embodiment of the present invention;

[0032] Figure 9 is a structural block diagram of a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0034] The chip packaging method, the chip electrostatic clamping device, and the chip according to the embodiments of the present invention will be described below with reference to the accompanying drawings.

[0035] Currently, large electrical equipment such as home appliances, automotive components, and industrial control systems require performance testing, as performance testing of all aspects of a device is often an important basis for determining its stability. For example, EMC testing is a key test item, and surge testing, a key parameter within EMC testing, is also very important. Surge testing involves applying a large ripple voltage to the power supply or ground while the DUT (Device Under Test) is operating normally. For example, a 4.5kV surge standard is required. Conventional MCU processes can only guarantee that overvoltages below 10V will not cause damage. However, if the overvoltage ripple far exceeds 10V, the silicon manufacturer cannot guarantee performance. Therefore, without additional processing, overvoltage damage can easily occur within the chip, and the most common damage is a short circuit between the power supply and ground. The chip packaging method of the present invention improves EMC surge performance by optimizing the wiring method. It utilizes some redundant IO ports on the chip and optimizes the packaging. The pads of the IO ports are wired to the power supply or ground, thereby strengthening the surge and overvoltage resistance test. The surge performance can be improved without the need for additional area or circuit processing, reaching the highest standards in the industry, greatly improving the service life of the chip, and reducing the protection cost of the chip.

[0036] Figure 1 is a flow chart of a chip packaging method according to an embodiment of the present invention.

[0037] like Figure 1 As shown, the present invention proposes a chip packaging method, which includes the following steps:

[0038] S10, determining redundant IO ports on the chip.

[0039] Specifically, the chip packaging method of an embodiment of the present invention is applicable to chips that include an internal electrostatic clamping circuit. This electrostatic clamping circuit can be positioned between a power line and a ground line, and the electrostatic clamping circuit includes a discharge switch transistor for discharging high currents to ground to prevent the high currents from interfering with the normal operation of the chip device. It is understood that the redundant IO ports on the chip in this embodiment can be redundant GPIOs (General Purpose Input / Output). Generally speaking, during use, chips often have some unused functions, resulting in some unused pads being left floating. Analysis of most chips shows that during the chip design process, a number of redundant IO ports are often included as backup. In this embodiment, the number of redundant IO ports on the chip can be determined based on the specific application scenario of the chip. It is understood that the number of redundant IO ports on the same chip can be different or the same in different application scenarios.

[0040] S20, performing wire bonding packaging on the pads of at least some of the redundant IO ports, so that the driving transistors corresponding to at least some of the IO ports and the discharge switch transistors in the electrostatic clamping circuit are connected in parallel between the power pin and the ground pin of the chip.

[0041] Figure 2 : This is a circuit diagram of an electrostatic clamping circuit according to an embodiment of the present invention. After analyzing an example of surge test failure, it is found that the failure points are mainly concentrated at the connection point of the discharge switch tube M0. Therefore, it can be clearly seen that this failure point is caused by the insufficient ability of the discharge switch tube M0 in the electrostatic clamping circuit 10 to release high voltage. Therefore, if the burden of the discharge switch tube M0 releasing high voltage is reduced, or the size of the discharge switch tube M0 is increased to improve the ability of the discharge switch tube M0 to release high voltage, the problem can be solved.

[0042] It should be noted that Figure 2 The trigger unit 11 in the circuit can be an RC clam (resistance-capacitance electrostatic clamp circuit). In the surge test, when a surge signal is provided to the power line, a high-speed overvoltage ripple EOS (Electrical Overstress) signal can be generated on the external power line. The EOS signal is generally at a speed of nanoseconds. The RC clam circuit will still function to generate a pulse input to the control end of the discharge switch tube M0, thereby turning on the discharge switch tube M0 so that the large current caused by the surge signal can be discharged to the ground through the discharge switch tube M0.

[0043] The embodiment of the present invention can share part of the high voltage release through the redundant IO port to reduce the burden of the discharge switch tube M0 in releasing the high voltage. Therefore, this embodiment can improve the high voltage release capability of the chip without adding external circuits.

[0044] Specifically, after determining the redundant IO ports on the chip, the chip can be further wire-bonded and packaged so that the driver tube in the redundant IO port can be connected in parallel with the discharge switch tube in the electrostatic clamping circuit. As a result, when a large current is released from the power line to the ground line through the electrostatic clamping circuit, part of the current can be released from the power line to the ground line through the driver tube in the IO port, thereby reducing the burden on the electrostatic clamping circuit and generally improving the chip's ability to release high voltage.

[0045] In some embodiments of the present invention, the driving tube corresponding to each IO port in at least some of the IO ports includes an upper bridge driving tube and a lower bridge driving tube, and the upper bridge driving tube is connected to the lower bridge driving tube and then connected between the power pin and the ground pin, and the node between the upper bridge driving tube and the lower bridge driving tube is connected to the pad of the corresponding IO port, wherein the pads of at least some of the redundant IO ports are wired and packaged, including: wiring the pads of at least some of the IO ports to the power pin; or wiring the pads of at least some of the IO ports to the ground pin; or wiring the pads of some of the IO ports in at least some of the IO ports to the power pin, and wiring the pads of other IO ports in at least some of the IO ports to the ground pin.

[0046] Specifically, if Figure 3 As shown, in the interface circuit 20 corresponding to the IO port of the present invention, the driver transistors include an upper bridge driver transistor M1 and a lower bridge driver transistor M2. After being connected, the upper bridge driver transistor M1 and the lower bridge driver transistor M2 are connected between the power pin VDD and the ground pin VSS, i.e., the power ground. Then, the node P between the upper bridge driver transistor M1 and the lower bridge driver transistor M2 is connected to the pad A of the corresponding IO port.

[0047] In this embodiment, at least part of the pads of the IO ports can be wired to the power pins, as shown in FIG. Figure 4 As shown, the pad A of the IO port can be wired to the pad D of the power pin, that is, the upper bridge driver tube M1 is short-circuited, so that during the surge test, the large current on the power line can be directly released to the ground through the lower bridge driver tube M2.

[0048] In this embodiment, the pads of at least part of the IO ports can be wired to the ground pins, as shown in FIG. Figure 5 As shown, the pad A of the IO port can be wired to the pad S of the ground pin, that is, the lower bridge driver tube M2 is short-circuited, so that during the surge test, the large current on the power line can be released to the ground through the upper bridge driver tube M1. It should be noted that Figure 4 and Figure 5 The driver tube indicated by the dotted line does not work or has no effect in this circuit.

[0049] It is understandable that Figure 4 and Figure 5 This embodiment is described using only one IO port as an example. In actual applications, two or more IO ports may be configured for the package. Furthermore, in some embodiments, the pads A of at least some of the IO ports may be bonded to the pads D of the power pins, while the pads A of other IO ports may be bonded to the pads D of the ground pins.

[0050] More specifically, there's no upper limit on the number of pads that can be bonded to power or ground pins on an IO port, as long as the chip allows. A greater number of pads provides greater resistance to surge currents. It's understandable that the more redundant IO ports bonded, the greater the current they can share, the faster the release time, and the greater the surge current relief.

[0051] In some specific embodiments, the upper bridge driving transistor in this embodiment is a PMOS transistor, and the lower bridge driving transistor is an NMOS transistor.

[0052] More specifically, after bonding at least some of the pads of the IO ports to the power pins or ground pins through the above embodiment, the chip is subjected to surge detection, and the results obtained are as follows: Figure 6 As shown, compared with the test results obtained when at least part of the IO port pads are not wired to the power pins or ground pins Figure 7 As shown, the VDD signal inside the chip of this embodiment is still lower than 10 volts under the surge signal test, so the chip tube will not be instantly broken down, thereby improving the life of the chip. In addition, this embodiment does not require the addition of additional external circuits, thereby reducing the chip control cost.

[0053] In summary, the chip packaging method of the embodiment of the present invention optimizes the wiring method, utilizes the redundant IO port circuits on the chip, and optimizes the packaging. The pads of the IO port are wired to the power supply or ground, thereby strengthening the surge and overvoltage resistance test. The surge performance can be improved without the need for additional area or circuit processing, reaching the highest standards in the industry, greatly improving the service life of the chip, and reducing the protection cost of the chip.

[0054] Furthermore, the present invention provides a chip, which is packaged by the chip packaging method in the above embodiment.

[0055] The embodiment of the present invention uses the chip packaging method in the above embodiment to package the chip, so that the chip packaged by the chip packaging method in the above embodiment can enhance the chip's surge resistance and overvoltage test, and can improve the surge performance without the need for additional area or circuit processing, reaching the highest standards in the industry, greatly improving the service life of the chip, and reducing the chip protection cost.

[0056] Figure 8FIG. 4 is a structural block diagram of an electrostatic clamping device according to an embodiment of the present invention.

[0057] Furthermore, if Figure 8 As shown, the present invention proposes an electrostatic clamping device 100, which includes an electrostatic clamping circuit 10 and an interface circuit 20 corresponding to at least one redundant IO port, wherein the electrostatic clamping circuit 10 includes a discharge switch tube M0 and a trigger unit 11. It should be noted that the figure only shows the interface circuit corresponding to one redundant IO port, and this embodiment may include multiple interface circuits, whose circuits are the same as the interface circuit 20 in this embodiment, so they are not repeated in the figure.

[0058] The electrostatic clamping circuit 10 includes a discharge switch transistor M0 and a trigger unit 11. The discharge switch transistor M0 is connected between the chip's power pin VDD and ground pin VSS. The trigger unit 11 is used to trigger the discharge switch transistor M0 to turn on, thereby discharging electrostatic discharge. The interface circuit 20 corresponding to the redundant IO port includes an upper bridge driver transistor M1 and a lower bridge driver transistor M2. The upper bridge driver transistor M1 and the lower bridge driver transistor M2 are connected to each other and then connected between the chip's power pin VDD and ground pin VSS. The node P between the upper bridge driver transistor M1 and the lower bridge driver transistor M2 is connected to the redundant IO port's pad A, which is connected to the power pin VDD or the ground pin VSS, thereby connecting one of the upper bridge driver transistor M1 and the lower bridge driver transistor M2 in parallel with the discharge switch transistor M0.

[0059] In one embodiment of the present invention, when there are multiple redundant IO ports, pads of at least some of the redundant IO ports are connected to power pins.

[0060] In one embodiment of the present invention, when there are multiple redundant IO ports, pads of at least some of the redundant IO ports are connected to ground pins.

[0061] In one embodiment of the present invention, when there are multiple redundant IO ports, pads of some of the redundant IO ports are connected to ground pins, and pads of another part of the redundant IO ports are connected to power pins.

[0062] In one embodiment of the present invention, the upper bridge driving transistor is an NMOS transistor, and the lower bridge driving transistor is a PMOS transistor.

[0063] It should be noted that for details not disclosed in the electrostatic clamping device of the embodiment of the present invention, please refer to the details disclosed in the chip packaging method of the embodiment of the present invention, and the details will not be repeated here.

[0064] In summary, the electrostatic clamping device of the embodiment of the present invention is connected between the power pin and the ground pin of the chip through the discharge switch tube in the electrostatic clamping circuit. The trigger unit in the electrostatic clamping circuit is used to trigger the discharge switch tube to open to perform electrostatic discharge or overvoltage release. At the same time, the driving tubes in some redundant IO ports are used to participate in the release. The packaging is optimized and the pads of the IO ports are wired to the power supply or ground, thereby strengthening the surge and overvoltage resistance test. The surge performance can be improved without additional area or circuit processing, reaching the highest industry standards, greatly improving the service life of the chip, and reducing the protection cost of the chip.

[0065] Figure 9 is a structural block diagram of a chip according to an embodiment of the present invention.

[0066] Furthermore, the present invention also proposes a chip 200, such as Figure 9 As shown, the chip 200 includes the electrostatic clamping device 100 in the above embodiment.

[0067] The chip of this embodiment can enhance the chip's surge overvoltage resistance test through the electrostatic clamping device in the above embodiment. It can improve the surge performance without the need for additional area or circuit processing, reaching the highest industry standards, greatly improving the chip's service life, and reducing the chip protection cost.

[0068] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0069] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0070] In addition, the terms "first" and "second" used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in this embodiment. Therefore, the features defined by the terms "first" and "second" in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of such features. In the description of the present invention, the word "plurality" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0071] In the present invention, unless otherwise clearly specified or limited in the embodiments, the terms "installed," "connected," "connect," and "fixed" appearing in the embodiments should be understood in a broad sense. For example, the connection may be a fixed connection, a detachable connection, or an integral connection. It can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be internal communication between two elements, or an interaction between two elements. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood based on the specific implementation.

[0072] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0073] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A chip packaging method, characterized in that: The chip includes an electrostatic clamping circuit, and the method includes: Determining redundant IO ports on the chip; Performing wire bonding on the pads of at least some of the redundant IO ports, so that the driver transistors corresponding to the at least some of the IO ports and the discharge switch transistors in the electrostatic clamping circuit are connected in parallel between the power pin and the ground pin of the chip, wherein when a large current is discharged from the power line to the ground line through the electrostatic clamping circuit, part of the current is discharged from the power line to the ground line through the driver transistors corresponding to the redundant IO ports; The driving transistor corresponding to each of the at least some of the IO ports includes an upper bridge driving transistor and a lower bridge driving transistor, wherein the upper bridge driving transistor is connected to the lower bridge driving transistor and then connected between the power pin and the ground pin, and the node between the upper bridge driving transistor and the lower bridge driving transistor is connected to the pad of the corresponding IO port, wherein the pads of at least some of the redundant IO ports are wire-bonded and packaged, including: Bonding the pads of at least part of the IO ports to the power pins; or Bonding the pads of at least part of the IO ports to the ground pins; or The pads of some of the at least some of the IO ports are bonded to the power pins, and the pads of the other IO ports of the at least some of the IO ports are bonded to the ground pins.

2. The method according to claim 1, characterized in that The upper bridge driving tube is a PMOS tube, and the lower bridge driving tube is an NMOS tube.

3. A chip, characterized in that: The chip is packaged by executing the chip packaging method according to any one of claims 1-2.

4. An electrostatic clamping device for a chip, characterized in that: The chip includes at least one redundant IO port, and the device includes: An electrostatic clamping circuit, comprising a discharge switch tube and a trigger unit, wherein the discharge switch tube is connected between the power pin and the ground pin of the chip, and the trigger unit is used to trigger the discharge switch tube to turn on for electrostatic discharge; An interface circuit corresponding to at least one redundant IO port, the interface circuit comprising an upper bridge driver tube and a lower bridge driver tube, the upper bridge driver tube being connected to the lower bridge driver tube and then connected between a power pin and a ground pin of the chip, the node between the upper bridge driver tube and the lower bridge driver tube being connected to a pad of the redundant IO port, the pad being connected to the power pin or the ground pin, so that one of the upper bridge driver tube and the lower bridge driver tube is connected in parallel with the discharge switch tube, wherein, when a large current is released from the power line to the ground line through the electrostatic clamping circuit, part of the current is released from the power line to the ground line through the driver tube corresponding to the redundant IO port.

5. The device according to claim 4, characterized in that When there are multiple redundant IO ports, pads of at least some of the redundant IO ports are connected to power pins.

6. The device according to claim 4, characterized in that When there are multiple redundant IO ports, pads of at least some of the redundant IO ports are connected to ground pins.

7. The device according to claim 4, characterized in that When there are multiple redundant IO ports, the pads of some of the redundant IO ports are connected to the ground pin, and the pads of another part of the redundant IO ports are connected to the power pin.

8. The device according to any one of claims 4 to 7, characterized in that The upper bridge driving tube is a PMOS tube, and the lower bridge driving tube is an NMOS tube.

9. A chip, characterized in that: The device comprises an electrostatic clamping device according to any one of claims 4 to 8.

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